TI ADS1291 Low-power, 2-channel, 24-bit analog front-end for biopotential measurement Datasheet

ADS1291
ADS1292
ADS1292R
www.ti.com
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
Low-Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements
Check for Samples: ADS1291, ADS1292 , ADS1292R
FEATURES
1
•
23
•
•
•
•
•
•
•
•
•
•
•
•
•
Two Low-Noise PGAs and
Two High-Resolution ADCs
(ADS1292 and ADS1292R)
Low Power: 335 μW/channel
Input-Referred Noise: 8 μVPP
(150-Hz BW, G = 6)
Input Bias Current: 200 pA
Data Rate: 125 SPS to 8 kSPS
CMRR: –105 dB
Programmable Gain: 1, 2, 3, 4, 6, 8, or 12
Supplies: Unipolar or Bipolar
– Analog: 2.7 V to 5.25 V
– Digital: 1.7 V to 3.6 V
Built-In Right Leg Drive Amplifier, Lead-Off
Detection, Test Signals
Integrated Respiration Impedance
Measurement (ADS1292R)
Built-In Oscillator and Reference
Flexible Power-Down, Standby Mode
SPI™-Compatible Serial Interface
Operating Temperature Range: –40°C to +85°C
The
ADS1291,
ADS1292,
and
ADS1292R
incorporate all features commonly required in
portable, low-power medical electrocardiogram
(ECG), sports, and fitness applications.
With high levels of integration and exceptional
performance, the ADS1291, ADS1292, and
ADS1292R enable the creation of scalable medical
instrumentation systems at significantly reduced size,
power, and overall cost.
The ADS1291, ADS1292, and ADS1292R have a
flexible input multiplexer per channel that can be
independently connected to the internally-generated
signals for test, temperature, and lead-off detection.
Additionally, any configuration of input channels can
be selected for derivation of the right leg drive (RLD)
output signal. The ADS1291, ADS1292, and
ADS1292R operate at data rates up to 8 kSPS. Leadoff detection can be implemented internal to the
device, using the device internal excitation current
sink/source. The ADS1292R version includes a fully
integrated respiration impedance measurement
function.
The devices are packaged in a 5-mm × 5-mm, 32-pin
thin quad flat pack (TQFP). Operating temperature is
specified from –40°C to +85°C.
REF
APPLICATIONS
Reference
SPI
(ADS1292R)
INPUTS
A1
RESP
DEMOD
CLK
ADC1
Oscillator
MUX
Control
GPIO AND CONTROL
•
Medical Instrumentation (ECG) including:
– Patient monitoring: Holter, event, stress,
and vital signs including ECG, AED, and
telemedicine
– Sports and fitness
(heart rate, respiration, and ECG)
High-Precision, Simultaneous, Multichannel
Signal Acquisition
ADC2
A2
To Channel
¼
(ADS1292R)
DESCRIPTION
The ADS1291, ADS1292, and ADS1292R are
multichannel, simultaneous sampling, 24-bit, deltasigma (ΔΣ) analog-to-digital converters (ADCs) with a
built-in programmable gain amplifier (PGA), internal
reference, and an onboard oscillator.
SPI
•
Test Signals and
Monitors
RESP
MOD
¼
RESP
RLD
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY AND ORDERING INFORMATION (1)
PRODUCT
ADS1291I
ADS1292I
ADS1292RI
(1)
PACKAGE
DESIGNATOR
NUMBER OF
CHANNELS
ADC
RESOLUTION
MAXIMUM
SAMPLE
RATE (kSPS)
TQFP
PBS
1
24
8
–40°C to +85°C
No
QFN
RSM
1
24
8
–40°C to +85°C
No
TQFP
PBS
2
24
8
–40°C to +85°C
No
PACKAGE
OPTION
OPERATING
TEMPERATUR RESPIRATION
E RANGE
CIRCUITRY
QFN
RSM
2
24
8
–40°C to +85°C
No
TQFP
PBS
2
24
8
–40°C to +85°C
Yes
QFN
RSM
2
24
8
–40°C to +85°C
Yes
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS1291, ADS1292, ADS1292R
UNIT
AVDD to AVSS
–0.3 to +5.5
V
DVDD to DGND
–0.3 to +3.9
V
AGND to DGND
–0.3 to +0.3
V
Analog input to AVSS
AVSS – 0.3 to AVDD + 0.3
V
Digital input to DVDD
DVSS – 0.3 to DVDD + 0.3
V
±10
mA
±100
mA
Input current to any pin except supply pins
Input current
Momentary
±10
mA
Operating temperature range
Continuous
–40 to +85
°C
Storage temperature range
–60 to +150
°C
Maximum junction temperature (TJ)
ESD ratings
(1)
2
+150
°C
Human body model (HBM)
JEDEC standard 22, test method A114-C.01, all pins
±1000
V
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
±500
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
ADS1291
ADS1292
ADS1292R
www.ti.com
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD – AVSS = 3 V (1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF (2),
and gain = 6, unless otherwise noted.
ADS1291, ADS1292, ADS1292R
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale differential input voltage
(AINP – AINN)
±VREF/GAIN
V
See the Input Common-Mode Range
subsection of the PGA Settings and Input
Range section
Input common-mode range
Input capacitance
20
TA = +25°C, input = 1.5 V
Input bias current (PGA chop = 8 kHz)
TA = –40°C to +85°C, input = 1.5 V
DC input impedance
pA
±1
Chop rates other than 8 kHz
No pull-up or pull-down current source
pF
±200
nA
See Pace Detect section
1000
MΩ
Current source lead-off detection (nA),
AVSS + 0.3 V < AIN < AVDD – 0.3 V
500
MΩ
Current source lead-off detection (µA),
AVSS + 0.6 V < AIN < AVDD – 0.6 V
100
MΩ
PGA PERFORMANCE
Gain settings
1, 2, 3, 4, 6, 8, 12
With a 4.7-nF capacitor on PGA output
(see PGA Settings and Input Range section
for details)
Bandwidth
8.5
kHz
ADC PERFORMANCE
Resolution
24
Data rate
fCLK = 512 kHz
Bits
125
8000
SPS
CHANNEL PERFORMANCE (DC Performance)
Input-referred noise
Gain = 6 (3), 10 seconds of data
8
Gain = 6, 256 points, 0.5 seconds of data
8
Gain settings other than 6,
data rates other than 500 SPS
Integral nonlinearity
μVPP
11
μVPP
See Noise Measurements section
Full-scale with gain = 6, best fit
2
Offset error
ppm
μV
±100
Offset error drift
μV/°C
2
Offset error with calibration
μV
15
Gain error
Excluding voltage reference error
Gain drift
Excluding voltage reference drift
±0.1
Gain match between channels
±0.2
% of FS
2
ppm/°C
0.2
% of FS
CHANNEL PERFORMANCE (AC performance)
CMRR
Common-mode rejection ratio
fCM = 50 Hz and 60 Hz (4)
–120
dB
PSRR
Power-supply rejection ratio
fPS = 50 Hz and 60 Hz
90
dB
Crosstalk
fIN = 50 Hz and 60 Hz
–120
dB
Signal-to-noise ratio
fIN = 10 Hz input, gain = 6
107
dB
10 Hz, –0.5 dBFs, CFILTER = 4.7nF
–104
dB
100 Hz, –0.5 dBFs, CFILTER = 4.7nF
–95
dB
ADS1292R channel 1, 10 Hz, –0.5 dBFS,
CFILTER = 47 nF
–82
dB
SNR
THD
(1)
(2)
(3)
(4)
Total harmonic distortion
–105
Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V.
CFILTER is the capacitor accross the PGA outputs; see the PGA Settings and Input Range section for details.
Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted
(without electrode resistance) over a 10-second interval.
CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the two
channels.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
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3
ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2),
and gain = 6, unless otherwise noted.
ADS1291, ADS1292, ADS1292R
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL FILTER
–3-dB bandwidth
Digital filter settling
0.262 fDR
Full setting
Hz
4
Conversions
RIGHT LEG DRIVE (RLD) AMPLIFIER
μVRMS
RLD integrated noise
BW = 150 Hz
1.4
GBP
Gain bandwidth product
50 kΩ || 10 pF load, gain = 1
100
kHz
SR
Slew rate
50 kΩ || 10 pF load, gain = 1
0.07
V/μs
THD
Total harmonic distortion
fIN = 100 Hz, gain = 1
CMIR
Common-mode input range
Common-mode resistor matching
ISC
–85
AVSS + 0.3
Internal 200-kΩ resistor matching
Short-circuit current
dB
AVDD – 0.3
V
0.1
%
1.1
mA
5
μA
Quiescent power consumption
LEAD-OFF DETECT
Frequency
See Register Map section for settings
0, fDR/4
kHz
ILEAD_OFF [1:0] = 00
6
nA
ILEAD_OFF [1:0] = 01
22
nA
ILEAD_OFF [1:0] = 10
6
μA
ILEAD_OFF [1:0] = 11
22
μA
Current accuracy
±10
%
Comparator threshold accuracy
±10
mV
Current
RESPIRATION (ADS1292R)
Frequency
Internal source
32, 64
External source
Phase shift
See Register Map section for settings
Impedance range
IRESP = 30 µA
Impedance measurement noise
0.05-Hz to 2-Hz brick wall filter, 32-kHz
modulation clock, phase = 112.5,
using IRESP = 30 µA with 2-kΩ baseline load,
gain = 4
Maximum modulator current
Using Internal reference
32
0
kHz
64
kHz
112.5
168.75
Degrees
2000
10,000
Ω
40
mΩPP
100
μA
EXTERNAL REFERENCE
Reference input voltage
VREFN
Negative input
VREFP
Positive input
3-V supply VREF = (VREFP – VREFN)
2
2.5
VDD – 0.3
V
5-V supply VREF = (VREFP – VREFN)
2
4
VDD – 0.3
V
AVSS
AVSS + 2.5
Input impedance
4
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120
V
V
kΩ
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
ADS1291
ADS1292
ADS1292R
www.ti.com
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2),
and gain = 6, unless otherwise noted.
ADS1291, ADS1292, ADS1292R
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE
Output voltage
Output current drive
Register bit CONFIG2.VREF_4V = 0
2.42
Register bit CONFIG2.VREF_4V = 1
4.033
V
100
µA
Available for external use
VREF accuracy
V
±0.5
Internal reference drift
–40°C ≤ TA ≤ +85°C
Start-up time
Settled to 0.2% with 10-µF capacitor on
VREFP pin
%
45
ppm/°C
100
ms
20
µA
Analog supply reading error
1
%
Digital supply reading error
1
%
From power-supply ramp after power-on
reset (POR) to DRDY low
32
ms
From power-down mode to DRDY low
10
ms
From STANDBY mode to DRDY low
10
ms
1% accuracy
0.5
s
TA = +25°C
145
mV
490
μV/°C
Quiescent current consumption
SYSTEM MONITORS
Device wake up
VCAP1 settling time
Temperature sensor
reading
Voltage
Coefficient
TEST SIGNAL
Signal frequency
See Register Map section for settings
Signal voltage
See Register Map section for settings
At dc and 1 Hz
Accuracy
Hz
±1
mV
±2
%
CLOCK
Internal oscillator clock frequency
Nominal frequency
Internal clock accuracy
512
kHz
TA = +25°C
±0.5
–40°C ≤ TA ≤ +85°C
±1.5
Internal oscillator start-up time
External clock input frequency
%
μs
32
Internal oscillator power consumption
%
μW
30
CLKSEL pin = 0, CLK_DIV = 0
485
512
562.5
kHz
CLKSEL pin = 0, CLK_DIV = 1
1.94
2.048
2.25
MHz
DIGITAL INPUT/OUTPUT
VIH
DVDD = 1.8 V to
3.6 V
0.8 DVDD
DVDD + 0.1
V
VIL
DVDD = 1.8 V to
3.6 V
–0.1
0.2 DVDD
V
VIH
DVDD = 1.7 V to
1.8 V
DVDD – 0.2
VIL
Logic level
V
DVDD = 1.7 V to
1.8 V
0.2
VOH
DVDD = 1.7 V to
3.6 V
IOH = –500 μA
VOL
DVDD = 1.7 V to
3.6 V
IOL = +500 μA
IIN
Input current
0 V < VDigitalInput < DVDD
0.9 DVDD
V
V
–10
0.1 DVDD
V
+10
μA
POWER-SUPPLY REQUIREMENTS
AVDD
Analog supply
AVDD – AVSS
DVDD
Digital supply
DVDD – DGND
AVDD – DVDD
2.7
3
5.25
V
1.7
1.8
3.6
V
3.6
V
–2.1
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
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5
ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum specifications apply from –40°C to +85°C. Typical specifications are at +25°C. All specifications are
at DVDD = 1.8 V, AVDD – AVSS = 3 V(1), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(2),
and gain = 6, unless otherwise noted.
ADS1291, ADS1292, ADS1292R
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT (RLD Amplifier Turned Off)
IAVDD
Normal mode
IDVDD
AVDD – AVSS = 3 V
205
μA
AVDD – AVSS = 5 V
250
μA
DVDD = 3.3 V
75
μA
DVDD = 1.8 V
32
μA
POWER DISSIPATION (Analog Supply = 3 V, RLD Amplifier Turned Off)
Quiescent power
dissipation
Normal mode
670
Standby mode
160
Normal mode
450
Standby mode
160
µW
ADS1292R
Normal mode
335
µW
ADS1292
Normal mode
335
µW
ADS1291
Normal mode
450
µW
Normal mode
1300
µW
Standby mode
340
µW
Normal mode
950
µW
Standby mode
340
µW
ADS1292R
Normal mode
670
µW
ADS1292
Normal mode
670
µW
ADS1291
Normal mode
860
µW
DVDD = 1.8 V
1
µW
DVDD = 3.3 V
4
µW
DVDD = 1.8 V
5
µW
DVDD = 3.3 V
10
µW
ADS1292 and
ADS1292R
ADS1291
Quiescent power
dissipation, per
channel
740
µW
µW
495
µW
POWER DISSIPATION (Analog Supply = 5 V, RLD Amplifier Turned Off)
Quiescent power
dissipation
ADS1292 and
ADS1292R
ADS1291
Quiescent power
dissipation, per
channel
POWER DISSIPATION IN POWER-DOWN MODE
Analog supply = 3 V
Analog supply = 5 V
TEMPERATURE
Specified temperature range
–40
+85
°C
Operating temperature range
–40
+85
°C
Storage temperature range
–60
+150
°C
THERMAL INFORMATION
ADS1291,
ADS1292,
ADS1292R
THERMAL METRIC (1)
UNITS
PBS (TQFP)
32 PINS
θJA
Junction-to-ambient thermal resistance
68.4
θJCtop
Junction-to-case (top) thermal resistance
25.9
θJB
Junction-to-board thermal resistance
30.5
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
24.3
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
ADS1291
ADS1292
ADS1292R
www.ti.com
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
NOISE MEASUREMENTS
The ADS1291, ADS1292, and ADS1292R noise performance can be optimized by adjusting the data rate and
PGA setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly.
Increasing the programmable gain amplifier (PGA) value reduces the input-referred noise, which is particularly
useful when measuring low-level biopotential signals. Table 1 through Table 8 summarize the ADS1291,
ADS1292, and ADS1292R noise performance. The data are representative of typical noise performance at TA =
+25°C. The data shown are the result of averaging the readings from multiple devices and are measured with the
inputs shorted together. For the shown data rates, the ratio is approximately 6.6.
Table 1 through Table 8 show measurements taken with an internal reference. The data are also representative
of the ADS1291, ADS1292, and ADS1292R noise performance when using a low-noise external reference such
as the REF5025.
In Table 1 through Table 8, µVRMS and µVPP are measured values. SNR, noise-free bits, ENOB, and dynamic
range are calculated with Equation 1, Equation 2, and Equation 3.
SNR = ENOB ´ 6.02
(1)
2 VREF
Noise-Free Bits = 2 log
Gain ´ Peak-to-Peak Noise
(2)
VREF
ENOB = 2 log
2 ´ Gain ´ RMS Noise
(3)
Table 1. Input-Referred Noise (μVRMS/μVPP) 3-V Analog Supply and 2.42-V Reference (1)
PGA GAIN = 1
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
1.5
10.3
001
250
65.5
2.2
010
500
131
011
1000
100
(1)
PGA GAIN = 2
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
121.0
18.83
20.10
0.8
5.6
ENOB
120.0
18.71
14.4
117.8
18.34
19.58
1.2
19.94
7.5
117.1
18.29
3.0
18.9
115.1
17.95
19.11
19.46
1.7
10.9
113.9
17.75
262
4.6
30.8
111.3
17.25
18.91
18.49
2.5
15.6
110.6
17.23
2000
524
10.1
99
104.5
18.37
15.57
17.36
5.3
48
104.0
15.60
101
4000
1048
55.2
563
17.28
89.7
13.06
14.91
26.0
265
90.3
13.14
110
8000
2096
287.3
15.00
2930
75.4
10.68
12.53
144.1
1470
75.4
10.67
111
NA
NA
—
12.52
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 2. Input-Referred Noise (μVRMS/μVPP) 3-V Analog Supply and 2.42-V Reference (1)
PGA GAIN = 3
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.6
4.1
001
250
65.5
0.9
010
500
131
011
1000
100
(1)
PGA GAIN = 4
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
119.2
18.58
19.80
0.5
3.4
ENOB
117.9
18.42
5.5
115.9
18.15
19.26
0.8
19.58
5.0
114.8
17.88
1.3
7.7
113.0
17.67
18.77
19.07
1.1
6.6
111.9
17.47
262
1.9
12.0
109.5
17.02
18.59
18.19
1.6
10.3
108.7
16.83
2000
524
3.7
31
103.7
18.06
15.65
17.23
2.9
23
103.2
15.69
101
4000
1048
17.0
173
17.14
90.5
13.18
15.03
12.2
124
90.8
13.24
110
8000
2096
91.9
15.09
937
75.8
10.74
12.59
66.8
681
76.1
10.78
111
NA
NA
—
12.63
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
Table 3. Input-Referred Noise (μVRMS/μVPP) 3-V Analog Supply and 2.42-V Reference (1)
PGA GAIN = 6
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.5
3.0
001
250
65.5
0.7
010
500
131
011
1000
100
(1)
PGA GAIN = 8
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
115.9
18.04
19.26
0.4
2.6
ENOB
114.0
17.82
4.1
112.8
17.58
18.73
0.6
18.94
3.9
111.0
17.22
0.9
5.6
109.9
17.14
18.25
18.44
0.8
5.5
108.0
16.75
262
1.3
8.7
106.8
16.49
17.93
17.73
1.2
7.6
104.9
16.26
2000
524
2.2
16
102.1
17.42
15.64
16.96
2.0
14
100.7
15.36
101
4000
1048
7.5
77
16.72
91.5
13.34
15.19
5.5
56
91.7
13.39
110
8000
2096
42.7
15.24
436
76.4
10.84
12.69
31.3
319
76.6
10.88
111
NA
NA
—
12.73
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 4. Input-Referred Noise (μVRMS/μVPP) 3-V Analog Supply and 2.42-V Reference (1)
PGA GAIN = 12
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.4
2.5
001
250
65.5
0.5
010
500
131
011
1000
100
(1)
SNR
NOISEFREE
BITS
ENOB
111.3
17.31
18.48
3.5
108.4
16.81
18.01
0.8
5.0
105.0
16.29
17.44
262
1.1
6.9
102.1
15.82
16.97
2000
524
1.7
11
98.6
15.21
16.38
101
4000
1048
3.5
36
92.0
13.44
15.29
110
8000
2096
20.1
205
76.9
10.93
12.78
111
NA
NA
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 5. Input-Referred Noise (μVRMS/μVPP) 5-V Analog Supply and 4.033-V Reference (1)
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
1.6
10.2
001
250
65.5
2.2
010
500
131
011
1000
100
(1)
8
PGA GAIN = 1
DR BITS
OF
CONFIG1
REGISTER
PGA GAIN = 2
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
124.9
19.58
20.75
0.9
5.4
ENOB
124.3
19.50
13.3
122.3
19.20
20.31
1.2
20.65
8.1
121.3
18.91
3.1
18.9
119.3
18.69
19.82
20.15
1.7
10.6
118.2
18.52
262
4.9
31.9
115.2
17.94
19.63
19.14
2.7
17.9
114.4
17.77
2000
524
15.5
167
105.2
19.00
15.55
17.48
7.5
80
105.5
15.62
101
4000
1048
89.6
959
17.53
90.0
13.03
14.95
45.0
481
89.9
13.02
110
8000
2096
460.1
14.94
4923
75.8
10.67
12.59
229.0
2450
75.8
10.67
12.59
111
NA
NA
—
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
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ADS1292R
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
Table 6. Input-Referred Noise (μVRMS/μVPP) 5-V Analog Supply and 4.033-V Reference (1)
PGA GAIN = 3
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.6
4.2
001
250
65.5
0.9
010
500
131
011
1000
100
(1)
PGA GAIN = 4
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
123.4
19.28
20.50
0.5
3.6
ENOB
122.3
19.08
5.7
120.7
18.82
20.04
0.7
20.32
4.8
119.5
18.66
1.3
8.4
117.3
18.27
19.49
19.86
1.1
7.4
116.2
18.04
262
2.0
13.3
113.5
17.62
19.31
18.85
1.6
11.0
112.7
17.48
2000
524
5.1
53
105.3
18.72
15.61
17.49
3.9
38
105.2
15.67
101
4000
1048
28.7
307
17.47
90.3
13.08
15.00
20.7
222
90.6
13.14
110
8000
2096
149.3
15.06
1598
76.0
10.70
12.62
111.8
1196
76.0
10.71
111
NA
NA
—
12.63
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 7. Input-Referred Noise (μVRMS/μVPP) 5-V Analog Supply and 4.033-V Reference (1)
PGA GAIN = 6
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.5
3.0
001
250
65.5
0.6
010
500
131
011
1000
100
(1)
PGA GAIN = 8
SNR
NOISEFREE
BITS
SNR
NOISEFREE
BITS
ENOB
μVRMS
μVPP
120.4
18.78
19.99
0.4
2.7
ENOB
118.5
18.48
4.0
117.5
18.36
19.52
0.6
19.68
3.8
115.7
18.01
0.9
6.0
114.3
17.75
18.99
19.21
0.8
5.3
112.8
17.53
262
1.4
8.8
110.8
17.20
18.74
18.41
1.2
8.1
109.5
16.92
2000
524
2.8
24
104.6
18.19
15.74
17.38
2.3
18
103.6
15.73
101
4000
1048
13.3
142
17.22
91.0
13.20
15.12
9.3
100
91.5
13.29
110
8000
2096
71.5
15.21
765
76.4
10.77
12.69
52.3
560
76.6
10.80
111
NA
NA
—
12.72
—
—
—
—
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
Table 8. Input-Referred Noise (μVRMS/μVPP) 5-V Analog Supply and 4.033-V Reference (1)
PGA GAIN = 12
DR BITS
OF
CONFIG1
REGISTER
OUTPUT
DATA
RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
μVRMS
μVPP
000
125
32.75
0.4
2.6
001
250
65.5
0.5
010
500
131
011
1000
100
(1)
SNR
NOISEFREE
BITS
ENOB
115.7
17.96
19.21
3.4
112.9
17.59
18.75
0.8
5.2
109.8
16.96
18.24
262
1.1
6.9
106.6
16.56
17.70
2000
524
1.9
14
101.9
15.57
16.83
101
4000
1048
5.9
63
92.0
13.37
15.29
110
8000
2096
33.8
362
76.9
10.85
12.77
111
NA
NA
—
—
—
—
—
At least 1000 consecutive readings were used to calculate the peak-to-peak noise values in this table.
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ADS1292
ADS1292R
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TIMING CHARACTERISTICS
tCLK
CLK
tCSSC
tSCLK
SCLK
tCSH
tSDECODE
CS
1
tSPWL
tSPWH
3
2
8
1
tDIHD
tDIST
tSCCS
3
2
8
tDOPD
DIN
tCSDOZ
tCSDOD
Hi-Z
Hi-Z
DOUT
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
Timing Requirements For Figure 1 (1)
2.7 V ≤ DVDD ≤ 3.6 V
PARAMETER
tCLK
DESCRIPTION
MAX
UNIT
1775
2170
1775
2170
ns
Master clock period (CLK_DIV bit of LOFF_STAT register = 1)
444
542
444
542
ns
CS low to first SCLK, setup time
tSCLK
tSPWH,
TYP
1.7 V ≤ DVDD ≤ 2 V
Master clock period (CLK_DIV bit of LOFF_STAT register = 0)
tCSSC
MIN
MAX
MIN
TYP
6
17
ns
SCLK period
50
66.6
ns
SCLK pulse width, high and low
15
25
ns
tDIST
DIN valid to SCLK falling edge: setup time
10
10
ns
tDIHD
Valid DIN after SCLK falling edge: hold time
10
11
tDOPD
SCLK rising edge to DOUT valid
tCSH
CS high pulse
tCSDOD
CS low to DOUT driven
tSCCS
L
12
ns
22
ns
2
2
10
20
ns
Eighth SCLK falling edge to CS high
3
3
tCLKs
tSDECODE
Command decode time
4
tCSDOZ
CS high to DOUT Hi-Z
(1)
10
tCLKs
4
10
tCLKs
20
ns
Specifications apply from –40°C to +85°C. Load on DOUT = 20 pF || 100 kΩ.
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
PIN CONFIGURATIONS
25 GPIO2/RCLK2
26 GPIO1/RCLK1
27 VCAP2
28 RLDINV
29 RLDIN/RLDREF
30 RLDOUT
31 RESP_MODP/IN3P
32 RESP_MODN/IN3N
PBS PACKAGE
TQFP-32
(TOP VIEW)
22 DRDY
IN1P
4
21 DOUT
IN2N
5
20 SCLK
IN2P
6
19 DIN
PGA2N
7
18 CS
PGA2P
8
17 CLK
VREFP
START 16
3
PWDN/RESET 15
IN1N
CLKSEL 14
23 DVDD
AVSS 13
2
AVDD 12
PGA1P
VCAP1 11
24 DGND
VREFN 10
1
9
PGA1N
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
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PIN ASSIGNMENTS
NAME
TERMINAL
FUNCTION
DESCRIPTION
AVDD
12
Supply
Analog supply
AVSS
13
Supply
Analog ground
CLK
17
Digital input
Master clock input
CLKSEL
14
Digital input
Master clock select
CS
18
Digital input
Chip select
DGND
24
Supply
DIN
19
Digital input
DOUT
21
Digital output
SPI data out
DRDY
22
Digital output
Data ready; active low
DVDD
23
Supply
GPIO1/RCLK1
26
Digital input/output
General-purpose I/O 1 or resp clock 1 (ADS1292R)
GPIO2/RCLK2
25
Digital input/output
General-purpose I/O 2 or resp clock 2 (ADS1292R)
IN1N (1)
3
Analog input
Differential analog negative input 1
(1)
4
Analog input
Differential analog positive input 1
IN2N (1)
5
Analog input
Differential analog negative input 2
IN2P (1)
6
Analog input
Differential analog positive input 2
PGA1N
1
Analog output
PGA1 inverting output
IN1P
Digital ground
SPI data in
Digital power supply
PGA1P
2
Analog output
PGA1 noninverting output
PGA2N
7
Analog output
PGA2 inverting output
PGA2P
8
Analog output
PGA2 noninverting output
PWDN/RESET
15
Digital input
RESP_MODN/IN3N (1)
32
Analog input/output
Power-down or system reset; active low
N-side respiration excitation signal for respiration or auxiliary input 3N
RESP_MODP/IN3P (1)
31
Analog input/output
P-side respiration excitation signal for respiration or auxiliary input 3P
RLDIN/RLDREF
29
Analog input
Right leg drive input to MUX or RLD amplifier noninverting input; connect
to AVDD if not used
RLDINV
28
Analog input
Right leg drive inverting input; connect to AVDD if not used
RLDOUT
30
Analog input
Right leg drive output
SCLK
20
Digital input
SPI clock
START
16
Digital input
Start conversion
VCAP1
11
—
Analog bypass capacitor
Analog bypass capacitor
VCAP2
27
—
VREFN
10
Analog input
VREFP
9
Analog input/output
(1)
Connect unused analog inputs to AVDD.
12
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Negative reference voltage; must be connected to AVSS
Positive reference voltage
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ADS1292R
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =
512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted.
INPUT-REFERRED NOISE
NOISE HISTOGRAM
4
1200
1000
2
1
Occurences
Input−Referred Noise (µV)
3
0
−1
800
600
400
−2
200
−3
Peak−to−Peak Over 10 seconds = 8 µV
G001
4
3
3.5
2
2.5
1
1.5
0
0.5
−1
−0.5
0
10
−2
8
−1.5
6
Time (sec)
−3
4
−2.5
2
−4
0
−3.5
−4
Input−Referred Noise (µV)
G002
Figure 2.
Figure 3.
INTERNAL REFERENCE vs TEMPERATURE
CMRR vs FREQUENCY
−95
Common−Mode Rejection Ratio (dB)
Internal Reference (V)
2.424
2.422
2.42
2.418
2.416
−40
−15
10
35
Temperature (°C)
60
−105
−110
−115
Gain = 1
Gain = 2
Gain = 3
Gain = 4
Gain = 6
Gain = 8
Gain = 12
−120
−125
−130
−135
85
Data Rate = 8 kSPS
AIN = AVDD − 0.3 V to AVSS + 0.3 V
−100
10
100
Frequency (Hz)
G003
Figure 4.
G004
Figure 5.
LEAKAGE CURRENT vs INPUT VOLTAGE
LEAKAGE CURRENT vs TEMPERATURE
0.7
2.5
0.6
0.5
Leakage Current (nA)
2
Leakage Current (nA)
1k
64 kHz Chop Rate
32 kHz Chop Rate
0.4
0.3
8 kHz Chop Rate
0.2
1.5
AVDD = 3 V, Chop = 8 k
AVDD = 3 V, Chop = 32 k
AVDD = 3 V, Chop = 64 k
AVDD = 5 V, Chop = 8 k
AVDD = 5 V, Chop = 32 k
AVDD = 5 V, Chop =64 k
1
0.5
0.1
0
0
0.5
1
1.5
2
Input Signal (V)
2.5
3
0
−40
−15
G030
Figure 6.
10
35
Temperature (°C)
60
85
G006
Figure 7.
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =
512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted.
PSRR vs FREQUENCY
THD vs FREQUENCY
−55
Data Rate = 8 kSPS, −0.5 dBFS
Data Rate = 8 kSPS, −0.5 dBFS
110
−65
100
−75
THD (dB)
Power Supply Rejection Ratio (dB)
120
90
80
70
Gain = 1
Gain = 2
Gain = 3
Gain = 4
60
50
10
−85
Gain = 1
Gain = 2
Gain = 3
Gain = 4
Gain = 6
Gain = 8
Gain = 12
−95
−105
Gain = 6
Gain = 8
Gain = 12
−115
100
Frequency (Hz)
−125
1k
10
100
Frequency (Hz)
G007
Figure 8.
INL vs PGA GAIN
INL vs TEMPERATURE
Integral Nonlinearity (ppm)
Integral Nonlinearity (ppm)
4
3
2
1
2
0
−2
−40 °C
−20 °C
0 °C
25 °C
−4
0
2
4
6
PGA Gain
8
10
−1
12
G009
−0.5
0
0.5
Input Range (Normalized to Full−Scale)
Figure 11.
THD FFT PLOT
(60-Hz Signal)
FFT PLOT
(60-Hz Signal)
1
G010
0
PGA Gain = 1
Input = 10Hz, −0.5 dBFS
THD = −103 dB
SNR =117 dB
Data Rate =500 sps
−40
−60
−80
−100
−120
−40
−60
−80
−100
−140
−120
−160
−140
0
50
100
150
Frequency (Hz)
200
PGA Gain = 1
Input = 10Hz, −0.5 dBFS
THD = −101 dB
SNR = 80 dB
Data Rate = 8 ksps
−20
Amplitude (dBFS)
−20
Amplitude (dBFS)
40 °C
50 °C
70 °C
85 °C
Figure 10.
0
250
−160
0
1000
G011
Figure 12.
14
G008
Figure 9.
4
−180
1k
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2000
Frequency (Hz)
3000
4000
G012
Figure 13.
Copyright © 2011–2012, Texas Instruments Incorporated
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ADS1291
ADS1292
ADS1292R
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.42 V, VREFN = AVSS, external clock =
512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF, and gain = 6, unless otherwise noted.
OFFSET vs PGA GAIN
(Absolute Value)
TEST SIGNAL AMPLITUDE ACCURACY
300
60
Data from 96 devices, Two lots
250
Number of Bins
Offset (uV)
200
150
100
40
20
50
G013
0.6
0.5
0.4
0.3
0.2
0.1
0
12
0
10
−0.1
6
8
PGA Gain (dB)
−0.2
4
−0.3
2
−0.4
0
−0.5
0
Error (%)
G014
Figure 14.
Figure 15.
LEAD-OFF COMPARATOR THRESHOLD ACCURACY
LEAD-OFF CURRENT SOURCE ACCURACY
DISTRIBUTION
140
120
Data from 96 devices, Two Lots
120
Data from 125 devices, Two lots
Current Setting = 24 nA
2.5
2
1.5
Threshold Error (mV)
1
−2
12
10
8
6
4
2
0
−2
−4
0
−6
0
−8
20
−10
20
0.5
40
0
40
60
−0.5
60
80
−1
80
−1.5
Number of Bins
Number of Bins
100
100
Error in Current Magnitude (nA)
G015
Figure 16.
Copyright © 2011–2012, Texas Instruments Incorporated
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G016
Figure 17.
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
www.ti.com
OVERVIEW
The ADS1291, ADS1292, and ADS1292R are low-power, multichannel, simultaneously-sampling, 24-bit deltasigma (ΔΣ) analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These
devices integrate various electrocardiogram (ECG)-specific functions that make them well-suited for scalable
ECG, sports, and fitness applications. The devices can also be used in high-performance, multichannel data
acquisition systems by powering down the ECG-specific circuitry.
The ADS1291, ADS1292, and ADS1292R have a highly programmable multiplexer that allows for temperature,
supply, input short, and RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be
programmed as the patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4,
6, 8, and 12). The ADCs in the device offer data rates from 125 SPS to 8 kSPS. Communication to the device is
accomplished using an SPI-compatible interface. The device provides two general-purpose I/O (GPIO) pins for
general use. Multiple devices can be synchronized using the START pin.
The internal reference can be programmed to either 2.42 V or 4.033 V. The internal oscillator generates a 512kHz clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of
electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using an
external pull-up or pull-down resistor or the device internal current source or sink. An internal ac lead-off
detection feature is also available. Apart from the above features, the ADS1292R provides options for internal
respiration circuitry. Figure 18 shows a block diagram for the ADS1291, ADS1292, and ADS1292R.
AVDD
VCAP1
PGA1P
PGA1N
Power-Supply Signal
RESP_EN
Temperature Sensor Input
VREFP
VCAP2
VREFN
DVDD
Reference
RESP
DEMOD1
(ADS1292R)
Test Signal
DRDY
Lead-Off Excitation Source
SPI
IN1P
EMI
Filter
CLKSEL
DS
ADC1
PGA1
IN1N
IN2P
Oscillator
EMI
Filter
CLK
GPIO1/
RCLK
Control
MUX
CS
SCLK
DIN
DOUT
IN2N
GPIO2/
RCLK
RESP_MODP/
IN3P
DS
ADC2
PGA2
RESP_MODN/
IN3N
RESP
PWDN/
RESET
START
(AVDD + AVSS)/2
Resp Mod
(ADS1292R)
AVSS
RLD
Amplifier
RLDIN/
RLDREF
RLD
OUT
RLD
INV
PGA2N
PGA2P
DGND
Figure 18. Functional Block Diagram
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THEORY OF OPERATION
This section contains details of the ADS1291, ADS1292, and ADS1292R internal functional elements. The
analog blocks are discussed first followed by the digital interface. Blocks implementing ECG-specific functions
are covered in the end.
Throughout this document, fCLK denotes the signal frequency at the CLK pin, tCLK denotes the signal period of the
CLK pin, fDR denotes the output data rate, tDR denotes the output data time period, and fMOD denotes the
frequency at which the modulator samples the input.
EMI FILTER
An RC filter at the input acts as an electromagnetic interference (EMI) filter on channels 1 and 2. The –3-dB filter
bandwidth is approximately 3 MHz.
INPUT MULTIPLEXER
The ADS1291, ADS1292, and ADS1292R input multiplexers are very flexible and provide many configurable
signal-switching options. Figure 19 shows the multiplexer for the ADS1291, ADS1292, and ADS1292R. Note that
TESTP, TESTM, and RLDIN/RLDREF are common to both channels. INP and INN are separate for each of the
three pins. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration.
Switch settings for each channel are selected by writing the appropriate values to the CH1SET or CH2SET
register (see the CH1SET and CH2SET Registers in the Register Map section for details). More details of the
ECG-specific features of the multiplexer are discussed in the Input Multiplexer subsection of the ECG-Specifc
Functions.
Device Noise Measurements
Setting CHnSET[3:0] = 0001 sets the common-mode voltage of (VREFP + VREFN)/2 to both inputs of the
channel. This setting can be used to test the inherent noise of the device in the user system.
Test Signals (TestP and TestN)
Setting CHnSET[3:0] = 0101 provides internally-generated test signals for use in sub-system verification at
power-up. This functionality allows the entire signal chain to be tested out. Although the test signals are similar to
the CAL signals described in the IEC60601-2-51 specification, this feature is not intended for use in compliance
testing.
Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in
the Register Map section for details). INT_TEST enables the test signal and TEST_FREQ controls switching at
the required frequency.
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INT_TEST
Device
MUX1[3:0] = 0101
TESTP
TEMPP
MVDDP
MUX1[3:0] = 0100
MUX1[3:0] = 0011
From LOFFP
MUX1[3:0] = 0000
IN2P
To PGA2_INP
MUX1[3:0] = 0110 or
MUX1[3:0] = 1000
MUX1[3:0] = 0001
MUX1[3:0] = 0010
EMI
Filter
VREFP + VREFN
2
MUX1[3:0] = 0111 or
MUX1[3:0] = 1000
MUX1[3:0] = 0001
MUX1[3:0] = 0000
IN2N
From LOFFN
RLD_REF
MVDDN
TEMPN
INT_TEST
TESTM
RLDIN/
RLDREF
To PGA2_INN
MUX1[3:0] = 0010
MUX1[3:0] = 1001
MUX1[3:0] = 0011
MUX1[3:0] = 0100
MUX1[3:0] = 1001
MUX1[3:0] = 0101
INT_TEST
MUX1[3:0] = 0101
TESTP
TEMPP
MVDDP
MUX1[3:0] = 0100
MUX1[3:0] = 0011
From LOFFP
MUX1[3:0] = 0000
IN1P
To PGA1_INP
MUX1[3:0] = 0111 or
MUX1[3:0] = 1000
MUX1[3:0] = 0001
MUX1[3:0] = 0010
EMI
Filter
VREFP + VREFN
2
MUX1[3:0] = 0110 or
MUX1[3:0] = 1000
MUX1[3:0] = 0001
MUX1[3:0] = 0000
IN1N
From LOFFN
RLD_REF
MVDDN
TEMPN
RESP
MOD
INT_TEST
TESTM
To PGA1_INN
MUX1[3:0] = 0010
MUX1[3:0] = 1001
MUX1[3:0] = 0011
MUX1[3:0] = 0100
MUX1[3:0] = 1001
MUX1[3:0] = 0101
RESP_MODP/IN3P
RESP_MODN/IN3N
NOTE: MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section.
Figure 19. Input Multiplexer Block for Both Channels
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Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P)
In applications where the respiration modulator output is not used, the RESP_MODN/IN3N and
RESP_MODN/IN3P signals can be used as a third multiplexed differential input channel. These inputs can be
multiplexed to either of the ADC channels.
Temperature Sensor (TEMPP, TEMPN)
The ADS1291, ADS1292, and ADS1292R contain an on-chip temperature sensor. This sensor uses two internal
diodes with one diode having a current density 16x that of the other, as shown in Figure 20. The difference in
diode current densities yields a difference in voltage that is proportional to absolute temperature.
Temperature Sensor Monitor
AVDD
1x
2x
To MUX TEMPP
To MUX TEMPN
8x
1x
AVSS
Figure 20. Temperature Sensor Measurement in the Input
As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device
temperature tracks the PCB temperature closely. Note that self-heating of the ADS1291, ADS1292, and
ADS1292R causes a higher reading than the temperature of the surrounding PCB.
The scale factor of Equation 4 converts the temperature reading to °C. Before using this equation, the
temperature reading code must first be scaled to μV.
Temperature (°C) =
Temperature Reading (mV) - 145,300 mV
490 mV/°C
+ 25°C
(4)
Supply Measurements (MVDDP, MVDDN)
Setting CHnSET[3:0] = 0011 sets the channel inputs to different supply voltages of the device. For channel 1
(MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2 (MVDDP – MVDDN) is DVDD/4. Note that to avoid
saturating the PGA while measuring power supplies, the gain must be set to '1'.
Lead-Off Excitation Signals (LoffP, LoffN)
The lead-off excitation signals are fed into the multiplexer before the switches. The comparators that detect the
lead-off condition are also connected to the multiplexer block before the switches. For a detailed description of
the lead-off block, refer to the Lead-Off Detection subsection in the ECG-Specific Functions section.
Auxiliary Single-Ended Input
The RLDIN/RLDREF pin is primarily used for routing the right leg drive signal to any of the electrodes in case the
right leg drive electrode falls off. However, the RLDIN/RLDREF pin can be used as a multiple single-ended input
channel. The signal at the RLDIN/RLDREF pin can be measured with respect to the midsupply [(AVDD +
AVSS)/2]. This measurement is done by setting the channel multiplexer setting MUXn[3:0] to '0010' in the
CH1SET and CH2SET registers.
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ANALOG INPUT
The ADS1291, ADS1292, and ADS1292R analog input is fully differential. Assuming PGA = 1, the differential
input (INP – INN) can span between –VREF to +VREF. Note that the absolute range for INP and INN must be
between AVSS – 0.3 V and AVDD + 0.3 V. Refer to Table 10 for an explanation of the correlation between the
analog input and the digital codes. There are two general methods of driving the ADS1291, ADS1292, and
ADS1292R analog input: single-ended or differential, as shown in Figure 21 and Figure 22. Note that INP and
INN are 180°C out-of-phase in the differential input method. When the input is single-ended, the INN input is held
at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage
and the peak-to-peak amplitude is (common-mode + 1/2 VREF) and (common-mode – 1/2 VREF). When the input
is differential, the common-mode is given by (INP + INN)/2. Both INP and INN inputs swing from (common-mode
+ 1/2 VREF to common-mode – 1/2 VREF). For optimal performance, it is recommended that the ADS1291,
ADS1292, and ADS1292R be used in a differential configuration.
-1/2 VREF to
+1/2 VREF
VREF
Peak-to-Peak
Device
Device
Common
Voltage
Common
Voltage
Single-Ended Input
VREF
Peak-to-Peak
Differential Input
Figure 21. Methods of Driving the ADS1291, ADS1292, and ADS1292R: Single-Ended or Differential
CM + 1/2 VREF
+1/2 VREF
INP
CM Voltage
-1/2 VREF
INN = CM Voltage
CM - 1/2 VREF
t
Single-Ended Inputs
INP
CM + 1/2 VREF
+VREF
CM Voltage
CM - 1/2 VREF
INN
-VREF
t
Differential Inputs
(INP) + (INN)
, Common-Mode Voltage (Single-Ended Mode) = INN.
2
Input Range (Differential Mode) = (AINP - AINN) = 2 VREF.
Common-Mode Voltage (Differential Mode) =
Figure 22. Using the ADS1291, ADS1292, and ADS1292R in Single-Ended and Differential Input Modes
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PGA SETTINGS AND INPUT RANGE
The PGA is a differential input or differential output amplifier, as shown in Figure 23. It has seven gain settings
(1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET
Registers in the Register Map section for details). The ADS1291, ADS1292, and ADS1292R have CMOS inputs
and hence have negligible current noise.
From MuxP
RS = 2 kW
PGA1P
PgaP
CP1
R2
150 kW
R1
60 kW
(for Gain = 6)
R2
150 kW
CFILTER
4.7 nF
RS = 2 kW
PgaN
PGA1N
From MuxN
CP2
Figure 23. PGA Implementation
The PGA resistor string that implements the gain has 360 kΩ of resistance for a gain of 6. This resistance
provides a current path across the outputs of the PGA in the presence of a differential input signal. This current
is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.
The PGA output is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor RS
= 2 kΩ and an external capacitor CFILTER (4.7 nF, typical). This filter acts as an anti-aliasing filter with the –3-dB
bandwidth of 8.4 kHz. The internal RS resistor is accurate to 15% so actual bandwidth will vary. This RC filter
also suppresses the glitch at the PGA output caused by ADC sampling. The minimum value of CEXT that can be
used is 4 nF. A larger value CFILTER capacitor can be used for increased attenuation at higher frequencies for
anti-aliasing purposes. If channel 1 of the ADS1292R is used for respiration measurement, then a 4.7-nF
external capacitor is recommended. The tradeoff is that a larger capacitor value gives degraded THD
performance. See Figure 24 for a diagram explaining the THD versus CFILTER value for a 10-Hz input signal.
−85
THD (dB)
−90
−95
−100
−105
5
10
15
CFILTER (nF)
20
25
G025
Figure 24. THD versus CFILTER Value
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Special care must be taken in PCB layout to minimize the parasitic capacitance CP1/CP2. The absolute value of
these capacitances must be less than 20 pF. Ideally, CFILTER should be placed right at the pins to minimize these
capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is
perfectly matched, the 60-Hz CMRR as a function of this mismatch is given by Equation 5.
Gain
CMRR = 20log
2p ´ 2e3 ´ DCP ´ 60
(5)
where ΔCP = CP1 – CP2
For example, a mismatch of 20 pF with a gain of 6 limits the CMRR to 112 dB. If ΔCP is small, then the CMRR is
limited by the PGA itself and is as specified in the Electrical Characteristics table. The PGA are chopped
internally at either 8, 32, or 64 kSPS, as determined by the CHOP bits (see the RLD_SENS: Right Leg Drive
Sense Selection register, bits[7:6]). The digital decimation filter filters out the chopping ripple in the normal path
so the chopping ripple is not a concern. If PGA output is used for hardware PACE detection, the chopping ripple
must be filtered. First-order filtering is provided by the RC filter at the PGA output. Additional filtering may be
needed to suppress the chopping ripple. If the PGA output is routed to other circuitry, a 20-kΩ series resistance
must be added in the path near the CFILTER capacitor. The routing should be matched to maintain the CMRR
performance.
Input Common-Mode Range
The usable input common-mode range of the front end depends on various parameters, including the maximum
differential input signal, supply voltage, and PGA gain. Equation 6 describes this range.
AVDD - 0.2 -
Gain VMAX_DIFF
2
> CM > AVSS + 0.2 +
Gain VMAX_DIFF
2
where:
VMAX_DIFF = maximum differential signal at the input of the PGA
CM = common-mode range
(6)
For example:
If VDD = 3 V, gain = 6, and VMAX_DIFF = 350 mV
Then 1.25 V < CM < 1.75 V
Input Differential Dynamic Range
The differential (INP – INN) signal range depends on the analog supply and reference used in the system.
Equation 7 shows this range.
VREF
±VREF 2 VREF
Max (INP - INN) <
;
Full-Scale Range =
=
Gain
Gain
Gain
(7)
The 3-V supply, with a reference of 2.42 V and a gain of 6 for ECGs, is optimized for power with a differential
input signal of approximately 300 mV. For higher dynamic range, a 5-V supply with a reference of 4.033 V (set
by the VREF_4V bit of the CONFIG2 register) can be used to increase the differential dynamic range.
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ADC ΔΣ Modulator
Power Spectral Density (dB)
Each channel of the ADS1291, ADS1292, and ADS1292R has a 24-bit ΔΣ ADC. This converter uses a secondorder modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD
= fCLK/4 or fCLK/16, as determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of
128 kHz. As in the case of any ΔΣ modulator, the ADS1291, ADS1292, and ADS1292R noise is shaped until
fMOD/2, as shown in Figure 25. The on-chip digital decimation filters explained in the Digital Decimation Filter
section can be used to filter out the noise at higher frequencies. These on-chip decimation filters also provide
antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of analog antialiasing filters
that are typically needed with nyquist ADCs.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0.001
0.01
0.1
Normalized Frequency (fIN/fMOD)
1
G001
Figure 25. Power Spectral Density (PSD) of a ΔΣ Modulator (4-Bit Quantizer)
DIGITAL DECIMATION FILTER
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection
and ac lead-off detection.
The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can
be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a
global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.
Sinc Filter Stage (sinx/x)
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator,
then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the
converter.
Equation 8 shows the scaled Z-domain transfer function of the sinc filter.
½H(z)½ =
1 - Z- N
3
1 - Z- 1
(8)
The frequency domain transfer function of the sinc filter is shown in Equation 9.
3
sin
½H(f)½ =
Npf
fMOD
N ´ sin
pf
fMOD
where:
N = decimation ratio
(9)
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The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation. Figure 26 shows the sinc filter frequency response and Figure 27
shows the sinc filter roll-off. With a step change at input, the filter takes 3 tDR to settle. After a START signal
rising edge, the filter takes tSETTLE time to give the first data output. The filter settling times at various data rates
are discussed in the START subsection of the SPI Interface section. Figure 28 and Figure 29 show the filter
transfer function until fMOD/2 and fMOD/16, respectively, at different data rates. Figure 30 shows the transfer
function extended until 4 fMOD. It can be seen that the ADS1291, ADS1292, and ADS1292R passband repeats
itself at every fMOD. The input R-C anti-aliasing filters in the system should be chosen such that any interference
in frequencies around multiples of fMOD are attenuated sufficiently.
0
0
-20
-0.5
-40
Gain (dB)
Gain (dB)
-1
-60
-80
-1.5
-2
-100
-2.5
-120
-3
-140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.05
Normalized Frequency (fIN/fDR)
0.2
0.25
0.3
0.35
Figure 27. Sinc Filter Roll-Off
0
0
DR[2:0] = 000
DR[2:0] = 000
-20
DR[2:0] = 110
-40
DR[2:0] = 110
-40
Gain (dB)
Gain (dB)
0.15
Normalized Frequency (fIN/fDR)
Figure 26. Sinc Filter Frequency Response
-20
0.1
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
0.01
Normalized Frequency (fIN/fMOD)
Figure 28. Transfer Function of On-Chip
Decimation Filters Until fMOD/2
10
0.02
0.03
0.04
0.05
0.06
0.07
Normalized Frequency (fIN/fMOD)
Figure 29. Transfer Function of On-Chip
Decimation Filters Until fMOD/16
DR[2:0] = 110
DR[2:0] = 000
-10
Gain (dB)
-30
-50
-70
-90
-110
-130
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency (fIN/fMOD)
Figure 30. Transfer Function of On-Chip Decimation Filters
Until 4fMOD for DR[2:0] = 000 and DR[2:0] = 110
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REFERENCE
Figure 31 shows a simplified block diagram of the ADS1291, ADS1292, and ADS1292R internal reference. The
reference voltage is generated with respect to AVSS. The VREFN pin must always be connected to AVSS.
1 mF
VCAP1
(1)
R1
2.42 V or
4.033 V
Bandgap
VREFP
(1)
R3
10 mF
R2
0.1 mF
(1)
VREFN
AVSS
To ADC Reference Inputs
(1) For VREF = 2.42 V: R1 = 100 kΩ, R2 = 200 kΩ, and R3 = 200 kΩ. For VREF = 4.033 V: R1 = 84 kΩ, R2 = 120 kΩ, and R3 = 280 kΩ.
Figure 31. Internal Reference
The external band-limiting capacitors determine the amount of reference noise contribution. For high-end ECG
systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the
reference noise does not dominate the system noise. When using a 3-V analog supply, the internal reference
must be set to 2.42 V. In case of a 5-V analog supply, the internal reference can be set to 4.033 V by setting the
VREF_4V bit in the CONFIG2 register.
Alternatively, the internal reference buffer can be powered down and VREFP can be applied externally. Figure 32
shows a typical external reference drive circuitry. Power-down is controlled by the PD_REFBUF bit in the
CONFIG2 register. This power-down is also used to share internal references when two devices are cascaded.
By default the device wakes up in external reference mode.
100 kW
10 pF
+5 V
0.1 mF
100 W
+5 V
VIN
10 mF
OUT
22 mF
REF5025
TRIM
To VREFP Pin
OPA211
100 W
0.1 mF
100 mF
22 mF
Figure 32. External Reference Driver
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CLOCK
The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and
external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is
trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the
Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG2 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 9.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that
during power-down the external clock be shut down to save power.
Table 9. CLKSEL Pin and CLK_EN Bit
CLKSEL PIN
CONFIG2.CLK_EN
BIT
CLOCK SOURCE
CLK PIN STATUS
0
X
External clock
Input: external clock
1
0
Internal clock oscillator
3-state
1
1
Internal clock oscillator
Output: internal clock oscillator
The ADS1291, ADS1292, and ADS1292R have the option to choose between two different external clock
frequencies (512 kHz or 2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the
LOFF_STAT register. The modulator must be clocked at 128 kHz, regardless of the external clock frequency.
Figure 33 shows the relationship between the external clock (fCLK) and the modulator clock (fMOD). The default
mode of operation is fCLK = 512 kHz. The higher frequency option has been provided to allow the SPI to run at a
higher speed. SCLK can be only twice the speed of fCLK during a register read or write, see section on sending
multi-byte commands. Having the 2.048 MHz option allows for register read and writes to be performed at SCLK
speeds up to 4.096 MHz.
fCLK
Frequency
Divider
Divide-By-4
fMOD
Frequency
Divider
Divide-By-16
CLK_DIV
(Bit 6 of LOFF_STAT
Register)
Figure 33. Relationship Between External Clock (fCLK) and Modulator Clock (fMOD)
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DATA FORMAT
The ADS1291, ADS1292, and ADS1292R outputs 24 bits of data per channel in binary twos complement format,
MSB first. The LSB has a weight of VREF/(223 – 1). A positive full-scale input produces an output code of
7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes
for signals exceeding full-scale. Table 10 summarizes ideal output codes for different input signals. All 24 bits
toggle when the analog input is at positive or negative full-scale.
Table 10. Ideal Output Code versus Input Signal
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE (1)
≥ VREF
7FFFFFh
23
+VREF/(2
(1)
– 1)
000001h
0
000000h
–VREF/(223 – 1)
FFFFFFh
≤ –VREF (223/223 – 1)
800000h
Excludes effects of noise, linearity, offset, and gain error.
SPI INTERFACE
The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads
conversion data, reads and writes registers, and controls ADS1291, ADS1292, and ADS1292R operation. The
DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are
available.
Chip Select (CS)
CS selects the ADS1291, ADS1292, and ADS1292R for SPI communication. CS must remain low for the entire
duration of the serial communication. After the serial communication is finished, always wait four or more tCLK
cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored,
and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of
whether CS is high or low.
Serial Clock (SCLK)
SCLK is the serial peripheral interface (SPI) serial clock. SCLK is used to shift commands in and shift data out
from the device. The serial clock features a Schmitt-triggered input and clocks data on the DIN and DOUT pins
into and out of the ADS1291, ADS1292, and ADS1292R. Even though the input has hysteresis, it is
recommended to keep SCLK as clean as possible to prevent glitches from accidentally forcing a clock event. The
absolute maximum SCLK limit is specified in the Serial Interface Timing table. When shifting in commands with
SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so could result in the device
serial interface being placed into an unknown state, requiring CS to be taken high to recover.
For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of
bits of resolution, and output data rate. (For multiple cascaded devices, see the Cascade Mode subsection of the
Multiple Device Configuration section.) The minimum speed can be calculated with Equation 10.
tDR - 4 tCLK
tSCLK <
NBITS ´ NCHANNELS + 24
(10)
For example, if the ADS1292R is used in a 500-SPS mode (2 channels, 24-bit resolution), the minimum SCLK
speed is approximately 36 kHz.
Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for
data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation
applies if data must be read in between two consecutive DRDY signals. Equation 10 assumes that there are no
other commands issued in between data captures. SCLK can only be twice the speed of fCLK during register
reads and writes. For faster SPI interface, use fCLK = 2.048 MHz and set the CLK_DIV register bit (in the
LOFF_STAT register) to '1'.
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Data Input (DIN)
The data input pin (DIN) is used along with SCLK to communicate with the ADS1291, ADS1292, and ADS1292R
(opcode commands and register data). The device latches data on DIN on the SCLK falling edge.
Data Output (DOUT)
The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1291,
ADS1292, and ADS1292R. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a highimpedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for
more details), the DOUT output line also indicates when new data are available. This feature can be used to
minimize the number of connections between the device and the system controller.
Figure 34 shows the data output protocol for the ADS1292 and ADS1292R.
DRDY
CS
SCLK
DOUT
STAT
CH1
CH2
24-Bit
24-Bit
24-Bit
DIN
Figure 34. SPI Bus Data Output for the ADS1292 and ADS1292R (Two Channels)
Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command (see the
RDATAC: Read Data Continuous section) can be used to set the device in a mode to read the data continuously
without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read
just one data output from the device (see the SPI Command Definitions section for more details). The conversion
data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK
rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read
operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS1292R, the number of data outputs is (24 status bits + 24 bits × 2 channels) = 72 bits. The format of
the 24 status bits is: (1100 + LOFF_STAT[4:0] + GPIO[1:0] + 13 '0's). The data format for each channel data is
twos complement, MSB first. When channels are powered down using user register settings, the corresponding
channel output is set to '0'. However, the sequence of channel outputs remains the same.
The ADS1291, ADS1292, and ADS1292R also provide a multiple readback feature. Data can be read out
multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte.
Data Ready (DRDY)
DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the
data ready signal. The behavior of DRDY is determined by whether the device is in RDATAC mode or the
RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and
RDATA: Read Data subsections of the SPI Command Definitions section for further details).
When reading data with the RDATA command, the read operation can overlap the occurrence of the next DRDY
without data corruption.
The START pin or the START command is used to place the device either in normal data capture mode or pulse
data capture mode.
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Figure 35 shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an
ADS1291, ADS1292, and ADS1292R with a selected data rate that gives 24-bit resolution). DOUT is latched out
at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first
SCLK falling edge regardless of the status of CS and regardless of whether data are being retrieved from the
device or a command is being sent through the DIN pin.
DRDY
Bit 71
DOUT
Bit 70
Bit 69
SCLK
Figure 35. DRDY with Data Retrieval (CS = 0)
GPIO
The ADS1291, ADS1292, and ADS1292R have a total of two general-purpose digital input/output (GPIO) pins
available in the normal mode of operation. The digital I/O pins are individually configurable as either inputs or as
outputs through the GPIOC bits register. The GPIOD bits in the GPIO register control the level of the pins. When
reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs
or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect.
When configured as an output, a write to the GPIOD bit sets the output value.
If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on
or after a reset. Figure 36 shows the GPIO port structure. The pins should be shorted to DGND with a series
resistor if not used.
GPIO Data (read)
GPIO Pin
GPIO Data (write)
GPIO Control
Figure 36. GPIO Port Pin
Power-Down and Reset (PWDN/RESET)
The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 29 fMOD clock cycles, the device
is powered down. The implementation is such that the device is always reset when PWDN/RESET makes a
transition from high to low. If the device is powered down it is reset first and then if 210 clock elapses it is
powered down. Hence, all registers must be rewritten after power up.
There are two methods to reset the ADS1291, ADS1292, and ADS1292R: pull the PWDN/RESET pin low, or
send the RESET opcode command. When using the PWDN/RESET pin, take it low to force a reset. Make sure
to follow the minimum pulse width timing specifications before taking the PWDN/RESET pin back high. The
RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 tCLK
cycles to complete initialization of the configuration registers to the default states and start the conversion cycle.
Note that an internal RESET is automatically issued to the digital filter whenever the CONFIG1, RESP1, and
RESP2 registers are set to a new value with a WREG command.
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START
The START pin must be set high or the START command sent to begin conversions. When START is low or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1291, ADS1292, and
ADS1292R feature two modes to control conversion: continuous mode and single-shot mode. The mode is
selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is
used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for
more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that
data are ready. Figure 37 shows the timing diagram and Table 11 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Refer to Table 10 for the settling time as a function of tMOD. Note that when START is held high and
there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are
available on the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is
recommended to add one tMOD cycle delay before issuing SCLK to retrieve data.
tSETTLE
START Pin
or
START Opcode
DIN
tDR
4/fCLK
DRDY
(1) Settling time uncertainty is one tMOD cycle.
Figure 37. Settling Time
Table 11. Settling Time for Different Data Rates
(1)
(2)
30
DR[2:0]
SETTLING TIME (1)
UNIT (2)
000
4100
tMOD
001
2052
tMOD
010
1028
tMOD
011
516
tMOD
100
260
tMOD
101
132
tMOD
110
68
tMOD
111
—
—
Settling time uncertainty is one tMOD cycle.
tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1.
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Continuous Mode
Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in
Figure 38, the DRDY output goes high when conversions are started and goes low when data are ready.
Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to
complete. Figure 39 and Table 12 show the required DRDY timing to the START pin and the START and STOP
opcode commands when controlling conversions in this mode. To keep the converter running continuously, the
START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the
START signal is pulsed or a STOP command must be issued, followed by a START command. This conversion
mode is ideal for applications that require a fixed continuous stream of conversions results.
START Pin
or
or
(1)
DIN
(1)
START
Opcode
STOP
Opcode
tDR
tSETTLE
DRDY
(1)
START and STOP opcode commands take effect on the seventh SCLK falling edge.
Figure 38. Continuous Conversion Mode
tSDSU
DRDY and DOUT
tDSHD
START Pin
or
STOP Opcode
(1)
STOP(1)
STOP(1)
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
Figure 39. START to DRDY Timing
Table 12. Timing Characteristics for Figure 39 (1)
SYMBOL
(1)
MIN
UNIT
tSDSU
START pin low or STOP opcode to DRDY setup time
to halt further conversions
DESCRIPTION
8
tMOD
tDSHD
START pin low or STOP opcode to complete current
conversion
8
tMOD
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
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Single-Shot Mode
The single-shot mode is enabled by setting the SINGLE_SHOT bit in the CONFIG1 register to '1'. In single-shot
mode, the ADS1291, ADS1292, and ADS1292R perform a single conversion when the START pin is taken high
or when the START opcode command is sent. As seen in Figure 39, when a conversion is complete, DRDY goes
low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY
remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START
opcode again. When switching from continuous mode to pulse mode, make sure the START signal is pulsed or
issue a STOP command followed by a START command.
This conversion mode is provided for applications that require non-standard or non-continuous data rates.
Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data
rate by a factor of four. Note that this mode leaves the system more susceptible to aliasing effects, requiring
more complex analog anti-aliasing filters at the inputs. Loading on the host processor increases because it must
toggle the START pin or send a START command to initiate a new conversion cycle.
START
tSETTLE
4/fCLK
Data Updating
4/fCLK
DRDY
Figure 40. DRDY with No Data Retrieval in Single-Shot Mode
MULTIPLE DEVICE CONFIGURATION
The ADS1291, ADS1292, and ADS1292R are designed to provide configuration flexibility when multiple devices
are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one
additional chip select signal per device, multiple devices can be connected together. The number of signals
needed to interface n devices is 3 + n.
The right leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices
subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,
one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL
pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This
master device clock is used as the external clock source for the other devices.
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When using multiple devices, the devices can be synchronized with the START signal. The delay from START to
the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more
details on the settling times). Figure 41 shows the behavior of two devices when synchronized with the START
signal.
Device1
START
START1
CLK
DRDY
DRDY1
CLK
Device2
START2
DRDY
DRDY2
CLK
CLK
Note 1
START
DRDY1
Note 2
DRDY2
(1) Start pulse must be at least one tMOD cycle wide.
(2) Settling time number uncertainty is one tMOD cycle.
Figure 41. Synchronizing Multiple Converters
Standard Mode
Figure 42 shows a configuration with two devices cascaded together. One of the devices is an ADS1292R (twochannel with RESP) and the other is an ADS1292 (two-channel). Together, they create a system with four
channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected
by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure
allows the other device to take control of the DOUT bus.
START
(1)
START
CLK
CLK
DRDY
CS
INT
GPO0
GPO1
ADS1292
(Device 0)
SCLK
SCLK
DIN
MOSI
DOUT
MISO
Host Processor
START
CLK
DRDY
CS
SCLK
ADS1292R
(Device 1)
DIN
DOUT
Figure 42. Multiple Device Configurations
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SPI COMMAND DEFINITIONS
The ADS1291, ADS1292, and ADS1292R provide flexible configuration control. The opcode commands
summarized in Table 13 control and configure the ADS1291, ADS1292, and ADS1292R operation. The opcode
commands are stand-alone, except for the register read and register write operations that require a second
command byte plus data. CS can be taken high or held low between opcode commands but must stay low for
the entire command operation (especially for multi-byte commands). System opcode commands and the RDATA
command are decoded by the ADS1291, ADS1292, and ADS1292R on the seventh SCLK falling edge. The
register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing
requirements when pulling CS high after issuing a command.
Table 13. Command Definitions
COMMAND
DESCRIPTION
FIRST BYTE
SECOND BYTE
System Commands
WAKEUP
Wake-up from standby mode
0000 0010 (02h)
STANDBY
Enter standby mode
0000 0100 (04h)
RESET
Reset the device
0000 0110 (06h)
START
Start or restart (synchronize) conversions
0000 1000 (08h)
STOP
Stop conversion
0000 1010 (0Ah)
OFFSETCAL
Channel offset calibration
0001 1010 (1Ah)
Data Read Commands
RDATAC
Enable Read Data Continuous mode.
This mode is the default mode at power-up. (1)
0001 0000 (10h)
SDATAC
Stop Read Data Continuously mode
0001 0001 (11h)
RDATA
Read data by command; supports multiple read back.
0001 0010 (12h)
Register Read Commands
RREG
WREG
(1)
(2)
Read n nnnn registers starting at address r rrrr
001r rrrr (2xh) (2)
000n nnnn (2)
Write n nnnn registers starting at address r rrrr
(2)
000n nnnn (2)
010r rrrr (4xh)
When in RDATAC mode, the RREG command is ignored.
n nnnn = number of registers to be read or written – 1. For example, to read or write three registers, set n nnnn = 0 (0010). r rrrr =
starting register address for read and write opcodes.
WAKEUP: Exit STANDBY Mode
This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the
SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical
Characteristics for details). There are no restrictions on the SCLK rate for this command and it can be
issued any time. Any following command must be sent after 4 tCLK cycles.
STANDBY: Enter STANDBY Mode
This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the
reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are
no restrictions on the SCLK rate for this command and it can be issued any time. Do not send any other
command other than the wakeup command after the device enters the standby mode.
RESET: Reset Registers to Default Values
This command resets the digital filter cycle and returns all register settings to the default values. See the Reset
(RESET) subsection of the SPI Interface section for more details. There are no restrictions on the SCLK rate
for this command and it can be issued any time. It takes 9 fMOD cycles to execute the RESET command.
Avoid sending any commands during this time.
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START: Start Conversions
This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the
START command is immediately followed by a STOP command then have a gap of 4 tCLK cycles between them.
When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.
(See the START subsection of the SPI Interface section for more details.) There are no restrictions on the
SCLK rate for this command and it can be issued any time.
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it
can be issued any time.
OFFSETCAL: Channel Offset Calibration
This command is used to cancel the channel offset. The CALIB_ON bit in the RESP2 register must be set to '1'
before issuing this command. OFFSETCAL must be executed every time there is a change in the PGA gain
settings.
RDATAC: Read Data Continuous
This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the device default mode; the device defaults to this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 tCLK cycles. RDATAC timing is shown in Figure 43. As Figure 43 shows,
there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. To
retrieve data from the device after RDATAC command is issued, make sure either the START pin is high or the
START command is issued. Figure 43 shows the recommended way to use the RDATAC command. RDATAC is
ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to
be re-configured.
START
DRDY
(1)
tUPDATE
CS
SCLK
RDATAC Opcode
DIN
Hi-Z
DOUT
Status Register + 2-Channel Data
Next Data
(1) tUPDATE = 4 x tCLK. Do not read data during this time.
Figure 43. RDATAC Usage
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SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 tCLK cycles.
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 44
shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type
systems where register setting must be read or changed often between conversion cycles.
START
DRDY
CS
SCLK
RDATA Opcode
DIN
RDATA Opcode
Hi-Z
DOUT
Status Register+ 8-Channel Data (216 Bits)
Figure 44. RDATA Usage
Sending Multi-Byte Commands
The ADS1291, ADS1292, and ADS1292R serial interface decodes commands in bytes and requires 4 tCLK cycles
to decode and execute. Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of
one byte (or opcode) and the next.
Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be
inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs.
Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to
multiple bytes.
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RREG: Read From Register
This opcode reads register data. The Register Read command is a two-byte opcode followed by the output of the
register data. The first byte contains the command opcode and the register address. The second byte of the
opcode specifies the number of registers to read – 1.
First opcode byte: 001r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1.
The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 45. When
the device is in read data continuous mode it is necessary to issue a SDATAC command before the RREG
command can be issued. The RREG command can be issued at any time. However, because this command is a
multi-byte command, there are restrictions on the SCLK rate depending on the way the SCLKs are issued. See
the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for
the entire command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA
DOUT
REG DATA + 1
Figure 45. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001)
WREG: Write to Register
This opcode writes register data. The Register Write command is a two-byte opcode followed by the input of the
register data. The first byte contains the command opcode and the register address.
The second byte of the opcode specifies the number of registers to write – 1.
First opcode byte: 010r rrrr, where r rrrr is the starting register address.
Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1.
After the opcode bytes, the register data follows (in MSB-first format), as shown in Figure 46. The WREG
command can be issued at any time. However, because this command is a multi-byte command, there are
restrictions on the SCLK rate depending on the way the SCLKs are issued. See the Serial Clock (SCLK)
subsection of the SPI Interface section for more details. Note that CS must be low for the entire command.
CS
1
9
17
25
SCLK
DIN
OPCODE 1
OPCODE 2
REG DATA 1
REG DATA 2
DOUT
Figure 46. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001)
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
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REGISTER MAP
Table 14 describes the various ADS1291, ADS1292, and ADS1292R registers.
Table 14. Register Assignments
ADDRESS
RESET
VALUE
(Hex)
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
XX
REV_ID7
REV_ID6
REV_ID5
1
0
0
REV_ID1
REV_ID0
Device Settings (Read-Only Registers)
00h
ID
Global Settings Across Channels
01h
CONFIG1
02
SINGLE_
SHOT
0
0
0
0
DR2
DR1
DR0
02h
CONFIG2
80
1
PDB_LOFF_
COMP
PDB_REFBUF
VREF_4V
CLK_EN
0
INT_TEST
TEST_FREQ
03h
LOFF
10
COMP_TH2
COMP_TH1
COMP_TH0
1
ILEAD_OFF1
ILEAD_OFF0
0
FLEAD_OFF
Channel-Specific Settings
04h
CH1SET
00
PD1
GAIN1_2
GAIN1_1
GAIN1_0
MUX1_3
MUX1_2
MUX1_1
MUX1_0
05h
CH2SET
00
PD2
GAIN2_2
GAIN2_1
GAIN2_0
MUX2_3
MUX2_2
MUX2_1
MUX2_0
06h
RLD_SENS
00
CHOP1
CHOP0
PDB_RLD
RLD_LOFF_
SENS
RLD2N
RLD2P
RLD1N
RLD1P
07h
LOFF_SENS
00
0
0
FLIP2
FLIP1
LOFF2N
LOFF2P
LOFF1N
LOFF1P
08h
LOFF_STAT
00
0
CLK_DIV
0
RLD_STAT
IN2N_OFF
IN2P_OFF
IN1N_OFF
IN1P_OFF
RESP_CTRL
GPIO and Other Registers
09h
RESP1
00
RESP_
DEMOD_EN1
RESP_MOD_
EN
RESP_PH3
RESP_PH2
RESP_PH1
RESP_PH0
1
0Ah
RESP2
02
CALIB_ON
0
0
0
0
RESP_FREQ
RLDREF_INT
1
0Bh
GPIO
0C
0
0
0
0
GPIOC2
GPIOC1
GPIOD2
GPIOD1
User Register Description
ID: ID Control Register (Factory-Programmed, Read-Only)
Address = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REV_ID7
REV_ID6
REV_ID5
1
0
0
REV_ID1
REV_ID0
This register is programmed during device manufacture to indicate device characteristics.
Bits[7:5]
REV_ID[7:5]: Revision identification
000 = Reserved
001 = Reserved
010 = ADS1x9x device
011 = ADS1292R device
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
Bit 4
Reads high
Bits[3:2]
Reads low
Bits[1:0]
REV_ID[1:0]: Revision identification
00
01
10
11
38
= ADS1191
= ADS1192
= ADS1291
= ADS1292 and ADS1292R
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
CONFIG1: Configuration Register 1
Address = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SINGLE_SHOT
0
0
0
0
DR2
DR1
DR0
This register configures each ADC channel sample rate.
Bit 7
SINGLE_SHOT: Single-shot conversion
This bit sets the conversion mode
0 = Continuous conversion mode (default)
1 = Single-shot mode
Bits[6:3]
Must be set to '0'
Bits[2:0]
DR[2:0]: Channel oversampling ratio
These bits determine the oversampling ratio of both channel 1 and channel 2.
(1)
DATA RATE (1)
BIT
OVERSAMPLING RATIO
000
fMOD/1024
125 SPS
001
fMOD/512
250 SPS
010
fMOD/256
500 SPS (default)
011
fMOD/128
1 kSPS
100
fMOD/64
2 kSPS
101
fMOD/32
4 kSPS
110
fMOD/16
8 kSPS
111
Do not use
Do not use
fCLK = 512 kHz and CLK_DIV = 0 or fCLK = 2.048 MHz and CLK_DIV = 1.
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ADS1291
ADS1292
ADS1292R
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CONFIG2: Configuration Register 2
Address = 02h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
PDB_LOFF_
COMP
PDB_REFBUF
VREF_4V
CLK_EN
0
INT_TEST
TEST_FREQ
This register configures the test signal, clock, reference, and LOFF buffer.
Bit 7
Must be set to '1'
Bit 6
PDB_LOFF_COMP: Lead-off comparator power-down
This bit powers down the lead-off comparators.
0 = Lead-off comparators disabled (default)
1 = Lead-off comparators enabled
Bit 5
PDB_REFBUF: Reference buffer power-down
This bit powers down the internal reference buffer so that the external reference can be used.
0 = Reference buffer is powered down (default)
1 = Reference buffer is enabled
Bit 4
VREF_4V: Enables 4-V reference
This bit chooses between 2.42-V and 4.033-V reference.
0 = 2.42-V reference (default)
1 = 4.033-V reference
Bit 3
CLK_EN: CLK connection
This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bit 2
Must be set to '0'
Bit 1
INT_TEST: Test signal selection
This bit determines whether the test signal is turned on or off.
0 = Off (default)
1 = On; amplitude = ±(VREFP – VREFN)/2400
Bit 0
TEST_FREQ: Test signal frequency
This bit determines the test signal frequency.
0 = At dc (default)
1 = Square wave at 1 Hz
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
LOFF: Lead-Off Control Register
Address = 03h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COMP_TH2
COMP_TH1
COMP_TH0
1
ILEAD_OFF1
ILEAD_OFF0
0
FLEAD_OFF
This register configures the lead-off detection operation.
Bits[7:5]
COMP_TH[2:0]: Lead-off comparator threshold
These bits determine the lead-off comparator threshold. See the Lead-Off Detection subsection of the ECG-Specific
Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4
Must be set to '1'
Bits[3:2]
ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 6 nA (default)
01 = 22 nA
10 = 6 µA
11 = 22 µA
Bit 1
Must be set to '0'
Bit 0
FLEAD_OFF: Lead-off frequency
This bit selects ac or dc lead-off.
0 = At dc lead-off detect (default)
1 = At ac lead-off detect at fDR/4 (500 Hz for an 2-kHz output rate)
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ADS1292
ADS1292R
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CH1SET: Channel 1 Settings
Address = 04h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD1
GAIN1_2
GAIN1_1
GAIN1_0
MUX1_3
MUX1_2
MUX1_1
MUX1_0
This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer
section for details.
Bit 7
PD1: Channel 1 power-down
0 = Normal operation (default)
1 = Channel 1 power-down (1)
Bits[6:4]
GAIN1[2:0]: Channel 1 PGA gain setting
These bits determine the PGA gain setting for channel 1.
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12
Bits[3:0]
MUX1[3:0]: Channel 1 input selection
These bits determine the channel 1 input selection.
0000 = Normal electrode input (default)
0001 = Input shorted (for offset measurements)
0010 = RLD_MEASURE
0011 = MVDD (2) for supply measurement
0100 = Temperature sensor
0101 = Test signal
0110 = RLD_DRP (positive input is connected to RLDIN)
0111 = RLD_DRM (negative input is connected to RLDIN)
1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)
1001 = Route IN3P and IN3N to channel 1 inputs
1010 = Reserved
(1)
(2)
42
When powering down channel 1, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001.
For channel 1, (MVDDP – MVDDN) is [0.5(AVDD + AVSS)]; for channel 2, (MVDDP – MVDDN) is DVDD/4. Note that to avoid saturating
the PGA while measuring power supplies, the gain must be set to '1'.
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
CH2SET: Channel 2 Settings
Address = 05h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD2
GAIN2_2
GAIN2_1
GAIN2_0
MUX2_3
MUX2_2
MUX2_1
MUX2_0
This register configures the power mode, PGA gain, and multiplexer settings channels. See the Input Multiplexer
section for details.
Bit 7
PD2: Channel 2 power-down
0 = Normal operation (default)
1 = Channel 2 power-down (1)
Bits[6:4]
GAIN2[2:0]: Channel 2 PGA gain setting
These bits determine the PGA gain setting for channel 2.
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12
Bits[3:0]
MUX2[3:0]: Channel 2 input selection
These bits determine the channel 2 input selection.
0000 = Normal electrode input (default)
0001 = Input shorted (for offset measurements)
0010 = RLD_MEASURE
0011 = VDD/2 for supply measurement
0100 = Temperature sensor
0101 = Test signal
0110 = RLD_DRP (positive input is connected to RLDIN)
0111 = RLD_DRM (negative input is connected to RLDIN)
1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)
1001 = Route IN3P and IN3N to channel 2 inputs
1010 = Reserved
(1)
When powering down channel 2 and for ADS1291, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001.
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ADS1291
ADS1292
ADS1292R
SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
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RLD_SENS: Right Leg Drive Sense Selection
Address = 06h
BIT 7
CHOP1
BIT 6
CHOP0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDB_RLD
RLD_LOFF_
SENS
RLD2N
RLD2P
RLD1N
RLD1P
This register controls the selection of the positive and negative signals from each channel for right leg drive
derivation. See the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for
details.
Bits[7:6]
CHOP[1:0]: Chop frequency
These bits determine PGA chop frequency
00 = fMOD/16
01 = Reserved
10 = fMOD/2
11 = fMOD/4
Bit 5
PDB_RLD: RLD buffer power
This bit determines the RLD buffer power state.
0 = RLD buffer is powered down (default)
1 = RLD buffer is enabled
Bit 4
RLD_LOFF_SENSE: RLD lead-off sense function
This bit enables the RLD lead-off sense function.
0 = RLD lead-off sense is disabled (default)
1 = RLD lead-off sense is enabled
Bit 3
RLD2N: Channel 2 RLD negative inputs
This bit controls the selection of negative inputs from channel 2 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN2N
Bit 2
RLD2P: Channel 2 RLD positive inputs
This bit controls the selection of positive inputs from channel 2 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN2P
Bit 1
RLD1N: Channel 1 RLD negative inputs
This bit controls the selection of negative inputs from channel 1 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN1N
Bit 0
RLD1P: Channel 1 RLD positive inputs
This bit controls the selection of positive inputs from channel 1 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN1P
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
LOFF_SENS: Lead-Off Sense Selection
Address = 07h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
FLIP2
FLIP1
LOFF2N
LOFF2P
LOFF1N
LOFF1P
This register selects the positive and negative side from each channel for lead-off detection. See the Lead-Off
Detection subsection of the ECG-Specific Functions section for details. Note that the LOFF_STAT register bits
should be ignored if the corresponding LOFF_SENS bits are set to '1'.
Bits[7:6]
Must be set to '0'
Bit 5
FLIP2: Current direction selection
This bit controls the direction of the current used for lead-off derivation for channel 2.
0 = Disabled (default)
1 = Enabled
Bit 4
FLIP1: Current direction selection
This bit controls the direction of the current used for lead-off derivation for channel 1.
0 = Disabled (default)
1 = Enabled
Bit 3
LOFF2N: Channel 2 lead-off detection negative inputs
This bit controls the selection of negative input from channel 2 for lead-off detection.
0 = Disabled (default)
1 = Enabled
Bit 2
LOFF2P: Channel 2 lead-off detection positive inputs
This bit controls the selection of positive input from channel 2 for lead-off detection.
0 = Disabled (default)
1 = Enabled
Bit 1
LOFF1N: Channel 1 lead-off detection negative inputs
This bit controls the selection of negative input from channel 1 for lead-off detection.
0 = Disabled (default)
1 = Enabled
Bit 0
LOFF1P: Channel 1 lead-off detection positive inputs
This bit controls the selection of positive input from channel 1 for lead-off detection.
0 = Disabled (default)
1 = Enabled
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ADS1292R
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LOFF_STAT: Lead-Off Status
Address = 08h
BIT 7
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RLD_STAT
(read only)
IN2N_OFF
(read only)
IN2P_OFF
(read only)
IN1N_OFF
(read only)
IN1P_OFF
(read only)
CLK_DIV
This register stores the status of whether the positive or negative electrode on each channel is on or off. See the
Lead-Off Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STAT values
if the corresponding LOFF_SENS bits are not set to '1'.
'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENS bits[3:0] are '0', the LOFF_STAT bits should be
ignored.
Bit 7
Must be set to '0'
Bit 6
CLK_DIV : Clock divider selection
This bit sets the modultar divider ratio between fCLK and fMOD. Two external clock values are supported: 512 kHz and
2.048 MHz.
0 = fCLK and fMOD/4 (default, use when fCLK = 512 kHz)
1 = fCLK and fMOD/16 (use when fCLK = 2.048 MHz)
Bit 5
Must be set to '0'
Bit 4
RLD_STAT: RLD lead-off status
This bit determines the status of RLD.
0 = RLD is connected (default)
1 = RLD is not connected
Bit 3
IN2N_OFF: Channel 2 negative electrode status
This bit determines if the channel 2 negative electrode is connected or not.
0 = Connected (default)
1 = Not connected
Bit 2
IN2P_OFF: Channel 2 positive electrode status
This bit determines if the channel 2 positive electrode is connected or not.
0 = Connected (default)
1 = Not connected
Bit 1
IN1N_OFF: Channel 1 negative electrode status
This bit determines if the channel 1 negative electrode is connected or not.
0 = Connected (default)
1 = Not connected
Bit 0
IN1P_OFF: Channel 1 positive electrode status
This bit determines if the channel 1 positive electrode is connected or not.
0 = Connected (default)
1 = Not connected
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
RESP1: Respiration Control Register 1
Address = 09h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESP_
DEMOD_EN1
RESP_MOD_
EN
RESP_PH3
RESP_PH2
RESP_PH1
RESP_PH0
1
RESP_CTRL
This register controls the respiration functionality. This register applies to the ADS1292R version only. For the
ADS1291 and ADS1292 devices, 02h must be written to the RESP1 register.
Bit 7
RESP_DEMOD_EN1: Enables respiration demodulation circuitry
This bit enables and disables the demodulation circuitry on channel 1.
0 = RESP demodulation circuitry turned off (default)
1 = RESP demodulation circuitry turned on
Bit 6
RESP_MOD_EN: Enables respiration modulation circuitry
This bit enables and disables the modulation circuitry on channel 1.
0 = RESP modulation circuitry turned off (default)
1 = RESP modulation circuitry turned on
Bits[5:2]
RESP_PH[3:0]: Respiration phase (1)
These bits control the phase of the respiration demodulation control signal.
(1)
RESP_PH[3:0]
RESP_CLK = 32kHz
RESP_CLK = 64 kHz
0000
0° (default)
0° (default)
0001
11.25°
22.5°
0010
22.5°
45°
0011
33.75°
67.5°
0100
45°
90°
0101
56.25°
112.5°
0110
67.5°
135°
0111
78.75°
157.5°
1000
90°
Not available
1001
101.25°
Not available
1010
112.5°
Not available
1011
123.75°
Not available
1100
135°
Not available
1101
146.25°
Not available
1110
157.5°
Not available
1111
168.75°
Not available
The RESP_PH3 bit is ignored when RESP_CLK = 64 kHz.
Bit 1
Must be set to '1'
Bit 0
RESP_CTRL: Respiration control
This bit sets the mode of the respiration circuitry.
0 = Internal respiration with internal clock
1 = Internal respiration with external clock
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RESP2: Respiration Control Register 2
Address = 0Ah
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CALIB_ON
0
0
0
0
RESP_FREQ
RLDREF_INT
1
This register controls the respiration and calibration functionality.
Bit 7
CALIB_ON: Calibration on
This bit is used to enable offset calibration.
0 = Off (default)
1 = On
Bits[6:3]
Must be '0'
Bit 2
RESP_FREQ: Respiration control frequency (ADS1292R only)
This bit controls the respiration control frequency when RESP_CTRL = 0. This bit must be written with '1' for the ADS1291
and ADS1292.
0 = 32 kHz (default)
1 = 64 kHz
Bit 1
RLDREF_INT: RLDREF signal
This bit determines the RLDREF signal source.
0 = RLDREF signal fed externally
1 = RLDREF signal (AVDD – AVSS)/2 generated internally (default)
Bit 0
Must be set to '1'
GPIO: General-Purpose I/O Register
Address = 0Bh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
GPIOC2
GPIOC1
GPIOD2
GPIOD1
This register controls the GPIO pins.
Bits[7:4]
Must be '0'
Bits[3:2]
GPIOC[2:1]: GPIO 1 and 2 control
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)
Bits[1:0]
GPIOD[2:1]: GPIO 1 and 2 data
These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the
GPIOD has no effect. GPIO is not available in certain respiration modes.
48
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SBAS502A – DECEMBER 2011 – REVISED MARCH 2012
ECG-SPECIFIC FUNCTIONS
INPUT MULTIPLEXER (REROUTING THE RIGHT LEG DRIVE SIGNAL)
The input multiplexer has ECG-specific functions for the right leg drive signal. The RLD signal is available at the
RLDOUT pin once the appropriate channels are selected for RLD derivation, feedback elements are installed
external to the chip, and the loop is closed. This signal can be fed after filtering or fed directly into the RLDIN pin,
as shown in Figure 47. This RLDIN signal can be multiplexed into any one of the input electrodes by setting the
MUX bits of the appropriate channel set registers to '0110' for P-side or '0111' for N-side. Figure 47 shows the
RLD signal generated from channel 1 and routed to the N-side of channel 2. This feature can be used to
dynamically change the electrode that is used as the reference signal to drive the patient body. Note that the
corresponding channel cannot be used and can be powered down.
RLD1P = 1
IN1P
EMI
Filter
PGA1
RLD1N = 1
MUX1[3:0] = 0000
IN1N
RLD2P = 0
IN2P
EMI
Filter
PGA2
RLD2N = 0
MUX1[3:0] = 0111
IN2N
RLDREF_INT = 1
(AVDD + AVSS)
MUX
2
RLDREF_INT = 0
RLD_AMP
ADS1292R
RLDIN/RLDREF
RLDOUT
Filter or
Feedthrough
1M
RLDINV
(1)
1.5 nF(1)
(1) Typical values for example only.
Figure 47. Example RLDOUT Signal Configured to be Routed to IN2N
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ADS1292
ADS1292R
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Input Multiplexer (Measuring the Right Leg Drive Signal)
The RLDOUT signal can also be routed to a channel (that is not used for the calculation of RLD) for
measurement. Figure 48 shows the register settings to route the RLDIN signal to channel 2. The measurement is
done with respect to the voltage (AVDD + AVSS)/2. This feature is useful for debugging purposes during product
development.
RLD1P = 1
IN1P
EMI
Filter
PGA1
RLD1N = 1
MUX1[3:0] = 0000
IN1N
RLD2P = 0
IN2P
EMI
Filter
PGA2
MUX1[3:0] = 0010
IN2N
RLD2N = 0
RLDREF_INT = 1
(AVDD + AVSS)
2
MUX
MUX1[3:0] = 0010
RLDREF_INT = 0
RLD_AMP
Device
RLDIN/RLDREF
RLDOUT
1M
Filter or
Feedthrough
RLDINV
(1)
1.5 nF(1)
(1) Typical values for example only.
Figure 48. RLDOUT Signal Configured to be Read Back by Channel 2
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LEAD-OFF DETECTION
Patient electrode impedances are known to decay over time. It is necessary to continuously monitor these
electrode connections to verify a suitable connection is present. The ADS1291, ADS1292, and ADS1292R leadoff detection functional block provides significant flexibility to the user to choose from various lead-off detection
strategies. Though called lead-off detection, this is in fact an electrode-off detection.
The basic principle is to inject an excitation signal and measure the response to find out if the electrode is off. As
shown in the lead-off detection functional block diagram in Figure 49, this circuit provides two different methods
of determining the state of the patient electrode. The methods differ in the frequency content of the excitation
signal. Lead-off can be selectively done on a per channel basis using the LOFF_SENS register. Also, the internal
excitation circuitry can be disabled and just the sensing circuitry can be enabled.
Patient
Skin,
Electrode Contact
Model
Patient
Protection
Resistor
47 nF
51 k
IN1P_OFF/
IN2P_OFF
30 k
VINP
51 k
EMI
Filter
30 k
LOFF1P/
LOFF2P
47 nF
47 nF
51 k
VINN
PGA
LOFF1N/
LOFF2N
AVDD
AVSS
To ADC
IN1N_OFF/
IN2N_OFF
4-Bit
DAC
COMP_TH[2:0]
30 k
RLD OUT
NOTE: The RP value must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the
relevant specification the latest revision of IEC 60601).
Figure 49. Lead-Off Detection
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DC Lead-Off
In this method, the lead-off excitation is with a dc signal. The dc excitation signal can be chosen from either an
external pull-up or pull-down resistor or a current source or sink, as shown in Figure 50. One side of the channel
is pulled to supply and the other side is pulled to ground. The internal current source and current sink can be
swapped by setting the FLIP1 and FLIP2 bits in the LOFF_SENS register. In case of current source or sink, the
magnitude of the current can be set by using the ILEAD_OFF[1:0] bits in the LOFF register. The current source
or sink gives larger input impedance compared to the 10-MΩ pull-up or pull-down resistor.
AVDD
AVDD
Device
Device
10 MW
INP
INP
PGA
INN
PGA
INN
10 MW
a) External Pull-Up/Pull-Down Resistors
b) Input Current Source
Figure 50. DC Lead-Off Excitation Options
Sensing of the response can be done either by looking at the digital output code from the device or by monitoring
the input voltages with an on-chip comparator. If either of the electrodes is off, the pull-up resistors and the pulldown resistors saturate the channel. By looking at the output code it can be determined that either the P-side or
the N-side is off. To pinpoint which one is off, the comparators must be used. The input voltage is also monitored
using a comparator and a 4-bit digital-to-analog converter (DAC) whose levels are set by the COMP_TH[2:0] bits
in the LOFF register. The output of the comparators are stored in the LOFF_STAT register. These two registers
are available as a part of the output data stream. (See the Data Output Protocol (DOUT) subsection of the SPI
Interface section.) If dc lead-off is not used, the lead-off comparators can be powered down by setting the
PD_LOFF_COMP bit in the CONFIG2 register.
An example procedure to turn on dc lead-off is given in the Lead-Off subsection of the Quick-Start Guide section.
AC Lead-Off
In this method, an out-of-band ac signal is used for excitation. The ac signal is generated by alternatively
providing an internal current source and current sink at the input with a fixed frequency. The excitation frequency
is a function of the output data rate and is fDR/4. This out-of-band excitation signal is passed through the channel
and measured at the output.
Sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the
output. The ac excitation signals are introduced at a frequency that is above the band of interest, generating an
out-of-band differential signal that can be filtered out separately and processed. By measuring the magnitude of
the excitation signal at the output spectrum, the lead-off status can be calculated. Therefore, the ac lead-off
detection can be accomplished simultaneously with the ECG signal acquisition.
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RLD Lead-Off
The ADS1291, ADS1292, and ADS1292R provide two modes for determining whether the RLD is correctly
connected:
• RLD lead-off detection during normal operation
• RLD lead-off detection during power-up
The following sections provide details of the two modes of operation.
RLD Lead-Off Detection During Normal Operation
During normal operation, the ADS1291, ADS1292, and ADS1292R RLD lead-off at power-up function cannot be
used because it is necessary to power off the RLD amplifier.
RLD Lead-Off Detection At Power-Up
This feature is included in the ADS1291, ADS1292, and ADS1292R for use in determining whether the right leg
electrode is suitably connected. At power-up, the ADS1291, ADS1292, and ADS1292R provides a procedure to
determine the RLD electrode connection status using a current sink, as shown in Figure 51. The reference level
of the comparator is set to determine the acceptable RLD impedance threshold.
Patient
Skin,
Electrode Contact
Model
Patient
Protection
Resistor
To ADC input (through VREF
connection to any of the channels).
47 nF
51 k
RLD_STAT
30 k
RLD_LOFF_SENS
AVSS
NOTE: The RP value must be selected in order to be below the maximum allowable current flow into a patient (in accordance with the
relevant specification the latest revision of IEC 60601).
Figure 51. RLD Lead-Off Detection at Power-Up
When the RLD amplifier is powered on, the current source has no function. Only the comparator can be used to
sense the voltage at the output of the RLD amplifier. The comparator thresholds are set by the same LOFF[7:5]
bits used to set the thresholds for other negative inputs.
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Right Leg Drive (RLD DC Bias Circuit)
The right leg drive (RLD) circuitry is used as a means to counter the common-mode interference in a ECG
system as a result of power lines and other sources, including fluorescent lights. The RLD circuit senses the
common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an
inverted common-mode signal. The negative feedback loop restricts the common-mode movement to a narrow
range, depending on the loop gain. Stabilizing the entire loop is specific to the individual user system based on
the various poles in the loop. The ADS1291, ADS1292, and ADS1292R integrates the muxes to select the
channel and an operational amplifier. All the amplifier terminals are available at the pins, allowing the user to
choose the components for the feedback loop. The circuit shown in Figure 52 shows the overall functional
connectivity for the RLD bias circuit.
The reference voltage for the right leg drive can be chosen to be internally generated (AVDD + AVSS)/2 or it can
be provided externally with a resistive divider. The selection of an internal versus external reference voltage for
the RLD loop is defined by writing the appropriate value to the RLDREF_INT bit in the RESP2 register.
From
MUX1P
RLD1P
400 k
PGA1P
150 k
RLD2P
400 k
PGA2P
60 k
150 k
From
MUX1N
From
MUX2P
150 k
60 k
400 k
PGA1N
RLD1N
150 k
400 k
PGA2N
From
MUX2N
RLD2N
RLDINV
(1)
CEXT
1.5 nF
(1)
REXT
1M
RLDOUT
RLD
Amp
(AVDD + AVSS)
2
RLDREF_INT
RLDIN/RLDREF
RLDREF_INT
To MUX
(1) Typical values.
Figure 52. RLD Channel Selection
If the RLD function is not used, the amplifier can be powered down using the PDB_RLD bit. This bit is also used
in daisy-chain mode to power-down all but one of the RLD amplifiers.
The functionality of the RLDIN pin is explained in the Input Multiplexer section.
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RLD Configuration with Multiple Devices
RLDIN/
RLDREF
RLD
OUT
Power-Down
(AVDD+AVSS)
2
RLDIN/
RLDREF
RLD
OUT
Device N
VA1
RLDINV
VA2
To Input MUX
(AVDD+AVSS)
2
To Input MUX
To Input MUX
Figure 53 shows multiple devices connected to an RLD.
Device 2
VA1
VA2
RLDINV
RLDIN/
RLDREF
(AVDD+AVSS)
2
Device 1
VA1
RLD
OUT
REXT
VA2
RLDINV
CEXT
Figure 53. RLD Connection for Multiple Devices
PACE DETECT
The ADS1291 and ADS1292 provide flexibility for PACE detection by using an external hardware. The external
hardware approach is made possible by bringing out the output of the PGA at pins: PGA1P, PGA1N and PGA2P,
PGA2N.
External hardware circuitry can be used to detect the presence of the pulse. The output of the PACE detection
logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the
SPI port and loaded 2 tCLKs before DRDY goes low.
When in pace detection mode, the chopping ripple can interfere with pace detect in hardware. It is therefore
preffered to chop thee PGA at a higher frequency (32 kHz or 64 kHz). The RC filter at the PGA output,
suppresses this ripple to a reasonable level. Additionally, suppression can be obtained with an additional RC
stage. The trade-off with chopping the PGA at a higher frequency is an increase in the input bias current.
Figure 6 shows bias current versus input voltage for three different chop frequencies.
RESPIRATION
The ADS1292R provides two options for respiration: internal respiration with external clock and internal
respiration with internal clock, as shown in Table 15.
Table 15. Respiration Control
RESP_CTRL
DESCRIPTION
0
Internal respiration with internal clock
1
Internal respiration with external clock
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Internal Respiration Circuitry with Internal Clock (ADS1292R)
This mode is set by RESP_CTRL = 0. Figure 54 shows a block diagram of the internal respiration circuitry. The
internal modulation and demodulator circuitry can be selectively used. The modulation block is controlled by the
RESP_MOD_EN bit and the demodulation block is controlled by the RESP_DEMOD_EN bit. The modulation
signal is a square wave of the magnitude VREFP – AVSS. When the internal modulation circuitry is used, the
output of the modulation circuitry is available at the RESP_MODP and RESP_MODM pins of the device. This
availability allows custom filtering to be added to the square wave modulation signal. In this mode, GPIO1 and
GPIO2 can be used for other purposes. The modulation frequency of the respiration circuit is set by the
RESP_FREQ bits.
CLK (512 kHz)
CLK GEN
RESP_FREQ
RESP_MOD_EN
RESP_MODP
VREFP
RESP_CTRL
Modulation
Block
RESP_MODN
RESP_MOD_EN
AVSS
I/O
RESP_CTRL
RESP_MOD_CLK
I/O
GPIO1
I/O
GPIO2
IN1P
EMI
Filter
VBIAS
MUX
Ch1
PGA
Ch1
ADC
Demodulation
Block
IN1N
RESP_DEMOD_EN
PGA1P
PGA1N
47 nF
Figure 54. Internal Respiration Timing Diagram
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Internal Respiration Circuitry with External Clock (ADS1292R)
This mode is set by RESP_CTRL = 1. In this mode GPIO1 and GPIO2 are automatically configured as inputs.
GPIO1 and GPIO2 cannot be used for other purposes. The signals must be provided as described in Figure 55.
(Modulation Clock)
GPIO1
tPHASE
tBLKDLY
(Blocking Signal)
GPIO2
Figure 55. Internal Respiration (RESP_CTRL = 1) Timing Diagram
Table 16. Timing Characteristics for Figure 55 (1)
1.65 V ≤ DVDD ≤ 3.6 V
PARAMETER
DESCRIPTION
tPHASE
Respiration phase delay
tBLKDLY
Modulation clock rising edge to XOR signal
(1)
MIN
TYP
0
MAX
168.75
0
5
UNIT
Degrees
ns
Specifications apply from –40°C to +85°C.
ADS1292R Application
The ADS1292R channel 1 with respiration enabled mode cannot be used to acquire ECG signals. If the right arm
(RA) and left arm (LA) leads are intended to measure respiration and ECG signals, the two leads can be wired
into channel 1 for respiration and channel 2 for ECG signals, as shown in Figure 56.
R6
10 MW
AVDD
R5
10 MW
AVSS
C2
0.1 mF
IN1P
C1
2.2 nF
C3
2.2 nF
ADS1292R
R2
40.2 kW
RESP_MODP
Left Arm Lead
IN2P
IN2N
RESP_MODN
Right Arm Lead
C6
0.1 mF
R4
10 MW
C4
2.2 nF
R1
40.2 kW
C5
2.2 nF
AVDD
R3
10 MW
IN1N
AVSS
NOTE: Patient and input protection circuitry not shown.
Figure 56. Typical Respiration Circuitry
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Figure 57 shows a respiration test circuit. Figure 58 and Figure 59 plot noise on channel 1 for the ADS1292R as
baseline impedance, gain, and phase are swept. The x-axis is the baseline impedance, normalized to a 30-µA
modulation current (as shown in Equation 11).
10
ADS1292R
RESP_MODP
RBASELINE = 2.21 kW
RESP_MODN
R2
40.2 kW
Channel 1 Noise (µV)
IN1P
R2
40.2 kW
9
Data Rate = 125Hz
Respiration Modulation Clock = 32kHz
8
7
6
5
4
PGA=3, PHASE = 112.5
PGA = 4, PHASE = 112.5
PGA = 3, PHASE = 135
PGA = 4, PHASE = 135
3
2
1
2.2
IN1N
Channel 1 Noise (µV)
Figure 57. Respiration Noise Test Circuit
5.2
8.2
11.2
14.2
Normalized Baseline Respiration Impedance (kΩ)
G058
Figure 58. Channel 1 Noise versus Impedance for
32-kHz Modulation Clock and Phase
(BW = 32 Hz, Respiration Modulation Clock = 32
kHz)
15
Data Rate = 125Hz
14
Respiration Modulation Clock = 64kHz
13
12
11
10
9
8
7
6
5
PGA=2, PHASE = 135
4
PGA = 3, PHASE = 135
3
PGA = 2, PHASE = 157.5
2
PGA = 3, PHASE = 157.5
1
2.2
7.2
12.2
15
Normalized Baseline Respiration Impedance (kΩ)
G059
Figure 59. Channel 1 Noise versus Impedance for 64-kHz Modulation Clock and Phase
(BW = 32 Hz, Respiration Modulation Clock = 64 kHz)
RACTUAL ´ IACTUAL
RNORMALIZED =
30 mA
where:
RACTUAL is the baseline body impedance,
IACTUAL is the modulation current, as calculated by (VREFP – AVSS) divided by the impedance of the
modulation circuit.
(11)
For example, if modulation frequency = 32 kHz, RACTUAL = 3 kΩ, IACTUAL = 50 µA, and RNORMALIZED = (3 kΩ × 50
µA)/29 µA = 5.1 kΩ.
Referring to Figure 58 and Figure 59, it can be noted that gain = 4 and phase = 112.5° yield the best
performance at 4.6 µVPP. Low-pass filtering this signal with a high-order 2-Hz cutoff can reduce the noise to less
than 1200 nVPP. The impedance resolution is 1200 nVPP/30 µA = 40 mΩ.
When the modulation frequency is 32 kHz, gains of 3 and 4 and phase of 112.5° and 135° are recommended.
When the modulation frequency is 64 kHz, gains of 2 and 3 and phase of 135° and 157° are recommended for
best performance.
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QUICK-START GUIDE
PCB LAYOUT
Power Supplies and Grounding
The ADS1291, ADS1292, and ADS1292R have two supplies: AVDD and DVDD. AVDD should be as quiet as
possible. AVDD provides the supply to the charge pump block and has transients at fCLK. It is important to
eliminate noise from AVDD that is non-synchronous with the ADS1291, ADS1292, and ADS1292R operation.
Each ADS1291, ADS1292, and ADS1292R supply should be bypassed with 10-μF and a 0.1-μF solid ceramic
capacitors. It is recommended that placement of the digital circuits (such as the DSP, microcontrollers, and
FPGAs) in the system is done such that the return currents on those devices do not cross the ADS1291,
ADS1292, and ADS1292R analog return path. The ADS1291, ADS1292, and ADS1292R can be powered from
unipolar or bipolar supplies.
The capacitors used for decoupling can be of the surface-mount, low-cost, low-profile multi-layer ceramic type. In
most cases the VCAP1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected
to high or low frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class
1 capacitor (for example, C0G or NPO) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, X8R,
and such) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming
from the capacitor. When using internal reference, noise on the VCAP1 node results in performance degradation.
Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies
Figure 60 illustrates the ADS1291, ADS1292, and ADS1292R connected to a unipolar supply. In this example,
the analog supply (AVDD) is referenced to analog ground (AVSS) and the digital supply (DVDD) is referenced to
digital ground (DGND).
+1.8 V
+3 V
0.1 mF
1 mF
1 mF
0.1 mF
DVDD
AVDD
VREFP
VREFN
4.7 nF
0.1 mF
10 mF
PGA1N
(1)
VCAP1
PGA1P
VCAP2
Device
PGA2N
4.7 nF
PGA2P
AVSS
DGND
1 mF
1 mF
NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.
(1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF.
Figure 60. Single-Supply Operation
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Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies
Figure 61 illustrates the ADS1291, ADS1292, and ADS1292R connected to a bipolar supply. In this example, the
analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog
return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND).
+1.5 V
+1.8 V
1 mF
0.1 mF
0.1 mF
1 mF
DVDD
AVDD
VREFP
VREFN
4.7 nF
(1)
10 mF
0.1 mF
PGA1N
-1.5 V
PGA1P
PGA2N
VCAP1
Device
VCAP2
4.7 nF
PGA2P
AVSS
DGND
1 mF
1 mF
1 mF
0.1 mF
-1.5 V
NOTE: Place the capacitors for supply, reference, VCAP1, and VCAP2 as close to the package as possible.
(1) When using the ADS1292R and the channel 1 respiration function, this capacitor must be 47 nF.
Figure 61. Bipolar Supply Operation
Shielding Analog Signal Paths
As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS.
These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should
be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding.
Leakage currents between the PCB traces can exceed the ADS1291, ADS1292, and ADS1292R input bias
current if shielding is not implemented. Digital signals should be kept as far as possible from the analog input
signals on the PCB.
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POWER-UP SEQUENCING
Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals
should remain low until the power supplies have stabilized, as shown in Figure 62. At this time, begin supplying
the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET,
the configuration register must be programmed, see the CONFIG1: Configuration Register 1 subsection of the
Register Map section for details. The power-up sequence timing is shown in Table 17.
tPOR
Power Supplies
tRST
RESET
18 tCLK
Start Using the Device
Figure 62. Power-Up Timing Diagram
Table 17. Power-Up Sequence Timing
SYMBOL
DESCRIPTION
tPOR
Wait after power-up until reset
tRST
Reset low width
MIN
TYP
MAX
UNIT
212
tMOD
1
tMOD
SETTING THE DEVICE FOR BASIC DATA CAPTURE
This section outlines the procedure to configure the device in a basic state and capture data. This procedure is
intended to put the device in a data sheet condition to check if the device is working properly in the user's
system. It is recommended that this procedure be followed initially to get familiar with the device settings. Once
this procedure has been verified, the device can be configured as needed. For details on the timings for
commands refer to the appropriate sections in the data sheet. Also, some sample programming codes are added
for the ECG-specific functions. Figure 63 details a flow chart of the configuration procedure.
Lead-Off
Sample code to set dc lead-off with current source or sink resistors on all channels
WREG LOFF 10h // Comparator threshold at 95% and 5%, current source or sink resistor // DC lead-off
WREG CONFIG2 E0h // Turn-on dc lead-off comparators
WREG LOFF_SENS 0Fh // Turn on both P- and N-side of all channels for lead-off sensing
Observe the status bits of the output data stream to monitor lead-off status.
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Analog/Digital Power-Up
Set CLKSEL Pin = 0 and
Provide External Clock
fCLK = 512 kHz
Yes
// Follow Power-Up Sequencing
External
Clock
No
Set CLKSEL Pin = 1
and Wait for Oscillator
to Wake Up
// If START is Tied High, After This Step
// DRDY Toggles at fMOD/256
Set PWDN/RESET = 1
Wait for 1 s for
Power-On Reset
// Delay for Power-On Reset and Oscillator Start-Up
Issue Reset Pulse,
Wait for 18 tCLKs
Set PDB_REFBUF = 1
and Wait for Internal
Reference To Settle
// Activate DUT
//CS can be Either Tied Permanently Low
// Or Selectively Pulled Low Before Sending
// Commands or Reading/Sending Data From/To Device
Send SDATAC
Command
// Device Wakes Up in RDATAC Mode, so Send
// SDATAC Command so Registers can be Written
SDATAC
External Reference
// If Using Internal Reference, Send This Command
-- WREG CONFIG2 A0h
No
Yes
Write Certain Registers,
Including Input Short
// DRATE = 500 SPS
WREG CONFIG1 02h
// Set All Channels to Input Short
WREG CHnSET 01h
Set START = 1
// Activate Conversion
// After This Point DRDY Should Toggle at
// fCLK Review
RDATAC
// Put the Device Back in RDATAC Mode
RDATAC
Capture Data and
Check Noise
Set Test Signals
Capture Data and
Test Signals
// Look for DRDY and Issue 24 + n
24 SCLKs
// Activate a (1 mV VREF/2.4) Square-Wave Test Signal
// On All Channels
SDATAC
WREG CONFIG2 A3h
WREG CHnSET 05h
RDATAC
// Look for DRDY and Issue 24 + n
24 SCLKs
Figure 63. Initial Flow at Power-Up
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2011) to Revision A
Page
•
Changed device graphic ....................................................................................................................................................... 1
•
Changed device status from Mixed Status to Production Data ............................................................................................ 1
•
Changed second Features bullet .......................................................................................................................................... 1
•
Updated Family and Ordering Information table ................................................................................................................... 2
•
Moved ADS1292R to production status ................................................................................................................................ 2
•
Deleted footnote 2 from Family and Ordering Information table .......................................................................................... 2
•
Changed values of AVDD to AVSS and DVDD to DGND rows in Absolute Maximum Ratings table .................................. 2
•
Changed Operating temperature range parameter in Absolute Maximum Ratings table ..................................................... 2
•
Changed DC Channel Performance, INL parameter test conditions in Electrical Characteristics table .............................. 3
•
Changed AC Channel Performance, SNR and THD parameters test conditions in Electrical Characteristics table ........... 3
•
Added third Channel Performance, THD parameter row to Electrical Characteristics table ................................................ 3
•
Added Digital Filter section to Electrical Characteristics table .............................................................................................. 4
•
Deleted Right Leg Drive Amplifier, Quiescent power consumption parameter test condition from Electrical
Characteristics table ............................................................................................................................................................. 4
•
Changed Respiration, Impedance measurement noise parameter test conditions in Electrical Characteristics table ......... 4
•
Changed Respiration, Maximum modulator current parameter in Electrical Characteristics table ...................................... 4
•
Changed Power-Supply Requirements, Digital supply parameter in Electrical Characteristics table .................................. 5
•
Changed first IDVDD Supply Current, Normal mode parameter test conditions in Electrical Characteristics table ................ 6
•
Changed 3-V Power Dissipation, Quiescent power dissipation, per channel parameter typical specifications in
Electrical Characteristics table .............................................................................................................................................. 6
•
Added CFILTER to Typical Characteristics conditions ........................................................................................................... 13
•
Updated Figure 5 ................................................................................................................................................................ 13
•
Updated Figure 9 and Figure 12 ......................................................................................................................................... 14
•
Added CFILTER to Typical Characteristics conditions ........................................................................................................... 14
•
Added CFILTER to Typical Characteristics conditions ........................................................................................................... 15
•
Changed description of CHnSET setting in Supply Measurements (MVDDP, MVDDN) section ....................................... 19
•
Changed second paragraph of PGA Settings and Input Range section ............................................................................ 21
•
Changed description of PD_REFBUF bit in the Reference section ................................................................................... 25
•
Updated second column title in Table 9 ............................................................................................................................. 26
•
Updated Figure 41 .............................................................................................................................................................. 33
•
Updated description of DOUT and DRDY in RDATAC: Read Data Continuous section ................................................... 35
•
Updated RLD_STAT in address 08h of Table 14 ............................................................................................................... 38
•
Changed description of bit 1 in CONFIG2: Configuration Register 2 ................................................................................. 40
•
Changed descriptions of bits[3:0] in CH2SET: Channel 2 Settings .................................................................................... 43
•
Updated Figure 54 .............................................................................................................................................................. 56
•
Added description of Figure 55, Figure 55, and Table 16 to Internal Respiration Circuitry with External Clock
(ADS1292R) section ........................................................................................................................................................... 57
•
Added ADS1292R Application section ............................................................................................................................... 57
•
Updated Figure 58 and Figure 59 ....................................................................................................................................... 58
•
Updated Figure 60 and added footnote 1 ........................................................................................................................... 59
•
Updated Figure 61 and added footnote 1 ........................................................................................................................... 60
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS1291 ADS1292 ADS1292R
Submit Documentation Feedback
63
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
ADS1291IPBS
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1291IPBSR
ACTIVE
TQFP
PBS
32
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1292IPBS
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1292IPBSR
ACTIVE
TQFP
PBS
32
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1292RIPBS
ACTIVE
TQFP
PBS
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS1292RIPBSR
ACTIVE
TQFP
PBS
32
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Mar-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS1291IPBSR
TQFP
PBS
32
1000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
ADS1292IPBSR
TQFP
PBS
32
1000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
ADS1292RIPBSR
TQFP
PBS
32
1000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1291IPBSR
TQFP
PBS
32
1000
346.0
346.0
33.0
ADS1292IPBSR
TQFP
PBS
32
1000
346.0
346.0
33.0
ADS1292RIPBSR
TQFP
PBS
32
1000
346.0
346.0
33.0
Pack Materials-Page 2
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