AD AD9216 10-bit, 65/80/105 msps dual a/d converter Datasheet

10-Bit, 65/80/105 MSPS
Dual A/D Converter
AD9216
Preliminary Technical Data
AVDD
VIN+_A
VIN- _A
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-todigital converter. It features dual high performance sample-and
hold amplifiers and an integrated voltage reference. The
AD9216 uses a multistage differential pipelined architecture
with output error correction logic to provide 10-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 105 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well
beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 (all speed grades) and can compensate for wide
variations in the clock duty cycle, allowing the converters to
maintain excellent performance. The digital output data is
presented in either straight binary or twos complement format.
Out-of-range signals indicate an overflow condition, whic h can
be used with the most significant bit to determine low or high
overflow.
ADC
10
REFT_A
REFB_A
VREF
SENSE
AGND
10
Clock
Duty Cycle
Stabilizer
+ 0.5V
-
Mode
Control
REFT_B
REFB_B
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
3G, Radio Point-to-Point, LMDS, MMDS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
SHA
AGND
Output Mux/
Buffers
Integrated Dual 10-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist, AD9216-105)
SFDR = 75 dBc (to Nyquist, AD9216-105)
Low Power: 280mW at 105MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 75dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
specified over the industrial temperature range (–40°C to
+85°C).
VIN+_B
SHA
VIN-_B
ADC
AD9216
10
Output Mux/
Buffers
FEATURES
OTR_A
D9A-D0A
OEB_A
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
OTR_B
10
D10B -D0B
OEB_B
DRVDD DRGND
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
1.
Pin compatible with AD9238, dual 12-bit
20/40/65MSPS ADC and AD9248, dual 14-bit
20/40/65MSPS ADC.
2.
Speed grade options off 105 MSPS, 80 MSPS, and
65 MSPS allow flexibility between power, cost, and
performance to suit an application.
3.
Low power consumption:
AD9216-105: 105 MSPS = 280 mW
AD9216-80: 80 MSPS = 238 mW
AD9216-65: 65 MSPS = 215mW
4.
The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential
operation.
5.
Typical channel isolation of 75 dB @ fIN = 10 MHz.
6.
The clock duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
Fabricated on an advanced CMOS process, the AD9216 is
available in a space saving 64-lead LFCSP (9x9) and is
Rev. PrD_6/15/2004
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD9216
Preliminary Technical Data
Theory of Operation............................................................ 13
TABLE OF CONTENTS
General Description .............................................................. 1
Analog Input ....................................................................... 13
Product Highlights ................................................................ 1
Clock Input and Considerations .......................................... 15
DC Specifications (Continued) ............................................. 4
Power Dissipation and Standby Mode ................................ 15
Switching Specifications ....................................................... 4
Digital Outputs.................................................................... 15
AC Specifications ................................................................. 5
Timing ................................................................................ 16
Absolute Maximum Ratings ..................................................... 7
Data Format ........................................................................ 16
ESD Caution ......................................................................... 7
Voltage Reference............................................................... 17
Terminology........................................................................ 10
Evaluation Board Diagrams (TBD) ........................................ 19
Typical Performance CharacteristiC PLOTS (TBD).............. 12
Outline Dimensions ................................................................ 20
Equivalent Circuits ................................................................. 13
REVISION HISTORY
PrA: Initial Version
PrB: included specification tables, ordering guide, package and pin configuration and Theory of operation sections.
PrC: Corrected pin configuration figure (Fig3) pin naming errors , updated supply spec, corrected timing diagram and latency.
PrD: Removed 120MSPS Grade, Updated DCS,OEB_B pin descriptions, updated input referred noise, Demux Timing Diagram needs
updating
Rev. PrD
Page 2 of 20
6/15/2004
Preliminary Technical Data
AD9216
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parameter
Temp
Test
Level
AD9216BCP-65/80
Min Typ
Max
AD9216BCP-105
Min Typ
Max
Unit
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
1
Gain Error
2
Differential Nonlinearity (DNL)
Full
VI
10
10
Bits
Full
Full
Full
Full
25°C
Full
25°C
VI
VI
IV
V
I
V
I
10
Full
Full
V
V
±15
±30
Full
Full
Full
Full
VI
V
V
V
±5
0.8
±2.5
0.1
25°C
25°C
V
V
0.8
0.4
0.8
0.4
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
2
7
1
2
2
7
V p-p
V p-p
pF
k?
Full
Full
IV
IV
Full
Full
Full
V
V
V
TBD/TBD
TBD/TBD
±0.01
TBD
TBD
±0.01
mA
mA
% FSR
Full
Full
Full
V
VI
V
TBD/TBD
215/238
1/1
TBD
280
1
mW
mW
mW
Full
Full
V
V
±0.1
±0.05
±0.1
±0.05
% FSR
% FSR
2
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
1
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
3
Input Capacitance
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
2
IAVDD
2
IDRVDD
PSRR
POWER CONSUMPTION
4
DC Input
2
Sine Wave Input
5
Standby Power
MATCHING CHARACTERISTICS
Offset Error
Gain Error
10
±0.3
±1.0
±0.5
±0.5
±0.5
±0.5
2.7
2.25
3.0
2.5
±TBD
±TBD
±0.30
±1.0
±0.5
±0.5
±0.5
±0.5
±TBD
±TBD
±TBD
±TBD
±TBD
±TBD
±15
±30
±35
3.3
3.6
±5
0.8
±2.5
0.1
2.7
2.25
3.0
2.5
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
±35
3.3
3.6
mV
mV
mV
mV
V
V
1
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
2
3
Rev. PrD
Page 3 of 20
6/15/2004
AD9216
Preliminary Technical Data
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parame ter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
1
LOGIC OUTPUTS
DRVDD = 2.5V
High Level Output
Voltage
Low Level Output Voltage
Test
Level
AD9216BCP-65/80
Min
Typ
Max
AD9216BCP-105
Min
Typ
Max
Unit
Temp
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2.0
2.0
V
V
µA
µA
pF
Full
IV
2.45
Full
IV
0.8
+10
+10
- 10
- 10
0.8
+10
+10
- 10
- 10
2
2
2.45
V
0.05
0.05
V
1
Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Parameter
SWITCHING PERFORMANCE
Max Conversion Rate
Min Conversion Rate
CLK Period
1
CLK Pulsewidth High
1
CLK Pulsewidth Low
DATA OUTPUT PARAMETER
2
Output Delay (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (tJ)
3
Wake-Up Time
OUT-OF-RANGE RECOVERY
TIME
Temp
Test
Level
AD9216BCP-65/80
Min
Typ Max
AD9216BCP-105
Min Typ Max
Full
Full
Full
Full
Full
VI
V
V
V
V
65/80
105
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
2.0
1
MSPS
MSPS
ns
ns
ns
1
15.4/12.2
6.2/5
6.2/5
9.5
4.2
4.2
4.8
6
1.0
0.5
2.5
2
6.0
2.0
4.8
6
1.0
0.5
2.5
2
Unit
6.0
ns
Cycles
ns
ps rms
ms
1
The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx).
Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
2
Specifications subject to change without notice.
N
N+1
N+2
N–1
tA
ANALOG
INPUT
N+8
N+3
N+7
N+4
N+6
N+5
CLK
DATA
OUT
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N-1
t
N
N+1
PD
Figure 2. Timing Diagram
Rev. PrD
Page 4 of 20
6/15/2004
Preliminary Technical Data
AD9216
AC SPECIFICATIONS
Table 4. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parameter
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO
fINPUT = 2.4 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
fINPUT = 100 MHz
TOTAL HARMONIC DISTORTION
fINPUT = 2.4 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
fINPUT = 100 MHz
WORST HARMONIC (2nd or 3rd)
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
SPURIOUS FREE DYNAMIC RANGE
fINPUT = 2.4 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 69 MHz
Rev. PrD
Temp
Test
Level
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
V
IV
V
IV
V
IV
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
V
IV
V
IV
V
IV
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
V
I
V
I
V
I
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
AD9216BCP-65/80
Min Typ
Max
TBD
AD9216BCP-105
Min Typ
Max
58
58
58
57
TBD
TBD
56
58
58
58
57
TBD
TBD
55
9.4
9.4
9.4
9.3
8.9
V
V
I
V
I
V
I
V
- 70.0
- 69.0
- 70.0
- 70.0
Full
Full
Full
V
V
V
- 75.0
25°C
Full
25°C
Full
25°C
Full
25°C
V
V
I
V
I
V
I
75.0
75.0
75.0
TBD
- 69.0
- 68.0
- 67.0
- 66.0
- 74.0
75.0
TBD
Page 5 of 20
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
9.3
9.1
9.1
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
57
56
56
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
57
57
57
74.0
74.0
Unit
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
6/15/2004
AD9216
fINPUT = 100 MHz
CROSSTALK
Preliminary Technical Data
25°C
Full
V
V
- 80.0
- 80.0
dBc
dB
Specifications subject to change without notice.
Rev. PrD
Page 6 of 20
6/15/2004
Preliminary Technical Data
AD9216
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9216 Absolute Maximum Ratings 1
Parameter
Pin Name
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF,
OEB, DFS
VINA, VINB
VREF
SENSE
REFB, REFT
PDWN
2
ENVIRONMENTAL
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
With Respect To
Rating
Min
Max
Unit
AGND
DRGND
DRGND
DRVDD
DRGND
AGND
AGND
AGND
AGND
AGND
AGND
- 0.3
- 0.3
- 0.3
- 3.9
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
- 45
+85
+150
+300
+150
°C
°C
°C
°C
- 65
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (64-lead LQFP); ? ?JA = 54°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS
I
100% production tested.
II
100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although this
product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Rev. PrD
Page 7 of 20
6/15/2004
AD9216
Preliminary Technical Data
Table 6. ORDERING GUIDE
Model
Temperature Range
Package Description
AD9216BCP-65
AD9216BCPZ-80
AD9216BCPZ-105
AD9216BCPZRL7-65
AD9216BCPZRL7-80
AD9216BCPZRL7105
AD9216-65PCB
AD9216-40PCB
AD9216-105PCB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
64-Lead Lead Frame Chip Scale Package (LFCSP)
64-Lead Lead Frame Chip Scale Package (LFCSP)
64-Lead Lead Frame Chip Scale Package (LFCSP)
64-Lead Lead Frame Chip Scale Package (LFCSP)
64-Lead Lead Frame Chip Scale Package (LFCSP)
64-Lead Lead Frame Chip Scale Package (LFCSP)
Package Option
AGND
VIN+_A
VIN-_A
AGND
AVDD
REFT_A
REFB_A
DRVDD
D5_A
D4_A
D3_A
52
51
50
49
D6_A
DRGND
OEB_A
OTR_A
59
58
54
53
MUX_SELECT
PDWN_A
57 D9_A (MSB)
56 D8_A
55 D7_A
SHARED_REF
61
60
64
AVDD
CLK_A
63
62
Evaluation Board with AD9216BCPZ-65
Evaluation Board with AD9216BCPZ-80
Evaluation Board with AD9216BCPZ-105
1
48
2
3
47
46
4
45
5
6
44
43
AD9216
64 Lead for
LF-CSP
TOP VIEW
(Not to Scale)
7
8
VREF
SENSE 9
REFB_B 10
REFT_B 11
42
41
40
39
38
12
13
37
36
14
VIN+_B 15
AGND 16
35
34
D0_A
DNC
DNC
DNC
DNC
DRVDD
DRGND
OTR_B
D9_B (MSB)
D8_B
D7_B
D6_B
D5_B
31
32
D4_B
D3_B
29
30
D1_B
D2_B
27
28
DRGND
DRVDD
26
DNC
D0_B
24
25
DNC
DNC
22
23
20
21
PDWN_B
OEB_B
DNC
AVDD
CLK_B
19
33
17
18
AGND
VIN-_B
DCS
DFS
AVDD
D2_A
D1_A
Figure 3. Pin Configuration
Rev. PrD
Page 8 of 20
6/15/2004
Preliminary Technical Data
AD9216
Table 7. Pin Function Descriptions
Pin
Number
Mnemonic
Description
2
3
15
14
6
7
11
10
8
9
18
63
19
20
21
60
22
59
46–51, 5457
27, 30-38
Analog Input Pin (+) for Channel A
Analog Input Pin (- ) for Channel A
Analog Input Pin (+) for Channel B
Analog Input Pin (- ) for Channel B
Differential Reference (+) for Channel A
Differential Reference (- ) for Channel A
Differential Reference (+) for Channel B
Differential Reference (- ) for Channel B
Voltage Reference Input/Output
Reference Mode Selection
Clock Input Pin for Channel B
Clock Input Pin for Channel A
Enable Duty Cycle Stabilizer (DCS) Mode ( Tie to AVDD to enable)
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)
Power-Down Function Selection for Channel B (Active High)
Power-Down Function Selection for Channel A (Active High)
Output Enable Bit for Channel B (Low Setting Enables Channel B Output Data Bus)
Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
Channel A Data Output Bits
39
58
62
VIN+_A
VIN–_A
VIN+_B
VIN- _B
REFT_A
REFB_A
REFT_B
REFB_B
VREF
SENSE
CLK_B
CLK_A
DCS
DFS
PDWN_B
PDWN_A
OEB_B
OEB_A
D0_A (LSB)-D9_A
(MSB)
D0_B (LSB) –D9_B
(MSB)
OTR_B
OTR_A
SHARED_REF
61
MUX_SELECT
5, 12, 17,
64
1, 4, 13, 16
28, 40, 53
29, 41, 52
AVDD
23-26, 4245
Rev. PrD
AGND
DRGND
DRVDD
DNC
Channel B Data Output Bits
Out-of-Range Indicator for Channel B
Out-of-Range Indicator for Channel A
Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared
Reference Mode)
Data Multiplexed Mode. (See description for how to enable; high setting disables output data
Multiplexed mode)
Analog Power Supply
Analog Ground
Digital Output Ground
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF
Do Not Connect Pins. Should be left floating.
Page 9 of 20
6/15/2004
AD9216
Preliminary Technical Data
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
TERMINOLOGY
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the A/D converter.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-Bits resolution indicates that all 2048
codes must be present over all operating ranges.
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels relative to the peak carrier
signal (dBc).
Effective Number of Bits (ENOB)
Using the following formula:
ENOB = (SINAD − 1.76 ) 6.02
effective number of bits for a
device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels relative to the peak carrier
signal (dBc).
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN- . Offset error is defined as the
deviation of the actual transition from that point.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal
(dBc).
Rev. PrD
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be
aliased down into the first Nyquist zone (DC - fCLOCK/2) on the
output of the ADC. Care must be taken that the bandwidth of
the sampled signal does not overlap Nyquist zones and alias
onto itself. Nyquist sampling performance is limited by the
bandwidth of the input SHA and clock jitter (jitter adds more
noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the A/D
converter to reacquire the analog input after a transient from
10% above positive full scale to 10% above negative full scale,
or from 10% below negative full scale to 10% below positive
full scale.
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Preliminary Technical Data
Crosstalk
Coupling onto one channel being driven by a (- 0.5 dBFS)
signal when the adjacent interfering channel is driven by a full-
Rev. PrD
AD9216
scale signal. Measurement includes all spurs resulting from
both direct coupling and mixing components.
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AD9216
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTIC PLOTS (TBD)
Rev. PrD
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Preliminary Technical Data
AD9216
EQUIVALENT CIRCUITS
Figure xx. Equivalent Digital Output Circuit
Figure xx. Equivalent Analog Input Circuit
Figure xx. Equivalent Digital Input Circuit
THEORY OF OPERATION
The AD9216 consists of two high performance analog-todigital converters (ADCs) that are based on the AD9215
converter core. The dual ADC paths are independent, except for
a shared internal band gap reference source, VREF. Each of the
ADC’s paths consists of a proprietary front end sample-andhold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The pipelined ADC is divided into three
sections, consisting of a 4-bit first stage followed by five 1.5bit stages and a final 3-bit fl ash. Each stage provides sufficient
overlap to correct for fl ash errors in the preceding stages. The
quantized outputs from each stage are combined through the
digital correction logic block into a final 10-bit result. The
pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge of the
respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution fl ash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the fl ash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
Rev. PrD
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switched
capacitor, SHA, that has been designed for optimum
performance while processing a differential input signal. The
SHA input accepts inputs over a wide common-mode range. An
input common-mode voltage of mid supply is recommended to
maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure 4, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
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AD9216
Preliminary Technical Data
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network will create a low-pass filter at the ADC’s
input; therefore, the precise values are dependant on the
application. In IF under sampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth. For
best dynamic performance, the source impedances driving
VIN+ and VIN- should be matched such that common- mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the ADC.
levels are defined as follows:
VCM MIN = V REF 2
VCM MAX = (AVDD + V REF
)2
The minimum common- mode input level allows the AD9216 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a singleended source may be driven into VIN+ or VIN- . In this
configuration, one input will accept the signal, while the
opposite input should be set to mid-scale by connecting it to an
appropriate reference. For example, a 2 VP-P signal may be
applied to VIN+ while a 1 V reference is applied to VIN- . The
AD9216 will then accept an input signal varying between 2 V
and 0 V. In the single-ended configuration, distortion
performance may degrade significantly as compared to the
differential case. However, the effect will be less noticeable at
lower input freque ncies and in the lower speed grade models
(AD9216-65 and AD9216-80).
Differential Input Configurations
As previously detailed, optimum performance will be achieved
while driving the AD9216 in a differential input configuration.
For base band applications, the AD8138 differential driver
provides excellent performance and a flexible interface to the
ADC. The output common- mode voltage of the AD8138 is
easily set to AVDD/2, and the driver can be configured in a
Sallen-Key filter topology to provide band limiting of the input
signal.
Figure 4. Switched Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common-mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
REFT = 1 2 (AVDD + V REF )
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9216. This is especially true in
IF under sampling applications where freque ncies in the 70
MHz to 200 MHz range are being sampled. For these
applications, differential transformer coupling is the
recommended input configuration, as shown in Figure 5.
REFB = 1 2 ( AVDD − V REF )
Span = 2 × (REFT − REFB) = 2 × V REF
AD9216
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the mid-supply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance will be achieved with the
AD9216 set to the largest input span of
2 VP-P. The relative SNR degradation will be 3 dB when
changing from 2 VP-P mode to 1 VP-P mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
Rev. PrD
Figure 5. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
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Preliminary Technical Data
AD9216
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common- mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
I DRVDD = V DRVDD × CLOAD × fCLOCK × N
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels
asynchronously may degrade performance significantly. In
some applications, it is desirable to skew the clock timing of
adjacent channels. The AD9216’s separate clock inputs allow
for clock timing skew (typ ically ±1 ns) between the channels
without significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the non-sampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster Input
clock rates (where it becomes difficult to maintain 50% duty
cycles) can benefit from using DCS as a wide range of input
clock duty cycles can be accommodated. Maintaining a 50%
duty cycle clock is particularly important in high speed
applicatio ns, when proper track-and-hold times for the
converter are required to maintain high performance. The DCS
can be enabled by tying the DCS pin high.
The duty cycle stabilizer utilizes a delay locked loop to create
the non-sampling edge. As a result, any changes to the
sampling frequency will require approximately 2 µs to 3 µs to
allow the DLL to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT ) due only to aperture jitter (tJ ) can be
calculated
where N is the number of bits changing and CLOAD is the
average load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
will result in a typical power consumption of 1 mW for the
ADC. Note that if DCS is enabled, it is mandatory to disable
the clock of an independently powered-down channel.
Otherwise, significant distortion will result on the active
channel. If the clock inputs remain active while in total standby
mode, typical power dissipation of TBD mW will result.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time will be directly related to
the recharging of the REFT and REFB decoupling capacitors
and to the duration of the power-down. Typically, it takes
approximately 5 ms to restore full operation with fully
discharged 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB.
with the following equation:
[
SNR deg radation = 20 × log 10 1 2 × p × f INPUT × t J
]
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered. Because the buffer and voltage reference
remain powered, the wake-up time is reduced to several clock
cycles.
In the equation, the rms aperture jitter, tJ , represents the rootsum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9216, it is
important to minimize input clock jitter. The clock input
circuitry should use stable references, for example using analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source
Rev. PrD
DIGITAL OUTPUTS
The AD9216 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the
digital supply of the interfaced logic. The output drivers are
sized to provide sufficient output current to drive a wide variety
of logic families. However, large drive currents tend to cause
current glitches on the supplies that may affect converter
performance. Applications requiring the ADC to drive large
capacitive loads or large fan-outs may require external buffers
or latches.
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AD9216
Preliminary Technical Data
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
AD9216 using the DCS pin. This provides a stable 50% duty
cycle to internal circuits.
TIMING
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9216
is 1 MSPS. At clock rates below 1 MSPS, dynamic
performance may degrade.
The AD9216 provides latched data outputs with a pipeline
delay of six clock cycles. Data outputs are available one
propagation delay (tPD ) after the rising edge of the clock signal.
Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the
Figure 6. NEEDS UPDATING Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and
MUX_SELECT
DATA FORMAT
must remain active in this mode and that each channel's powerdown pin must remain low.
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
Data Format Select pin (DFS). Connecting DFS to AGND will
produce offset binary output data. Conversely, connecting DFS
to AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be
multiplexed onto a single 10-Bits output bus. The multiplexing
is accomplished by toggling the MUX_SELECT bit, which
directs channel data to the same or opposite channel data port.
When MUX_SELECT is logic high, the Channel A data is
directed to Channel A output bus, and Channel B data is
directed to the Channel B output bus. When MUX_SELECT is
logic low, the channel data is reversed, i.e., Channel A data is
directed to the Channel B output bus and Channel B data is
directed to the Channel A output bus. By toggling the
MUX_SELECT bit, multiplexed data is available on either of
the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT bit. After the
MUX_SELECT rising edge, either data port will ha ve the data
for its respective channel; after the falling edge, the alternate
channel’s data will be placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 6 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
Rev. PrD
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Preliminary Technical Data
AD9216
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9216. The input range can be adjusted by varying the
reference voltage applied to the AD9216, using either the
internal reference with different external resistor configurations
or an externally applied reference voltage. The input span of
the ADC tracks reference voltage changes linearly.
completing the loop and provid ing a 0.5 V reference output. If
a resistor divider is connected as shown in Figure xx, the
switch will again be set to the SENSE pin. This will put the
reference amplifier in a non- inverting mode with the VREF
output defined as fo llows:
V REF = 0.5 × (1 + R 2 R1)
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either
an internal or an external reference.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common mode voltage).
The Shared Reference mode allows the user to connect the
references from the dual ADCs together externally for superior
gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be treated
independently and can provide superior isolation between the
dual channels. To enable Shared Reference mode, the
SHARED_REF pin must be tied high and external differential
references must be externally shorted. (REFT_A must be
externally shorted to REFT_B and REFB_A must be shorted to
REFB_B.)
Internal Reference Connection
A comparator within the AD9216 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 8. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 7), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin,
AD9216
Figure 7. Internal Reference Configuration
Table 8. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential
Span (VP-P)
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
N/A
0.5
0.5 × (1 + R2/R1)
1.0
2 × External Reference
1.0
2 × VREF (See Figure xx)
2.0
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a
single reference (internal or external) may be necessary to
reduce gain matching errors to an acceptable level. A high
precision external reference may also be selected to provide
lower gain and offset temperature drift. Figure 10 shows the
typical drift characteristics of the internal reference in both 1 V
and 0.5 V modes. When the SENSE pin is tied to AVDD, the
internal reference will be disabled, allowing the use of an
external reference. An internal reference buffer will load the
external reference with an equivalent 7 kΩ load. The internal
buffer will still generate the positive and negative full-scale
references, REFT and REFB, for the ADC core. The input span
will always be twice the value of the reference voltage;
therefore, the external reference must be limited to a maximum
Rev. PrD
of 1 V. If the internal reference of the AD9216 is used to drive
multiple converters to improve gain matching, the loading of
the reference by the other converters must be considered.
Figure X depicts how the internal reference voltage is affected
by loading.
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AD9216
Preliminary Technical Data
AD9216
Figure xx. VREF Accuracy vs. Load
Figure xx. Programmable Reference Configuration
Figure xx. Typical VREF Drift
Rev. PrD
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Preliminary Technical Data
AD9216
EVALUATION BOARD DIAGRAMS (TBD)
Rev. PrD
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AD9216
Preliminary Technical Data
PR04775-0-6/04(PrD)
OUTLINE DIMENSIONS
Figure 8. 64-Lead Lead Frame Chip Scale Package (LFCSP)
Rev. PrD
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