AD AD5749 Industrial current out driver, single-supply, 55 v maximum supply, programmable range Datasheet

Industrial Current Out Driver, Single-Supply,
55 V Maximum Supply, Programmable Ranges
AD5749
FEATURES
APPLICATIONS
Process control
Actuator control
PLCs
FUNCTIONAL BLOCK DIAGRAM
DVCC GND
AVDD GND
CLEAR
CLRSEL
SCLK/OUTEN*
SDIN/R0*
SYNC/RSET*
SDO/VFAULT*
HW SELECT
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
AD5749
AVDD
STATUS
REGISTER
R3
R2
VIN
VREF
RESET
IOUT RANGE
SCALING
IOUT
FAULT/TEMP*
NC/IFAULT*
OVERTEMP
REXT1
IOUT OPEN FAULT
RSET
REXT2
IOUT OPEN FAULT
POWERON RESET
AD2/R1*
AD1/R2*
IOUT
OPEN FAULT
AD0/R3*
*DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT,
HARDWARE MODE DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR
FAULT/TEMP PIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT
FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.
08923-001
Current output ranges: 0 mA to 24 mA or 4 mA to 20 mA
±0.03% FSR typical total unadjusted error (TUE)
±5 ppm/°C typical output drift
2% overrange
Flexible serial digital interface
On-chip output fault detection
PEC error checking
Asynchronous CLEAR function
Power supply range
AVDD: 12 V (± 10%) to 55 V (maximum)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
Figure 1.
GENERAL DESCRIPTION
The AD5749 is a single channel, low cost, precision, current output
driver with hardware or software programmable output ranges.
The software ranges are configured via an SPI-/MICROWIRE™compatible serial interface. The AD5749 targets applications in
PLC and industrial process control. The analog input to the
AD5749 is provided from a low voltage, single-supply digital-toanalog converter (DAC) and is internally conditioned to provide
the desired output current/voltage range.
The output current range is programmable across two current
ranges: 0 mA to 24 mA, or 4 mA to 20 mA. Current output is
open-circuit protected and can drive inductive loads of 0.1 H.
The device is specified to operate with a power supply range
from 10.8 V to 55 V. Output loop compliance is 0 V to AVDD −
2.75 V.
The flexible serial interface is SPI and MICROWIRE compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications. The interface also
features an optional PEC error checking feature using CRC-8
error checking, useful in industrial environments where data
communication corruption can occur.
The device also includes a power-on reset function ensuring
that the device powers up in a known state and an asynchronous CLEAR pin that sets the outputs to the low end of the
selected current range.
An HW SELECT pin is used to configure the part for hardware
or software mode on power-up.
Table 1. Related Devices
Part No.
AD5750
AD5751
AD5748
AD5410/
AD5420
AD5412/
AD5422
Description
Industrial current/voltage output (I/V) driver with
programmable ranges
Industrial I/V output driver, single-supply, 55 V maximum
supply, programmable ranges
Industrial I/V output driver with programmable ranges
Single-channel, 12-/16-bit, serial input, current source
output DAC
Single-channel, 12-/16-bit, serial input, I/V output DAC
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD5749
TABLE OF CONTENTS
Features .............................................................................................. 1
OUTEN........................................................................................ 18
Applications ....................................................................................... 1
Software Control ........................................................................ 18
Functional Block Diagram .............................................................. 1
Hardware Control ...................................................................... 21
General Description ......................................................................... 1
Transfer Function ....................................................................... 21
Revision History ............................................................................... 2
Detailed Description of Features .................................................. 22
Specifications..................................................................................... 3
Output Fault Alert—Software Mode ....................................... 22
Timing Characteristics ................................................................ 5
Output Fault Alert—Hardware Mode ..................................... 22
Absolute Maximum Ratings............................................................ 7
Asynchronous Clear (CLEAR) ................................................. 22
ESD Caution .................................................................................. 7
External Current Setting Resistor ............................................ 22
Pin Configuration and Function Descriptions ............................. 8
Programmable Overrange Modes ............................................ 22
Typical Performance Characteristics ........................................... 10
Packet Error Checking ............................................................... 23
Terminology .................................................................................... 15
Applications Information .............................................................. 24
Theory of Operation ...................................................................... 16
Transient Voltage Protection .................................................... 24
Software Mode ............................................................................ 16
Thermal Considerations............................................................ 24
Currrent Output Architecture .................................................. 18
Layout Guidelines....................................................................... 25
Driving Inductive Loads ............................................................ 18
Galvanically Isolated Interface ................................................. 25
Power-On State of the AD5749 ................................................ 18
Microprocessor Interfacing ....................................................... 25
Default Registers at Power-On ................................................. 18
Outline Dimensions ....................................................................... 26
Reset Function ............................................................................ 18
Ordering Guide .......................................................................... 26
REVISION HISTORY
7/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5749
SPECIFICATIONS
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. RLOAD = 300 Ω. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter 1
INPUT VOLTAGE RANGE
Input Leakage Current
REFERENCE INPUT
Reference Input Voltage
Input Leakage Current
CURRENT OUTPUT
Output Current Ranges
Output Current Overranges 2
ACCURACY (INTERNAL RSET)
Total Unadjusted Error (TUE)
A Version2
Relative Accuracy (INL)
Offset Error
Offset Error TC2
Dead Band on Output, RTI
Gain Error
Gain TC2
Full-Scale Error
Full-Scale TC2
ACCURACY (EXTERNAL RSET)
Total Unadjusted Error (TUE)
A Version2
Relative Accuracy (INL)
Offset Error
Offset Error TC2
Dead Band on Output, RTI
Gain Error
Gain TC2
Full-Scale Error
Full-Scale TC2
Min
Typ
0 to 4.096
−1
Max
+1
4.096
Unit
V
μA
Test Conditions/Comments
Output unloaded
V
External reference must be exactly as stated;
otherwise, accuracy errors show up as error in output
−1
+1
μA
0
4
0
3.92
24
20
24.5
20.4
mA
mA
mA
mA
+0.5
+0.3
+0.02
+16
+10
% FSR
% FSR
% FSR
μA
μA
ppm FSR/°C
mV
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
−0.5
−0.3
−0.02
−16
−10
−0.2
−0.125
−0.2
−0.125
−0.3
−0.1
−0.02
−14
−11
−0.08
−0.07
−0.1
−0.07
±0.15
±0.01
+5
±3
8
±0.02
±10
±0.02
±4
±0.02
±0.01
+5
±2
8
±0.02
±1
±0.02
±2
14
+0.2
+0.125
+0.2
+0.125
+0.3
+0.1
+0.02
+14
+11
+14
+0.08
+0.07
+0.1
+0.07
% FSR
% FSR
% FSR
μA
See Detailed Description of Features section
See Detailed Description of Features section
TA = 25°C
TA = 25°C
Referred to 4.096 V input range
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
ppm FSR/°C
mV
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
Rev. 0 | Page 3 of 28
Referred to 4.096 V input range
TA = 25°C
TA = 25°C
AD5749
Parameter 1
OUTPUT CHARACTERISTICS2
Current Loop Compliance
Voltage
Resistive Load
Inductive Load
Settling Time
4 mA to 20 mA, Full-Scale
Step
120 μA Step, 4 mA to
20 mA Range
DC PSRR
Output Impedance
DIGITAL INPUTS2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS2
FAULT, IFAULT, TEMP, VFAULT
VOL, Output Low Voltage
VOH, Output High Voltage
SDO
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Output
Capacitance
High Impedance Leakage
Current
POWER REQUIREMENTS
AVDD
DVCC
Input Voltage
AIDD
DICC
Power Dissipation
1
2
Min
Typ
0
Max
Unit
AVDD − 2.75
V
Test Conditions/Comments
H
Chosen such that compliance is not exceeded
Needs appropriate capacitor at higher inductance
values; see the Driving Inductive Loads section
8.5
μs
250 Ω load
1.2
μs
250 Ω load
See the Test Conditions/
Comments column
130
1
μA/V
MΩ
5
V
V
μA
pF
Per pin
Per pin
0.6
V
V
V
10 kΩ pull-up resistor to DVCC
At 2.5 mA
10 kΩ pull-up resistor to DVCC
0.5
DVCC − 0.5
3
V
V
pF
Sinking 200 μA
Sourcing 200 μA
JEDEC compliant
2
0.8
+1
−1
0.4
3.6
0.5
DVCC − 0.5
−1
+1
μA
10.8
55
V
5.5
5.6
V
mA
6.2
1
mA
mA
mW
2.7
4.4
5.2
0.3
108
Temperature range: −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization, not production tested.
Rev. 0 | Page 4 of 28
Output unloaded, output disabled;
R3, R2, R1, R0 = 0000, RSET = 0
Output enabled
VIH = DVCC, VIL = GND
AVDD = 24 V, output unloaded
AD5749
TIMING CHARACTERISTICS
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. RLOAD = 300 Ω. All specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter 1, 2
t1
t2
t3
t4
t5
t6
t7
t8
t9, t10
t11
t12
t13
1
2
Limit at TMIN, TMAX
20
8
8
5
10
5
5
5
1.5
5
40
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)
Minimum SYNC high time (write mode)
Data setup time
Data hold time
CLEAR pulse low/high activation time
Minimum SYNC high time (read mode)
SCLK rising edge to SDO valid (SDO CL = 15 pF)
RESET pulse low time
Guaranteed by characterization, but not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
Rev. 0 | Page 5 of 28
AD5749
Timing Diagrams
t1
SCLK
1
2
16
t3
t6
t2
t4
t5
SYNC
t8
t7
SDIN
D15
D0
CLEAR
t10
t9
IOUT
08923-002
RESET
t13
Figure 2. Write Mode Timing Diagram
SCLK
SYNC
SDIN
t11
A2
A1
A0
R=1
0
X
X
X
X
X
X
X
X
X
X
X
SDO
X
X
X
X
X
R3
R2
R1
R0
CLRSEL OUTEN
Figure 3. Readback Mode Timing Diagram
Rev. 0 | Page 6 of 28
RSET
PEC
ERROR
OVER
TEMP
IOUT
FAULT
VOUT
FAULT
08923-003
t12
AD5749
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
AVDD to GND
DVCC to GND
Digital Inputs to GND
Digital Outputs to GND
VREF to GND
VIN to GND
IOUT to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
32-Lead LFCSP Package
θJA Thermal Impedance
Lead Temperature
Soldering
Rating
−0.3 V to +58 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V, or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V, or 7 V
(whichever is less)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to AVDD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
125°C
28°C/W
JEDEC industry standard
J-STD-020
Rev. 0 | Page 7 of 28
AD5749
32
31
30
29
28
27
26
25
NC/IFAULT
FAULT/TEMP
RESET
HW SELECT
NC
NC
NC
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD5749
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
DNC
DNC
GND
GND
DNC
DNC
IOUT
AVDD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE IS TIED TO GND.
08923-004
AD2/R1
AD1/R2
AD0/R3
REXT2
REXT1
VREF
VIN
GND
9
10
11
12
13
14
15
16
SDO/VFAULT
CLRSEL
CLEAR
DVCC
GND
SYNC/RSET
SCLK/OUTEN
SDIN/R0
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
SDO/VFAULT
2
CLRSEL
3
CLEAR
4
5
6
DVCC
GND
SYNC/RSET
7
SCLK/OUTEN
8
SDIN/R0
9
AD2/R1
10
AD1/R2
11
AD0/R3
Description
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
This pin is a CMOS output.
In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range
selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear
(CLEAR) section for more details.
Digital Power Supply.
Ground Connection.
Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift
register data into the AD5749 and also updates the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current
sense resistor is used.
If RSET = 0, the external sense resistor is chosen.
If RSET = 1, the internal sense resistor is chosen.
Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling
edge of SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current range setting on the part.
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current range setting on the part.
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD0 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current range setting on the part.
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output
current range setting on the part.
Rev. 0 | Page 8 of 28
AD5749
Pin No.
12, 13
Mnemonic
REXT2, REXT1
14
15
16
17
18
19, 20, 23, 24
21, 22
25, 26, 27, 28
29
VREF
VIN
GND
AVDD
IOUT
DNC
GND
NC
HW SELECT
30
RESET
31
FAULT/TEMP
32
NC/IFAULT
33 (EPAD)
EPAD
Description
A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to
improve the IOUT temperature drift performance.
Buffered Reference Input.
Buffered Analog Input (0 V to 4.096 V).
Ground Connection.
Positive Analog Supply.
Current Output.
Do not connect to these pins.
Ground Connection.
No Connect. Can be tied to GND.
This part is used to configure the part to hardware or software mode.
HW SELECT = 0 selects software control.
HW SELECT = 1 selects hardware control.
In software mode, this pin resets the part to its power-on state. Active low.
In hardware mode, there is no reset. If using the part in hardware mode, the RESET pin should be tied
high.
Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an
open-circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output
and must be connected to a pull-up resistor.
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is
asserted low when an overtemperature error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is
asserted low when an open-circuit error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
The exposed paddle is tied to GND.
Rev. 0 | Page 9 of 28
AD5749
TYPICAL PERFORMANCE CHARACTERISTICS
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
0
–0.002
–0.004
–0.006
4.096
55V
0.05
–0.02
4.096
VIN (V)
08923-009
3.803
3.511
3.218
2.926
2.633
4.096
VIN (V)
08923-006
3.803
3.511
3.218
2.926
2.633
2.341
2.048
1.755
1.463
1.170
0.878
–0.05
0.585
–0.005
Figure 9. Total Unadjusted Error vs. VIN, External RSET Resistor
Figure 6. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor
0.05
TOTAL UNADJUSTED ERROR (%FSR)
4mA TO 20mA EXTERNAL RSET LINEARITY
0mA TO 24mA EXTERNAL RSET LINEARITY
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
4mA TO 20mA INTERNAL RSET TUE
0mA TO 24mA INTERNAL RSET TUE
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
Figure 7. Integral Nonlinearity Current Mode, External RSET Sense Resistor
Rev. 0 | Page 10 of 28
VIN (V)
Figure 10. Total Unadjusted Error vs. VIN, Internal RSET Resistor
08923-010
4.096
3.803
3.511
3.218
2.926
2.633
2.341
2.048
1.755
1.463
1.170
–0.05
0.878
55V
0.585
48V
SUPPLY VOLTAGE (AVDD)
08923-007
24V
0.293
–0.04
–0.008
0.020
0.293
–0.04
0.020
–0.004
2.341
–0.03
2.048
–0.003
–0.01
1.755
–0.002
0
1.463
–0.001
0.01
1.170
0
0.878
0.001
0.02
0.585
0.002
0.03
0.293
0.003
4mA TO 20mA EXTERNAL RSET TUE
0mA TO 24mA EXTERNAL RSET TUE
0.04
0.020
TOTAL UNADJUSTED ERROR (%FSR)
4mA TO 20mA INTERNAL RSET RESISTOR
0mA TO 24mA INTERNAL RSET RESISTOR
0.004
–0.010
48V
SUPPLY VOLTAGE (AVDD)
Figure 8. Integral Nonlinearity Current Mode, Internal RSET Sense Resistor
0.005
0.008
24V
08923-005
3.803
3.511
3.218
2.926
2.633
2.341
2.048
1.755
1.463
1.170
0.878
0.585
0.293
–0.010
0.020
–0.008
Figure 5. Integral Nonlinearity Error vs. VIN, External RSET Resistor
INTEGRAL NONLINEARITY (%FSR)
0.002
–0.005
VIN (V)
INTEGRAL NONLINEARITY (%FSR)
0.006
0.004
–0.004
0.010
4mA TO 20mA INTERNAL RSET LINEARITY
0mA TO 24mA INTERNAL RSET LINEARITY
0.008
INTEGRAL NONLINEARITY (%FSR)
0.004
INTEGRAL NONLINEARITY (%FSR)
0.010
4mA TO 20mA EXTERNAL RSET RESISTOR
0mA TO 24mA EXTERNAL RSET RESISTOR
08923-008
0.005
AD5749
0.005
4mA TO 20mA EXTERNAL RSET POSITIVE TUE
0mA TO 24mA EXTERNAL RSET POSITIVE TUE
0.004
INTEGRAL NONLINEARITY (%FSR)
0.015
0.010
0.005
0
–0.005
–0.010
4mA TO 20mA EXTERNAL RSET NEGATIVE TUE
0mA TO 24mA EXTERNAL RSET NEGATIVE TUE
–0.015
24V
48V
SUPPLY VOLTAGE (AVDD)
55V
0.010
0.001
0
–0.001
–0.002
–0.003
–40
25
TEMPERATURE (°C)
105
Figure 14. Integral Nonlinearity Error vs. Temperature,
External RSET Sense Resistor
0.10
4mA TO 20mA INTERNAL RSET NEGATIVE TUE
0mA TO 24mA INTERNAL RSET NEGATIVE TUE
0.08
0.005
POSITIVE/NEGATIVE TUE (%FSR)
0
–0.005
–0.010
–0.015
0.06
4mA TO
0mA TO
4mA TO
0mA TO
20mA INTERNAL RSET POSITIVE TUE
24mA INTERNAL RSET POSITIVE TUE
20mA INTERNAL RSET NEGATIVE TUE
24mA INTERNAL RSET NEGATIVE TUE
0.04
0.02
0
–0.02
–0.04
–0.06
–0.020
24V
48V
SUPPLY VOLTAGE (AVDD)
55V
–0.10
08923-012
–0.025
Figure 12. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor
–40
105
Figure 15. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor
0.10
0.005
4mA TO 20mA INTERNAL RSET LINEARITY
0mA TO 24mA INTERNAL RSET LINEARITY
0.08
POSITIVE/NEGATIVE TUE (%FSR)
0.004
25
TEMPERATURE (°C)
08923-015
–0.08
0mA TO 24mA INTERNAL RSET POSITIVE TUE
4mA TO 20mA INTERNAL RSET POSITIVE TUE
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.004
–40
25
TEMPERATURE (°C)
105
Figure 13. Integral Nonlinearity Error vs. Temperature,
Internal RSET Sense Resistor
20mA EXTERNAL RSET POSITIVE TUE
24mA EXTERNAL RSET POSITIVE TUE
20mA EXTERNAL RSET NEGATIVE TUE
24mA EXTERNAL RSET NEGATIVE TUE
–0.10
08923-013
–0.005
4mA TO
0mA TO
4mA TO
0mA TO
–40
25
TEMPERATURE (°C)
105
08923-016
TOTAL UNADJUSTED ERROR (%FSR)
0.002
–0.005
Figure 11. Total Unadjusted Error Current Mode, External RSET Sense Resistor
INTEGRAL NONLINEARITY (%FSR)
0.003
08923-014
–0.020
4mA TO 20mA EXTERNAL RSET LINEARITY
0mA TO 24mA EXTERNAL RSET LINEARITY
–0.004
08923-011
TOTAL UNADJUSTED ERROR (%FSR)
0.020
Figure 16. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor
Rev. 0 | Page 11 of 28
AD5749
4
50
45
3
OFFSET ERROR (µA)
ZERO-SCALE ERROR (µA)
40
35
30
25
20
15
2
1
0
–1
10
–2
0
25
TEMPERATURE (°C)
105
–3
0.05
35
0.04
FULL-SCALE ERROR (%FSR)
40
30
25
20
15
10
–40
25
TEMPERATURE (°C)
105
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.05
–40
Figure 18. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor
105
0.10
0.08
FULL-SCALE ERROR (%FSR)
2
OFFSET ERROR (µA)
25
TEMPERATURE (°C)
Figure 21. Full-Scale Error vs. Temperature, External RSET Sense Resistor
3
1
0
–1
–2
4mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
–40
25
TEMPERATURE (°C)
4mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
105
–0.10
08923-019
–3
4mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
Figure 19. Offset Error vs. Temperature, Internal RSET Sense Resistor
–40
25
TEMPERATURE (°C)
105
08923-022
0
105
–0.04
4mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
08923-018
5
25
TEMPERATURE (°C)
Figure 20. Offset Error vs. Temperature, External RSET Sense Resistor
Figure 17. Zero-Scale Error vs. Temperature, External RSET Sense Resistor
ZERO-SCALE ERROR (µA)
–40
08923-021
–40
08923-020
4mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
08923-017
5
Figure 22. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor
Rev. 0 | Page 12 of 28
AD5749
12
0.10
0.000010
0.000008
10
0.000006
8
0.02
0
0.000004
0.000002
6
IOUT
0
4
–0.000002
–0.02
–0.000004
2
–0.04
–0.000006
VDD
–0.06
0
–0.000008
–0.08
–40
25
TEMPERATURE (°C)
08923-023
–0.10
105
–2
–10
–0.000010
–8
–4
–2
0
2
4
6
8
10
TIME (ms)
0
0.10
4mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
–2
0.06
–4
0.04
–6
0.02
IOUT (µA)
GAIN ERROR (%FSR)
–6
Figure 26. Output Current vs. Time on VDD Power-Up
Figure 23. Gain Error vs. Temperature, External RSET Sense Resistor
0.08
IOUT (A)
0.04
VDD (V)
GAIN ERROR (%FSR)
0.06
08923-026
0.08
4mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
0
–8
–10
–0.02
–12
–0.04
–14
–0.06
–40
25
TEMPERATURE (°C)
–18
–2
08923-024
–0.10
105
Figure 24. Gain Error vs. Temperature, Internal RSET Sense Resistor
–1
0
1
2
3
4
5
6
7
8
TIME (µs)
08923-027
–16
–0.08
Figure 27. Output Current vs. Time on Output Enable, 0 mA to 24 mA Range
2.10
0.025
2.05
0.020
CURRENT (A)
1.95
1.90
1.85
0.015
0.010
1.80
1.75
0.005
AVDD COMPLIANCE VOLTAGE
1.65
–40
25
TEMPERATURE (°C)
105
0
–12
–6
1
8
14
21
28
34
41
48
54
TIME (µs)
Figure 25. Output Compliance vs. Temperature
Tested When IOUT = 10.8 mA, 0 mA to 24 mA Range Selected
Figure 28. 4 mA to 20 mA Output Current Step
Rev. 0 | Page 13 of 28
61
68
08923-028
1.70
08923-025
COMPLIANCE (V)
2.00
AD5749
3000
4.10
2500
4.05
4.00
AIDD (mA)
DVCC = 5V
1500
3.95
3.90
1000
3.85
500
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
LOGIC LEVEL (V)
4.5
5.0
3.75
24
48
AVDD (V)
Figure 30. AIDD vs. AVDD, IOUT = 0 mA
Figure 29. DICC vs. Logic Input Voltage
Rev. 0 | Page 14 of 28
55
08923-031
3.80
DVCC = 3V
08923-029
DICC (µA)
2000
AD5749
TERMINOLOGY
Zero-Scale TC
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Total Unadjusted Error (TUE)
TUE is a measure of the output error taking all the various
errors into account: INL error, offset error, gain error, and
output drift over supplies, temperature, and time. TUE is
expressed as a percentage of full-scale range (% FSR).
Relative Accuracy or Integral Nonlinearity (INL)
INL is a measure of the maximum deviation, in % FSR, from a
straight line passing through the endpoints of the output driver
transfer function. A typical INL vs. input voltage plot is shown
in Figure 5.
Full-Scale Error
Full-scale error is the deviation of the actual full-scale analog
output from the ideal full-scale output. Full-scale error is
expressed as a percentage of full-scale range (% FSR).
Full-Scale TC
Full-scale TC is a measure of the change in the full-scale error
with a change in temperature. It is expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the output. It is the
deviation in slope of the output transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature is
shown in Figure 23.
Offset Error
Offset error is a measurement of the difference between the
actual VOUT and the ideal VOUT expressed in millivolts (mV)
in the linear region of the transfer function. It can be negative
or positive.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a half-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change
of the output voltage. The output slewing speed is usually
limited by the slew rate of the amplifier used at its output. Slew
rate is measured from 10% to 90% of the output signal and is
expressed in V/μs.
Current Loop Voltage Compliance
Current loop voltage compliance is the maximum voltage at
the IOUT pin for which the output current is equal to the
programmed value.
Gain Error TC
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in ppm
FSR/°C.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5749 is powered on. It is specified as the
area of the glitch in nV-sec.
Zero-Scale Error
Zero-scale error is the deviation of the actual zero-scale analog
output from the ideal zero-scale output. Zero-scale error is
expressed in millivolts (mV).
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output is affected by changes in the
power supply voltage.
Rev. 0 | Page 15 of 28
AD5749
THEORY OF OPERATION
Figure 31 and Figure 32 show a typical configuration of AD5749 in
software mode and in hardware mode, respectively, in an output
module system. The HW SELECT pin chooses whether the part
is configured in software or hardware mode. The analog input to
the AD5749 is provided from a low voltage, single-supply DAC
such as the AD506x or AD566x, which can provide an output
range of 0 V to 4.096 V. The supply and reference for the DAC,
as well as the reference for the AD5749, can be supplied from a
reference such as the ADR392. The AD5749 can operate with a
single supply up to 55 V.
The AD5749 is a single-channel, low cost, precision, current
output driver with hardware or software programmable output
ranges. The software ranges are configured via an SPI-/
MICROWIRE-compatible serial interface. The hardware ranges
are programmed using the range pins (R0 to R3). The analog
input to the AD5749 is provided from a low voltage, single-supply
DAC (0 V to 4.096 V), which is internally conditioned to provide
the desired output current range.
The output current range is programmable across two ranges:
0 mA to 24 mA, or 4 mA to 20 mA. An overrange of 2% is
available on the 0 mA to 24 mA and 4 mA to 20 mA current
ranges. The output range is selected by programming the R3
to R0 bits in the control register (see Table 7 and Table 8).
SOFTWARE MODE
The software-selectable output ranges are 0 mA to 24 mA, or
4 mA to 20 mA.
ADP1720
ADR392
SDI/DIN
MCU
SDO
AGND
AVDD
GND
AD5749
VREF
REFIN
VIN
AD506x
AD566x
SYNC1
SCLK
SDIN
SDO
SERIAL
INTERFACE
SYNC
IOUT
RANGE
SCALE
IOUT
0mA TO 20mA,
0mA TO 24mA,
4mA TO 20mA
IOUT OPEN FAULT
OVERTEMP FAULT
STATUS REGISTER
HW SELECT
FAULT
08923-032
SCLK
VDD
AVDD
Figure 31. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Rev. 0 | Page 16 of 28
AD5749
AVDD AGND
ADP1720
AVDD GND
ADR392
SDI/DIN
MCU
SDO
AD5749
VREF
REFIN
IOUT
RANGE
SCALE
VIN
AD506x
AD566x
SYNC1
DVCC
IOUT
0mA TO 20mA,
0mA TO 24mA,
4mA TO 20mA
HW SELECT
OUTEN
R3
R2
R1
TEMP
IFAULT
R0
OUTPUT RANGE
SELECT PINS
08923-033
SCLK
VDD
Figure 32. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Table 6. Suggested Parts for Use with the AD5749
DAC
AD5660
AD5664R
AD5668
AD5060
AD5064/AD5066
AD5662
AD5664
1
2
Reference
Internal
Internal
Internal
ADR434
ADR434
ADR392 2
ADR3922
Power
ADP1720 1
N/A
N/A
ADP1720
N/A
ADR3922
N/A
Resolution/Accuracy
16-bit/12-bit
16-bit/12-bit
16-bit/12-bit
16-bit/16-bit
16-bit/16-bit
16-bit/12-bit
16-bit/12-bit
Description
Mid-end system, single channel, internal reference
Mid-end system, quad channel, internal reference
Mid-end system, octal channel, internal reference
High-end system, single channel, external reference
High-end system, quad channel, external reference
Mid-end system, single channel, external reference
Mid-end system, quad channel, external reference
ADP1720 input range up to 28 V.
ADR392 input range up to 15 V.
Rev. 0 | Page 17 of 28
AD5749
CURRRENT OUTPUT ARCHITECTURE
DEFAULT REGISTERS AT POWER-ON
The voltage input from the analog input VIN core (0 V to 4.096 V)
is converted to a current (see Figure 33), which is then mirrored
to the supply rail so that the application simply sees a current
source output with respect to an internal reference voltage. The
reference is used to provide internal offsets for range and gain
scaling. The selectable output range is programmable through
the digital interface (software mode) or via the range pins (R0 to
R3) (hardware mode).
The AD5749 power-on-reset circuit ensures that all registers are
loaded with zero code.
AVDD
R2
RANGE DECODE
FROM INTERFACE
RESET FUNCTION
T2
IOUT
A1
R1
08923-034
VREF
T1
RANGE
SCALING
If hardware mode is selected, the part powers up to the
conditions defined by the R3 to R0 bits and the status of the
OUTEN pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
R3
A2
VIN
In software SPI mode, the part powers up with the output
disabled (OUTEN bit = 0). The user must set the OUTEN bit in
the control register to enable the output and, in the same write,
set the output range configuration using the R3 to R0 bits.
Figure 33. Current Output Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 μF
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
POWER-ON STATE OF THE AD5749
On power-up, the AD5749 senses whether hardware or software
mode is loaded and sets the power-up conditions accordingly.
In software SPI mode, the output powers up in the tristate
condition (0 mA).
To put the part into normal operation, the user must set the
OUTEN bit in the control register to enable the output and, in
the same write, set the output range configuration using the R3
to R0 range bits. If the CLEAR pin is still high (active) during
this write, the part automatically clears to its normal clear state
as defined by the programmed range and by the CLRSEL pin or
the CLRSEL bit (see the Asynchronous Clear (CLEAR) section
for more details). The CLEAR pin must be taken low to operate
the part in normal mode.
The CLEAR pin is typically driven directly from a microcontroller.
In cases where the power supply for the AD5749 supply is
independent of the microcontroller power supply, the user can
connect a weak pull-up resistor to DVCC or a pull-down resistor
to ground to ensure that the correct power-up condition is
achieved independent of the microcontroller. A 10 kΩ pull-up/
pull-down resistor on the CLEAR pin should be sufficient for
most applications.
If hardware mode is selected, the part powers up to the conditions
defined by the R3 to R0 range bits and the status of the OUTEN
or CLEAR pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
In software mode, the part can be reset using the RESET pin
(active low) or the reset bit (reset = 1). A reset disables the
output to its power-on condition. The user must write to the
OUTEN bit to enable the output and, in the same write, set the
output range configuration. The RESET pin is a level sensitive
input; the part stays in reset mode as long as the RESET pin is
low. The reset bit clears to 0 following a reset command to the
control register.
In hardware mode, there is no reset. If using the part in
hardware mode, the RESET pin should be tied high.
OUTEN
In software mode, the output can be enabled or disabled using
the OUTEN bit in the control register. When the output is
disabled, it is placed into tristate. The user must set the OUTEN
bit to enable the output and simultaneously set the output range
configuration.
In hardware mode, the output can be enabled or disabled using
the OUTEN pin. When the output is disabled, it is placed into
tristate. The user must write to the OUTEN pin to enable the
output. It is recommended that the output be disabled when
changing the ranges.
SOFTWARE CONTROL
Software control is enabled by connecting the HW SELECT pin
to ground. In software mode, the AD5749 is controlled over a
versatile 3-wire serial interface that operates at clock rates up to
50 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and
DSP standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
The input shift register consists of 16 control bits, as shown in
Table 7. The timing diagram for this write operation is shown in
Figure 2. The first three bits of the input shift register are used to set
the hardware address of the AD5749 device on the printed circuit
board (PCB). Up to eight devices can be addressed per board.
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any
write sequence.
Rev. 0 | Page 18 of 28
AD5749
Table 7. Input Shift Register Contents for a Write Operation—Control Register
MSB
D15
A2
D14
A1
D13
A0
D12
R/W
D11
0
D10
R3
D9
R2
D8
R1
D7
R0
D6
CLRSEL
D5
OUTEN
D4
CLEAR
D3
RSET
D2
RESET
D1
0
LSB
D0
0
Table 8. Input Shift Register Descriptions for Control Register
Bit
A2, A1, A0
R/W
R3, R2, R1, R0
Description
Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system
controller.
A2
A1
A0
Function
0
0
0
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0.
0
0
1
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1.
0
1
0
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0.
0
1
1
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1.
1
0
0
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0.
1
0
1
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1.
1
1
0
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0.
1
1
1
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1.
Indicates a read from or a write to the addressed register.
Selects the output configuration in conjunction with RSET.
RSET
R3
R2
R1
R0
Output Configuration
0
0
0
0
0
4 mA to 20 mA (external 15 kΩ current sense resistor).
0
0
0
0
1
Unused command. Do not program.
0
0
0
1
0
0 mA to 24 mA (external 15 kΩ current sense resistor).
0
0
0
1
1
Unused command. Do not program.
0
0
1
0
0
Unused command. Do not program.
0
0
1
0
1
Unused command. Do not program.
0
0
1
1
0
Unused command. Do not program.
0
0
1
1
1
Unused command. Do not program.
0
1
0
0
0
Unused command. Do not program.
0
1
0
0
1
Unused command. Do not program.
0
1
0
1
0
Unused command. Do not program.
0
1
0
1
1
Unused command. Do not program.
0
1
1
0
0
Unused command. Do not program.
0
1
1
0
1
Unused command. Do not program.
0
1
1
1
0
Unused command. Do not program.
0
1
1
1
1
Unused command. Do not program.
1
0
0
0
0
4 mA to 20 mA (internal current sense resistor).
1
0
0
0
1
Unused command. Do not program.
1
0
0
1
0
0 mA to 24 mA (internal current sense resistor).
1
0
0
1
1
Unused command. Do not program.
1
0
1
0
0
Unused command. Do not program.
1
0
1
0
1
Unused command. Do not program.
1
0
1
1
0
Unused command. Do not program.
1
0
1
1
1
Unused command. Do not program.
1
1
0
0
0
Unused command. Do not program.
1
1
0
0
1
Unused command. Do not program.
1
1
0
1
0
Unused command. Do not program.
1
1
0
1
1
Unused command. Do not program.
1
1
1
0
0
Unused command. Do not program.
1
1
1
0
1
3.92 mA to 20.4 mA (internal current sense resistor).
1
1
1
1
0
Unused command. Do not program.
1
1
1
1
1
0 mA to 24.5 mA (internal current sense resistor).
Rev. 0 | Page 19 of 28
AD5749
Bit
CLRSEL
OUTEN
CLEAR
RSET
RESET
Description
Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section.
CLRSEL
Function
0
Clear to zero-scale.
1
Clear to midscale.
Output enable bit. This bit must be set to 1 to enable the output.
Software clear bit; active high.
Select internal/external current sense resistor.
RSET
Function
1
Select internal current sense resistor; used with R3 to R0 bits to select range.
0
Select external current sense resistor; used with R3 to R0 bits to select range.
Resets the part to its power-on state.
Rev. 0 | Page 20 of 28
AD5749
Readback Operation
HARDWARE CONTROL
Readback mode is activated by selecting the correct device address
(A2, A1, A0) and then setting the R/W bit to 1. By default, the
SDO pin is disabled. After having addressed the AD5749 for a
read operation, setting R/W to 1 enables the SDO pin and SDO
data is clocked out on the 5th rising edge of SCLK. After the data
has been clocked out on SDO, a rising edge on SYNC disables
(tristate) the SDO pin again. Status register data (see Table 9)
and control register data are both available during the same
read cycle.
Hardware control is enabled by connecting the HW SELECT
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins, in
conjunction with the RSET pin, are used to configure the
output range, as per Table 8.
The status bits comprise four read-only bits. They are used to
notify the user of specific fault conditions that occur, such as
an open circuit on the output, overtemperature error or an
interface error. If any of these fault conditions occur, a hardware
FAULT is also asserted low, which can be used as a hardware
interrupt to the controller.
See the Detailed Description of Features section for a full
explanation of fault conditions.
In hardware mode, there is no status register. The fault conditions
(open circuit, and overtemperature) are available on Pin IFAULT
and Pin TEMP. If any one of these fault conditions is set, a low is
asserted on the specific fault pin. IFAULT and TEMP are opendrain outputs and, therefore, can be connected together to allow the
user to generate one interrupt to the system controller to communicate a fault. If hardwired in this way, it is not possible to isolate
which fault occurred in the system.
TRANSFER FUNCTION
The AD5749 consists of an internal signal conditioning block
that maps the analog input voltage to a programmed output
range. The available analog input range is 0 V to 4.096 V.
For all ranges, the AD5749 implements a straight linear
mapping function, where 0 V maps to the lower end of the
selected range and 4.096 V maps to the upper end of the
selected range.
Table 9. Input Shift Register Contents for a Read Operation—Status Register
MSB
D15
A2
D14
A1
D13
A0
D12
1
D11
0
D10
R3
D9
R2
D8
R1
D7
R0
D6
CLRSEL
D5
OUTEN
D4
RSET
D3
PEC Error
D2
OVER TEMP
D1
IOUT Fault
LSB
D0
Unused
Table 10. Status Bit Options
Bit
PEC Error
OVER TEMP
IOUT Fault
Description
This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.
This bit is set if the AD5749 core temperature exceeds approximately 150°C.
This bit is set if there is an open circuit on the IOUT pin.
Rev. 0 | Page 21 of 28
AD5749
DETAILED DESCRIPTION OF FEATURES
OUTPUT FAULT ALERT—SOFTWARE MODE
•
In software mode, the AD5749 is equipped with one FAULT
pin; this is an open-drain output allowing several AD5749
devices to be connected together to one pull-up resistor for
global fault detection. In software mode, the FAULT pin is
forced active low by any one of the following fault scenarios:
ASYNCHRONOUS CLEAR (CLEAR)
•
•
•
The voltage at IOUT attempts to rise above the compliance
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with window
limits because this requires an actual output error before
the fault output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive capability. Thus, the fault output activates slightly before the
compliance limit is reached. Because the comparison is
made within the feedback loop of the output amplifier, the
output accuracy is maintained by its open-loop gain, and
an output error does not occur before the fault output
becomes active.
An interface error is detected due to the packet error
checking failure (PEC). See the Packet Error Checking
section.
The core temperature of the AD5749 exceeds approximately 150°C.
OUTPUT FAULT ALERT—HARDWARE MODE
In hardware mode, the AD5749 is equipped with two fault pins:
IFAULT and TEMP. These are open-drain outputs allowing
several AD5749 devices to be connected together to one pull-up
resistor for global fault detection. In hardware control mode,
these fault pins are forced active by any one of the following
fault scenarios:
•
An open-circuit is detected. The voltage at IOUT attempts
to rise above the compliance range, due to an open-loop
circuit or insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with window limits because this requires an
actual output error before the fault output becomes active.
Instead, the signal is generated when the internal amplifier
in the output stage has less than approximately 1 V of
remaining drive capability. Thus, the fault output activates
slightly before the compliance limit is reached. Because the
comparison is made within the feedback loop of the output
amplifier, the output accuracy is maintained by its openloop gain, and an output error does not occur before the
fault output becomes active. If this fault is detected, the
IFAULT pin is forced low.
The core temperature of the AD5749 exceeds approximately 150°C. If this fault is detected, the TEMP pin is
forced low.
CLEAR is an active high clear that allows the output to be
cleared to either zero-scale or midscale, and is user-selectable
via the CLRSEL pin or the CLRSEL bit of the input shift register,
as described in Table 8. (The clear select feature is a logical
OR function of the CLRSEL pin and the CLRSEL bit). When
the CLEAR signal is returned low, the output returns to its
programmed value or to a new programmed value. A clear
operation can also be performed via the clear command in
the control register.
Table 11. CLRSEL Options
CLRSEL
0
1
Output Clear Value
Zero scale; for example:
4 mA on the 4 mA to 20 mA range
0 mA on the 0 mA to 24 mA range
Midscale; for example:
12 mA on the 4 mA to 20 mA range
12 mA on the 0 mA to 24 mA range
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor and is
part of the voltage-to-current conversion circuitry. The nominal
value of the internal current sense resistor is 15 kΩ. To allow for
overrange capability in current mode, the user can also select
the internal current sense resistor to be 14.7 kΩ, giving a nominal
2% overrange capability. This feature is available in the 0 mA to
24 mA, and 4 mA to 20 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5749, which can be used instead of
the internal resistor. The external resistor is selected via the
input shift register. If the external resistor option is not used,
the REXT1 and REXT2 pins should be left floating.
PROGRAMMABLE OVERRANGE MODES
The AD5749 contains an overrange mode The overranges are
selected by configuring the R3, R2, R1, and R0 bits (or pins)
accordingly.
The overranges are typically 2%. For these ranges, the analog
input remains the same (0 V to 4.096 V).
Rev. 0 | Page 22 of 28
AD5749
PACKET ERROR CHECKING
UPDATE ON SYNC HIGH
SYNC
To verify that data has been received correctly in noisy
environments, the AD5749 offers the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5749 should generate an 8-bit frame check
sequence using the following polynomial:
SCLK
D15
(MSB)
D0
(LSB)
16-BIT DATA
SDIN
16-BIT DATA TRANSER—NO ERROR CHECKING
C(x) = x8 + x2 + x1 + 1
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SCLK
D23
(MSB)
SDIN
FAULT
D8
(LSB)
16-BIT DATA
D7
D0
8-BIT FCS
FAULT GOES LOW IF
ERROR CHECK FAILS
16-BIT DATA TRANSER WITH ERROR CHECKING
Figure 34. PEC Error Checking Timing
Rev. 0 | Page 23 of 28
08923-035
This is added to the end of the data-word, and 24 data bits are
sent to the AD5749 before taking SYNC high. If the AD5749
receives a 24-bit data frame, it performs the error check when
SYNC goes high. If the check is valid, then the data is written to
the selected register. If the error check fails, the FAULT pin goes
low and Bit D3 of the status register is set. After reading this
register, this error flag is cleared automatically and the FAULT
pin goes high again.
AD5749
APPLICATIONS INFORMATION
TRANSIENT VOLTAGE PROTECTION
THERMAL CONSIDERATIONS
The AD5749 contains ESD protection diodes that prevent damage
from normal handling. The industrial control environment can,
however, subject I/O circuits to much higher transients. To protect
the AD5749 from excessively high voltage transients, external
power diodes and a surge current limiting resistor may be
required, as shown in Figure 35. The constraint on the resistor
value is that during normal operation the output level at IOUT
must remain within its voltage compliance limit of AVDD −
2.75 V and the two protection diodes and resistor must have
appropriate power ratings. Further protection can be added
with transient voltage suppressors if needed.
It is important to understand the effects of power dissipation
on the package and how it affects junction temperature. The
internal junction temperature should not exceed 125°C. The
AD5749 is packaged in a 32-lead, 5 mm × 5 mm LFCSP package. The thermal impedance, θJA, is 28°C/W. It is important that
the devices not be operated under conditions that cause the
junction temperature to exceed its limit. Worst-case conditions
occur when the AD5749 is operated from the maximum AVDD
(55 V) and driving the maximum current (24 mA) directly to
ground. The quiescent current of the AD5749 should also be
taken into account, nominally ~4 mA.
The calculations in Table 12 estimate maximum power
dissipation under these worst-case conditions, and determine
maximum ambient temperature based on this. These figures
assume that proper layout and grounding techniques are
followed to minimize power dissipation, as outlined in the
Layout Guidelines section.
AVDD
AVDD
IOUT
RP
RLOAD
08923-036
AD5749
Figure 35. Output Transient Voltage Protection
Table 12. Thermal and Supply Considerations
Considerations
Maximum allowed power dissipation when operating at an ambient
temperature of 85°C
32-Lead LFCSP Package
Maximum allowed ambient temperature when operating from a supply of
55 V and driving 24 mA directly to ground (include 4 mA for internal AD5749
current)
Maximum allowed supply voltage when operating at an ambient
temperature of 85°C and driving 24 mA directly to ground
TJMAX − (PD × θJA) = 125 − ((55 × 0.028) × 28) = 81.8°C
Rev. 0 | Page 24 of 28
TJMAX − TA
θ JA
TJMAX − TA
AI DD × θ JA
=
=
125 − 85
= 1.42 W
28
125 − 85
= 51 V
(0.028 × 28 )
AD5749
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The PCB on which the AD5749 is
mounted should be designed so that the AD5749 lies on the
analog plane.
The AD5749 should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
corresponding thermal land paddle on the PCB (GND).
Thermal vias should be designed into the PCB land paddle area
to further improve heat dissipation.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 5.0 kV. The serial loading structure
of the AD5749 makes it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 37 shows a
4-channel isolated interface to the AD5749 using an ADuM1400.
For further information, visit http://www.analog.com/icouplers.
CONTROLLER
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power
to dissipate easily.
AD5749
ADuM14001
SERIAL
CLOCK OUT
VIA
SERIAL
DATA OUT
VIB
SYNC OUT
CONTROL OUT
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
1ADDITIONAL PINS OMITTED FOR CLARITY.
GND
PLANE
VOA
TO
SCLK
VOB
TO
SDIN
VOC
VOD
TO
SYNC
TO
CLEAR
08923-038
LAYOUT GUIDELINES
Figure 37. Isolated Interface
BOARD
08923-037
MICROPROCESSOR INTERFACING
Figure 36. Paddle Connection to Board
The AD5749 has an exposed paddle beneath the device.
Connect this paddle to the GND of the AD5749. For optimum
performance, special considerations should be used to design
the motherboard and to mount the package. For enhanced
thermal, electrical, and board level performance, the exposed
paddle on the bottom of the package should be soldered to the
Microprocessor interfacing to the AD5749 is via a serial bus that
uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (minimum)
interface consisting of a clock signal, a data signal, and a SYNC
signal. The AD5749 requires a 16-bit data-word with data valid
on the falling edge of SCLK.
Rev. 0 | Page 25 of 28
AD5749
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
17
16
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
32
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
011708-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5749ACPZ
AD5749ACPZ-RL7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Package Option
CP-32-2
CP-32-2
AD5749
NOTES
Rev. 0 | Page 27 of 28
AD5749
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08923-0-7/10(0)
Rev. 0 | Page 28 of 28