ALSC AS29F040-55LI 5v 512k x 8 cmos flash eeprom Datasheet

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VCC
VSS
DQ0–DQ7
Erase voltage
generator
Input/output
buffers
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
Program/erase
control
Command
register
Program voltage
generator
STB
Chip enable
Output enable
Logic
CE
OE
STB
VCC detector
Timer
Data latch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AS29F040
32-pin TSOP
Y decoder
Address latch
WE
Sector protect
switches
X decoder
Y gating
Cell matr
A0–A18
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A7
5
29
A14
A6
6
28
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE
A1
11
23
A10
A0
12
22
CE
DQ0
13
21
DQ7
32-pin PLCC
A12
A16
A15
4
3
2
VCC
A17
A18
WE
1
32 31 30
AS29F040
14 15 16 17 18 19 20
VSS
DQ1
DQ2
DQ4
DQ3
DQ6
DQ5
6HOHFWLRQ#JXLGH
AS29F040-55
AS29F040-70
AS29F040-90
AS29F040-120 AS29F040-150 Unit
Maximum access time
tAA 55
70
90
120
150
ns
Maximum chip enable access time
tCE 55
70
90
120
150
ns
Maximum output enable access time
tOE 25
30
35
50
55
ns
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Copyright ©2000 Alliance Semiconductor. All rights reserved.
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• Organization:512K words × 8 bits
• Industrial and commercial temperature
• Sector architecture
- Eight 64K byte sectors
- Erase any combination of sectors or full chip
• Single 5.0±0.5V power supply for read/write operations
• Sector protection
• High speed 55/70/90/120/150 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified
address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• 10,000 write/erase cycle endurance
• Low power consumption
- 30 mA maximum read current
- 60 mA maximum program current
- 400 µA typical standby current
• JEDEC standard software, packages and pinouts
- 32-pin TSOP
- 32-pin PLCC
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
• Erase suspend/resume
- Supports reading data from or programming data to
a sector not being erased
• Low VCC write lock-out below 2.8V
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The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an
program capability, the 4 megabits of data is divided into eight 64K-byte sectors. The ×8 data appears on DQ0–DQ7. The
AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an
erased in-system with a single 5.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers.
The AS29F040 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high-speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls
The AS29F040 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register
use standard microprocessor write timings. An internal state machine uses register contents to control the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data
operates from the device in the same manner as other Flash or EPROM devices. The program command sequence is used to invoke
the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin.
The erase command sequence is used to invoke the automated on-chip erase algorithm that preprograms the sector if it is not
already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors.
A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in
any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase
operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will
automatically erase all unprotected sectors.
A factory shipped AS29F040 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the
array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase
returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.
The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate
voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during
power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The
device automatically resets to read mode after program and/or erase operations are completed.
The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits the alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program and/or erase commands disabled when VCC is less than V LKO (lockout
voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical
zero and OE a logical one to initiate write commands.
The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programme
one at a time using the EPROM programming mechanism of hot electron injection.
5
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CE
OE
WE
A0
A1
A6
A9
DQ0-DQ7
ID read MFR code
L
L
H
L
L
L
VID
Code
ID read device code
L
L
H
H
L
L
VID
Code
Read
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
High Z
Output disable
L
H
H
X
X
X
X
High Z
Write
L
H
L
A0
A1
A6
A9
DIN
Enable sector protect
L
VID
Pulse/L
L
H
L
VID
X
Sector unprotect
L
VID
Pulse/L
L
H
H
VID
X
Verify sector protect
L
L
H
L
H
L
VID
Code
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Mode
L = Low (<VIL); H = High (>V IH); VID = 12.0 ± 0.5V; X = don’t car .
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Item
Description
ID MFR code,
device code
Selected by A9 = VID(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (VIH), DOUT represents the device code for the AS29F040.
Read mode
Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low
and tOE after OE is low.
Standby
Selected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input levels and <100 µA
for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation
before entering standby.
Output disable Part remains powered up; but outputs disabled with OE pulled high.
Write
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Enable
sector protect
Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors.
Sector
unprotect
Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection.
Verify
sector protect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A16–18 select the defined sector addresses.
A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
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Equal sector architecture
ID sector address
Addresses
Size (Kbytes)
A18
A17
A16
0
00000h–0FFFFh
64
0
0
0
1
10000h–1FFFFh
64
0
0
1
2
20000h–2FFFFh
64
0
1
0
3
30000h–3FFFFh
64
0
1
1
4
40000h–4FFFFh
64
1
0
0
5
50000h–5FFFFh
64
1
0
1
6
60000h–6FFFFh
64
1
1
0
7
70000h–7FFFFh
64
1
1
1
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Sector
5($'#FRGHV
Mode
A18–A16
A9
A8–A7
A6
A5–A2
A1
A0
Code on DQ0–DQ7
MFG code (Alliance
Semiconductor)
X
VID
X
L
X
L
L
52h
Device code
X
VID
X
L
X
L
H
A4h
Sector protection
Sector
address
VID
Sector
address
L
Sector
address
H
L
01h protected
00h unprotected
L = Low (<VIL); H = High (>VIH); X = Don’t care.
&RPPDQG#IRUPDW
Command
sequence
Required
bus cycles
1st bus write
cycle
Address
2nd bus write
cycle
Data
Address
Data
Read
Data
55h
Reset/read
1
XXXXh
F0h
Read
Address
Reset/read
4
5555h
AAh
2AAAh
Autoselect ID
read
4
5555h
AAh
2AAAh
55h
3rd bus write
cycle
4th bus read/write
cycle
Address
Data
Address
Data
5555h
F0h
Read
Address
Read
Data
00h
MFR code
52h
01h
Device code
A4h
5555h
90h
XXX02h
Sector
protection
4
5555h
AAh
2AAAh
55h
5555h
A0h
Program
Address
Program
Data
Chip erase
6
5555h
AAh
2AAAh
55h
5555h
80h
5555h
AAh
6
5555h
AAh
Sector erase
suspend
1
XXXXh
B0h
Sector erase
resume
1
XXXXh
30h
1
2
3
4
5
6
2AAAh
55h
5555h
80h
5555h
Address
6th bus write
cycle
Data
Address
Data
55h
5555h
10h
55h
Sector
Address
30h
01 = protected
00 = unprotected
Program
Sector erase
5th bus write
cycle
AAh
2AAAh
2AAAh
Bus operations defined in "Mode definitions," on page 3.
Reading from or programming to non-erasing sectors allowed in Erase Suspend mode.
Address bit A15 = X = Don’t care for all address commands except Program Address.
Address bit A16 = X = Don’t care for all address commands except Program Address and Sector Address.
Address bit A17 = X = Don’t care for all address commands except Program Address and Sector Address.
Address bit A18 = X = Don’t care for all address commands except Program Address and Sector Address.
7
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Description
Reset/read
Initiate read or reset operations by writing the read/reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode
until command register contents are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no
spurious memory content alterations during power up.
AS29F040 provides manufacturer and device codes in two ways. External PROM programmers typically
access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read
the device code with only +5V, since multiplexing +12V on address lines is generally undesirable.
ID read
Initiate device ID read by writing the ID read command sequence into the command register. Follow
with a read sequence from address XXX00h to return MFG code. Follow ID read command sequence
with a read sequence from address XXX01h to return device code.
To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A16 produc e a1
on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command sequence.
Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two
unlock write cycles precede the program setup command and program data write cycle. Upon
execution of the program command, no additional CPU controls or timings are necessary. Addresses are
latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or
WE, whichever is first. The AS29F040’s automated on-chip program algorithm provides adequate
internally-generated programming pulses and verifies the programmed cell margin.
Byte/word
programming
Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The
AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to
complete the programming operation.
The AS29F040 ignores commands written during the programming operation.
AS29F040 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1
requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded
programming time limits); reading this data after a read/reset operation returns a 0. When
programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset
command returns the device to read mode.
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock
write cycles; and finally the Chip erase command.
Chip erase
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Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase
algorithm is invoked with the Chip erase command sequence, AS29F040 automatically programs and
verifies the entire memory array for an all-zero pattern prior to erase. The AS29F040 returns to read
mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.
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Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock
write cycles, and finally the sector erase command. Identify the sector to be erased by addressing any
location in the sector. The address is latched on the falling edge of WE; the command, 30h, is latched
on the rising edge of WE. The sector erase operation begins after a 80 µs time-out.
Sector erase
To erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase
after following the six bus cycle operation above. Timing between writes of additional sectors must be
<80 µs, or the AS29F040 ignores the command and erasure begins. During the erase time-out period
any falling edge of WE resets the time-out. Any command (other than sector erase or erase suspend)
during the time-out period resets the AS29F040 to read mode, and the device ignores the sector erase
command string. Erase such ignored sectors by restarting the sector erase command on the ignored
sectors.
The entire array need not be written with 0s prior to erasure. AS29F040 writes 0s to the entire sector
prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors
unaffected. AS29F040 requires no CPU control or timing signals during sector erase operations.
Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector erase
command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling must be performed
on addresses that fall within the sectors being erased. AS29F040 returns to read mode after sector erase
unless DQ5 is set high by exceeding the time limit.
Erase suspend allows interruption of sector erase operations to perform data reads from or writes to
a sector not being erased. Erase suspend applies only during sector erase operations, including the timeout period. Writing an erase suspend command during sector erase time-out results in immediate
termination of the time-out period and suspension of erase operation.
AS29F040 ignores any commands during erase suspend other than read/reset, program, or erase
resume commands. Writing the Erase Resume command continues erase operations. Addresses are
DON’T CARE when writing Erase suspend or Erase resume commands.
Erase suspend
AS29F040 takes 0.2–15 µs to suspend erase operations after receiving erase suspend command. To
determine completion of erase suspend, check DQ6 after selecting an address of a sector not being
erased. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F040
ignores redundant writes of erase suspend.
While in erase-suspend mode AS29F040 allows reading data (erase-suspend-read mode) from or
programming data (erase-suspend-program mode) to any sector not undergoing sector erase, treated as
standard read or standard programming mode. AS29F040 defaults to erase-suspend-read mode while
an erase operation has been suspended.
Write the resume command 30h to continue operation of sector erase. AS29F040 ignores redundant
writes of the resume command. AS29F040 permits multiple suspend/resume operations during sector
erase.
Sector protect
9
When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for
about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are
activated for about <5 µs. In both cases, the device returns to read mode without altering the specified
sectors.
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Active during automated on-chip algorithms or sector time outs. DQ6 toggles when CE or OE toggles,
or an Erase Resume command is invoked. When the automated on-chip algorithm is complete, DQ6
stops toggling and valid data can be read. DQ6 is valid after the rising edge of the fourth pulse of WE
Toggle bit 1 (DQ6)
during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising
edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during
writes, and <5 µs during erase (if all selected sectors are protected).
Exceeding time
limit (DQ5)
Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains
active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are
defective; during sector erase, the sector is defective (in this case, reset the device and execute
a program or erase command sequence to continue working with functional sectors); during byte
programming, that particular byte is defective. Attempting to program 0 to 1 will set DQ5 = 1.
Sector erase timer
(DQ3)
Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will
be accepted. If DQ3 = 0, the device will accept additional sector erase commands. Check DQ3 before
and after each Sector Erase command to verify that the command was accepted.
During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased.
During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector
Toggle bit 2 (DQ2)
addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction
with DQ6 to determine whether device is in auto erase or erase suspend mode.
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In progress
DQ7
DQ6
DQ5
DQ3
DQ2
Auto programming (byte)
DQ7
Toggle
0
0
No toggle
Program/erase in auto erase
0
Toggle
0
1
Toggle*
Read erasing sector
1
No toggle
0
0
Toggle
Read non-erasing
sector
Data
Data
Data
Data
Data
Program in erase
suspend
DQ7
Toggle
0
0
Toggle*
Auto programming (byte)
DQ7
Toggle
1
0
No toggle
Program/erase in auto erase
0
Toggle
1
1
Toggle†
Program in erase suspend
DQ7
Toggle
1
0
No toggle†
Erase
suspend
mode
Exceeded time limits
* Toggles with
† Toggles with
Status
OE or CE only for erasing or erase suspended sector addresses.
OE or CE only for erasing or erase suspended sector addresses.
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Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement
of data last written when read during the automated on-chip algorithm (0 during erase algorithm);
reflects true data when read after completion of an automated on-chip algorithm (1 after completion of
erase agorithm).
DATA polling
(DQ7)
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Write erase command sequence
(see below)
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Write program command sequence
(see below)
DATA polling or toggle bit
successfully completed
DATA poll device-program
Erase complete
Chip erase command sequence
Sector erase command sequence
5555h/AAh
5555h/AAh
2AAAh/55h
2AAAh/55h
5555h/80h
5555h/80h
5555h/A0h
5555h/AAh
5555h/AAh
Program address/program data
2AAAh/55h
2AAAh/55h
5555h/10h
Sector address/30h
Programming completed
Program command sequence
5555h/AAh
2AAAh/55h
Sector address/30h
Optional multiple
sector erase commands*
Sector address/30h
*
;
The system software should check the status of DQ3 prior to and
following each subsequent sector erase command to ensure command
completion. The device may not have accepted the command if DQ3 is
high on second status check.
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START
Read byte (DQ0–DQ7)
Address = VA *
Read byte (DQ0–DQ7)
two times with OE toggling
Address = don’t care
Does
DQ6
toggle?
YES DONE
DQ7 =
data?
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START
NO DONE
NO
NO
Is time
elapsed = 1ms?
YES
NO
YES
NO
DQ5 = 1?
YES
YES
Read byte (DQ0–DQ7)
Address = VA *
DQ7†=
data ?
DQ5 = 1?
Read byte (DQ0–DQ7)
two times with OE toggling
Address = don’t care
Does
DQ6
toggle*?
YES DONE
NO
DONE
NO
Issue Reset/read
command
Addr = X
Data = F0h
YES
DONE
Issue Reset/read
command
Addr = X
Data = F0h
*
VA = Byte address for programming. VA = any of the sector addresses
within the sector being erased during sector erase. VA = valid address
equals any non-protected sector group address during chip erase.
†
DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change
simultaneously.
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*
DONE
DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when
DQ5 changes to 1.
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Start
VA* = 0000h
Program byte with 00h
ADDR =VA
Is VA = VA_Start†?
YES
Increment VA
NO
Is VA = 7FFFFh?
NO
Program byte with 00h
ADDR = VA
Increment VA
YES
Reset VA = 0000
Verify data
ADDR = VA
Program byte with customer data
ADDR =VA
NO
Verify OK?
NO
Increment VA
Is
FAIL
VA = VA_End**?
YES
YES
NO
Increment VA
IncrementVA
Is VA = VA_End?
YES
* VA = Current Address
† VA_Start = Starting Address
** VA_End
43
of Customer Code
= Ending Address of Customer Code
PASS
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9&&# #813±3189
Symbol
Test conditions
Min
Max
Unit
Input load current
ILI
VIN = VSS to VCC, VCC = VCC MAX
-
±1
µA
A9 Input load current
ILIT
VCC = VCC MAX, A9 = 12.5V
90
µA
ILO
VOUT = VSS to VCC, VCC = VCC MAX
-
±1
µA
IOS
VOUT = 0.5V
-
200
mA
ICC
CE = VIL, OE = VIH
-
30
mA
Active current, program/erase
ICC2
CE = VIL, OE = VIH
-
60
mA
Standby current (TTL)
ISB1
CE = OE = VIH, VCC = VCC MAX
-
1.0
mA
Standby current (CMOS)
ISB2
CE = VCC + 0.5V, OE = VIH,
VCC = VCC MAX
-
400
µA
Input low voltage
VIL
-0.5
0.8
V
Input high voltage
VIH
2.0
VCC + 0.5
V
Output low voltage
VOL
IOL = 12mA, VCC = VCC MIN
-
0.45
V
VOH1
IOH = -2.5 mA, V CC = VCC MIN
2.4
-
V
VOH2
IOH = -100 µA, VCC = VCC MIN
VCC - 0.4
-
V
Output leakage current
Output short circuit current
*
†
Active current, read @ 6MHz
**
Output high voltage
Low VCC lock out voltage
VLKO
2.8
4.2
V
Input HV select voltage
VID
11.5
12.5
V
*
Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems
caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.)
†
The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is
less than 2 mA/MHz with OE at VIH.
**
ICC active while program or erase operations are in progress.
0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP
20 ns
20 ns
20 ns
+0.8V
-0.5V
-2.0V
0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP
VCC + 2.0V
VCC + 0.5V
+ 2.0V
20 ns
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20 ns
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-70
-90
-120
-150
JEDEC
Symbol
Std
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tAVAV
tRC
Read cycle time
55
-
70
-
90
-
120
-
150
-
ns
tAVQV
tACC
Address to output delay
-
55
-
70
-
90
-
120
-
150
ns
tELQV
tCE
Chip enable to output
-
55
-
70
-
90
-
120
-
150
ns
tGLQV
tOE
Output enable to output
-
25
-
30
-
35
-
50
-
55
ns
tEHQZ
tDF
Chip enable to output High Z
-
15
-
20
-
20
-
30
-
35
ns
tGHQZ
tDF
Output enable to output High Z
-
15
-
20
-
20
-
30
-
35
ns
tAXQX
tOH
Output hold time from addresses,
CE or OE, whichever occurs first
0
-
0
-
0
-
0
-
0
-
ns
.H\#WR#VZLWFKLQJ#ZDYHIRUPV
Rising input
Falling input
Undefined / don’t care
5HDG#ZDYHIRUP
tRC
Addresses stable
Addresses
tACC
CE
tDF
tOE
OE
WE
tOH
tCE
Outputs
45
High Z
Output valid
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-55
-70
-90
-120
-150
Std
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tAVAV
tWC
Write cycle time
55
-
70
-
90
-
120
-
150
-
ns
tAVWL
tAS
Address setup time
0
-
0
-
0
-
0
-
0
-
ns
tWLAX
tAH
Address hold time
40
-
45
-
45
-
50
-
50
-
ns
tDVWH
tDS
Data setup time
25
-
30
-
45
-
50
-
50
-
ns
tWHDX
tDH
Data hold time
0
-
0
-
0
-
0
-
0
-
ns
tOES
Output enable setup time
0
-
0
-
0
-
0
-
0
-
ns
tOEH
Output enable hold time:
Toggle and DATA polling
10
-
10
-
10
-
10
-
10
-
ns
tGHWL
tGHWL
Read recover time before write
0
-
0
-
0
-
0
-
0
-
ns
tELWL
tCS
CE setup time
0
-
0
-
0
-
0
-
0
-
ns
tWHEH
tCH
CE hold time
0
-
0
-
0
-
0
-
0
-
ns
tWLWH
tWP
Write pulse width
35
-
35
-
45
-
50
-
50
-
ns
tWHWL
tWPH
Write pulse width high
20
-
20
-
20
-
20
-
20
-
ns
tWHWH1
tWHWH1
Programming pulse time
15
-
15
-
15
-
15
-
15
-
µs
tWHWH2
tWHWH2
Erase operation
0.3
-
0.3
-
0.3
-
0.3
-
0.3
-
sec
:ULWH#ZDYHIRUP
:(#FRQWUROOHG
3rd bus cycle
tAS
tWC
5555h
Addresses
DATA polling
Program address
Program address
tAH
tCH
CE
tGHWL;tOES
OE
tWP
WE
DATA
tCS
tWHWH1 or 2
tWPH
tDH
A0h
tDS
Program
data
DQ7
DOUT
VSS
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-70
-90
-120
-150
JEDEC
Symbol
Std
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tAVAV
tWC
Write cycle time
55
-
70
-
90
-
120
-
150
-
ns
tAVEL
tAS
Address setup time
0
-
0
-
0
-
0
-
0
-
ns
tELAX
tAH
Address hold time
40
-
45
-
45
-
50
-
50
-
ns
tDVEH
tDS
Data setup time
25
-
30
-
45
-
50
-
50
-
ns
tEHDX
tDH
Data hold time
0
-
0
-
0
-
0
-
0
-
ns
tOES
Output enable setup time
0
-
0
-
0
-
0
-
0
-
ns
tOEH
Output enable hold time:
Toggle and DATA polling
10
-
10
-
10
-
10
-
10
-
ns
tGHEL
tGHEL
Read recover time before
write
0
-
0
-
0
-
0
-
0
-
ns
tWLEL
tWS
WE setup time
0
-
0
-
0
-
0
-
0
-
ns
tEHWH
tWH
WE hold time
0
-
0
-
0
-
0
-
0
-
ns
tELEH
tCP
CE pulse width
35
-
35
-
45
-
50
-
50
-
ns
tEHEL
tCPH
CE pulse width high
20
-
20
-
20
-
20
-
20
-
ns
tWHWH1
tWHWH1
Programming pulse time
15
-
15
-
15
-
15
-
15
-
µs
tWHWH2
tWHWH2
Erase operation
0.3
-
0.3
-
0.3
-
0.3
-
0.3
-
sec
:ULWH#ZDYHIRUP#5
&(#FRQWUROOHG
DATA polling
Addresses
5555h
Program address
tWC
tAS
Program address
tAH
WE
tGHEL, tOES
OE
tWH
tCP
CE
tCPH
tWS
DATA
tWHWH1 or 2
tDH
A0h
Program
data
DQ7
DOUT
tDS
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Addresses
tAS
5555h
2AAAh
5555h
5555h
2AAAh
Sector address
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tAH
CE
tGHWL
OE
tWP
tWC
WE
tWPH
tCS
10h for Chip Erase
tDH
Data
AAh
55h
80h
AAh
55h
30h
tDS
'$7$#SROOLQJ#ZDYHIRUP
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
DQ7
Output DQ7
Input DQ7
Output
High Z
tWHWH1 or 2
7RJJOH#ELW#ZDYHIRUP
CE
tOEH
WE
OE
DQ6
tDH
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Limits
)/$6+
Parameter
Min
Typical
Max
Unit
Sector erase and verify-1 time (excludes 00h programming prior to erase)
-
1.0
-
sec
Byte program time
-
45
-
µs
Chip programming time
-
23
-
sec
Erase/program cycles
-
-
10,000
cycles
/DWFKXS#WROHUDQFH#
Parameter
Min
Max
Unit
Input voltage with respect to VSS on A9 and OE
-1.0
+13.0
V
Input voltage with respect to VSS on all DQ, address and control pins
-1.0
VCC+1.0
V
Current
-100
+100
mA
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
$&#WHVW#FRQGLWLRQV
Test condition
Device under Test
100 pF*
Output load
VSS
*including scope
and jig capacitance
Unit
1 TTL gate
Input rise and fall times
5
ns
0.0-3.0
V
Input timing measurement reference levels
1.5
V
Output timing measurement reference levels
1.5
Input pulse levels
$EVROXWH#PD[LPXP#UDWLQJV
Parameter
Symbol
Min
Max
Unit
Input voltage (Input or DQ pin)
VIN
–2.0
+7.0
V
Input voltage (A9 pin, OE)
VIN
–2.0
+13.0
V
Power supply voltage
VCC
-0.5
+5.5
V
Operating temperature
TOPR
–55
+125
°C
Storage temperature (plastic)
TSTG
–65
+125
°C
Short circuit output current
IOUT
-
200
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
49
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Parameter
Supply voltage
Min
Typ
Max
Unit
VCC
+4.5
5.0
+5.5
V
VSS
0
0
0
V
VIH
2.0
-
VCC + 0.5
V
VIL
–0.5
-
0.8
V
7623#SLQ#FDSDFLWDQFH
Symbol
Parameter
Test setup
Typ
Max
Unit
CIN
Input capacitance
VIN = 0
6
7.5
pF
COUT
Output capacitance
VOUT = 0
8.5
12
pF
CIN2
Control pin capacitance
VIN = 0
7.5
9
pF
3/&&#SLQ#FDSDFLWDQFH
Symbol
Parameter
Test setup
Typ
Max
Unit
CIN
Input capacitance
VIN = 0
6
7.5
pF
COUT
Output capacitance
VOUT = 0
8.5
12
pF
CIN2
Control pin capacitance
VIN = 0
7.5
9
pF
'DWD#UHWHQWLRQ
Parameter
Minimum pattern data retention time
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Temp. (°C)
Min
Unit
150°
10
years
125°
20
years
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Input voltage
Symbol
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1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
32-pin TSOP
9
j
g
24
10
23
11
12
22
21
13
20
14
15
19
a
b
c
d
e
f
g
h
i
j
18
16
17
e
i
f
d
a
0–5°
a
b
c
4
3
2
1
b
32
31
30
5
29
6
28
7
27
8
a
b
c
d
e
f
g
h
i
j
32-pin PLCC
typical (inch)
0.49
0.45
0.59
0.55
0.52
0.09
0.136
0.075
0.52
0.028
JEDEC outline
Body size
Package thickness
Board standoff
Lead pitch
Coplanarity
MS-016 AE
0.450 in. × 0.550 in.
0.110 in.
0.020 in. (min)
0.050 in.
0.004 in. (max)
26
32-pin PLCC
9
d
25
10
j
32-pin TSOP
min
max
(mm) (mm)
1.20
0.25
0.5
0.7
0.1
0.21
18.30 18.50
19.80 20.20
7.90
8.10
0.95
1.05
0.05
0.15
0.50
c
e
24
11
23
12
22
13
21
14
15
16
17
18
19
20
h
g
f
i
$65<)373#RUGHULQJ#FRGHV55ns
70 ns
(commercial/industrial) (commercial/industrial)
90 ns
(commercial/industrial)
120 ns
(commercial/industrial)
150 ns
(commercial/industrial)
TSOP, 8×20 mm, 32-pin
AS29F040-55TC
AS29F040-55TI
AS29F040-70TC
AS29F040-70TI
AS29F040-90TC
AS29F040-90TI
AS29F040-120TC
AS29F040-120TI
AS29F040-150TC
AS29F040-150T
PLCC, 0.55×0.45”, 32-pin
AS29F040-55LC
AS29F040-55LI
AS29F040-70LC
AS29F040-70LI
AS29F040-90LC
AS29F040-90LI
AS29F040-120LC
AS29F040-120LI
AS29F040-150LC
AS29F040-150LI
Package \ Access time
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AS29F
Flash EEPROM prefix
040
Device number
–XXX
Address access time
X
Package:
X
L= PLCC
T= TSOP
Temperature range:
C = Commercial: 0°C to 70°C
I = Industrial: -40°C to 85°C
* Industrial and Commercial temperature range available
4;
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as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
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