Cypress CY7C1350G 4-mbit (128 k x 36) pipelined sram with noblâ ¢ architecture Datasheet

CY7C1350G
4-Mbit (128 K × 36) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Byte write capability
■
128 K × 36 common I/O architecture
■
3.3 V power supply (VDD)
■
2.5 V / 3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 2.8 ns (for 200-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable (OE)
■
Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
■
Burst capability – linear or interleaved burst order
■
“ZZ” sleep mode option
The CY7C1350G is a 3.3 V, 128 K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Logic Block Diagram
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWA
BWB
BWC
BWD
MEMORY
ARRAY
WRITE
DRIVERS
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05524 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 25, 2013
CY7C1350G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Document Number: 38-05524 Rev. *N
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
Product Status ........................................................... 19
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 2 of 22
CY7C1350G
Selection Guide
Description
200 MHz
2.8
265
40
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
4.0
225
40
Unit
ns
mA
mA
Pin Configurations
VSS
CLK
WE
CEN
OE
ADV/LD
91
90
89
88
87
86
85
A
VDD
92
A
CE3
93
81
BWA
94
82
BWB
95
83
BWC
96
NC/18M
BWD
97
NC/9M
CE2
98
84
A
CE1
99
A
1
80
DQC
2
79
3
DQB
DQC
78
VDDQ
4
DQB
77
5
VDDQ
VSS
76
DQC
6
VSS
75
7
DQB
DQC
74
DQC
8
DQB
73
9
DQB
DQC
72
10
DQB
VSS
71
VDDQ
11
VSS
70
12
VDDQ
DQC
69
DQC
13
DQB
68
NC
14
DQB
67
VDD
15
VSS
66
NC
NC
16
65
VSS
17
64
VDD
ZZ
DQD
18
63
19
DQA
DQD
62
VDDQ
20
DQA
61
21
VDDQ
VSS
60
DQD
22
VSS
59
23
DQA
DQD
58
DQD
24
DQA
57
DQD
25
DQA
56
26
DQA
VSS
55
27
VSS
VDDQ
54
28
VDDQ
DQD
53
DQD
29
DQA
52
DQPD
30
DQA
51
DQPA
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC/72M
NC/36M
A
A
A
A
A
A
A
CY7C1350G
A
MODE
31
BYTE D
DQPC
A
BYTE C
100
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout[1]
DQPB
BYTE B
BYTE A
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 20.
Document Number: 38-05524 Rev. *N
Page 3 of 22
CY7C1350G
Pin Configurations (continued)
Figure 2. 119-Ball BGA (14 × 22 × 2.4 mm) pinout[2]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
4
5
6
7
VDDQ
A
A
NC/18M
A
A
VDDQ
NC/576M
CE2
A
A
VSS
A
VSS
CE3
A
DQPB
NC
A
DQPC
ADV/LD
VDD
NC
A
NC/1G
DQC
NC
DQB
DQC
DQC
VSS
CE1
VSS
DQB
DQB
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
VSS
VSS
NC/9M
BWB
VSS
VSS
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
DQD
VDDQ
DQD
DQD
BWD
VSS
BWA
VSS
DQA
DQA
DQA
VDDQ
DQD
DQD
VSS
CEN
A1
VSS
DQA
DQA
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
NC/144M
A
MODE
VDD
NC
A
NC/288M
NC
NC/72M
A
A
A
NC/36M
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
WE
VDD
CLK
NC
Note
2. Errata: The ZZ ball (T7) needs to be externally connected to ground. For more information, see "Errata" on page 20.
Document Number: 38-05524 Rev. *N
Page 4 of 22
CY7C1350G
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D]
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ[3]
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQPX are placed in a tristate condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQP[A:D]
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE
VDD
VDDQ
Input
strap pin
Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
Power supply Power supply inputs to the core of the device.
I/O power
supply
VSS
Ground
NC
–
Power supply for the I/O circuitry.
Ground for the device.
No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address
expansion pins in this device and will be used as address pins in their respective densities.
Note
3. Errata: The ZZ pin needs to be externally connected to ground. For more information, see "Errata" on page 20.
Document Number: 38-05524 Rev. *N
Page 5 of 22
CY7C1350G
Functional Overview
a burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
The CY7C1350G is a synchronous-pipelined burst SRAM
designed specifically to eliminate wait states during write/read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 2.8 ns (200-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[A:D] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Write Accesses
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus, provided OE is active LOW. After
the first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (read/write/deselect) can
be initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tristate following the next clock rise.
Burst Read Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW in order to load a new address into the SRAM, as
described in the Single Read Accesses section above. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enables inputs or WE. WE is latched at the beginning of
Document Number: 38-05524 Rev. *N
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:D]. In addition, the address for the subsequent access
(read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device and
the write is complete.
The data written during the write operation is controlled by
BW[A:D] signals. The CY7C1350G provides byte write capability
that is described in the Write Cycle Description table. Asserting
the write enable input (WE) with the selected byte write select
(BW[A:D]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte write capability
has been included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1350G is a common I/O device, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP[A:D] inputs. Doing so will tristate the
output drivers. As a safety precaution, DQs and DQP[A:D] are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW[A:D] inputs must be
driven in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Page 6 of 22
CY7C1350G
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
10
11
00
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD  0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to snooze current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit snooze current This parameter is sampled
0
–
ns
Document Number: 38-05524 Rev. *N
Page 7 of 22
CY7C1350G
Truth Table
The Truth Table for part CY7C1350G is as follows. [4, 5, 6, 7, 8, 9, 10]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
H
L
L
X
X
X
L
L–H
Tristate
Continue deselect cycle
None
X
L
H
X
X
X
L
L–H
Tristate
Read cycle (begin burst)
External
L
L
L
H
X
L
L
L–H Data out (Q)
Next
X
L
H
X
X
L
L
L–H Data out (Q)
External
L
L
L
H
X
H
L
L–H
Tristate
Next
X
L
H
X
X
H
L
L–H
Tristate
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
External
L
L
L
L
L
X
L
L–H
Data in (D)
Write cycle (continue burst)
Next
X
L
H
X
L
X
L
L–H
Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
L
L
L
H
X
L
L–H
Tristate
WRITE ABORT (continue burst)
Next
X
L
H
X
H
X
L
L–H
Tristate
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tristate
IGNORE CLOCK EDGE (stall)
SNOOZE MODE
Notes
4. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
5. Write is defined by BWX, and WE. See Write Cycle Descriptions table.
6. When a write cycle is detected, all DQs are tri-stated, even during byte writes.
7. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. CEN = H, inserts wait states.
9. Device will power-up deselected and the DQs in a tristate condition, regardless of OE.
10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tristate when OE is
inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
Document Number: 38-05524 Rev. *N
Page 8 of 22
CY7C1350G
Partial Truth Table for Read/Write
The Partial Truth Table for read or write for part CY7C1350G is as follows. [11, 12, 13]
WE
BWD
BWC
BWB
BWA
Read
Function
H
X
X
X
X
Write no bytes written
L
H
H
H
H
Write byte A(DQA and DQPA)
L
H
H
H
L
Write byte B(DQB and DQPB)
L
H
H
L
H
Write bytes A, B
L
H
H
L
L
Write byte C (DQC and DQPC)
L
H
L
H
H
Write bytes C, A
L
H
L
H
L
Write bytes C, B
L
H
L
L
H
Write bytes C, B, A
L
H
L
L
L
Write byte D(DQD and DQPD)
L
L
H
H
H
Write bytes D, A
L
L
H
H
L
Write bytes D, B
L
L
H
L
H
Write bytes D, B, A
L
L
H
L
L
Write bytes D, C
L
L
L
H
H
Write bytes D, C, A
L
L
L
H
L
Write bytes D, C, B
L
L
L
L
H
Write all bytes
L
L
L
L
L
Notes
11. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
12. Write is defined by BWX, and WE. See Write Cycle Descriptions table.
13. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done on which byte write is active.
Document Number: 38-05524 Rev. *N
Page 9 of 22
CY7C1350G
DC input voltage  0.5 V to VDD + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature 65 °C to +150 °C
Ambient temperature with
power applied 55 °C to +125 °C
Supply voltage on VDD relative to GND  0.5 V to +4.6 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage on VDDQ relative to GND 0.5 V to +VDD
Range
DC voltage applied to outputs
in tristate  0.5 V to VDDQ + 0.5 V
Commercial
Ambient
Temperature (TA)
VDD
VDDQ
0 °C to +70 °C
3.3 V – 5% /
+ 10%
2.5 V – 5%
to VDD
Industrial
40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [14, 15]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
Output HIGH voltage
VOL
VIH
VIL
IX
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O, IOH =1.0 mA
Output LOW voltage
for 3.3 V I/O, IOL=8.0 mA
for 2.5 V I/O, IOL=1.0 mA
Input HIGH voltage [14]
VDDQ = 3.3 V
VDDQ = 2.5 V
Input LOW voltage [14]
VDDQ = 3.3 V
VDDQ = 2.5 V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
Input current of MODE
Input = VSS
Input current of ZZ
IOZ
IDD
ISB1
ISB2
Test Conditions
Output leakage current
VDD operating supply current
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
Input = VDD
Input = VSS
Input = VDD
GND  VI  VDDQ, output disabled
VDD = Max., IOUT = 0 mA,
5-ns cycle,
f = fMAX = 1/tCYC
200 MHz
7.5-ns cycle,
133 MHz
VDD = Max, device deselected, 5-ns cycle,
VIN  VIH or VIN  VIL
200 MHz
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
VDD = Max, device deselected, All speeds
VIN  0.3 V or VIN > VDDQ – 0.3 V,
f=0
Min
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
5
Max
Unit
3.6
V
VDD
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3 V
V
VDD + 0.3 V
V
0.8
V
0.7
V
5
A
30
–
–5
–
5
–
–
5
–
30
5
265
A
A
A
A
A
mA
–
225
mA
–
110
mA
–
90
mA
–
40
mA
Notes
14. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05524 Rev. *N
Page 10 of 22
CY7C1350G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15]
Description
Automatic CE power-down
current – CMOS inputs
ISB3
ISB4
Automatic CE power-down
current – TTL inputs
Test Conditions
Min
Max
Unit
VDD = Max, device deselected, 5-ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 200 MHz
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
VDD = Max, device deselected, All speeds
VIN  VIH or VIN  VIL, f = 0
–
95
mA
–
75
mA
–
45
mA
Capacitance
Parameter [16]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
100-pin TQFP 119-ball BGA
Max
Max
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
Unit
5
5
pF
5
5
pF
5
7
pF
Thermal Resistance
Parameter [16]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 119-ball BGA
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
Unit
30.32
34.1
°C/W
6.85
14.0
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
RL = 50 
GND
5 pF
R = 351 
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1 ns
 1 ns
VT = 1.5 V
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
Z0 = 50 
(c)
(b)
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
RL = 50 
GND
5 pF
R =1538 
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
Z0 = 50 
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
16. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05524 Rev. *N
Page 11 of 22
CY7C1350G
Switching Characteristics
Over the Operating Range
Parameter [17, 18]
tPOWER
Description
VDD(typical) to the first access [19]
-200
-133
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
5.0
–
7.5
–
ns
tCH
Clock HIGH
2.0
–
3.0
–
ns
tCL
Clock LOW
2.0
–
3.0
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.8
–
4.0
ns
tDOH
Data output hold after CLK rise
1.0
–
1.5
–
ns
0
–
0
–
ns
–
2.8
–
4.0
ns
–
2.8
–
4.0
ns
0
–
0
–
ns
–
2.8
–
4.0
ns
tCLZ
Clock to low Z
[20, 21, 22]
[20, 21, 22]
tCHZ
Clock to high Z
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[20, 21, 22]
OE HIGH to output high Z
[20, 21, 22]
Setup Times
tAS
Address setup before CLK rise
1.2
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.2
–
1.5
–
ns
tWES
GW, BWX setup before CLK rise
1.2
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.2
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.2
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.2
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
0.5
–
ns
tWEH
GW, BWX hold after CLK rise
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
17. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
18. Test conditions shown in (a) of Figure 3 on page 11 unless otherwise noted.
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can
be initiated.
20. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 11. Transition is measured ±200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
tristate prior to low Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document Number: 38-05524 Rev. *N
Page 12 of 22
CY7C1350G
Switching Waveforms
Figure 4. Read/Write Timing [23, 24, 25]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BW[A:D]
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
23. For this waveform ZZ is tied LOW.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05524 Rev. *N
Page 13 of 22
CY7C1350G
Switching Waveforms (continued)
Figure 5. NOP, STALL, and DESELECT Cycles [26, 27, 28]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A5
tCHZ
D(A1)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
DON’T CARE
Q(A2)
D(A4)
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 6. ZZ Mode Timing [29, 30]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
29. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
30. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05524 Rev. *N
Page 14 of 22
CY7C1350G
Ordering Information
The following table contains only the list of parts that are currently available. If you do not see what you are looking for, contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
200
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY7C1350G-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1350G-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1350G-133BGXC
51-85115 119-ball BGA (14 × 22 × 2.4 mm) Pb-free
Commercial
CY7C1350G-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1350G-200AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
Ordering Code Definitions
CY
7
C
1350
G - XXX XX
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BG
A = 100-pin TQFP; BG = 119-ball BGA
Speed Grade: XXX = 133 MHz or 200 MHz
Process Technology: G  90 nm
Part Identifier: 1350 = PL, 128 Kb × 36 (4 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05524 Rev. *N
Page 15 of 22
CY7C1350G
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05524 Rev. *N
Page 16 of 22
CY7C1350G
Package Diagrams
Figure 8. 119-ball BGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05524 Rev. *N
Page 17 of 22
CY7C1350G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
EIA
Electronic Industries Alliance
mA
milliampere
I/O
Input/Output
mm
millimeter
JEDEC
Joint Electron Devices Engineering Council
ms
millisecond
NoBL
No Bus Latency
mV
millivolt
OE
Output Enable
nm
nanometer
SRAM
Static Random Access Memory
ns
nanosecond
TQFP
Thin Quad Flat Pack

ohm
TTL
Transistor-Transistor Logic
%
percent
WE
Write Enable
pF
picofarad
V
volt
W
watt
Document Number: 38-05524 Rev. *N
Symbol
Unit of Measure
Page 18 of 22
CY7C1350G
Errata
This section describes the Ram9 Sync/NoBL ZZ pin, JTAG and Chip Enable issues. Details include trigger conditions, the devices
affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have
further questions.
Part Numbers Affected
Density & Revision
4Mb-Ram9 NoBL™ SRAMs: CY7C135*G
Package Type
Operating Range
All packages
Commercial/
Industrial
Product Status
All of the devices in the Ram9 4Mb Sync/NoBL family are qualified and available in production quantities.
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync/NoBL family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
Document Number: 38-05524 Rev. *N
Page 19 of 22
CY7C1350G
Document History Page
Document Title: CY7C1350G, 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
224380
See ECN
RKF
New data sheet.
*A
276690
See ECN
VBL
Updated Ordering Information (Changed TQFP package to Pb-free TQFP
package, added comment of BGA Pb-free package availability below the
table).
*B
332895
See ECN
SYT
Changed status from Preliminary to Final.
Updated Features (Removed 225 MHz and 100 MHz frequencies related
information).
Updated Selection Guide (Removed 225 MHz and 100 MHz frequencies
related information).
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 119-ball BGA Package as per JEDEC standards).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, removed 225 MHz and 100 MHz frequencies related information).
Updated Thermal Resistance (Replaced TBD’s for JA and JC to their
respective values).
Updated Switching Characteristics (Removed 225 MHz and 100 MHz
frequencies related information).
Updated Ordering Information (By removing Shaded Parts, changed the
package name for 100-pin TQFP from A100RA to A101, removed comment
on the availability of BGA Pb-free package).
*C
351194
See ECN
PCI
Updated Ordering Information (Updated part numbers).
*D
419264
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 15 (Changed test condition
from VDDQ < VDD to VDDQ < VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams.
*E
419705
See ECN
RXU
Updated Features (Added 100 MHz frequency related information).
Updated Selection Guide (Added 100 MHz frequency related information).
Updated Electrical Characteristics (Added 100 MHz frequency related
information).
Updated Switching Characteristics (Added 100 MHz frequency related
information).
*F
480368
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*G
2896584
03/20/2010
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagrams.
*H
3053085
10/08/2010
NJY
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*I
3211361
03/31/2011
CS
Updated Ordering Information (Added CY7C1350G-133BGXC part number).
*J
3353361
08/24/2011
PRIT
Updated Functional Description (Updated Note as “For best practices
recommendations, refer to SRAM System Design Guidelines.” and referred the
note in same place in this section).
Updated Package Diagrams.
Document Number: 38-05524 Rev. *N
Page 20 of 22
CY7C1350G
Document History Page (continued)
Document Title: CY7C1350G, 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
Orig. of
Change
Rev.
ECN No.
Issue Date
*K
3590312
05/10/2012
*L
3753416
09/24/2012
PRIT
Updated Package Diagrams (spec 51-85115 (Changed revision from *C to
*D)).
*M
3990978
05/04/2013
PRIT
Added Errata.
*N
4039645
06/25/2013
PRIT
Added Errata Footnotes.
Updated in new template.
Document Number: 38-05524 Rev. *N
Description of Change
NJY / PRIT Updated Features (Removed 250 MHz, 166 MHz and 100 MHz frequencies
related information).
Updated Functional Description (Removed the Note “For best practices
recommendations, refer to SRAM System Design Guidelines.”).
Updated Selection Guide (Removed 250 MHz, 166 MHz and 100 MHz
frequencies related information).
Updated Functional Overview (Removed 250 MHz, 166 MHz and 100 MHz
frequencies related information).
Updated Electrical Characteristics (Removed 250 MHz, 166 MHz and 100 MHz
frequencies related information).
Updated Switching Characteristics (Removed 250 MHz, 166 MHz and
100 MHz frequencies related information).
Page 21 of 22
CY7C1350G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
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cypress.com/go/interface
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cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
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USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05524 Rev. *N
Revised June 25, 2013
Page 22 of 22
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this
document may be the trademarks of their respective holders.