NSC DS75162AN Ieee-488 gpib transceiver Datasheet

DS75160A/DS75161A/DS75162A
IEEE-488 GPIB Transceivers
General Description
Features
This family of high-speed-Schottky 8-channel bi-directional
transceivers is designed to interface TTL/MOS logic to the
IEEE Standard 488-1978 General Purpose Interface Bus
(GPIB). PNP inputs are used at all driver inputs for minimum
loading, and hysteresis is provided at all receiver inputs for
added noise margin. The IEEE-488 required bus termination
is provided internally with an active turn-off feature which
disconnects the termination from the bus when VCC is removed.
The General Purpose Interface Bus is comprised of 16 signal lines Ð 8 for data and 8 for interface management. The
data lines are always implemented with DS75160A, and the
management lines are either implemented with DS75161A
in a single-controller system, or with DS75162A in a multicontroller system.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
8-channel bi-directional non-inverting transceivers
Bi-directional control implemented with TRI-STATEÉ
output design
Meets IEEE Standard 488-1978
High-speed Schottky design
Low power consumption
High impedance PNP inputs (drivers)
500 mV (typ) input hysteresis (receivers)
On-chip bus terminators
No bus loading when VCC is removed
Pin selectable open collector mode on DS75160A driver outputs
Accommodates multi-controller systems
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/5804 – 15
Order Number DS75162AWM, DS75162AN
See NS Package Number M24B or N24B
Dual In-Line Package
TL/F/5804 – 1
Top View
Order Number DS75160AN or DS75160AWM
See NS Package Number M20B or N20A
TL/F/5804 – 16
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/5804
Order Number DS75161AN or DS75161AWM
See NS Package Number M20B or N20B
RRD-B30M36/Printed in U. S. A.
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DS75160A/DS75161A/DS75162A IEEE-488 GPIB Transceivers
February 1996
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC, Supply Voltage
Supply Voltage, VCC
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 4 sec.)
Maximum Power Dissipation* at 25§ C
Molded Package
TA, Ambient Temperature
IOL, Output Low Current
Bus
Terminal
7.0V
5.5V
b 65§ C to a 150§ C
260§ C
Min
4.75
Max
5.25
Units
V
0
70
§C
48
16
mA
mA
1897 mW
*Derate molded package 15.2 mW/§ C above 25§ C.
Electrical Characteristics (Notes 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
VIK
Input Clamp Voltage
VHYS
Input Hysteresis
Bus
VOH
High-Level
Output Voltage
Terminal
IOH e b800 mA
2.7
3.5
Bus (Note 5)
IOH e b5.2 mA
2.5
3.4
Low-Level
Output Voltage
Terminal
IOL e 16 mA
0.3
0.5
Bus
IOH e 48 mA
0.4
0.5
VI e 5.5V
0.2
100
VI e 2.7V
0.1
20
b 10
b 100
mA
3.0
3.7
V
VOL
IIH
High-Level
Input Current
IIL
Low-Level
Input Current
VBIAS
Terminator Bias
Voltage at Bus Port
ILOAD
Terminator
Bus Loading
Current
2
II e b18 mA
Terminal and
TE, PE, DC,
SC Inputs
b 0.8
400
VI e 0.5V
Driver
Disabled
II(bus) e 0 (No Load)
VI(bus) e b1.5V to 0.4V
VI(bus) e 0.4V to 2.5V
Bus
Driver
Disabled
V
2.5
500
0
ICC
CIN
Short-Circuit
Output Current
Supply Current
Bus-Port
Capacitance
Terminal
V
2.5
b 3.2
VI(bus) e 3.7V to 5V
0
2.5
VI(bus) e 5V to 5.5V
0.7
2.5
Bus (Note 5)
40
b 15
b 35
b 75
b 35
b 75
b 150
Transmit, TE e 2V, PE e 2V, VI e 0.8V
85
125
Receive, TE e 0.8V, PE e 2V, VI e 0.8V
70
100
DS75161A
TE e 0.8V, DC e 0.8V, VI e 0.8V
84
125
DS75162A
TE e 0.8V, DC e 0.8V, SC e 2V, VI e 0.8V
85
125
Bus
VCC e 5V or 0V, VI e 0V to 2V,
f e 1 MHz
20
30
DS75160A
V
mA
b 3.2
VI(bus) e 2.5V to 3.7V
VI e 2V, VO e 0V (Note 4)
V
mV
b 1.3
VCC e 0V, VI(bus) e 0V to 2.5V
IOS
b 1.5
mA
mA
mA
mA
pF
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the 0§ C to a 70§ C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA e 25§ C and VCC e 5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: This characteristic does not apply to outputs on DS75161A and DS75162A that are open collector.
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2
Switching Characteristics VCC e 5.0V g 5%, TA e 0§ C to 70§ C (Note 1)
Symbol
Parameter
From
To
Conditions
DS75160A
DS75161A
DS75162A
Units
Min Typ Max Min Typ Max Min Typ Max
tPLH
Propagation Delay Time,
Low to High Level Output
tPHL
Propagation Delay Time,
High to Low Level Output
tPLH
Propagation Delay Time,
Low to High Level Output
tPHL
Propagation Delay Time,
High to Low Level Output
tPZH
Output Enable Time
to High Level
tPHZ
Output Disable Time
From High Level
tPZL
Output Enable Time
to Low Level
tPLZ
Output Disable Time
From Low Level
tPZH
Output Enable Time
to High Level
tPHZ
Output Disable Time
From High Level
tPZL
Output Enable Time
to Low Level
tPLZ
Output Disable Time
From Low Level
tPZH
Output Pull-Up Enable
Time (DS75160A Only)
tPHZ
Output Pull-UP Disable
Time (DS75160A Only)
Terminal Bus
Bus
VL e 5.0V
RL e 240X
Terminal
CL e 30 pF
Figure 2
VI e 3.0V
VL e 0V
RL e 480X
CL e 15 pF
Figure 1
TE, DC,
or SC
(Note 2)
(Note 3)
TE, DC,
or SC
Bus
VI e 0V
VL e 2.3V
RL e 38.3X
CL e 15 pF
Figure 1
VI e 3.0V
VL e 0V
RL e 3 kX
CL e 15 pF
Terminal Figure 1
VI e 0V
VL e 5V
RL e 280X
CL e 15 pF
Figure 1
(Note 2)
(Note 3)
PE
(Note 2)
VL e 2.3V
RL e 38.3X
CL e 30 pF
Figure 1
Bus
VI e 3V
VL e 0V
RL e 480X
CL e 15 pF
Figure 1
10
20
10
20
10
20
ns
14
20
14
20
14
20
ns
14
20
14
20
14
20
ns
10
20
10
20
10
20
ns
19
32
23
40
23
40
ns
15
22
15
25
15
25
ns
24
35
28
48
28
48
ns
17
25
17
27
17
27
ns
17
33
18
40
18
40
ns
15
25
22
33
22
33
ns
25
39
28
52
28
52
ns
15
27
20
35
20
35
ns
10
17
NA
NA
ns
10
15
NA
NA
ns
Note 1: Typical values are for VCC e 5.0V and TA e 25§ C and are meant for reference only.
Note 2: Refer to Functional Truth Tables for control input definition.
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the VI voltage source when the output
connected to that input becomes active.
Switching Load Configurations
TL/F/5804 – 8
VC logic high e 3.0V
VC logic low e 0V
VC logic high e 3.0V
*CL includes jig and probe capacitance
VC logic low e 0V
FIGURE 1
TL/F/5804 – 9
*CL includes jig and probe capacitance
FIGURE 2
3
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Connection Diagrams (Continued)
Dual-In-Line Package
TL/F/5804 – 2
Top View
Dual-In-Line Package
TL/F/5804 – 3
Top View
Order Number DS75161AN, DS75162AN or DS75161AWM
See NS Package Number M20B, N20A or N22A
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4
Functional Description
Logic Diagrams
DS75160A
DS75160A
This device is an 8-channel bi-directional transceiver with
one common direction control input, denoted TE. When
used to implement the IEEE-488 bus, this device is connected to the eight data bus lines, designated DIO1 –DIO8. The
port connections to the bus lines have internal terminators,
in accordance with the IEEE-488 Standard, that are deactivated when the device is powered down. This feature guarantees no bus loading when VCC e 0V. The bus port outputs also have a control mode that either enables or disables the active upper stage of the totem-pole configuration. When this control input, denoted PE, is in the high
state, the bus outputs operate in the high-speed totem-pole
mode. When PE is in the low state, the bus outputs operate
as open collector outputs which are necessary for parallel
polling.
DS75161A
This device is also an 8-channel bi-directional transceiver
which is specifically configured to implement the eight management signal lines of the IEEE-488 bus. This device,
paired with the DS75160A, forms the complete 16-line interface between the IEEE-488 bus and a single controller instrumentation system. In compliance with the system organization of the management signal lines, the SRQ, NDAC,
and NRFD bus port outputs are open collector. In contrast
to the DS75160A, these open collector outputs are a fixed
configuration. The direction control is divided into three
groups. The DAV, NDAC, and NRFD transceiver directions
are controlled by the TE input. The ATN, SRQ, REN, and
IFC transceiver directions are controlled by the DC input.
The EOI transceiver direction is a function of both the TE
and DC inputs, as well as the logic level present on the ATN
channel. The port connections to the bus lines have internal
terminators identical to the DS75160A.
DS75162A
This device is identical to the DS75161A, except that an
additional direction control input is provided, denoted SC.
The SC input controls the direction of the REN and IFC
transceivers that are normally controlled by the DC input on
the DS75161A. This additional control function is instrumental in implementing multiple controller systems.
Table of Signal Line Abbreviations
Signal Line
Classification
Control
Signals
Mnemonic
Definition
DC
Direction Control
PE
TE
Pull-Up Enable
Talk Enable
SC
System Controller
B1–B8 Bus Side of Device
D1–D8 Terminal Side
of Device
ATN
Attention
DAV
Data Valid
EOI
End or Identify
Management
IFC
Interface Clear
Signals
NDAC Not Data Accepted
Data
I/O Ports
NRFD
REN
SRQ
Device
DS75161A/
DS75162A
DS75160A
All
DS75162A
TL/F/5804 – 4
DS75160A
DS75161A/
DS75162A
Not Ready for Data
Remote Enable
Service Request
5
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Logic Diagrams (Continued)
DS75161A
DS75162A
TL/F/5804–5
TL/F/5804 – 6
TL/F/5804 – 7
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6
Switching Waveforms
Transmit Propagation Delays
TL/F/5804 – 10
Receive Propagation Delays
TL/F/5804 – 11
Terminal Enable/Disable Times
TL/F/5804 – 12
Bus Enable/Disable Times
TL/F/5804 – 13
*Input signal: f e 1.0 MHz, 50% duty cycle, tr e tf s 5 ns
Performance Characteristics
Bus Port Load Characteristics
TL/F/5804 – 14
Refer to Electrical Characteristics table
7
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Functional Truth Tables
DS75160A
Control Input
Level
Data Transceivers
TE
PE
Direction
Bus Port Configuration
H
H
L
H
L
X
T
T
R
Totem-Pole Output
Open Collector Output
Input
DS75161A
Control Input Level
TE
DC
H
H
L
L
H
L
H
L
H
L
X
X
X
X
H
L
Transceiver Signal Direction
ATN*
EOI REN IFC SRQ NRFD NDAC DAV
R
T
R
T
R
T
R
T
H
H
L
L
R
T
R
T
T
R
T
R
R
R
T
T
R
R
T
T
T
T
R
R
T
R
R
T
DS75162A
Control Input Level
SC
TE
DC
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
L
X
X
X
X
H
L
Transceiver Signal Direction
ATN*
EOI REN IFC SRQ NRFD NDAC DAV
R
T
R
T
R
T
R
T
H
H
L
L
T
T
T
T
R
R
R
R
T
T
T
T
R
R
R
R
T
R
T
R
T
R
T
R
R
R
T
T
R
R
T
T
R
R
T
T
R
R
T
T
T
T
R
R
T
T
R
R
T
R
R
T
H e High level input
L e Low level input
X e Don’t care
T e Transmit, i.e., signal outputted to bus
R e Receive, i.e., signal outputted to terminal
*The ATN signal level is sensed for internal multiplex control of EOI transmission direction logic.
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8
Physical Dimensions inches (millimeters)
Order Number DS75160AWM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DS75160AN or DS75161AN
NS Package Number N20A
9
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DS75160A/DS75161A/DS75162A IEEE-488 GPIB Transceivers
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DS75162AN
NS Package Number N22A
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