Cypress CY25402SXC-XXX Two pll programmable clock generator with spread spectrum Datasheet

CY25402
CY25422
PRELIMINARY
Two PLL Programmable Clock Generator
with Spread Spectrum
Features
Benefits
• Two fully integrated phase-locked loops (PLLs)
• Input Frequency range:
— External crystal: 8 to 48 MHz
— External reference: 8 to 166 MHz clock
• Wide operating output frequency range
— 3 to 166 MHz
• Programmable Spread Spectrum modulation frequency
range of 30 to 120 kHz with Lexmark profile
• Center Spread: ±0.125% to ±2.5%
• Down Spread: –0.25% to –5%
• Frequency select feature with option to select four different
frequencies
• Low-jitter, high-accuracy outputs
• Up to three clock outputs
• Programmable output drive strength
• Glitch-free outputs while frequency switching
• Four independent output voltages: 3.3V, 3.0V, 2.5V, and
1.8V
• 8-pin SOIC package
• Commercial and Industrial temperature range
• Multiple high-performance PLLs allow synthesis of
unrelated frequencies
• Nonvolatile programming for customized PLL frequencies,
spread spectrum characteristics, drive strength, crystal load
capacitance, and output frequencies
• Two Spread Spectrum capable PLLs with Lexmark profile
for maximum for EMI reduction
• Spread Spectrum PLLs can be disabled or enabled
separately
• PLLs can be programmed for system frequency margin
tests
• Meets critical timing requirements in complex system
designs
• Suitable for PC, consumer, and networking applications
• Ability to synthesize standard frequencies with ease
• Application compatibility in standard and low-power
systems
Block Diagram
XIN
XOUT
FS0
OSC
Output
Dividers
and
Drive
Strength
Control
PLL1
(SS)
MUX
and
Control
Logic
CLK1
CLK2
CLK3
FS1
PLL2
(SS)
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12565 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 02, 2007
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CY25402
CY25422
PRELIMINARY
Pin Configuration
XIN
1
8
XOUT
VDD
2
7
GND
CLK1
3
6
CLK3/SSON
CLK2/FS0
4
5
PD#/OE/FS1
8 LD SOIC
Pin Description - Memory Programmable 2-PLL device with 2 Spread Spectrum PLLs
Pin Number
Name
I/O
Description
1
XIN
Input
Crystal or Clock Input
2
VDD
Power
Power Supply
3
CLK1
Output
Programmable Clock Output
4
CLK2/FS0
Output/input
Programmable Clock Output or FS0
5
PD#/OE/FS1
Input
Power Down, Output Enable or FS1
6
CLK3/SSON
Output/Input
Programmable Clock Output or SSON
7
GND
Power
Power Supply Ground
8
XOUT
Output
Crystal Output
General Description
The CY25402 and CY25422 are two PLL programmable
Spread Spectrum Clock Generators used to reduce EMI found
in high-speed digital electronic systems. Both PLLs have
Spread Spectrum capability. The spread spectrum feature are
turned on or off using the control pin SSON.
The advantage of having two PLLs is that a single device can
generate up to two independent frequencies from a single
crystal or reference input frequency. Generally, a design
requires up to two oscillators to achieve the same result with
a single CY25402 or CY25422.
The device uses Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy significantly reduces the cost of complying with
regulatory agency (EMC) requirements and improves
time-to-market without degrading the system performance.
The CY25402 and CY25422 use a factory/field-programmable
configuration memory array to provide customization for
output frequencies, frequency select options, spread characteristics like spread percentage and modulation frequency,
output drive strength and crystal load capacitance. A
customized device are configured using CyberclocksTM
software or by contacting the factory.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range
Document #: 001-12565 Rev. *A
for center spread is from ±0.125% to ±2.50%. The range for
down spread is from –0.25% to –5.0%. Contact the factory for
smaller or larger spread percentage amounts, if required.
The input to the CY25402 and CY25422 is either a crystal or
a clock signal. The input frequency range for crystals is 8 MHz
to 48 MHz, and for clock signals is 8 MHz to 166 MHz.
The CY25402 and CY25422 have up to three clock outputs
and each output has three possible input sources.There are
two frequency select lines FS(1:0) that provide an option to
select four different sets of frequencies among the two PLLs.
Each output has programmable output divider options. Output
1 has eight possible divider values and outputs 2–3 have four
possible divider values for maximum flexibility. The 2 bit or 3
bit output dividers are programmable providing a wide output
frequency range.
The outputs are glitch-free when frequency is switched using
output dividers. The outputs have a predictable phase
relationship if the clock source is the same PLL and divider
values are 2, 3, 4, or 6.
The CY25402 and CY25422 are available in an 8-pin SOIC
package with commercial and industrial operating temperature
ranges.
Table 1. Supply Voltage Options
Device
VDD Supply Voltage
CY25402
CY25422
2.5V, 3.0V or 3.3V
1.8V
Page 2 of 8
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CY25402
CY25422
PRELIMINARY
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
4.5
V
VDD
Supply Voltage
VIN
Input Voltage
Relative to VSS
–0.5
TS
Temperature, Storage
Non Functional
–65
+150
°C
ESDHBM
ESD Protection (Human
Body Model)
MIL-STD-883, Method 3015
2000
–
Volts
UL-94
Flammability Rating
@1/8 in.
MSL
Moisture Sensitivity Level
SOIC package
–0.5
VDD + 0.5 VDC
V-0
1
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
3.0
–
Operating Voltage, 3.0V
2.7
–
3.3
V
Operating Voltage, 2.5V
2.25
–
2.75
V
VDD4
Operating Voltage, 1.8V
1.65
–
1.95
V
TAC
Commercial Ambient Temperature
TAI
Industrial Ambient Temperature
CLOAD
Max. Load Capacitance
tPU
Power-up time for all VDD pins to reach minimum specified voltage (power ramps must
be monotonic)
VDD1
Operating Voltage, 3.3V
VDD2
VDD3
Max. Unit
3.6
V
0
–
+70
°C
–40
–
+85
°C
–
–
15
pF
0.05
–
500
ms
DC Electrical Specifications
Parameter
Description
Conditions
VOL
Output Low Voltage, All CLK pins
All VDD levels, IOL = 8 mA
VOH
Output High Voltage, All CLK pins
All VDD levels, IOH = –8 mA
VIL
All Inputs except XIN
All VDD levels
VIH
All Inputs except XIN
All VDD levels
VILX
Input Low Voltage, clock input to XIN pin
All VDD levels
All VDD levels
Min.
Typ.
Max.
Unit
0
–
0.4
V
VDD – 0.4
–
VDD
V
–0.3
–
0.2 * VDD
V
0.8 * VDD
–
VDD + 0.3
V
–0.3
–
0.36
V
VIHX
Input High Voltage, clock input to XIN pin
1.44
–
2.0
V
IILPDOE
Input Low Current, PD#/OE and FS0,1 pins VIN = VSS
(Internal pull up = 100k typical)
–
–
10
μA
IIHPDOE
Input High Current, PD#/OE and FS0,1 pins VIN = VDD
(Internal pull up = 100k typical)
–
–
1
μA
IILSR
Input Low Current, SSON pin
VIN = VSS
(Internal pull down = 100k typical)
–
–
1
μA
IIHSR
Input High Current, SSON pin
VIN = VDD
(Internal pull down = 100k typical)
–
–
10
μA
IDD[1]
Supply Current
All clocks running, CL = 0
–
–
12
mA
CIN
Input Capacitance - All inputs except XIN
SSON, OE, PD# or FS inputs
–
–
7
pF
Note
1. Configuration dependent.
Document #: 001-12565 Rev. *A
Page 3 of 8
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CY25402
CY25422
PRELIMINARY
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ. Max. Unit
FIN (crystal)
Crystal Frequency
8
–
48
MHz
FIN (clock)
Input Clock Frequency (XIN)
8
–
166
MHz
FOUT
Output Clock Frequency
3
–
166
MHz
DC
Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2; t1/t2,
50% of VDD
45
50
55
%
DC
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
60
%
ER
CLK1-3 Rising Edge Rate
VDD = All, 20% to 80% VDD
0.8
–
–
V/ns
EF
CLK1-3 Falling Edge Rate
VDD = All, 20% to 80% VDD
0.8
–
–
V/ns
TCCJ1
Cycle-to-cycle Jitter
Configuration dependent. See Table 2
–
-
–
ps
TLTJ
Long Term Jitter
Configuration dependent. See Table 2
–
-
–
ns
T10
PLL Lock Time
–
–
3
ms
Table 2. Configuration Example for Jitter
Max Jitter (ps) on
Output 1(48MHz)
Max Jitter (ps) on Output 2
(27 MHz)
Max Jitter (ps) on
Output 3 (166 MHz)
TCCJ1
155
255
170
27MHz
TLTJ
770
580
630
48 MHz
TCCJ1
135
225
100
48 MHz
TLTJ
535
575
520
Reference
27MHz
Description
Recommended Crystal Specification for SMD Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum Frequency
8
14
28
MHz
Fmax
Maximum Frequency
14
28
48
MHz
R1(max)
Maximum Motional Resistance (ESR)
135
50
30
Ω
C0(max)
Maximum Shunt Capacitance
4
4
2
pF
CL(max)
Maximum Parallel Load Capacitance
18
14
12
pF
DL(max)
Maximum Crystal Drive Level
300
300
300
μW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Description
Range 1 Range 2 Range 3
Unit
Fmin
Minimum Frequency
8
14
24
MHz
Fmax
Maximum Frequency
14
24
32
MHz
R1(max)
Maximum Motional Resistance (ESR)
90
50
30
Ω
C0(max)
Maximum Shunt Capacitance
7
7
7
pF
CL(max)
Maximum Parallel Load Capacitance
DL(max)
Maximum Crystal Drive Level
Document #: 001-12565 Rev. *A
18
12
12
pF
1000
1000
1000
μW
Page 4 of 8
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CY25402
CY25422
PRELIMINARY
Test and Measurement Setup
Figure 1. Test and Measurement Setup
V DDs
0.1 μF
Outputs
C LOAD
DUT
GND
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
t1
t2
VDD
50% of VDD
Clock
Output
0V
Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
t3
t4
V DD
80% of VDD
Clock
Output
Document #: 001-12565 Rev. *A
20% of VDD
0V
Page 5 of 8
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PRELIMINARY
CY25402
CY25422
Ordering Information
Part Number[2]
Type
VDD(V)
Temperature Range
Lead-free
CY25402SXC-xxx
8-pin SOIC
3.3, 3.0 or 2.5
Commercial, 0°C to 70°C
CY25402SXC-xxxT
8-pin SOIC-Tape & Reel
3.3, 3.0 or 2.5
Commercial, 0°C to 70°C
CY25402FSXC
8-pin SOIC
3.3, 3.0 or 2.5
Commercial, 0°C to 70°C
CY25402FSXC
8-pin SOIC-Tape & Reel
3.3, 3.0 or 2.5
Commercial, 0°C to 70°C
CY25422SXC-xxx
8-pin SOIC
1.8
Commercial, 0°C to 70°C
CY25422SXC-xxxT
8-pin SOIC-Tape & Reel
1.8
Commercial, 0°C to 70°C
CY25422FSXC
8-pin SOIC
1.8
Commercial, 0°C to 70°C
CY25422FSXCT
8-pin SOIC-Tape & Reel
1.8
Commercial, 0°C to 70°C
CY25402SXI-xxx
8-pin SOIC
3.3, 3.0 or 2.5
Industrial, -40°C to +85°C
CY25402SXI-xxxT
8-pin SOIC-Tape & Reel
3.3, 3.0 or 2.5
Industrial, -40°C to +85°C
CY25402FSXI
8-pin SOIC
3.3, 3.0 or 2.5
Industrial, -40°C to +85°C
CY25402FSXIT
8-pin SOIC-Tape & Reel
3.3, 3.0 or 2.5
Industrial, -40°C to +85°C
CY25422SXI-xxx
8-pin SOIC
1.8
Industrial, -40°C to +85°C
CY25422SXI-xxxT
8-pin SOIC-Tape & Reel
1.8
Industrial, -40°C to +85°C
CY25422FSXI
8-pin SOIC
1.8
Industrial, -40°C to +85°C
CY25422FSXIT
8-pin SOIC-Tape & Reel
1.8
Industrial, -40°C to +85°C
Note
2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
F in the part number indicates field programmable using CyberClocks Online software.
Document #: 001-12565 Rev. *A
Page 6 of 8
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CY25402
CY25422
PRELIMINARY
Package Drawing and Dimensions
Figure 4. 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-12565 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY25402
CY25422
PRELIMINARY
Document History Page
Document Title: CY25402/CY25422 Two PLL Programmable Clock Generator
with Spread Spectrum
Document Number: 001-12565
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
690296
See ECN
RGL
New Data Sheet
*A
815788
See ECN
RGL
Minor Change: To post on web
Document #: 001-12565 Rev. *A
Description of Change
Page 8 of 8
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