CLARE CPC1465 Shdsl/isdn dc termination ic Datasheet

CPC1465
SHDSL/ISDN DC Termination IC
Features
Description
• Meets wetting (sealing) current requirements per
ITU-T G.991.2
• Integrated bridge rectifier for polarity correction
• Uses inexpensive opto-coupler for DC signalling
• Electronic inductor, breakover, and latch circuits
• Current limiting and excess power protection circuits
• ANSI SHDSL and ISDN compatible
• MLT and SARTS compatible
• Compatible with portable test sets
• Excellent linearity
• Compatible with GlobespanVirata and Conexant
SHDSL transceiver chip set families
• Small SOIC or DFN Package
• DFN package 60 percent smaller than SOIC
• SOIC is pin compatible with Agere LH1465AAE
The CPC1465 is a DC termination IC used in
Single-pair High-speed Digital Subscriber Line
(SHDSL) and Integrated Services Digital Network
subscriber line (ISDN) equipment. It provides a
polarity insensitive DSL loop sealing current DC
termination with a recognizable device signature for
MLT systems. The CPC1465 passes low frequency
ISDN network signalling information via an
inexpensive optocoupler to the NT1’s internal control
logic.
Ordering Information
Part Number Description
DC Termination IC, 16-pin SOIC in tubes,
47/tube
DC Termination IC, 16-pin SOIC tape and reel,
CPC1465DTR
1000/reel
DC Termination IC, 16-pin DFN in tubes,
CPC1465M
52/tube
DC Termination IC, 16-pin DFN tape and reel,
CPC1465MTR
1000/reel
CPC1465D
Applications
•
•
•
•
•
•
Router and bridge customer premises equipment
Leased line equipment
T1/E1 network line cards and repeaters
Network Termination 1 (NT1) equipment
Mechanized Loop Test (MLT) networks
Switched Access Remote Test System (SARTS)
networks
Figure 1. CPC1465 Typical 2-Wire DC Termination Application
dc
Blocking
Capacitor
CPC1465
1
TIP
RING
2.2kΩ
5%
4W
PR+
Electronic
Inductor,
Breakover,
Latch, and
Opto Driver
2
NC
3
NC
4
TIP
5
RING
6
NC
7
NC
8
PR-
Bridge
Rectifier
Current Limit
and Excess
Power Protection
TC
16
NC
15
NC
14
RS
13
PD
12
NC
11
NC
10
1μF
68.1Ω
1%
1/4W
Transceiver
COM
9
NOTE: Pinout is for the SOIC package
CPC1303
(5kVrms Isolation)
or
CPC1001N
(1500Vrms Isolation)
Pb
RoHS
2002/95/EC
DS-CPC1465 - R02
e3
1
4
2
3
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VCC
75kΩ
Digital
Control
Circuitr
1
CPC1465
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 DC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 AC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Transition Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Application Signalling Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 LED Trigger Characteristics During MLT Signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 LED Trigger Characteristics During Dial Test Set Signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
4
4
4
4
8
8
8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Surge Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Activation - On-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Deactivation - Off-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Photo-Diode (PD) Output Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 On-State Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Typical Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Over-Voltage Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
10
10
10
10
11
11
11
11
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Printed Circuit Board Layout Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
14
14
14
14
14
15
15
15
15
15
2
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R02
1. Specifications
1.1 Package Pinout
1.2 Pin Description
CPC1465D
SOIC
Pin
DFN
Pin
Name
Description
PR+
1
16 TC
1
1
PR+
Protection resistor positive side
NC
2
15 NC
2
2
NC
No connection
NC
3
14
NC
3
NC
No connection
TIP
4
13
RS
RING
5
12 PD
NC
6
11 NC
NC
7
10
NC
PR-
8
9
COM
4
CPC1465M
5
3
TIP
Tip lead
4
NC
No connection
5
NC
No connection
6
RING Ring lead
6
NC
No connection
7
7
NC
No connection
8
8
PR-
Protection resistor negative side
9
9
COM
Common
10
10
NC
No connection
11
11
NC
No connection
12
12
PD
Photo-diode (LED input current)
13
13
RS
Current limiting resistor
PR+
1
16 TC
NC
2
15 NC
14
14
NC
No connection
TIP
3
14
NC
15
15
NC
No connection
NC
4
13
RS
16
16
TC
Timing capacitor
NC
5
12 PD
RING
6
11 NC
NC
7
10
NC
PR-
8
9
COM
1.3 Absolute Maximum Ratings
Parameter
Minimum Maximum Unit
Maximum Voltage (T to R,
R to T)*
-
300
V
Power dissipation
-
1
W
-40
+85
°C
5
95
%
-40
+125
°C
Operating temperature
Operating relative humidity
Storage temperature
*Clare recommends the use of room-temperature-vulcanizing silicone RTV
sealant on the SOIC package tip and ring pins (pins 4 and 5) to guard
against the possibility of arcing.
Electrical absolute maximum ratings are at 25°C.
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
R02
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3
CPC1465
1.4 Electrical Characteristics
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements. Typical values are characteristic of the
device and are the result of engineering evaluations.
In addition, typical values are provided for
informational purposes only and are not part of the
testing requirements.
All electrical specifications are provided for TA=25°C
1.4.1 DC Characteristics, Normal Operation
For operational templates: (see Figure 2 on page 5) and (see Figure 3 on page 5).
Parameter
Conditions
Activate/Non-activate Voltage
Off State
Breakover current
-
Symbol
Minimum
Typical
Maximum
Unit
VAN
30.0
35.0
39.0
V
IBO
-
0.5
1
mA
DC Voltage drop
Active State, 1 mA ≤ ISL ≤ 20 mA
VON
-
12.5
15
V
DC leakage current
VOFF = 20 V
ILKG
-
1.5
5
μA
Hold/Release current
Active State
IH/R
0.1
0.5
1.0
mA
Minimum on current
VON < 54 V
IMIN1
20
38
-
mA
Minimum on current
54 V ≤ VON ≤ 100 V for 2 seconds,
source resistance 200 Ω to 4 kΩ
IMIN2
9.0
45
-
mA
Minimum on current
VON > 100 V
IMIN3
0
0.1
-
mA
Maximum on current
VON ≤ 70 V
IMAX1
-
38.4
70
mA
Maximum on current
VON > 70 V
IMAX2
-
-
V ON
----------1kΩ
mA
Photodiode drive current
Active State
IPD
0.2
0.3
10
mA
1.4.2 AC Characteristics, Normal Operation
For test conditions: (see Figure 4 on page 6) and (see Figure 5 on page 6).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
ac impedance
200 Hz to 50 kHz
ZMT
10
38
-
kΩ
Linearity distortion
f = 200 Hz to 40 kHz, ISL = 1 mA to
20 mA, VAPP ≤ 10.5 VPP
D1
75
78
-
dB
Linearity distortion
f = 200 Hz to 40 kHz, ISL = 1 mA to
20 mA, VAPP ≤ 12 VPP
D2
50
70
-
dB
1.4.3 Transition Characteristics, Normal Operation
For activation/deactivation test conditions: (see Figure 6 on page 7).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Activate time
(see Figure 7 on page 7)
t1
3.0
13
50
ms
Deactivate time
(see Figure 8 on page 7)
t2
3.0
-
100
ms
4
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Figure 2. I-V Requirements Template, 0 V to 50 V
1A
IMAX1
100 mA
VON
Current
10 mA
IMIN1
On State
VAN
1 mA
Transition
Region
100 μA
IHR
IBO
10 μA
1 μA
ILKG
Off State
Transition
Region
0
0
10
20
30
40
50
Absolute Voltage (V)
Figure 3. I-V Requirements Template, 0 V to 250 V
1A
70 V, 70 mA
IMAX1
100 mA
IMAX2
54 V, 9 mA
Current
10 mA
IMIN1
IMIN2
1 mA
100 μA
10 μA
1 μA
100 V, 0 mA
0
0
50
100
150
200
250
Absolute Voltage (V)
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CPC1465
Figure 4. Test Circuit for ac Impedance and Linearity
68 μF
DUT
Vmt
VAPP
ac generator
ISL
1 - 20 mA
dc current source
1k Ω
Vsig
1000 × V mt
Z mt = ---------------------------V sig
V mt
1000
Linearity = 20 log ---------------------------------------- + 20 log -----------V sig2ndHarmonic
67.5
Figure 5. Linearity Requirement Template
Acceptable
Linearity (dB)
75
Unacceptable
50
0
0
0.5
10.0
10.5
11.0
11.5
12.0
Applied ac Voltage (VPP)
6
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Figure 6. Test Circuit for Activate and Deactivate Times
1 μF
Pulse
generator
DUT
85 mH
85 Ω
Figure 7. Applied Waveform for Activation Test
43.5 V
40 V
Source Impedance
200 Ω to 4k Ω
t1
30 V
20 V
500 ms
10 V
Measure
0
Figure 8. Applied Waveform for Deactivation Test
2.0 mA
Current source limited to 30 V
Measure
1.5 mA
500 ms
1.0 mA
0.5 mA
t2
0
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CPC1465
1.5 Application Signalling Characteristics
These tests assume crowbar protection across the
CPC1465 limiting peak potentials to 250 V.
1.5.1 LED Trigger Characteristics During MLT Signalling
For test conditions: (see Figure 9 on page 9).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Applied ac Voltage
-
-
60
-
62
VPEAK
Applied ac frequency
-
-
2
-
3
Hz
Number of half-cycles applied
-
-
6
-
10
-
Total loop resistance
-
-
900
-
4500
Ω
-
-
-
1
-
-
Pulse width (opto on)
(see Figure 9 on page 9)
TON
10
-
-
ms
Pulse width (opto off)
(see Figure 9 on page 9)
TOFF
10
-
-
ms
Required opto-coupler response
Number of pulses per half-cycle applied
1.5.2 LED Trigger Characteristics During Dial Test Set Signalling
For test conditions: (see Figure 9 on page 9).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Applied dc battery Voltage
-
-
-43.5
-
-56
VDC
Frequency (pulses per second)
-
-
4
-
8
-
Percent break
-
-
40
-
60
%
Number of pulses
-
-
6
-
10
-
Total Loop Resistance
-
-
200
-
4000
Ω
-
-
-
1
-
-
Pulse width (opto on)
(see Figure 9 on page 9)
TON
10
-
-
ms
Pulse width (opto off)
(see Figure 9 on page 9)
TOFF
10
-
-
ms
Required opto-coupler response
Number of pulses per make/break
applied
8
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Figure 9. Test Circuit for LED Operation
RLOOP
200Ω - 4kΩ
900Ω - 4.5kΩ (MLT)
Series rotary dial
25Ω
1μF
VBAT
-43.5V to -56V
60VPEAK, 2 Hz - 3 Hz (MLT)
+
85Ω
85mH
25Ω
RING
Shunt rotary dial
TIP
CPC1465
1μF
1
PR+
TC
16
2
NC
NC
15
3
NC
NC
14
4
TIP
RS
13
5
RING
PD
12
1
4
6
NC
NC
11
2
3
7
2.2kΩ
5%
4W
8
NC
NC
10
PR-
COM
VCC
5V
68.1Ω
1%
1/4 W
CPC1001N
75kΩ
VOUT
9
NOTE: Pinout is for the SOIC package
Figure 10. Typical ISDN NT1 Application Diagram
CPC1465
TIP
RING
1
PR+
TC
16
2
NC
NC
15
3
NC
NC
14
4
TIP
RS
68.1Ω
1%
13 1/4 W
5
RING
PD
12
6
NC
NC
11
7
2.2kΩ
5%
4W 8
NC
NC
10
PR-
COM
1μF
VCC
5V
CPC1001N
3.6V
75kΩ
1
4
1μF
2
3
VOUT
9
NOTE: Pinout is for the SOIC package
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9
CPC1465
2. Functional Description
2.1 Introduction
The CPC1465 can be used for a number of designs
requiring a dc hold circuit such as SHDSL modem and
ISDN NT1 terminal applications. Typical SHDSL
applications will use a circuit design similar to the one
shown in Figure 10‚ “Typical ISDN NT1 Application
Diagram” on page 9 while the typical ISDN NT1 circuit
design will be similar to the one shown in Figure 10‚
“Typical ISDN NT1 Application Diagram” on page 9.
The DC Termination IC performs two functions in an
ISDN NT1 terminal; as an electronic inductor providing
a low impedance dc termination with a high
impedance ac termination, and second as part of the
dc signalling system for automated line testing
capability. The CPC1465 meets or exceeds the
requirements for an NT1 dc termination as described
in ANSI T1.601-1991.
Whereas the SHDSL modem application does not
have a signalling requirement, the signaling function
provides an excellent method to monitor for the loss of
sealing current. Generally, loss of sealing current in an
SHDSL application indicates loop loss.
As can be seen in the application circuit in Figure 1 on
page 1, CPC1465 designs require few external
components. For the most basic design, all that is
needed is a circuit protector, two resistors and a
capacitor.
2.2 Surge Protection
Although the CPC1465 is current limited, it is not an
over-voltage surge protector. To protect the CPC1465
against destructive over-voltage transients, Clare
recommends the use of a crowbar-type surge
protector that limits the surge voltage seen by the
CPC1465 to 250 V. The protection device must be
able to withstand the surge requirements specified by
the appropriate governing agency in regions where
the product will be deployed. Teccor, Inc. and Bourns,
Inc. make suitable surge protectors for most
applications. Devices such as Teccor’s P1800SC or
P2000SC Sidactors and Bourns’ TISP4220H3 or
TISP4240H3 thyristors should provide suitable
protection.
operational characteristics if the tip and ring leads are
reversed.
2.4 State Transitions
The dc tip to ring voltage-current characteristics of the
CPC1465 are shown in Figure 2‚ “I-V Requirements
Template, 0 V to 50 V”, and in Figure 3‚ “I-V
Requirements Template, 0 V to 250 V” on page 5.
Transition timings are illustrated in Figure 7‚ “Applied
Waveform for Activation Test”, and in Figure 8‚
“Applied Waveform for Deactivation Test”. The test
configuration for these timings is given in Figure 6‚
“Test Circuit for Activate and Deactivate Times”. All
timing figures are located on page 7.
State transition timings are set by the 1 μF capacitor
connected between the TC and COM pins.
2.4.1 Activation - On-State
Application of battery voltage to the loop causes the
CPC1465 to conduct whenever the voltage exceeds
approximately 35 V. With application of sufficient
voltage applied across the tip and ring terminals, the
CPC1465 will initially conduct a nominal 150 μA of
sealing current for approximately 20 ms prior to
activation. Once activated, the CPC1465 will remain in
the on state for as long as the loop current exceeds a
nominal 0.5 mA.
The CPC1465 turn-on timing circuit assures device
activation will occur within 50 ms of an applied voltage
greater than 43.5 V but not within the first 3 ms.
2.4.2 Deactivation - Off-State
While the CPC1465 activation protocol is based on an
initial minimum voltage level, deactivation is based on
a diminished sealing current level. Deactivation occurs
when the nominal sealing current level drops below
0.5 mA with guaranteed deactivation occurring for
sealing current levels less than 0.1 mA
The turn-off timing circuit deactivates the sealing
current hold circuit when 1 mA of sealing current has
been removed for 100 ms but ignores periods of loss
up to 3 ms.
2.3 Bridge Rectifier
The bridge rectifier in the CPC1465 ensures that the
device is polarity insensitive and provides consistent
10
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R02
2.5 Photo-Diode (PD) Output Behavior
Output from the PD pin provides a minimum of 0.2 mA
of photo-diode drive current for the opto-coupler LED
anytime sealing current exceeds 1 mA.
Because LED current is interrupted whenever loop
current is interrupted, the opto-coupler provides an
excellent means of indicating loop availability for
designs with a sealing current requirement.
2.6 On-State Behavior
2.6.1 Typical Conditions
On-state sealing current levels are determined by the
network’s power feed circuit and the loop’s dc
impedance. To compensate for low loop resistance or
very high loop voltage, the CPC1465 limits the
maximum sealing current to 70 mA.
The CPC1465 manages package power dissipation
by shunting excess sealing current through the 2.2 kΩ
4W power resistor located between the PR+ and PRpins.
2.6.2 Over-Voltage Conditions
Potentials in excess of 100 V applied to the tip and
ring interface will cause the CPC1465 to disable the
sealing current hold circuit and enter a standby state
with very little current draw. Once the over-voltage
condition is removed, the CPC1465 automatically
resumes normal operation.
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11
CPC1465
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 SOIC
10.160±0.381
(0.400±0.015)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
3. Sum of package height, standoff, and coplanarity does not exceed 2.108 (0.083).
PIN 16
10.363±0.127
(0.408±0.005)
7.493±0.127
(0.295±0.005)
PIN 1
1.270 TYP
(0.050 TYP)
2.108 MAX
(0.083 MAX)
See Note 3
0.406 TYP
(0.016 TYP)
8.890 TYP
(0.350 TYP)
0.635 X 45°
(0.025 X 45°)
1.016 TYP
(0.040 TYP)
Lead to Package Standoff:
MIN: 0.0254 (0.001)
MAX: 0.102 (0.004)
0.508±0.1016
(0.020±0.004)
0.254 ±0.0127
(0.010±0.0005)
DIMENSIONS
(mm)
inches
NOTE: The CPC1465 uses a slightly different package
than the LH1465AAE. Some adjustment to the
printed-circuit-board pad layout may be needed for
existing applications.
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R02
3.1.2 DFN
7.00 ± 0.25
(0.276 ± 0.01)
6.00 ± 0.25
(0.236 ± 0.01)
INDEX AREA
TOP VIEW
0.90 ± 0.10
(0.035 ± 0.004)
0.02, + 0.03, - 0.02
(0.0008, + 0.0012, - 0.0008)
1
SIDE VIEW
0.30 ± 0.05
(0.012 ± 0.002)
SEATING
PLANE
0.20
(0.008)
EXPOSED
METALLIC PAD
4.25 ± 0.05
(0.167 ± 0.002)
Terminal Tip
0.80
(0.032)
16
6.00 ± 0.05
(0.236 ± 0.002)
0.55 ± 0.10
(0.022 ± 0.004)
BOTTOM VIEW
Dimensions
mm
(inch)
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13
CPC1465
3.2 Printed Circuit Board Layout Pattern
3.2.1 SOIC
3.2.2 DFN
1.27
(0.050)
0.35
(0.014)
9.30
(0.366)
1.05
(0.041)
1.90
(0.075)
5.80
(0.228)
0.60
(0.024)
DIMENSIONS
mm
(inches)
0.80
(0.031)
DIMENSIONS
mm
(inches)
NOTE: As the metallic pad on the bottom of the DFN
package is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area.
3.3 Tape and Reel Packaging
3.3.1 SOIC
330.2 Dia
(13.00 Dia)
B0=10.70 + 0.15
(0.421 + 0.01)
Pin 1
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
W=16.00 + 0.30
(0.630 + 0.010)
Top Cover
Tape
K0=3.20 + 0.15
(0.193 + 0.01)
K1=2.70 + 0.15
(0.106 + 0.01)
Embossed
Carrier
Embossment
14
P=12.00
(0.47)
User Direction of Feed
A0=10.90 + 0.15
(0.429 + 0.010)
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
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R02
3.3.2 DFN
B0=7.24 + 0.10
(0.285 + 0.004)
330.2 Dia
(13.00 Dia)
Pin 1
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
W=16.00 + 0.30
(0.630 + 0.012)
P=12.00 + 0.10
(0.472 + 0.004)
K0=1.61 + 0.10
(0.063 + 0.004)
Embossed
Carrier
A0=6.24 + 0.10
(0.246 + 0.004)
User Direction of Feed
Embossment
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
3.4 Soldering
3.4.1 Moisture Reflow Sensitivity
3.4.2 Reflow Profile
Clare has characterized the moisture reflow sensitivity
for this product using IPC/JEDEC standard
J-STD-020. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-033 per
the labeled moisture sensitivity level (MSL), level 1 for
the SOIC package, and level 3 for the DFN package.
For proper assembly, this component must be
processed in accordance with the current revision of
IPC/JEDEC standard J-STD-020. Failure to follow the
recommended guidelines may cause permanent
damage to the device resulting in impaired
performance and/or a reduced lifetime expectancy.
3.5 Washing
Clare does not recommend ultrasonic cleaning of this
part.
Pb
RoHS
2002/95/EC
e3
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC1465 - R02
© Copyright 2008, Clare, Inc.
All rights reserved. Printed in USA.
4/16/08
R02
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