AD ADA4939-1YCPZ-R7 Ultralow distortion, differential adc driver Datasheet

Ultralow Distortion,
Differential ADC Driver
ADA4939-1/ADA4939-2
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
13 –VS
12 PD
+IN 2
11 –OUT
–IN 3
10 +OUT
07752-001
VOCM
+VS 8
+VS 7
+VS 6
9
+VS 5
+FB 4
19 –OUT1
18 +OUT1
17 VOCM1
16 –VS2
–IN1 1
+FB1 2
+VS1 3
+VS1 4
ADA4939-2
15 –VS2
–IN2 7
+OUT2 12
13 –OUT2
+VS2 10
+IN2 6
VOCM2 11
14 PD2
+FB2 8
+VS2 9
–FB2 5
07429-002
21 –VS1
20 PD1
24 +IN1
23 –FB1
22 –VS1
Figure 1. ADA4939-1
Figure 2. ADA4939-2
With the ADA4939-1/ADA4939-2, differential gain configurations
are easily realized with a simple external feedback network of four
resistors that determine the closed-loop gain of the amplifier.
The ADA4939-1/ADA4939-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary bipolar
process, enabling them to achieve very low levels of distortion with
an input voltage noise of only 2.3 nV/√Hz. The low dc offset and
excellent dynamic performance of the ADA4939-1/ADA4939-2
make them well suited for a wide variety of data acquisition and
signal processing applications.
–60
VOUT, dm = 2V p-p
–65
HD2
HD3
–70
–75
–80
–85
–90
–95
–100
–105
–110
1
10
100
FREQUENCY (MHz)
07429-021
The ADA4939-1/ADA4939-2 are low noise, ultralow distortion,
high speed differential amplifiers. They are an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The output common-mode voltage is user
adjustable by means of an internal common-mode feedback loop,
allowing the ADA4939-1/ADA4939-2 output to match the input
of the ADC. The internal feedback loop also provides exceptional
output balance as well as suppression of even-order harmonic
distortion products.
The ADA4939-1 (single) is available in a 3 mm × 3 mm, 16-lead
LFCSP, and the ADA4939-2 (dual) is available in a 4 mm × 4 mm,
24-lead LFCSP. The pinouts are optimized to facilitate printed
circuit board (PCB) layout and minimize distortion. The
ADA4939-1/ADA4939-2 are specified to operate over the
−40°C to +105°C temperature range; both operate on supplies
between 3.3 V and 5 V.
HARMONIC DISTORTION (dBc)
GENERAL DESCRIPTION
Rev. A
14 –VS
16 –VS
–FB 1
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
15 –VS
ADA4939-1
Extremely low harmonic distortion
−102 dBc HD2 at 10 MHz
−83 dBc HD2 at 70 MHz
−77 dBc HD2 at 100 MHz
−101 dBc HD3 at 10 MHz
−97 dBc HD3 at 70 MHz
−91 dBc HD3 at 100 MHz
Low input voltage noise: 2.3 nV/√Hz
High speed
−3 dB bandwidth of 1.4 GHz, G = 2
Slew rate: 6800 V/μs, 25% to 75%
Fast overdrive recovery of <1 ns
±0.5 mV typical offset voltage
Externally adjustable gain
Stable for differential gains ≥2
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
Figure 3. Harmonic Distortion vs. Frequency
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ADA4939-1/ADA4939-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Applications ....................................................................................... 1
Analyzing an Application Circuit ............................................ 17
General Description ......................................................................... 1
Setting the Closed-Loop Gain .................................................. 17
Functional Block Diagrams ............................................................. 1
Stable for Gains ≥2 ..................................................................... 17
Revision History ............................................................................... 2
Estimating the Output Noise Voltage ...................................... 17
Specifications..................................................................................... 3
Impact of Mismatches in the Feedback Networks ................. 18
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Absolute Maximum Ratings............................................................ 7
Input Common-Mode Voltage Range ..................................... 21
Thermal Resistance ...................................................................... 7
Input and Output Capacitive AC Coupling ............................ 21
Maximum Power Dissipation ..................................................... 7
Minimum RG Value of 50 Ω ...................................................... 21
ESD Caution .................................................................................. 7
Setting the Output Common-Mode Voltage .......................... 21
Pin Configurations and Function Descriptions ........................... 8
Layout, Grounding, and Bypassing .............................................. 22
Typical Performance Characteristics ............................................. 9
High Performance ADC Driving ................................................. 23
Test Circuits ..................................................................................... 15
Outline Dimensions ....................................................................... 24
Operational Description ................................................................ 16
Ordering Guide .......................................................................... 24
Definition of Terms .................................................................... 16
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Changed ADA4939 to ADA4939-1/ADA4939-2, CP-16-2 to
CP-16-21, and CP-24-1 to CP-24-10........................... Throughout
Changes to Figure 5, Figure 6, Table 9, and Table 10 ................... 8
Changes to Figure 54 ...................................................................... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
5/2008—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADA4939-1/ADA4939-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RF = 402 Ω, RG = 200 Ω, RT = 60.4 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±DIN to VOUT, dm Performance
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
INPUT CHARACTERISTICS
Offset Voltage
Test Conditions/Comments
Min
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p, ADA4939-1
VOUT, dm = 0.1 V p-p, ADA4939-2
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p, 25% to 75%
VIN = 0 V to 1.5 V step, G = 3.16
See Figure 41 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
f = 100 MHz, ADA4939-2
VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = 2.5 V
TMIN to TMAX variation
Input Bias Current
−3.4
−26
TMIN to TMAX variation
Input Offset Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
−11.2
Differential
Common mode
Typ
Maximum ∆VOUT; single-ended output, RF = RG = 10 kΩ
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 40 for test circuit
Rev. A | Page 3 of 24
Unit
1400
300
90
1400
6800
<1
MHz
MHz
MHz
MHz
V/µs
ns
−102
−83
−77
−101
−97
−91
−95
−89
2.3
6
−80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
±0.5
±2.0
−10
±0.5
+0.5
180
450
1
1.1
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V
Max
−83
0.9
+2.8
+2.2
+11.2
3.9
−77
4.1
100
−64
mV
µV/°C
µA
µA/°C
µA
kΩ
kΩ
pF
V
dB
V
mA
dB
ADA4939-1/ADA4939-2
Data Sheet
VOCM to VOUT, cm Performance
Table 2.
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
Gain
Test Conditions/Comments
Min
Max
670
2500
7.5
VIN = 1.5 V to 3.5 V, 25% to 75%
f = 100 kHz
VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2
ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V
ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V
Typ
1.3
8.3
−3.7
0.97
9.7
±0.5
−90
0.98
Unit
MHz
V/µs
nV/√Hz
3.5
11.5
+3.7
−73
0.99
V
kΩ
mV
dB
V/V
General Performance
Table 3.
Parameter
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Pin Bias Current per Amplifier
Enabled
Disabled
Test Conditions/Comments
Min
3.0
35.1
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V
0.26
Typ
36.5
16
0.32
−90
Max
Unit
5.25
37.7
V
mA
µA/°C
mA
dB
0.38
−80
Powered down
Enabled
≤1
≥2
500
100
V
V
ns
ns
PD = 5 V
PD = 0 V
30
−200
µA
µA
OPERATING TEMPERATURE RANGE
−40
Rev. A | Page 4 of 24
+105
°C
Data Sheet
ADA4939-1/ADA4939-2
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS/2, RF = 402 Ω, RG = 200 Ω, RT = 60.4 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±DIN to VOUT, dm Performance
Table 4.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
INPUT CHARACTERISTICS
Offset Voltage
Test Conditions/Comments
Min
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p, ADA4939-1
VOUT, dm = 0.1 V p-p, ADA4939-2
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p, 25% to 75%
VIN = 0 V to 1.0 V step, G = 3.16
See Figure 41 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
f = 100 MHz, ADA4939-2
VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = +VS/2
TMIN to TMAX variation
Input Bias Current
−3.5
−26
TMIN to TMAX variation
Input Offset Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
−11.2
Differential
Common mode
Typ
Maximum ∆VOUT, single-ended output, RF = RG = 10 kΩ
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, f = 10 MHz,
see Figure 40 for test circuit
Rev. A | Page 5 of 24
Unit
1400
300
90
1400
5000
<1
MHz
MHz
MHz
MHz
V/µs
ns
−100
−90
−83
−94
−82
−75
−87
−70
2.3
6
−80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
±0.5
±2.0
−10
±0.5
±0.4
180
450
1
0.9
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V
Max
−85
0.8
+3.5
+2.2
+11.2
2.4
−75
2.5
75
−61
mV
µV/°C
µA
µA/°C
kΩ
kΩ
pF
V
dB
V
mA
dB
ADA4939-1/ADA4939-2
Data Sheet
VOCM to VOUT, cm Performance
Table 5.
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
Gain
Test Conditions/Comments
Min
Max
560
1250
7.5
VIN = 0.9 V to 2.4 V, 25% to 75%
f = 100 kHz
VOS, cm = VOUT, cm, VDIN+ = VDIN− = 1.67 V
∆VOUT, dm/∆VOCM, ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM, ∆VOCM = ±1 V
Typ
1.3
8.3
−3.7
0.97
9.7
±0.5
−75
0.98
Unit
MHz
V/µs
nV/√Hz
1.9
11.2
+3.7
−73
0.99
V
kΩ
mV
dB
V/V
General Performance
Table 6.
Parameter
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Pin Bias Current per Amplifier
Enabled
Disabled
Test Conditions/Comments
Min
3.0
32.8
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS, ∆VS = 1 V
0.16
Typ
34.5
16
0.20
−84
Max
Unit
5.25
36.0
V
mA
µA/°C
mA
dB
0.26
−72
Powered down
Enabled
≤1
≥2
500
100
V
V
ns
ns
PD = 3.3 V
PD = 0 V
26
−137
µA
µA
OPERATING TEMPERATURE RANGE
−40
Rev. A | Page 6 of 24
+105
°C
Data Sheet
ADA4939-1/ADA4939-2
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Supply Voltage
Power Dissipation
Input Current, +IN, −IN, PD
Storage Temperature Range
Operating Temperature Range
ADA4939-1
ADA4939-2
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
5.5 V
See Figure 4
±5 mA
−65°C to +125°C
−40°C to +105°C
−40°C to +105°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. Calculate the power due to the load drive
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a
JEDEC standard 4-layer board with the exposed pad soldered to
a PCB pad that is connected to a solid plane.
3.0
Table 8. Thermal Resistance
Package Type
ADA4939-1, 16-Lead LFCSP (Exposed Pad)
ADA4939-2, 24-Lead LFCSP (Exposed Pad)
θJA
98
67
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4939-1/
ADA4939-2 package is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4939-1/
ADA4939-2. Exceeding a junction temperature of 150°C for an
extended period can result in changes in the silicon devices,
potentially causing failure.
2.5
ADA4939-2
2.0
1.5
ADA4939-1
1.0
0.5
0
–40
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
100
07429-004
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
MAXIMUM POWER DISSIPATION (W)
THERMAL RESISTANCE
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
Rev. A | Page 7 of 24
ADA4939-1/ADA4939-2
Data Sheet
–FB2 5
20 PD1
19 –OUT1
22 –VS1
TOP VIEW
(Not to Scale)
15 –VS2
14 PD2
+IN2 6
13 –OUT2
VOCM2 11
NOTES
1. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
ADA4939-2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 5. ADA4939-1 Pin Configuration
Figure 6. ADA4939-2 Pin Configuration
Table 9. ADA4939-1 Pin Function Descriptions
Pin No.
1
2
3
4
5 to 8
9
10
11
12
13 to 16
Mnemonic
−FB
+IN
−IN
+FB
+VS
VOCM
+OUT
−OUT
PD
−VS
EPAD
Description
Negative Output for Feedback Component Connection
Positive Input Summing Node
Negative Input Summing Node
Positive Output for Feedback Component Connection
Positive Supply Voltage
Output Common-Mode Voltage
Positive Output for Load Connection
Negative Output for Load Connection
Power-Down Pin
Negative Supply Voltage
Exposed Pad. The exposed pad must be connected to ground.
Table 10. ADA4939-2 Pin Function Descriptions
Pin No.
1
2
3, 4
5
6
7
8
9, 10
11
12
13
14
15, 16
17
18
19
20
21, 22
23
24
Mnemonic
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
−VS2
VOCM1
+OUT1
−OUT1
PD1
−VS1
−FB1
+IN1
EPAD
07429-006
9
VOCM
21 –VS1
24 +IN1
+VS1 4
+VS 8
+VS 7
+VS 6
+VS 5
+FB 4
11 –OUT
10 +OUT
+OUT2 12
TOP VIEW
(Not to Scale)
+VS2 10
ADA4939-1
18 +OUT1
17 VOCM1
16 –VS2
–IN2 7
–IN 3
–IN1 1
+FB1 2
+VS1 3
07429-005
+IN 2
12 PD
+FB2 8
+VS2 9
–FB 1
23 –FB1
13 –VS
14 –VS
16 –VS
PIN 1
INDICATOR
15 –VS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Description
Negative Input Summing Node 1
Positive Output Feedback 1
Positive Supply Voltage 1
Negative Output Feedback 2
Positive Input Summing Node 2
Negative Input Summing Node 2
Positive Output Feedback 2
Positive Supply Voltage 2
Output Common-Mode Voltage 2
Positive Output 2
Negative Output 2
Power-Down Pin 2
Negative Supply Voltage 2
Output Common-Mode Voltage 1
Positive Output 1
Negative Output 1
Power-Down Pin 1
Negative Supply Voltage 1
Negative Output Feedback 1
Positive Input Summing Node 1
Exposed Pad. The exposed pad must be connected to ground.
Rev. A | Page 8 of 24
Data Sheet
ADA4939-1/ADA4939-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS /2, RG = 200 Ω, RF = 402 Ω, RT = 60.4 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. Refer
to Figure 39 for test setup. Refer to Figure 42 for signal definitions.
2
0
–2
–4
–6
–8
–10
RG = 200Ω, RT = 60.4Ω
RG = 127Ω, RT = 66.3Ω
RG = 80.6Ω, RT = 76.8Ω
1
10
100
1k
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
–2
–3
–4
–5
–6
–7
–8
–9
VS = 3.3V
VS = 5.0V
1
10
100
1k
FREQUENCY (MHz)
–8
–10
VS = 3.3V
VS = 5.0V
NORMALIZED CLOSED-LOOP GAIN (dB)
–3
–4
–5
–6
–7
–8
–9
–40°C
+25°C
+105°C
100
FREQUENCY (MHz)
1k
100
1k
VOUT, dm = 2V p-p
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–40°C
+25°C
+105°C
–10
–11
10
10
FREQUENCY (MHz)
–12
07429-009
NORMALIZED CLOSED-LOOP GAIN (dB)
–2
1
–6
2
0
–12
–4
3
–1
–11
–2
Figure 11. Large Signal Frequency Response for Various Supplies
1
–10
1k
0
1
VOUT, dm = 100mV p-p
2
100
VOUT, dm = 2V p-p
–12
Figure 8. Small Signal Frequency Response for Various Supplies
3
10
FREQUENCY (MHz)
07429-008
NORMALIZED CLOSED-LOOP GAIN (dB)
–1
–12
RG = 200Ω, RT = 60.4Ω
RG = 127Ω, RT = 66.3Ω
RG = 80.6Ω, RT = 76.8Ω
G = +2.00
G = +3.16
G = +5.00
–12
2
0
–11
–10
Figure 10. Large Signal Frequency Response for Various Gains
1
–10
–8
1
VOUT, dm = 100mV p-p
2
–6
–14
Figure 7. Small Signal Frequency Response for Various Gains
3
–4
07429-011
–14
–2
Figure 9. Small Signal Frequency Response for Various Temperatures
1
10
100
FREQUENCY (MHz)
1k
07429-012
G = +2.00
G = +3.16
G = +5.00
–12
VOUT, dm = 2V p-p
0
07429-010
NORMALIZED CLOSED-LOOP GAIN (dB)
VOUT, dm = 100mV p-p
07429-007
NORMALIZED CLOSED-LOOP GAIN (dB)
2
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. A | Page 9 of 24
ADA4939-1/ADA4939-2
–2
–3
–4
–5
–6
–7
–8
–9
RL = 1kΩ
RL = 200Ω
–12
1
–2
–3
–4
–5
–6
–7
–8
–9
–10
RL = 1kΩ
RL = 200Ω
–11
10
100
1k
FREQUENCY (MHz)
–12
1
–55
HARMONIC DISTORTION (dBc)
VOCM GAIN (dB)
0
–3
–6
VOCM = 1.0V
VOCM = 3.9V
VOCM = 2.5V
–70
–75
–80
–85
–90
–95
–100
100
1k
–115
07429-019
10
1
–60
0.3
–70
HARMONIC DISTORTION (dBc)
–65
0.1
0
–0.1
–0.2
RL = 1kΩ
RL = 200Ω
–0.3
RL = 1kΩ OUT1
RL = 1kΩ OUT2
100
1k
FREQUENCY (MHz)
07429-020
10
VOUT, dm = 2V p-p
VS = ±2.5V
HD2,
HD3,
HD2,
HD3,
–75
RL, dm = 1kΩ
RL, dm = 1kΩ
RL, dm = 200Ω
RL, dm = 200Ω
–80
–85
–90
–95
–100
–105
RL = 200Ω OUT1
RL = 200Ω OUT2
1
100
Figure 17. Harmonic Distortion vs. Frequency at Various Gains
VOUT, dm = 100mV p-p
0.2
10
FREQUENCY (MHz)
0.4
–0.5
=2
=2
= 3.16
= 3.16
=5
=5
–110
Figure 14. VOCM Small Signal Frequency Response at Various DC Levels
–0.4
G
G
G
G
G
G
–105
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
HD2,
HD3,
HD2,
HD3,
HD2,
HD3,
–65
3
0.5
1k
VOUT, dm = 2V p-p
–60
1
100
Figure 16. Large Signal Frequency Response for Various Loads
VOUT, dm = 100mV p-p
–9
10
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads
6
0
–1
07429-022
–11
1
07429-016
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–1
–10
VOUT, dm = 2V p-p
2
1
07429-013
NORMALIZED CLOSED-LOOP GAIN (dB)
3
VOUT, dm = 100mV p-p
2
–110
1
10
100
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency at Various Loads
Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads
Rev. A | Page 10 of 24
07429-023
3
Data Sheet
Data Sheet
HD2,
HD3,
HD2,
HD3,
–70
–75
VS (SPLIT
VS (SPLIT
VS (SPLIT
VS (SPLIT
–50
SUPPLY) = ±2.5V
SUPPLY) = ±2.5V
SUPPLY) = ±1.65V
SUPPLY) = ±1.65V
–60
DISTORTION (dBc)
–65
HARMONIC DISTORTION (dBc)
–40
VOUT, dm = 2V p-p
–80
–85
–90
–95
–70
–80
–90
–100
–110
–100
HD2,
HD3,
HD2,
HD3,
–120
–105
1
10
–130
07429-062
–110
100
FREQUENCY (MHz)
0
1
2
3
4
5
VS = 5.0
VS = 5.0
VS = 3.3
VS = 3.3
6
7
VOUT, dm (V p-p)
07429-024
–60
ADA4939-1/ADA4939-2
Figure 22. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
Figure 19. Harmonic Distortion vs. Frequency at Various Supplies
–40
10
VOUT, dm = 2V p-p
–50
NORMALIZED SPECTRUM (dBc)
–60
–70
–80
–90
–100
f = 10MHz
f = 10MHz
f = 70MHz
f = 70MHz
VOCM (V)
–30
–40
–50
–60
–70
–80
–90
–110
69.5
69.8
69.9
70.0
70.1
70.2
70.3
70.4
70.5
Figure 23. 70 MHz Intermodulation Distortion
–40
–30
RL, dm = 200Ω
VOUT, dm = 2V p-p
–50
–35
–60
–40
CMRR (dB)
–70
–80
–90
–100
–45
–50
–55
–60
–110
HD2,
HD3,
HD2,
HD3,
–120
1.4
1.6
1.8
f = 10MHz
f = 10MHz
f = 70MHz
f = 70MHz
2.0
VOCM (V)
–65
07429-026
DISTORTION (dBc)
69.7
FREQUENCY (MHz)
Figure 20. Harmonic Distortion vs. VOCM at Various Frequencies
–130
1.2
69.6
07429-028
–120
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
–20
–100
07429-025
HD2,
HD3,
HD2,
HD3,
–110
–10
–70
1
10
100
FREQUENCY (MHz)
Figure 24. CMRR vs. Frequency
Figure 21. Harmonic Distortion vs. VOCM at Various Frequencies
Rev. A | Page 11 of 24
1k
07429-029
DISTORTION (dBc)
VOUT, dm = 2V p-p
VS = ±2.5V
0
ADA4939-1/ADA4939-2
Data Sheet
–60
VOUT, dm = HD2,
VOUT, dm = HD3,
VOUT, dm = HD2,
VOUT, dm = HD3,
RL, dm = 200Ω
–35
–40
OUTPUT BALANCE (dB)
–80
–90
–100
–45
–50
–55
–60
–110
100
–70
FREQUENCY (MHz)
1
1k
Figure 28. Output Balance vs. Frequency
70
RL, dm = 200Ω
100
GAIN
60
–40
50
0
50
–50
PHASE
40
–60
GAIN (dB)
PSRR (dB)
100
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. Frequency at Various Output Voltages
–30
10
–70
–50
–100
30
–150
20
–80
–200
10
–90
–250
1
10
100
1k
FREQUENCY (MHz)
07429-031
0
–100
–300
–10
0.01
0.1
1
10
100
–350
10k
1k
FREQUENCY (MHz)
Figure 26. PSRR vs. Frequency, RL = 200 Ω
Figure 29. Open-Loop Gain and Phase vs. Frequency
8
0
RL, dm = 200Ω
–5
6
–10
4
VOLTAGE (V)
–15
–20
S22
S11
–25
–30
–35
2
0
–2
VOUT
–4
–40
–6
–45
VIN × 3.16V
–50
1
10
100
1k
FREQUENCY (MHz)
07429-032
S-PARAMETERS (dB)
PHASE (Degrees)
10
07429-034
1
07429-027
–120
07429-030
–65
–8
0
10
20
30
40
TIME (ns)
Figure 30. Overdrive Recovery, G = 3.16
Figure 27. Return Loss (S11, S22) vs. Frequency
Rev. A | Page 12 of 24
50
60
07429-035
HARMONIC DISTORTION (dBc)
–70
–30
VS = ±1.65V
= 1V p-p
= 1V p-p
= 2V p-p
= 2V p-p
Data Sheet
–40
VOUT, dm = 2V p-p
VS = ±2.5V
–65
RL, dm = 200Ω
–50
–60
–70
–75
CROSSTALK (dB)
RL = 200Ω
–80
–85
RL = 1kΩ
–90
–95
–70
INPUT AMP 1 TO OUTPUT AMP 2
–80
–90
–100
INPUT AMP 2 TO OUTPUT AMP 1
–110
–120
–100
10
–140
07429-033
1
100
FREQUENCY (MHz)
1
0.10
3
OUTPUT VOLTAGE (V)
0.02
0
2
1
0
–1
–2
–3
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
–4
07429-038
–0.02
0
1
3
4
5
6
7
8
9
10
18
20
TIME (ns)
Figure 35. Large Signal Pulse Response
Figure 32. Small Signal Pulse Response
4.5
OUTPUT COMMON-MODE VOLTAGE (V)
2.60
2.55
2.50
2.45
2.40
0
2
4
6
8
10
12
14
16
TIME (ns)
18
20
07429-039
OUTPUT COMMON-MODE VOLTAGE (V)
2
07429-041
OUTPUT VOLTAGE (V)
4
0.04
1k
Figure 34. Crosstalk vs. Frequency for ADA4939-2
0.12
0.06
100
FREQUENCY (MHz)
Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads
0.08
10
07429-044
–130
–105
Figure 33. VOCM Small Signal Pulse Response
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
16
TIME (ns)
Figure 36. VOCM Large Signal Pulse Response
Rev. A | Page 13 of 24
07429-042
SPURIOUS-FREE DYNAMIC RANGE (dBc)
–60
ADA4939-1/ADA4939-2
ADA4939-1/ADA4939-2
Data Sheet
1k
3.5
RL, dm = 200Ω
VOUT, dm
2.5
2.0
PD
1.5
1.0
0.5
100
10
–0.5
0
100
200
300
400
500
600
700
TIME (ns)
800
900
1000
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 38. Voltage Noise Spectral Density, RTI
Figure 37. PD Response Time
Rev. A | Page 14 of 24
10M
07429-045
0
07429-043
VOLTAGE (V)
INPUT VOLTAGE NOISE (nV/ Hz)
3.0
Data Sheet
ADA4939-1/ADA4939-2
TEST CIRCUITS
402Ω
5V
0.1µF 200Ω
50Ω
VIN
ADA4939-1/
ADA4939-2
VOCM
60.4Ω
1kΩ
200Ω
07429-046
0.1µF
402Ω
Figure 39. Equivalent Basic Test Circuit, G = 2
402Ω
+2.5V
50Ω
VIN
49.9Ω
200Ω
60.4Ω
VOCM
200Ω
0.1µF
60.4Ω
49.9Ω
NETWORK
ANALYZER
INPUT
AC-COUPLED
ADA4939-1/
ADA4939-2
50Ω
49.9Ω
–2.5V
402Ω
07429-047
NETWORK
ANALYZER
OUTPUT
AC-COUPLED
49.9Ω
Figure 40. Test Circuit for Output Balance, CMRR
402Ω
5V
VIN
0.1µF 442Ω
60.4Ω
VOCM
ADA4939-1/
ADA4939-2
200Ω
200Ω
261Ω
0.1µF 442Ω
0.1µF
402Ω
Figure 41. Test Circuit for Distortion Measurements
Rev. A | Page 15 of 24
2:1
50Ω
DUAL
FILTER
CT
07429-048
50Ω
0.1µF 200Ω
LOW-PASS
FILTER
ADA4939-1/ADA4939-2
Data Sheet
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
–FB
RG
+IN
–DIN
–OUT
ADA4939-1/
ADA4939-2
VOCM
RG R
F
–IN
VOUT, cm = (V+OUT + V−OUT)/2
RL, dm VOUT, dm
+OUT
+FB
Balance
07429-049
+DIN
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
RF
Figure 42. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 39). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
Rev. A | Page 16 of 24
Output Balance Error 
VOUT , cm
VOUT , dm
Data Sheet
ADA4939-1/ADA4939-2
THEORY OF OPERATION
The ADA4939-1/ADA4939-2 differ from conventional op amps
in that they have two outputs whose voltages move in opposite
directions and an additional input, VOCM. Like op amps, they
rely on high open-loop gain and negative feedback to force
these outputs to the desired voltages. The ADA4939-1/
ADA4939-2 behave much like standard voltage feedback op
amps and facilitate single-ended-to-differential conversions,
common-mode level shifting, and amplifications of differential
signals. Like op amps, the ADA4939-1/ADA4939-2 have high
input impedance and low output impedance. Because they use
voltage feedback, the ADA4939-1/ADA4939-2 manifest a
nominally constant gain-bandwidth product.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced by the internal
common-mode feedback loop to be equal to the voltage applied
to the VOCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The ADA4939-1/ADA4939-2 use high open-loop gain and
negative feedback to force their differential and common-mode
output voltages in such a way as to minimize the differential
and common-mode error voltages. The differential error
voltage is defined as the voltage between the differential inputs
labeled +IN and −IN (see Figure 42). For most purposes, this
voltage is zero. Similarly, the difference between the actual
output common-mode voltage and the voltage applied to VOCM
is also zero. Starting from these two assumptions, any
application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 can be
determined by
VOUT , dm
VIN , dm

RF
RG
This presumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
STABLE FOR GAINS ≥2
The ADA4939-1/ADA4939-2 frequency response exhibits
excessive peaking for differential gains <2; therefore, operate the
devioce with differential gains ≥2.
ESTIMATING THE OUTPUT NOISE VOLTAGE
To estimate the differential output noise of the ADA4939-1/
ADA4939-2 use the noise model shown in Figure 43. The inputreferred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The output voltage due to vnIN is obtained
by multiplying vnIN by the noise gain, GN (defined in the GN
equation that follows). The noise currents are uncorrelated with
the same mean-square value, and each produces an output voltage
that is equal to the noise current multiplied by the associated
feedback resistance. The noise voltage density at the VOCM/VOCMx
pin is vnCM. When the feedback networks have the same feedback
factor, as in most cases, the output noise due to vnCM is commonmode. Each of the four resistors contributes (4kTRxx)1/2. The noise
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by RFx/RGx. Table 11 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density
terms.
VnRG1
RG1
RF1
VnRF1
inIN+
+
inIN–
VnIN ADA4939-1/
ADA4939-2
VnOD
VnRG2
RG2
RF2
VnCM
VnRF2
Figure 43. Noise Model
Rev. A | Page 17 of 24
07429-050
VOCM
ADA4939-1/ADA4939-2
Data Sheet
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN
inIN
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
Input Noise
Voltage Density
vnIN
inIN × (RF2)
inIN × (RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Output
Multiplication Factor
GN
1
1
0
RF1/RG1
RF2/RG2
1
1
Differential Output Noise
Voltage Density Term
vnO1 = GN(vnIN)
vnO2 = (inIN)(RF2)
vnO3 = (inIN)(RF1)
vnO4 = 0
vnO5 = (RF1/RG1)(4kTRG1)1/2
vnO6 = (RF2/RG2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB)
6
10
14
RF (Ω)
402
402
402
RG (Ω)
200
127
80.6
RIN, dm (Ω)
400
254
161
Differential Output Noise Density (nV/√Hz)
9.7
12.4
16.6
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB)
6
10
14
1
RF (Ω)
402
402
402
RG1 (Ω)
200
127
80.6
RT (Ω)
60.4
66.5
76.8
RIN, cm (Ω)
301
205
138
RG2 (Ω)1
228
155
111
Differential Output Noise Density (nV/√Hz)
9.1
11.1
13.5
RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by the appropriate output factor,
where:
2
is the circuit noise gain.
β1  β2 
RG1
RG2
β1 
and β2 
are the feedback factors.
RF1  RG1
RF2  RG2
GN 
When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =
β2 = β, and the noise gain becomes
GN 
1
R
1 F
β
RG
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms.
v nOD 
8
2
 vnOi
i 1
Table 12 and Table 13 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
The gain from the VOCM/VOCMx pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed. The
feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the VOCM
input are negligible. If the loops are intentionally mismatched by a
large amount, it is necessary to include the gain term from VOCM
to VO, dm and account for the extra noise. For example, if β1 = 0.5
and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the
VOCM/VOCMx pin is set to 2.5 V, a differential offset voltage is present
at the output of (2.5 V)(0.67) = 1.67 V. The differential output noise
contribution is (7.5 nV/√Hz)(0.67) = 5 nV/√Hz. Both of these
results are undesirable in most applications; therefore, it is best
to use nominally matched feedback factors.
Rev. A | Page 18 of 24
Data Sheet
ADA4939-1/ADA4939-2
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VOCM input, negligible VOCM noise contribution,
and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 44, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
RF
ADA4939-1/
ADA4939-2
+VS
–DIN
RG
+IN
VOCM
RG
VOUT, dm
–IN
Terminating a Single-Ended Input
This section deals with how to properly terminate a single-ended
input to the ADA4939-1/ADA4939-2 with a gain of 2, RF = 400 Ω,
and RG = 200 Ω. An example using an input source with a
terminated output voltage of 1 V p-p and source resistance of 50 Ω
illustrates the four simple steps that must be followed. Note that,
because the terminated output voltage of the source is 1 V p-p,
the open circuit output voltage of the source is 2 V p-p. The
source shown in Figure 46 indicates this open-circuit voltage.
1.
The input impedance must be calculated using the formula

 


 

R
200
G

  300Ω

RIN  
400
RF

 1
1

 



2
(
200
400
)
R
R
2

(

)
F
G
 


07429-051
+DIN
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG. The common-mode
voltage at the amplifier input terminals can be easily determined by
noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF and RG in the lower loop. This voltage is present at
both input terminals due to negative voltage feedback and is in
phase with the input signal, thus reducing the effective voltage
across RG in the upper loop and partially bootstrapping RG.
RF
Figure 44. ADA4939-1/ADA4939-2 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 45),
the input impedance is
RIN , SE
RF
400Ω
RIN
300Ω




R
G


RF

1




2
R
R


F 
G

VS
2V p-p
+VS
RS
RG
50Ω
200Ω
VOCM
RG
RF
ADA4939-1/
ADA4939-2
RL VOUT, dm
200Ω
+VS
–VS
RG
RG
ADA4939-1/
ADA4939-2
–VS
RF
400Ω
RL
VOUT, dm
Figure 46. Calculating Single-Ended Input Impedance RIN
07429-052
VOCM
RF
Figure 45. ADA4939-1/ADA4939-2 with Unbalanced (Single-Ended) Input
Rev. A | Page 19 of 24
07429-053
RIN, SE
ADA4939-1/ADA4939-2
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it would
be if RT = 50 Ω. These two effects have opposite impacts on
the output voltage, and for large resistor values in the feedback
loops (~1 kΩ), the effects essentially cancel each other out.
For small RF and RG, however, the diminished closed-loop
gain is not canceled completely by the increased VTH. This
can be seen by evaluating Figure 49.
To match the 50 Ω source resistance, the termination
resistor, RT, is calculated using RT||300 Ω = 50 Ω. The
closest standard 1% value for RT is 60.4 Ω.
RF
400Ω
+VS
RIN
50Ω
RS
VS
2V p-p
RG
50Ω
200Ω
RT
60.4Ω
VOCM
ADA4939-1/
ADA4939-2
RL
VOUT, dm
RG
200Ω
The desired differential output in this example is 2 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 2. The actual differential output voltage,
however, is equal to (1.09 V p-p)(400/227.4) = 1.92 V p-p.
To obtain the desired output voltage of 2 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry (see Step 4).
07429-054
–VS
RF
400Ω
Figure 47. Adding Termination Resistor RT
Figure 47 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for
the imbalance of the gain resistors, a correction resistor
(RTS) is added in series with RG in the lower loop. RTS is
equal to the Thevenin equivalent of the source resistance
RS and the termination resistance RT and is equal to RS||RT.
RS
VS
2V p-p
The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
4.
To make the output voltage VOUT = 2 V p-p, calculate RF by
RF 
Desired V
RTH
50Ω
RT
60.4Ω
VTH
1.09V p-p
OUT ,dm
27.4Ω
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent of the terminated source
and RTS in the lower feedback loop is shown in Figure 49.
400Ω
+VS
200Ω
VOCM
RG
RTS
27.4Ω
2VP P 227.4   417 
1.09VP P
422Ω
+VS
1V p-p
RS
RG
50Ω
200Ω
RT
60.4Ω
VOCM
RG
ADA4939-1/
ADA4939-2

RF
VS
2V p-p
RTS
27.4Ω
RL VOUT, dm
ADA4939-1/
ADA4939-2
RL
VOUT, dm
2.02V p-p
200Ω
–VS
RF
200Ω
422Ω
–VS
RF
400Ω
07429-056
VTH
1.09V p-p
27.4Ω
 RTS 
The final circuit is shown in Figure 50.
RF
RG
G
The closest standard 1 % values to 417 Ω are 412 Ω and
422 Ω. Choosing 422 Ω gives a differential output voltage
of 2.02 V p-p.
Figure 48. Calculating the Thevenin Equivalent
RTH
R
VTH
07429-055
3.
Figure 50. Terminated Single-Ended-to-Differential System with G = 2
Figure 49. Thevenin Equivalent and Matched Gain Resistors
Figure 49 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
Rev. A | Page 20 of 24
07429-057
2.
Data Sheet
Data Sheet
ADA4939-1/ADA4939-2
INPUT COMMON-MODE VOLTAGE RANGE
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The ADA4939-1/ADA4939-2 input common-mode range is
centered between the two supply rails, in contrast to other ADC
drivers with level-shifted input ranges, such as the ADA4937-1/
ADA4937-2. The centered input common-mode range is best
suited to ac-coupled, differential-to-differential and dual supply
applications.
The VOCM/VOCMx pin of the ADA4939-1/ADA4939-2 is internally
biased with a voltage divider comprising two 20 kΩ resistors at a
voltage approximately equal to the midsupply point, [(+VS) +
(−VS)]/2. Because of this internal divider, the VOCM/VOCMx pin
sources and sinks current, depending on the externally applied
voltage and its associated source resistance. Relying on the
internal bias results in an output common-mode voltage that is
within about 100 mV of the expected value.
For 5 V single-supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as
1.1 V to 3.9 V and is specified as 0.9 V to 2.4 V with a 3.3 V
supply. To avoid nonlinearities, the voltage swing at the +IN
and −IN terminals must be confined to these ranges.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc commonmode feedback current and causes the ADA4939-1/ADA4939-2
dc input common-mode voltage to equal the dc output commonmode voltage. These ac coupling capacitors must be placed in
both loops to keep the feedback factors matched.
Output ac coupling capacitors can be placed in series between
each output and its respective load. See Figure 54 for an
example that uses input and output capacitive ac coupling.
In cases where more accurate control of the output commonmode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. The output common-mode offset listed in the
Specifications section assumes that the VOCM input is driven by
a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM/VOCMx pin is approximately 10 kΩ. If
multiple ADA4939-1/ADA4939-2 devices share one reference
output, it is recommended that a buffer be used.
MINIMUM RG VALUE OF 50 Ω
Due to the wide bandwidth of the ADA4939-1/ADA4939-2, the
value of RG must be greater than or equal to 50 Ω to provide
sufficient damping in the amplifier front end. In the terminated
case, RG includes the Thevenin resistance of the source and load
terminations.
Rev. A | Page 21 of 24
ADA4939-1/ADA4939-2
Data Sheet
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4939-1 is sensitive to the PCB
environment in which it operates. Realizing its superior
performance requires attention to the details of high speed PCB
design. This section shows a detailed example of how the
ADA4939-1 was addressed.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended to use two parallel bypass
capacitors (1000 pF and 0.1 μF) for each supply. Place the 1000 pF
capacitor closer to the device. Further away, provide low frequency
bypassing, using 10 μF tantalum capacitors from each supply to
ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4939-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) must be
cleared of all ground and power planes (see Figure 51). Clearing
the ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the amplifier
at high frequencies.
Ensure that signal routing is short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, ensure that the
PCB traces are close together, and twist any differential wiring
such that the loop area is minimized which reduces radiated
energy and makes the circuit less susceptible to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity four-layer
circuit board, as described in EIA/JESD 51-7.
1.30
0.80
07429-058
07429-059
1.30 0.80
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
07429-060
POWER PLANE
BOTTOM METAL
Figure 53. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. A | Page 22 of 24
Data Sheet
ADA4939-1/ADA4939-2
HIGH PERFORMANCE ADC DRIVING
The VOCM pin of the ADA4939-1 is bypassed for noise reduction
and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs. With an output commonmode voltage of nominally 2.5 V, each ADA4939-1 output
swings between 2.0 V and 3.0 V, providing a gain of 2 and a 2 V p-p
differential signal to the ADC input.
The ADA4939-1/ADA4939-2 are ideally suited for broadband
ac-coupled and differential-to-differential applications on a
single supply.
The circuit in Figure 54 shows a front-end connection for an
ADA4939-1 driving an AD9445, 14-bit, 105 MSPS ADC, with
ac coupling on the ADA4939-1 input and output. (The AD9445
achieves its optimum performance when driven differentially.)
The ADA4939-1 eliminates the need for a transformer to drive
the ADC and perform a single-ended-to-differential conversion
and buffering of the driving signal.
The ADA4939-1 is configured with a single 5 V supply and gain
of 2 for a single-ended input to differential output. The 60.4 Ω
termination resistor, in parallel with the single-ended input
impedance of approximately 300 Ω, provides a 50 Ω termination
for the source. The additional 27.4 Ω (227.4 Ω total) at the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 54.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
5V (A) 3.3V (A) 3.3V (D)
412Ω
5V
50Ω
0.1µF
60.4Ω
VOCM
0.1µF
+
ADA4939-1
0.1µF
AVDD2 AVDD1 DRVDD
AD9445
VIN–
BUFFER T/H
24.3Ω
47pF
ADC
24.3Ω
200Ω
0.1µF
30nH
0.1µF
30nH
27.4Ω
412Ω
14
VIN+
CLOCK/
TIMING
REF
AGND
SENSE
07429-061
SIGNAL
GENERATOR
200Ω
Figure 54. ADA4939-1 Driving an AD9445 ADC with AC-Coupled Input and Output
Rev. A | Page 23 of 24
ADA4939-1/ADA4939-2
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.30
0.23
0.18
13
0.50
BSC
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.45
1.30 SQ
1.15
4
9
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
111808-A
TOP VIEW
5
8
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
2.20
2.10 SQ
2.00
6
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
06-11-2012-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4939-1YCPZ-R2
ADA4939-1YCPZ-RL
ADA4939-1YCPZ-R7
ADA4939-2YCPZ-R2
ADA4939-2YCPZ-RL
ADA4939-2YCPZ-R7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07429-0-5/16(A)
Rev. A | Page 24 of 24
Package Option
CP-16-21
CP-16-21
CP-16-21
CP-24-10
CP-24-10
CP-24-10
Ordering Quantity
250
5,000
1,500
250
5,000
1,500
Branding
H1E
H1E
H1E