Anpec APL78L12-KC-TR Three-terminal low current positive voltage regulator Datasheet

APL78L05/12
Three-Terminal Low Current Positive Voltage Regulator
Features
General Description
•
•
•
•
•
•
This series of fixed-voltage monolithic integrated-circuit voltage regulators is designed for a wide range
of applications. These applications include on-card
regulation for elimination of noise and distribution
problems associated with single-point regulation. In
addition, they can be used with power-pass elements
to make high-current voltage regulators. Each of
these regulators can deliver up to 100mA of output
current. The internal limiting and ternal shutdown features of these regulators make them essentially immune to overload. When used as a replacement for
a Zener diode-resistor combination, an effective improvement in output impedance can be obtained together with lower-bias current.
•
•
•
3-Ternimal Regulators
Maximum Input Voltage : 30V
Output Voltages of 5V,12V
Output Current Up to 100mA
No External Components
Internal Thermal Overload Protection
Internal Short-Circuit Limiting
Output Voltage Offered in 4% tolerance
SOP-8, SOT-89 and TO-92 Packages.
Applications
•
•
Pin Description
Battery-Powered Circuitry
Post Regulator for Switching Power Supply
V O UT
1
8
V IN
GND
2
7
GND
GND
3
6
GND
NC
4
5
NC
SOP-8 (Top View)
Ordering and Marking Information
L e a d F re e C o d e
H a n d l in g C o d e
Tem p. Range
Package C ode
APL
7 8 L 0 5 /1 2
XXXXX
XXXXX
V IN
2
GND
1
VOUT
TO-92 (Top View)
1
2
3
VOUT
GND
VIN
SOT-89 (Front View)
Package C ode
E : T O -9 2
K : S O P -8
D : S O T -8 9
Tem p. Range
C : 0 to 7 0 ° C
H a n d l in g C o d e
TU : Tube
TR : Tape & R eel
P B : P la s t ic B a g
TB : Tape & Box
L e a d F re e C o d e
L : L e a d F r e e D e v ic e
B l a n k : O r i g in a l D e v ic e
A P L 7 8 L 0 5 /1 2 -
A P L 7 8 L 0 5 /1 2 E :
3
- D a te C o d e
A P L 7 8 L 0 5 /1 2 D /K :
A P L 7 8 L 0 5 /1 2
XXXXX
XXXXX
- D a te C o d e
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to
obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
1
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APL78L05/12
Absolute Maximum Ratings
Symbol
VIN
TJ
TSTG
θJA
Parameter
Input Voltage
Operating Junction Temperature Range
Control Section
Power Transistor
Storage Temperature Range
Rating
Unit
30
VDC
°C
0 to 125
0 to 150
-65 to +150
Thermal Resistance from Junction to Ambient in Free Air
SOP-8
SOT-89/TO-92
°C
°C/W
160
180
Electrical Characteristics
VIN=10V, IOUT=40mA, TJ=25°C, CIN=0.33µF, COUT=0.1µF, unless otherwise specified
APL78L05
Symbol
Parameter
Test Condition
Typ.
Max.
Min.
VO
Output Voltage
Unit
4.8
5.0
5.2
Vdc
4.75
5
5.25
Vdc
29
26
9
5
2.8
150
100
60
30
6.0
0.15
0.08
1.9
1.5
0.1
1.0mA≤IOUT≤40mA
VO
Output Voltage (0° to +125°C) 7.0Vdc≤VIN≤20Vdc
Regline Line Regulation
Regload Load Regulation
IB
∆ IB
Quiescent Current
Quiescent Current Change
VIN-VO Dropout Voltage
Symbol
VIN=10V, 1.0mA≤IOUT≤40mA
7.0Vdc≤VIN≤20Vdc
8.0Vdc≤VIN≤20Vdc
1.0mA≤IOUT≤100mA
1.0mA≤IOUT≤40mA
Parameter
8.0Vdc≤VIN≤20Vdc
1.0mA≤IOUT≤40mA
IOUT=100mA
Test Condition
VO
Output Voltage
VO
Output Voltage (0° to +125°C) 14Vdc≤VIN≤27Vdc
mV
mV
mA
mA
Vdc
APL78L12
Typ.
Max.
Min.
Unit
11.5
12
12.5
Vdc
11.4
12
12.6
Vdc
250
100
50
6.5
mV
1.0mA≤IOUT≤40mA
VIN=19V, 1.0mA≤IOUT≤40mA
Regline
Line Regulation
Regload Load Regulation
IB
∆ IB
VIN-VO
14.5Vdc≤VIN≤27Vdc
1.0mA≤IOUT≤100mA
1.0mA≤IOUT≤40mA
Quiescent Current
Quiescent Current Change
Dropout Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
16Vdc≤VIN≤27Vdc
1.0mA ≤IOUT≤40mA
IOUT=100mA
2
1.5
1.9
mV
mA
mA
Vdc
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APL78L05/12
Application Circuit
V IN
A P L 7 8 L 0 5 /1 2
V OUT
C OUT=
0 .1 µ F
C in =
0 .3 3 µ F
Note1 : A common ground is required between the input and the output voltage. The input voltage must
remain typically 2V above the output voltage even during the low point on the input ripple voltage.
Note2 : Cin is required if regulator is located an appreciable distance from power supply filter.
Note3 : COUT is not needed for stability; however, it does improve transient response.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
3
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APL78L05/12
Typical Characteristics
Output Voltage vs. Input Voltage
Dropout Voltage vs. Junction Temperature
APL78L05
8
APL78L05
2.25
7
Dropout Voltage (V)
Output Voltage (V)
2
6
5
IO=1mA
4
IO=40mA
3
IO=100mA
2
IO=70mA
1.75
IO=40mA
1.5
IO=1mA
Dropout of Regulation is
defined as when
∆Vo=1% of Vo
1.25
1
1
0
0
2
4
6
8
10
0
25
Input Voltage (V)
75
100
125
Junction Temperature (°C)
Quiescent Current vs. Ambient Temperature
Quiescent Current vs. Input Voltage
APL78L05
3.0
APL78L05
3 .5
No Load
VIN=10V
IO=40mA
3
Quiescent Current (mA)
Quiescent Current (mA)
50
2.8
2.6
2.4
2.2
2 .5
2
1 .5
1
0 .5
0
0
25
50
75
100
125
0
Ambient Temperature (°C)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
5
10
15
20
25
30
35
Input Voltage (V)
4
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APL78L05/12
Typical Characteristics (Cont.)
Quiescent Current vs. Output Current
Dropout Voltage vs. Output Current
APL78L05
3
APL78L05
1.9
1.85
Dropout Voltage (V)
Quiescent Current (mA)
VIN=10V
2.5
2
1.5
1
1.8
1.75
1.7
Dropout of
Regulation is
defined as when
∆Vo=1% of Vo
1.65
0.5
1.6
0
0
20
40
60
80
100
0
20
40
60
80
Output Current (mA)
Output Current (mA)
PSRR vs. Frequency
Load-Transient Response
APL78L05
APL78L05
+0
100
COUT=0.1uF
COUT=0.1µF
VIN=10V
-10 IOUT=10mA
PSRR (dB)
-20
V
VOUT
(100mv/div)
OUT
-30
-40
-50
-60
OUT=10mA~80mA
=
IOUT
10mA~80mA
-70
-80
10
100
1k
10k
100k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
Time (20µs/div)
5
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APL78L05/12
Typical Characteristics (Cont.)
Maximum Power Dissipation vs.
Ambient Temperature APL78L05
Line Transient Response
Maximum Power Dissipation (mW)
APL78L05
VIN=9.5V~10.5V
COUT=0.1µF
IOUT=10mA
VOUT=10(mV/div)
TO-92 Type Package
No Heat Sink
1300
1100
900
700
500
300
100
25
Time (100us/div)
50
75
100
125
150
Ambient Temperature (°C)
Output Voltage vs.
Ambient Temperature
Region of Stable ESR vs.
Output Current
APL78L05
APL78L05
5.02
10
VIN=10V
IO=40mA
COUT=0.1uF
COUTESR(Ω)
Output Voltage(V)
5.015
5.01
5.005
1
Stable Region
0.1
5
Untested
4.995
0.01
0
25
50
75
100
125
0
Ambient Temperature (°C)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
20
40
60
80
100
Output Current(mA)
6
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APL78L05/12
Typical Characteristics
Figure 1. Current Regulator
The APL78L05/12 Series of fixed voltage regulators
are designed with Thermal Overload Protection that
Input
shuts down the circuit when subjected to an excessive power overload condition. Internal Short Circuit
APL78L05
R
0.33µ F
Protection limits the maximum current the circuit will
lO
pass.
Constant
Current to
Grounded
Load
In many low current applications, compensation ca-
The APL78L00 regulators can also be used as a cur-
pacitors are not required. However, it is recom-
rent source when connected as above. In order to
mended that the regulator input be bypassed with a
minimize dissipation the APL78L05 is chosen in this
capacitor if the regulator is connected to the power
application. Resistor R determines the current as
supply filter with long wire lengths, or if the output
follows :
IO =
load capacitance is large. The input bypass capacitor should be selected to provide good high-frequency
5.0V
R
+ IB
IB =3.8mA over line and load changes
characteristics to insure stable operation under all
For example, a 100mA current source would require
load conditions. A 0.33µF or larger tantalum, mylar,
R to be a 50Ω, 1/2W resistor and the output voltage
or other capacitor having low internal impedance at
compliance would be the input voltage less 7V.
high frequencies should be chosen. The bypass caFigure 2. ±15V Tracking Voltage Regulator
pacitor should be mounted with the shortest possible
leads directly across the regulators input terminals.
+20V
+VO
APL78L15
Good construction techniques should be used to mini-
10K
0.33µ F
2
7
mize ground loops and lead resistance drops since
6
MC1741
3
the regulator has no external sense lead. Bypassing
4
the output is also recommended.
0.33µ F
10K
MPSA70
6.5
-VO
20V
MPSU55
Figure 3. Positive and Negative Regulator
+VI
0.1µ F
0.33µ F
-VI
0.33µ F
+VO
APL78LXX
APL79LXX
0.1µ F
-VO
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
7
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APL78L05/12
Packaging Information
E
e1
0.015X45
SOP-8 pin ( Reference JEDEC Registration MS-012)
H
e2
D
A1
1
L
0.004max.
Dim
A
Mi ll im et er s
Inche s
A
Min .
1. 35
Max .
1. 75
Min.
0. 053
Max .
0. 069
A1
D
E
0. 10
4. 80
3. 80
0. 25
5. 00
4. 00
0. 004
0. 189
0. 150
0. 010
0. 197
0. 157
H
L
e1
e2
5. 80
0. 40
0. 33
6. 20
1. 27
0. 51
0. 228
0. 016
0. 013
0. 244
0. 050
0. 020
φ 1
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
1. 27B S C
0. 50B S C
8°
8°
8
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APL78L05/12
Package Information
TO-92
3
J
e
e1
2
D
1
L1
Q
b2
b
S
L2
A
S
E
L
SEATING PLANE
Dim
Millimeters
Min.
Max.
Inches
Min.
Max.
A
4.58
5.33
0.170
0.210
φ b
0.41
0.53
0.160
0.021
φ b2
0.41
0.48
0.160
0.019
φ D
E
4.96
5.20
0.175
0.205
3.94
4.19
0.125
0.165
e
2.42
2.66
0.095
0.105
e1
1.15
1.39
0.045
0.055
J
3.43
0.135
L
12.70
0.500
L1
1.27
0.050
L2
6.35
0.250
Q
2.93
0 . 11 5
S
2.42
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
2.66
9
0.080
0.105
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APL78L05/12
Package Information
SOT-89 (Reference EIAJ ED-7500A Reg stration SC-62)
D
D1
a
E
H
1
2
3
L
C
B1
B
e
e1
A
a
D im
A
B
B1
C
D
D1
e
e1
E
H
L
α
M illim eters
M in.
1.40
0.40
0.35
0.35
4.40
1.35
Inches
M ax.
1.60
0.56
0.48
0.44
4.60
1.83
M in.
0.055
0.016
0.014
0.014
0.173
0.053
1.50 B SC
3.00 B SC
2.29
3.75
0.80
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
M ax.
0.063
0.022
0.019
0.017
0.181
0.072
0.059 BSC
0.118 B SC
2.60
4.25
1.20
10°
10
0.090
0.148
0.031
0.102
0.167
0.047
10°
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APL78L05/12
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ram p-up
TL
tL
Tsm ax
Tsm in
Ram p-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
11
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APL78L05/12
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Tem peratures
3
3
Package Thickness
Volum e m m
Volum e m m
<350
≥ 350
<2.5 m m
240 +0/-5°C
225 +0/-5°C
≥2.5 m m
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Tem peratures
3
3
3
Package Thickness
Volum e mm
Volum e mm
Volum e mm
<350
350-2000
>2000
<1.6 m m
260 +0°C*
260 +0°C*
260 +0°C*
1.6 m m – 2.5 m m
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 m m
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device m anufacturer/supplier shall assure process com patibility up to and
including the stated classification tem perature (this m eans Peak reflow tem perature +0°C.
For exam ple 260°C+0°C) at the rated MSL level.
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t
E
D
P
Po
P1
F
Bo
W
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
D1
12
Ko
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APL78L05/12
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
A
B
330±1
62 ± 1.5
F
D
SOP-8
5.5 ± 0.1
C
12.75 +
0.1 5
D1
J
T1
T2
2 + 0.5
12.4 +0.2
2± 0.2
Po
P1
Ao
W
12 + 0.3
- 0.1
Bo
2.0 ± 0.1
6.4 ± 0.1
5.2± 0.1
1.55±0.1 1.55+ 0.25 4.0 ± 0.1
P
E
8± 0.1
1.75± 0.1
Ko
t
2.1± 0.1 0.3±0.013
(mm)
H2
H2A H2
H2
D2
A0
M
H3
H4
H
W1
H1
W2
L
L1
W
D
F1F2
T2
T
T1
D1
P1
P
P2
40
Box
Dimensions
205
C2
C1
B2
B0
B1
C0
A3
330
A2
A1
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
T3
T4
UNIT : mm
13
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APL78L05/12
Carrier Tape & Reel Dimensions(Cont.)
Application
TO-92
A
A1
A2
A3
B0
B1
B2
C0
C1
3.18~12
90±1
76±1
30±1
90±1
31±1
76±1
5.8
3.8
C2
H3
H4
L
L1
P
P1
P2
T
2.5 MIN
12.7±0.2
6.35±0.4
7.8
T1
27.0 MAX 20.0 MAX 11.0 MAX
T2
1.42 MAX 0.36~0.68
T3
T4
W
W1
W2
15
1.7
17.5~19
5.0~7.0
0.5 MAX
50.8±0.5 0.55 MAX
(mm)
Cover Tape Dimensions
Application
SOP- 8
TO-92
Carrier Width
12
17.5~19
Cover Tape Width
9.3
5.0~7.0
Devices Per Reel
2500
2000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
14
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