AD ADT7462ACPZ-500RL7 Flexible temperature and voltage monitor and system fan controller Datasheet

Flexible Temperature and Voltage Monitor
and System Fan Controller
ADT7462
FEATURES
GENERAL DESCRIPTION
One local and up to three remote temperature channels
Series resistance cancellation on remote channels
Thermal protection using THERM pins
Up to four PWM fan drive outputs
Supports both high and low frequency PWM drives
Up to eight TACH inputs
Measures the speed of 3-wire and 4-wire fans
Automatic fan speed control loop
Includes dynamic TMIN control
Monitors up to 13 voltage inputs
Monitors up to 7 VID inputs
Includes VID-on-fly support
Bidirectional reset
Chassis intrusion detect
SMBus 1.1- and SMBus 1.0-compatible
3.3 V and 5 V operation
Extended operating range from −40°C to +125°C
Space-saving 32-lead chip scale package
The ADT7462 is a flexible systems monitor IC, suitable for use
in a wide variety of applications. It can monitor temperature in
up to three remote locations, as well as its ambient temperature.
There are up to four PWM outputs. These can be used to control
the speed of a cooling fan by varying the % duty cycle of the
PWM drive signal applied to the fan. The ADT7462 supports
high frequency PWM for 4-wire fans and low frequency PWM
for 2-wire and 3-wire fans. There are up to eight TACH inputs,
which can be used to measure the speed of 3-wire and 4-wire
fans. There are up to 13 voltage monitoring inputs, ranging
from 12 V to 0.9 V.
The ADT7462 is fully compatible with SMBus 1.1 and SMBus 1.0.
The ADT7462 also includes a THERM I/O and a RESET I/O.
The ADT7462 is available in a 32-lead LFCSP_VQ. Many of the
pins are multifunctional. There are five easy configuration options,
which are set up using the easy configuration register. Users pick
the configuration closest to their requirements; individual pins
can be reconfigured after the easy configuration option has
been chosen.
APPLICATIONS
Servers and personal computers
Telecommunications equipment
Test equipment and measurement instruments
FUNCTIONAL BLOCK DIAGRAM
SMBus
ADDRESS
SCL SDA
ALERT
ADT7462
SMBus
ADDRESS
SELECTION
VID
REGISTER
PWM1 TO PWM4
PWM REGISTERS
ACOUSTIC
ENHANCEMENT
CONTROL
FAN2MAX
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC TMIN
CONTROL
FAN SPEED
COUNTER
TACH1 TO TACH8
INTERRUPT
MASKING
CI
LIMIT
COMPARATORS
THERMAL
PROTECTION
VALUE AND LIMIT
REGISTERS
INPUT SIGNAL
CONDITIONING
AND ANALOG
MULTIPLEXER
THERMAL DIODE INPUTS
VOLTAGE INPUTS
PWM
CONFIGURATION
REGISTERS
INTERRUPT
STATUS
REGISTERS
PERFORMANCE
MONITORING
VR_HOT2
VR_HOT1
THERM2
THERM1
ADDRESS POINTER
REGISTER
13-BIT
ADC
BAND GAP
TEMPERATURE
SENSOR
BAND GAP
REFERENCE
GND
RESET
CIRCUIT
GPIO STATUS AND
CONFIGURATION
REGISTERS
SCSI STATUS
RESET
GPIO1 TO GPIO8
SCSI_TERM1 AND
SCSI_TERM2
05569-001
VID0 TO VID6
SERIAL BUS
INTERFACE
Figure 1.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADT7462
TABLE OF CONTENTS
Features ...................................................................................... 1
Fan Drive Using PWM Control........................................33
Applications............................................................................... 1
Fan Speed Measurement and Control..................................35
General Description ................................................................. 1
TACH Inputs .......................................................................35
Functional Block Diagram ...................................................... 1
Fan Speed Measurement....................................................35
Revision History ....................................................................... 3
PWM Logic State ................................................................37
Specifications............................................................................. 4
Fan Speed Control ..............................................................37
Timing Diagram ................................................................... 5
Programming the Automatic Fan Speed Control Loop 39
Absolute Maximum Ratings.................................................... 6
Step 1—Configuring the MUX.........................................40
Thermal Resistance .............................................................. 6
Step 2—TMIN Settings for Thermal Calibration Channels . 40
ESD Caution.......................................................................... 6
Step 3—PWMMIN for Each PWM (Fan) Output.............42
Pin Configuration and Function Descriptions..................... 7
Step 4—PWMMAX for PWM (Fan) Outputs ....................42
Functional Description: Easy Configuration Options ..10
Step 5—TRANGE for Temperature Channels ......................43
Typical Performance Characteristics ...................................15
Step 6—TTHERM for Temperature Channels......................46
Serial Bus Interface.................................................................18
Step 7—THYST for Temperature Channels ........................47
ADD Input...........................................................................18
Dynamic TMIN Control Programming .............................49
SMBus Fixed Address ........................................................18
Step 8—Operating Points for Temperature Channels ...49
SMBus Operation ...............................................................18
Step 9—High and Low Limits for Temperature Channels 49
Write Operations ................................................................20
Step 10—Monitoring THERM..........................................52
Read Operations .................................................................21
Enhancing System Acoustics.............................................52
Alert Response Address.....................................................22
Step 11—Ramp Rate for Acoustic Enhancement ...........54
SMBus Timeout ..................................................................22
Fan Freewheeling Test Mode.............................................56
Temperature and Voltage Measurement..............................23
THERM I/O Operation .........................................................57
Temperature Measurement ...............................................23
General-Purpose I/O Pins .....................................................59
Series Resistance Cancellation..........................................24
EDO Circuitry.....................................................................59
Voltage Measurement ........................................................26
Other Digital Inputs ...........................................................60
Battery Measurement Input (VBATT).................................28
Reset I/O ..............................................................................60
ADC Information...............................................................29
Chassis Intrusion Input......................................................60
Dynamic VID Monitoring ....................................................30
Power-Up Sequence................................................................61
VID Code ............................................................................30
XOR Tree Test..........................................................................62
Dynamic VID Monitoring ................................................30
Register Map............................................................................63
Status and Mask Registers and ALERT................................32
Outline Dimensions ...............................................................90
Fan Control..............................................................................33
Ordering Guide...................................................................90
Rev. 0 | Page 2 of 92
ADT7462
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 3 of 92
ADT7462
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. 1
Table 1.
Parameter
POWER SUPPLY
Supply Voltage
Supply Current
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor, TA, Accuracy
Min
Typ
Max
Unit
3.0
3.3
1.5
5.5
4
V
mA
±0.5
±0.5
±0.5
±0.5
±2.25
±3.25
±3
±4
0.25
±2.25
±3.25
±2.75
±3.5
0.25
°C
°C
°C
°C
°C
°C
°C
°C
°C
°C
μA
μA
μA
kΩ
Resolution
Remote Sensor, TD, Accuracy (−40 ≤ TD ≤ +125°C)
±0.5
±0.5
±0.5
±0.5
Resolution
Remote Sensor Source Current3
85
34
5
2
Series Resistance Cancellation 3
ANALOG-TO-DIGITAL CONVERTER
Total Unadjusted Error, TUE 4, 5
Differential Nonlinearity, DNL
Conversion Time (Voltage Input)3
Conversion Time (Local Temperature)3
Conversion Time (Remote Temperature)3
INPUT RESISTANCE
Pin 7, Pin 8, Pin 13, Pin 21, Pin 22, Pin 25, Pin 28,
Pin 29
Pin 15, Pin 19
Pin 23, Pin 24
Pin 26, VBATT and +1.2V (When Measured)
VBATT Current Drain (When Measured)
VBATT Current Drain (When Not Measured)
FAN RPM TO DIGITAL CONVERTER
Accuracy
Internal Clock Frequency
OPEN DRAIN OUTPUTS (PWM, GPIO)
High Level Output Leakage Current, IOH
Output Low Voltage, VOL
DIGITAL OUTPUT (RESET, ALERT, THERM)
Output Low Voltage, VOL
RESET Pulse Width3
RESET Threshold
RESET Hysteresis3
OPEN DRAIN SERIAL BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Leakage Current, IOH
8.53
9.01
38.36
±3.5
±1
9.86
10.38
42.09
%
LSB
ms
ms
ms
Test Conditions/Comments
ADC active, interface inactive 2
TA Conditions
VCC Conditions
0 ≤ TA ≤ 85°C
3 V ≤ VCC ≤ 3.6 V
−40 ≤ TA ≤ +100°C
3 V ≤ VCC ≤ 3.6 V
0 ≤ TA ≤ 85°C
4.5 V ≤ VCC ≤ 5.5 V
−40 ≤ TA ≤ +100°C
4.5 V ≤ VCC ≤ 5.5 V
0 ≤ TA ≤ 85°C
−40 ≤ TA ≤ +100°C
0 ≤ TA ≤ 85°C
−40 ≤ TA ≤ +100°C
3 V ≤ VCC ≤ 3.6 V
3 V ≤ VCC ≤ 3.6 V
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
High level
Mid level
Low level
The ADT7462 cancels 2 kΩ in series with the
remote thermal diode
8 bits
140
kΩ
Attenuators enabled
100
225
66
120
80
16
kΩ
kΩ
kΩ
nA
nA
Attenuators enabled
Attenuators enabled
Attenuators cannot be disabled
CR2032 battery life > 10 years
CR2032 battery life > 10 years
82.8
90
0.1
140
3
180
3.05
70
0.1
140
100
±8
97.2
%
kHz
±1
0.4
μA
V
VOUT = VCC
IOUT = −3 mA, VCC = +3.3 V
0.4
V
ms
V
mV
IOUT = −3 mA, VCC = +3.3 V
3.1
0.4
±1
Rev. 0 | Page 4 of 92
V
μA
Falling voltage
IOUT = −3 mA, VCC = +3.3 V
VOUT = VCC
ADT7462
Parameter
SERIAL BUS DIGITAL INPUTS (SDA AND SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND
THERM, TACH, GPIO, VR_HOT, SCSI_TERM)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH (VID0 to VID6)
Input High Voltage, VIH (THERM)
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT CURRENTS
Input High Current, IIH
Input Low Current, IIL
Input Capacitance3
SERIAL BUS TIMING3
Clock Frequency
Glitch Immunity, tSW
Bus Free Time
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Detect Clock Low Timeout
Min
Typ
Max
Unit
0.4
V
V
mV
2.1
500
1.7
0.8
0.65
2/3 VCCP1
0.4
500
−1
+1
5
400
50
1.3
0.6
0.6
1.3
0.6
1000
300
100
25
Test Conditions/Comments
V
V
V
V
V
mV
Bit 3 and Bit 4 of Configuration Register 3 = 0
Bit 3 and Bit 4 of Configuration Register 3 = 0
Bit 3 of Configuration Register 3 = 1
Bit 4 of Configuration Register 3 = 1
Bit 3 and Bit 4 of Configuration Register 3 = 1
μA
μA
pF
VIN = VCC
VIN = 0
kHz
ns
μs
μs
μs
μs
μs
ns
ns
ns
ms
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally enabled
1
All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent the most likely parametric norm. Logic inputs
accept input high voltages up to 5 V, even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a
falling edge and VIH = 2.0 V for a rising edge.
2
Unused digital inputs connected to GND.
3
Guaranteed by design, not production tested.
4
Note that this specification does not apply if Pin 26 (VBATT, +1.2V) is being measured in single-channel mode. See Figure 22 in Typical Performance Characteristics for
VBATT accuracy.
5
For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of VCC ≥ 3.3 V and +25°C ≤ TA ≤ +125°C apply.
TIMING DIAGRAM
tR
tF
tHD;STA
tLOW
SCL
tHIGH
tHD;STA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tBUF
P
S
S
Figure 2. Serial Bus Timing Diagram
Rev. 0 | Page 5 of 92
P
05569-002
SDA
ADT7462
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Voltage on +12V Pin
Voltage on VBATT Pin
Voltage on Any Other Input or
Output Pin
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(Soldering 10 sec)
IR Reflow Peak Temperature
ESD Rating
Rating
6.5 V
20 V
4V
−0.3 V to +6.5 V
±5 mA
±20 mA
150°C
−40°C to +125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
300°C
260°C
1500 V
Package Type
32-Lead LFCSP_VQ
θJA
32.5
θJC
32.71
Unit
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 92
ADT7462
27 FAN2MAX/CI
28 THERM1/+1.5V1/GPIO7/VID6
29 THERM2/+1.5V2/GPIO8
30 PWM3
26 VR_HOT2/+1.2V/V BATT
25 VR_HOT1/+1.2V/+3.3V
24 VCCP2 /+1.5V/+1.8V/+2.5V
PIN 1
INDICATOR
2
3
23 VCCP1 /+1.5V/+1.8V/+2.5V
22 TACH8/+12V3
4
ADT7462
5
TOP VIEW
(Not to Scale)
6
21 TACH7/+5V
20 D3–/SCSI_TERM2
19 D3+/+1.25V/+0.9V
16
15
14
13
SCL
SDA
ADD
ALERT
PWM4/+3.3V
RESET
D1+/+2.5V/+1.8V
D1–/SCSI_TERM1
12
17 D2+
11
18 D2–
8
9
7
05569-009
1
10
VID0/GPIO1/TACH1
VID1/GPIO2/TACH2
VID2/GPIO3/TACH3
VID3/GPIO4/TACH4
VCC
GND
TACH5/+12V1
TACH6/+12V2
31 VID4/GPIO5/PWM1
32 VID5/GPIO6/PWM2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
Mnemonic
VID0/GPIO1/TACH1
2
VID1/GPIO2/TACH2
3
VID2/GPIO3/TACH3
4
VID3/GPIO4/TACH4
5
VCC
6
7
GND
TACH5/+12V1
8
TACH6/+12V2
9
10
11
12
SCL
SDA
ADD
ALERT
Description
VID0: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO1: Open Drain I/O. General-purpose input/output.
TACH1: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
VID1: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO2: Open Drain I/O. General-purpose input/output.
TACH2: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
VID2: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO3: Open Drain I/O. General-purpose input/output.
TACH3: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
VID3: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO4: Open Drain I/O. General-purpose input/output.
TACH4: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is
required. The ADT7462 can also be powered from a 5 V supply.
Ground Pin.
TACH5: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 5.
+12V1: Analog Input. Monitors 12 V power supply (#1). Attenuators switched on by default.
TACH6: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 6.
+12V2: Analog Input. Monitors 12 V power supply (#2). Attenuators switched on by default.
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
The state of this pin on power-up determines the SMBus device address.
Active Low Digital Output. The ALERT pin is used to signal out-of-limit comparisons of
temperature, voltage, and fan speed. This is compatible with SMBus ALERT.
Rev. 0 | Page 7 of 92
POR
Default
TACH1
TACH2
TACH3
TACH4
VCC
GND
TACH5
TACH6
SCL
SDA
ADD
ALERT
ADT7462
Pin
No.
13
Mnemonic
PWM4/+3.3V
14
RESET
15
D1+/+2.5V/+1.8V
16
D1−/SCSI_TERM1
17
18
19
D2+
D2−
D3+/+1.25V/+0.9V
20
D3−/SCSI_TERM2
21
TACH7/+5V
22
TACH8/+12V3
23
VCCP1/+1.5V/+1.8V/+2.5V
24
VCCP2/+1.5V/+1.8V/+2.5V
25
VR_HOT1/+1.2V/+3.3V
26
VR_HOT2/+1.2V/VBATT
27
FAN2MAX/CI
28
THERM1/+1.5V1/GPIO7/
VID6
Description
PWM4: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated
output to control the speed of Fan 4.
+3.3V: Analog Input. Monitors 3.3 V power supply.
Active Low Open Drain Digital I/O. Power-on reset, 5 mA driver (weak 100 kΩ pull-up), active
low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESET is asserted whenever
VCC is below the reset threshold. It remains asserted for approximately 180 ms after VCC rises
above the reset threshold. Pin 14 also functions as an active low RESET input and resets all
unlocked registers to their default values.
D1+: Anode Connection to Thermal Diode 1.
+2.5V: Monitors 2.5 V analog input.
+1.8V: Monitors 1.8 V analog input.
D1−: Cathode Connection to Thermal Diode 1.
SCSI_TERM1: Digital Input, SCSI Termination 1.
Anode Connection to Thermal Diode 2.
Cathode Connection to Thermal Diode 2.
D3+: Anode Connection to Thermal Diode 3.
+1.25V: Monitors 1.25 V analog input.
+0.9V: Monitors 0.9 V analog input.
D3−: Cathode connection to Thermal Diode 3.
SCSI_TERM2: Digital Input, SCSI Termination 2.
TACH7: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 7.
+5V: Analog Input. Monitors 5 V power supply.
TACH8: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 8.
+12V3: Analog Input. Monitors 12 V power supply (#3).
VCCP1: Monitors 1.2 V analog input.
+1.5V: Monitors 1.5 V analog input.
+1.8V: Monitors 1.8 V analog input.
+2.5V: Monitors 2.5 V analog input.
VCCP2: Monitors 1.2 V analog input.
+1.5V: Monitors 1.5 V analog input.
+1.8V: Monitors 1.8 V analog input.
+2.5V: Monitors 2.5 V analog input.
VR_HOT1: Digital Input Indicating Overtemperature Event on Voltage Regulator.
+1.2V1: 0 V to 1.2 V Analog Input. For example, can be used to monitor GBIT.
+3.3V: Analog Input. Monitors +3.3 V power supply.
VR_HOT2: Digital Input Indicating Overtemperature Event on Voltage Regulator.
+1.2V2: 0 V to 1.2 V Analog Input. For example, can be used to monitor FSB_VTT.
VBATT: Analog Input. Monitors battery voltage, nominally 3 V.
FAN2MAX: Sets fan to maximum speed when a fan fault condition occurs. Bidirectional open
drain, active low I/O.
CI: An active high input that captures a chassis intrusion event in Bit 6 of the digital status
register. This bit remains set until cleared, as long as battery voltage is applied to the VBATT
input, even when the ADT7462 is powered off.
THERM1: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT
output of the Intel® Pentium 4 processor to time and monitor PROCHOT assertions. Can be
used as an output to signal overtemperature conditions or for clock modulation purposes.
+1.5V1: 0 V to 1.5 V Analog Input. Can be used to monitor ICH.
GPIO7: Open Drain I/O. General-purpose input/output.
VID6: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
Rev. 0 | Page 8 of 92
POR
Default
PWM4
RESET
D1+
D1−
D2+
D2−
D3+
D3−
TACH7
TACH8
+1.8V
+2.25V
+3.3V
VBATT
CI
THERM1
ADT7462
Pin
No.
29
Mnemonic
THERM2/+1.5V2/GPIO8
30
PWM3
31
VID4/GPIO5/PWM1
32
VID5/GPIO6/PWM2
Description
THERM2: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT
output of the Intel Pentium 4 processor to time and monitor PROCHOT assertions. Can be
used as an output to signal overtemperature conditions or for clock modulation purposes.
+1.5V2: 0 V to 1.5 V Analog Input. Can be used to monitor 3GIO.
GPIO8: Open Drain I/O. General-purpose input/output.
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output
to control speed of Fan 3.
VID4: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO5: Open Drain I/O. General-purpose input/output.
PWM1: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated
output to control the speed of Fan 1.
VID5: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to
the VID value register (0x97).
GPIO6: Open Drain I/O. General-purpose input/output.
PWM2: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated
output to control the speed of Fan 2.
Rev. 0 | Page 9 of 92
POR
Default
THERM2
PWM3
PWM1
PWM2
Configuration Option 1
Configuration Option 1 is the default configuration. It is also
the most suitable for thermal monitoring, voltage monitoring,
and fan control for single and dual processor systems.
Two THERM I/Os
Voltage monitoring
+3.3V
+2.5V
+1.8V
VBATT
26 VBATT
25 +3.3V
27 CI
28 THERM1
29 THERM2
21
5
TOP VIEW
(Not to Scale)
20
6
19
16
15
14
17
13
18
8
12
7
Table 6. Configuration Option 1
The following is a detailed description of the five easy
configuration options that are available.
Four PWM drives and eight TACH inputs
ADT7462
Figure 4. Configuration Option 1
Once the most convenient easy configuration option has been
set, the user can configure any of the pins individually. The
setup complete bit (Bit 5 of Register 0x01) must then be set to 1
to indicate that the ADT7462 is configured correctly, and then
monitoring of the selected channels begins.
One local and three remote temperature channels
22
4
+2.5V
+1.8V
TACH8
TACH7
D3–
D3+
D2–
D2+
05569-010
Register 0x14 Setting
Bit 0 = 1
Bit 1 = 1
Bit 2 = 1
Bit 3 = 1
Bit 4 = 1
Features of Configuration Option 1 include the following:
3
23
SCL
SDA
ADD
ALERT
PWM4
RESET
D1+
D1–
Easy Configuration Option
Option 1
Option 2
Option 3
Option 4
Option 5
PIN 1
INDICATOR
2
9
Table 5. Easy Configuration Register Settings
24
1
11
TACH1
TACH2
TACH3
TACH4
VCC
GND
TACH5
TACH6
10
There are a number of multifunctional pins on the ADT7462
that need to be configured on power-up to suit the desired
application. Note that due to the large number of pins that need
to be configured, it could take several SMBus transactions to
achieve the required configuration. For this reason, the ADT7462
has five easy configuration options. The user sets a bit in the
easy configuration option register (0x14) to set up the required
configuration (see Table 5).
31 PWM1
32 PWM2
FUNCTIONAL DESCRIPTION:
EASY CONFIGURATION OPTIONS
30 PWM3
ADT7462
Pin
11
21
31
41
7
8
13
15
16
19
20
21
22
23
24
25
26
27
281
29
311
321
1
Function
TACH1
TACH2
TACH3
TACH4
TACH5
TACH6
PWM4
D1+
D1−
D3+
D3−
TACH7
TACH8
+1.8V
+2.5V
+3.3V
VBATT
CI
THERM1
THERM2
PWM1
PWM2
Configuration Register
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Bit Value
Bit 4 = 1
Bit 3 = 1
Bit 2 = 1
Bit 1 = 1
Bit 0 = 1
Bit 7 = 1
Bit 6 = 1
Bit 6 = 1
Bit 6 = 1
Bit 5 = 1
Bit 5 = 1
Bit 3 = 1
Bit 2 = 1
Bits [1:0] = 10
Bits [7:6] = 01
Bits [5:4] = 00
Bits [3:2] = 00
Bit 1 = 1
Bits [7:6] = 1×
Bits [5:4] = 1×
Bit 3 = 1
Bit 2 = 1
If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7
of Pin Configuration Register 1 (0x10) = 1.
RESET I/O
CI (chassis intrusion) or FAN2MAX
Figure 4 shows the pin configuration when Configuration
Option 1 is chosen.
Rev. 0 | Page 10 of 92
25 VR_HOT1
5
TOP VIEW
(Not to Scale)
20
6
19
17
16
18
8
15
7
Two VCCP voltage monitoring channels
VCCP2
VCCP1
TACH8
TACH7
D3–
D3+
D2–
D2+
05569-011
26 VR_HOT2
28 THERM1
29 THERM2
21
SCL
SDA
ADD
ALERT
PWM4
RESET
D1+
D1–
RESET I/O
Figure 5 shows the pin configuration when Configuration
Option 2 is chosen.
22
ADT7462
9
• Two VRD inputs
23
4
14
Two THERM I/Os
3
13
Up to four PWM drives and up to eight TACH inputs
(VID pins and TACHs/PWMs are MUX’d together)
PIN 1
INDICATOR
2
12
One local and three remote thermal channels
24
1
11
TACH1
TACH2
TACH3
TACH4
VCC
GND
TACH5
TACH6
10
Features of Configuration Option 2 include the following:
30 PWM3
32 PWM2
Configuration Option 2 is used for thermal monitoring and fan
control for Processor 1 and Processor 2 in a dual processor
system. It can also monitor one set of VIDs, if required.
31 PWM1
Configuration Option 2
27 FAN2MAX
ADT7462
Figure 5. Configuration Option 2
Table 7. Configuration Option 2
Pin
11
21
31
41
7
8
13
15
16
19
20
21
22
23
24
25
26
27
281
29
311
321
1
Function
TACH1
TACH2
TACH3
TACH4
TACH5
TACH6
PWM 4
D1+
D1−
D3+
D3−
TACH7
TACH8
VCCP1
VCCP2
VR_HOT1
VR_HOT2
FAN2MAX
THERM1
THERM2
PWM1
PWM2
Configuration Register
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Bit Value
Bit 4 = 1
Bit 3 = 1
Bit 2 = 1
Bit 1 = 1
Bit 0 = 1
Bit 7 = 1
Bit 6 = 1
Bit 6 = 1
Bit 6 = 1
Bit 5 = 1
Bit 5 = 1
Bit 3 = 1
Bit 2 = 1
Bits [1:0] = 00
Bits [7:6] = 00
Bits [5:4] = 1×
Bits [3:2] = 1×
Bit 1 = 0
Bits [7:6] = 1×
Bits [5:4] = 1×
Bit 3 = 1
Bit 2 = 1
If VIDs are selected, these pins are configured as VIDs. To enable VIDs,
set Bit 7 of Pin Configuration Register 1 (0x01) = 1.
Rev. 0 | Page 11 of 92
One local and one remote temperature channels
Up to three PWM drives and up to four TACH inputs
RESET I/O
Figure 6 shows the pin configuration when Configuration
Option 3 is chosen.
27 CI
28 +1.5V/GPIO7
26 VBATT
25 +1.2V
22 +12V3
4
ADT7462
5
TOP VIEW
(Not to Scale)
6
21 +5V
20 SCSI_TERM2
19 +0.9V
16
15
SCL
SDA
ADD
ALERT
+3.3V
RESET
+1.8V
SCSI_TERM1
14
17 D2+
13
18 D2–
8
12
7
05569-012
3
9
Three +12V
+5V
+3.3V
+2.5V
Mem_Core (+1.8V or +2.5V)
Two +1.5V (3GIO and ICH)
+1.2V (VCCP1, VCCP2, VCCP, GBIT)
Mem_VTT (0.984 V)
VBATT
24 VCCP2
23 VCCP1
PIN 1
INDICATOR
2
11
• Up to 13 different voltages monitored
1
30 PWM3
32 PWM2
TACH1
TACH2
TACH3
TACH4
VCC
GND
+12V1
+12V2
Features of Configuration Option 3 include the following:
10
Configuration Option 3 is chosen when the user wants to
monitor all the voltages in the system for Processor 1 and
Processor 2. Additional pins can be configured for fan control,
VIDs, or GPIOs, as required.
31 PWM1
Configuration Option 3
29 +1.5V/GPIO8
ADT7462
Figure 6. Configuration Option 3
Table 8. Configuration Option 3
Pin
11
21
31
41
7
8
13
15
16
19
20
21
22
23
24
25
26
27
281
29
311
321
1
Function
TACH1
TACH2
TACH3
TACH4
+12V1
+12V2
+3.3V
+1.8V
SCSI_TERM1
+0.9V
SCSI_TERM2
+5V
+12V3
VCCP1
VCCP2
+1.2V
VBATT
CI
+1.5V/GPIO7
+1.5V/GPIO8
PWM1
PWM2
Configuration Register
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Bit Value
Bit 4 = 1
Bit 3 = 1
Bit 2 = 1
Bit 1 = 1
Bit 0 = 0
Bit 7 = 0
Bit 6 = 0
Bit 6 = 0
Bit 6 = 0
Bit 5 = 0
Bit 5 = 0
Bit 3 = 0
Bit 2 = 0
Bits [1:0] = 00
Bits [7:6] = 00
Bits [5:4] = 01
Bits [3:2] = 00
Bit 1 = 1
Bits [7:6] = 01
Bits [5:4] = 01
Bit 3 = 1
Bit 2 = 1
If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7
of Pin Configuration Register 1 (0x01) = 1.
Rev. 0 | Page 12 of 92
26 VBATT
25 VR_HOT1
27 FAN2MAX
28 THERM1/+1.5V
30 PWM3
32 PWM2
Configuration Option 4 is chosen when the user wants to
monitor temperature, voltages, and fans for Processor 1 in
a dual processor system.
31 PWM1
Configuration Option 4
29 THERM2/+1.5V
ADT7462
Features of Configuration Option 4 include the following:
23 VCCP1
22 +12V3
4
ADT7462
5
TOP VIEW
(Not to Scale)
21 +5V
16
15
SCL
SDA
ADD
ALERT
PWM 4
RESET
D1+
D1–
14
17 D2+
13
18 D2–
8
Figure 7. Configuration Option 4
Table 9. Configuration Option 4
VRD input
Pin
11
21
31
41
7
8
13
15
16
19
20
21
22
23
24
25
26
27
281, 2
Figure 7 shows the pin configuration when Configuration
Option 4 is chosen.
19 +0.9V
7
THERM I/O
RESET I/O
20 SCSI_TERM2
05569-013
6
9
+12V
+5V
+3.3V
Two +1.5V
+1.2V (VCCP1)
+0.984V (Mem_VTT)
VBATT
3
12
Up to eight voltages monitored
24 +2.5V
PIN 1
INDICATOR
2
11
Up to four PWM drives and six TACH inputs
1
10
TACH1
TACH2
TACH3
TACH4
VCC
GND
TACH5
TACH6
One local and two remote temperature channels
292
311
321
1
Function
TACH1
TACH2
TACH3
TACH4
TACH5
TACH6
PWM4
D1+
D1−
+0.9V
SCSI_TERM2
+5V
+12V3
VCCP1
+2.5V
VR_HOT1
VBATT
FAN2MAX
THERM1/
+1.5V
THERM2/
+1.5V
PWM1
PWM2
Configuration Register
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Bit Value
Bit 4 = 1
Bit 3 = 1
Bit 2 = 1
Bit 1 = 1
Bit 0 = 1
Bit 7 = 1
Bit 6 = 1
Bit 6 = 1
Bit 6 = 1
Bit 5 = 0
Bit 5 = 0
Bit 3 = 0
Bit 2 = 0
Bits [1:0] = 00
Bits [7:6] = 01
Bits [5:4] = 1×
Bits [3:2] = 00
Bit 1 = 0
See
Table 51
See
Table 51
Bit 3 = 1
Bit 2 = 1
If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set
Bit 7 of Pin Configuration Register 1 (0x01) = 1.
2
It is not possible to monitor +1.5V monitoring on Pin 29 and THERM1 on
Pin 28. Pin 28 and Pin 29 must BOTH be configured as either +1.5V monitoring or as THERM I/O (see Table 51).
Rev. 0 | Page 13 of 92
25 +1.2V
ADT7462
21
5
TOP VIEW
(Not to Scale)
20
6
19
17
SCL
SDA
ADD
ALERT
+3.3V
RESET
+2.5V
SCSI_TERM1
16
18
8
14
7
VCCP2
+1.8V
TACH8
TACH7
D3–
D3+
D2–
D2+
05569-014
27 FAN2MAX
29 THERM2/+1.5V
26 VR_HOT2
22
4
9
Two +12V
+3.3V
Mem_Core (+1.969V)
+1.8 V
Two +1.5V
+1.2V (VCCP2)
23
15
Voltage monitoring
3
13
Up to three PWM drives and up to six TACHs
PIN 1
INDICATOR
2
12
One local and two remote temperature channels
24
1
11
TACH1
TACH2
TACH3
TACH4
VCC
GND
+12V1
+12V2
10
Features of Configuration Option 5 include the following:
30 PWM3
32 PWM2
Configuration Option 5 is chosen when the user wants to
monitor temperature, voltages, and fans for Processor 2 in
a dual processor system.
31 PWM1
Configuration Option 5
28 THERM1/+1.5V
ADT7462
Figure 8. Configuration Option 5
RESET I/O
Figure 8 shows the pin configuration when Configuration
Option 5 is chosen.
Table 10. Configuration Option 5
Pin
11
21
31
41
7
8
13
15
16
19
20
21
22
23
24
25
26
27
281, 2
29
311
321
1
Function
TACH1
TACH2
TACH3
TACH4
+12V1
+12V2
+3.3V
+2.5V
SCSI_TERM1
D3+
D3−
TACH7
TACH8
+1.8V
VCCP2
+1.2V
VR_HOT2
FAN2MAX
THERM1/
+1.5V
THERM2/
+1.5V
PWM1
PWM2
Configuration Register
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 1
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 2
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 3
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Pin Configuration Register 4
Bit Value
Bit 4 = 1
Bit 3 = 1
Bit 2 = 1
Bit 1 = 1
Bit 0 = 0
Bit 7 = 0
Bit 6 = 0
Bit 6 = 0
Bit 6 = 0
Bit 5 = 1
Bit 5 = 1
Bit 3 = 1
Bit 2 = 1
Bits [1:0] = 10
Bits [7:6] = 00
Bits [5:4] = 01
Bits [3:2] = 1×
Bit 1 = 0
See
Table 51
See
Table 51
Bit 3 = 1
Bit 2 = 1
If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set
Bit 7 of Pin Configuration Register 1 (0x01) = 1.
2
It is not possible to monitor +1.5V monitoring on Pin 28 and THERM2 on
Pin 29. Pin 28 and Pin 29 must BOTH be configured as either +1.5V
monitoring or as THERM I/O. See Table 51 for more information.
Rev. 0 | Page 14 of 92
ADT7462
TYPICAL PERFORMANCE CHARACTERISTICS
2
0.00160
0.00155
TEMPERATURE ERROR (°C)
DEV2
0.00145
DEV1
0.00140
DEV3
0.00135
VCC = 5.5V
VCC = 3.3V
0
05569-003
0.00130
1
0.00125
2.9
3.4
3.9
4.4
4.9
–1
–40
5.4
SUPPLY VOLTAGE (V)
05569-006
IDD (Amps)
0.00150
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 12. Remote Sensor Temperature Error
Figure 9. Supply Current vs. Supply Voltage
5
0.00144
0.00142
TEMPERATURE ERROR (°C)
DEV2
0.00138
IDD (Amps)
0.00136
DEV3
0.00134
DEV1
0.00132
0.00130
0.00128
05569-004
0.00126
0.00124
0.00122
–45
5
55
6
11
16
2
7
12
17
3
3
8
13
18
4
9
14
19
5
10
15
20
–20
0
2
MEAN
LO SPEC
HI SPEC
1
0
–1
–2
–3
105
–4
–40
TEMPERATURE (°C)
05569-007
0.00140
1
4
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. Supply Current vs. Temperature
Figure 13. Temperature Error Measuring Intel Pentium 4 Processor
140
2
VCC = 3.3V
–20
0
20
40
60
80
100
INT
EXT1
EXT2
EXT3
100
80
60
40
20
0
120
05569-008
0
–1
–40
TEMPERATURE READING (°C)
VCC = 5.5V
1
05569-005
TEMPERATURE ERROR (°C)
120
0
20
40
60
80
100
TIME (Seconds)
TEMPERATURE (°C)
Figure 14. DUT Response to Thermal Shock
Figure 11. Local Sensor Temperature Error
Rev. 0 | Page 15 of 92
120
ADT7462
60
25
20
TEMPERATURE ERROR (°C)
20
D+ TO GND
0
D+ TO VCC
–20
–40
0
20
40
60
60mV
5
0
40mV
–10
10
100
80
10
–5
05569-077
–60
100mV
15
05569-080
TEMPERATURE ERROR (°C)
40
100
RESISTANCE (MΩ)
15
7
10
6
50mV
125mV
0
–5
–10
100
1M
10M
100M
1G
100M
5
4
10mV
20mV
3
2
1
–1
10
1G
05569-081
0
05569-078
–15
–20
10
10M
Figure 18. Temperature Error vs. Common-Mode Noise Frequency
TEMPERATURE ERROR (°C)
TEMPERATURE ERROR (°C)
Figure 15. Temperature Error vs. Resistance (SRC)
5
1M
NOISE FREQUENCY (kHz)
100
POWER SUPPLY NOISE FREQUENCY (kHz)
1M
10M
100M
1G
NOISE FREQUENCY (kHz)
Figure 16. Local Temperature Error vs. Power Supply Noise Frequency
Figure 19. Temperature Error vs. Differential-Mode Noise Frequency
8
10
0
50mV
125mV
2
0
–2
–4
–6
–8
DEV1, EXT1
DEV1, EXT2
–20
DEV1, EXT3
DEV2, EXT1
–30
DEV2, EXT2
DEV2, EXT3
DEV3, EXT1
–40
–10
–12
10
–10
100
1M
10M
100M
DEV3, EXT2
05569-082
TEMPERATURE ERROR (°C)
4
05569-079
TEMPERATURE ERROR (°C)
6
DEV3, EXT3
–50
1G
POWER SUPPLY NOISE FREQUENCY (kHz)
0
2
4
6
8
10
CAPACITANCE (nF)
Figure 17. Remote Temperature Error vs. Power Supply Noise Frequency
Rev. 0 | Page 16 of 92
Figure 20. Temperature Error vs. Capacitance Between D+ and D−
ADT7462
0.200
5.0
0.198
4.5
4.0
POWER UP
0.194
3.5
TACH ERROR (%)
0.192
0.190
0.188
0.186
0.184
3.0
2.5
2.0
DEV1
DEV2
DEV3
1.5
1.0
0.182
0.180
–50
0
50
05569-083
STANDBY
0.5
0
2.9
150
100
05569-085
TEMPERATURE (°C)
0.196
3.4
3.9
TIMEOUT (Seconds)
4.4
4.9
5.4
SUPPLY (V)
Figure 21. Temperature vs. Power-On Reset Timeout
Figure 23. TACH Accuracy vs. Supply Voltage
3.0
1.5
DEV2
1.0
DEV1
0.5
TACH ERROR (%)
2.0
1.5
DEV1
DEV2
DEV3
0
0.5
1.0
1.5
2.0
DEV3
–0.5
–1.0
0.5
0
0
–1.5
2.5
–2.0
–50
3.0
VOLTAGE APPLIED (V)
05569-086
1.0
05569-084
VBATT READING (V)
2.5
0
50
100
TEMPERATURE (°C)
Figure 22. VBATT Measurement vs. Applied Voltage
Figure 24. TACH Accuracy vs. Temperature
Rev. 0 | Page 17 of 92
150
ADT7462
SERIAL BUS INTERFACE
The ADT7462 is controlled through use of the serial system
management bus (SMBus). The ADT7462 is connected to this
bus as a slave device, under the control of a master controller.
The SMBus interface in the ADT7462 is fully SMBus 1.1- and
SMBus 1.0-compliant. The SMBus address is determined by the
state of the ADD input on power-up.
3.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high can be interpreted as
a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.
4.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master releases
the data line during the 10th clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the
low period before the 9th clock pulse. This is known as a
No Acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse and then
takes it high during the 10th clock pulse to assert a stop
condition.
ADD INPUT
The ADD pin is a three-state input to the ADT7462. It is used
to determine the SMBus address used. This pin is sampled on
power-up only. Any changes subsequent to power-up are not
reflected until the ADT7462 is powered down and back up
again. The corresponding 7-bit SMBus address for the state of
the ADD pin is shown in Table 11.
Table 11. Corresponding SMBus Addresses for ADD Input
ADD Pin
High
Float
Low
SMBus Version
N/A
SMBus 1.1
SMBus 1.1
SMBus Address
N/A
0x5C
0x58
SMBUS FIXED ADDRESS
The ADT7462 supports SMBus fixed address mode and is fully
backwards-compatible with SMBus 1.1 and SMBus 1.0. The
ADT7462 powers up with a fixed SMBus address that cannot be
changed by the assign address call. The fixed address is set by the
state of the ADD input pin on power-up.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
SMBUS OPERATION
For the ADT7462, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so that the correct data register is
addressed. Then data can be written into that register or read
from it. The first byte of a write operation always contains an
address that is stored in the address pointer register. If data is to
be written to the device, the write operation contains a second
data byte that is written to the register selected by the address
pointer register.
The SMBus specification defines specific conditions for different
types of read and write operations. The general SMBus protocol
operates as follows:
1.
2.
The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit, which determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the 9th clock pulse, known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from it or
written to it. If the R/W bit = 0, the master writes to the
slave device. If the R/W bit = 1, the master reads from the
slave device.
This write operation is shown in Figure 25. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
Rev. 0 | Page 18 of 92
ADT7462
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value.
When reading data from a register, there are two possibilities.
If the ADT7462’s address pointer register value is
unknown or not the desired value, it must be set to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7462
as before, but only the data byte containing the register
address is sent because no data is written to the register
(see Figure 26).
However, it is not possible to write data to a register without
writing to the address pointer register, because the first data
byte of a write is always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7462 also supports the read byte protocol
(see System Management Bus Specifications Rev. 2.0 for more
information).
A read operation is then performed, consisting of the serial
bus address and the R/W bit set to 1, followed by the data
byte read from the data register (see Figure 27).
If several read or write operations must be performed in
succession, then the master can send a repeat start condition,
instead of a stop condition, to begin a new operation.
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 27).
1
9
1
9
SCL
A6
SDA
A5
A4
A3
A2
A1
R/W
A0
START BY
MASTER
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7462
ACK. BY
ADT7462
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7462
STOP BY
MASTER
FRAME 3 DATA BYTE
05569-015
SDA (CONTINUED)
Figure 25. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
START BY
MASTER
R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7462
ACK. BY
ADT7462
FRAME 1
SERIAL BUS ADDRESS BYTE
STOP BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
05569-016
•
Figure 26. Writing to the Address Pointer Register Only
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
START BY
MASTER
A0
R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
ADT7462
FRAME 1
SERIAL BUS ADDRESS BYTE
NO ACK.
STOP BY
BY MASTER MASTER
FRAME 2
DATA BYTE FROM ADT7462
Figure 27. Reading Data from a Previously Selected Register
Rev. 0 | Page 19 of 92
D0
05569-017
•
ADT7462
WRITE OPERATIONS
4.
The master sends a command code.
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7462
are discussed below. The following abbreviations are used in the
diagrams:
5.
The slave asserts an ACK on SDA.
6.
The master sends a data byte.
7.
The slave asserts an ACK on SDA.
8.
The master asserts a stop condition on SDA to end the
transaction.
1
S
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts an ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts an ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
W
3
4
5
6
A
REGISTER
ADDRESS
A
P
05569-018
For the ADT7462, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is shown in Figure 28.
SLAVE
ADDRESS
5
SLAVE
ADDRESS
6
7 8
A DATA A P
Figure 28. Setting a Register Address for a Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
In this operation, the master device writes a block of data to a
slave device. The start address for a block write must have been
set previously. In the case of the ADT7462, this is done by a
send byte operation to set a RAM address. The user writes the
number of registers to be written to in the block read command
to the #Bytes bits of the Configuration 0 register.
1.
The master device asserts a start condition on the SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts an ACK on the SDA.
4.
The master sends a command code that tells the slave
device to expect a block write. The ADT7462 command
code for a block write is 0xA0 (1010 0000).
5.
The slave asserts ACK on the SDA.
6.
The master sends the data bytes (the number of data bytes
sent is written to the #Bytes bits of the Configuration 0
register).
7.
The slave asserts an ACK on the SDA after each data byte.
8.
The master sends a packet error checking (PEC) byte.
9.
The ADT7462 checks the PEC byte and issues an ACK,
if correct. If incorrect (NO ACK), the master resends the
data bytes.
10. The master asserts a stop condition on the SDA to end the
transaction.
1
2
3
4
5
6
7
8
9
10
11 12
COMMAND
SLAVE W A A0h BLOCK A BYTE A DATA 1 A DATA 2 A DATA A PEC A
S ADDRESS
COUNT
32
WRITE
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts an ACK on SDA.
Rev. 0 | Page 20 of 92
Figure 30. Block Write to ADT7462
P
05569-020
In this operation, the master device sends a single command
byte to a slave device as follows:
S
SLAVE W A
ADDRESS
4
Block Write
Send Byte
2
3
Figure 29. Single Byte Write to a Register
The ADT7462 uses the following SMBus write protocols.
1
2
05569-019
S – Start
P – Stop
R – Read
W – Write
A – Acknowledge
A – No Acknowledge
ADT7462
4.
The master sends a command code that tells the slave
device to expect a block read. The ADT7462 command
code for a block read is 0xA1 (1010 0001).
Receive Byte
5.
The slave asserts an ACK on SDA.
The receive byte is useful when repeatedly reading a single
register. The register address needs to have been set up
previously. In this operation, the master device receives a single
byte from a slave device as follows:
6.
The master asserts a repeat start condition on the SDA.
7.
The master sends the 7-bit slave address followed by the
read bit (high).
8.
The slave asserts an ACK on the SDA.
9.
The ADT7462 sends a byte count telling the master how
many data bytes to expect. The maximum number of bytes
is 32.
READ OPERATIONS
The ADT7462 uses the following SMBus read protocols.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts an ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts a NO ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
10. The master asserts an ACK on SDA.
11. The master receives the expected number of data bytes.
12. The master asserts an ACK on SDA after each data byte.
In the ADT7462, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
14. A NO ACK is generated after the PEC byte to signal the
end of the read.
15. The master asserts a stop condition on the SDA to end the
transaction.
1
Figure 31. Single Byte Read from a Register
Block Read
In this operation, the master device reads a block of data from
a slave device. The start address for a block read must have been
set previously, as well as the number of bytes to be read
(maximum = 32). In the case of the ADT7462, the start address
is activated by a send byte operation to set a RAM address. The
number of bytes to be read should be written to the #Bytes bits
in the Configuration 0 register. The block read operation
consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
1.
The master device asserts a start condition on the SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts an ACK on the SDA.
5
6
7
COMMAND
S SLAVE
A
ADDRESS W A A1h BLOCK
READ
S
SLAVE
ADDRESS
8
A
2
9
3
10
11
4
12
BYTE A DATA 1 A
COUNT
13
DATA
32
A
R
14 15
PEC A
P
05569-022
2
05569-021
1
13. The ADT7462 issues a PEC byte to the master. The master
should check the PEC byte and issue another block read if
the PEC byte is incorrect.
Figure 32. Block Read from RAM
Note that although the ADT7462 supports packet error
checking (PEC), its use is optional. The PEC byte is calculated
using CRC-8. The frame check sequence (FCS) conforms to
CRC-8 by the polynomial
C( x ) = x 8 + x 2 + x 1 + 1
Consult the SMBus 1.1 specifications for more information.
Rev. 0 | Page 21 of 92
ADT7462
ALERT RESPONSE ADDRESS
SMBUS TIMEOUT
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The ADT7462 includes an SMBus timeout feature. If there is no
SMBus activity for 25 ms, the ADT7462 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
Configuration Register 3 (0x03)
Bit 1 SCL_Timeout = 1; SCL timeout enabled.
1.
SMBALERT is pulled low.
Bit 1 SCL_Timeout = 0; SCL timeout disabled (default).
2.
Master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
Bit 2 SDA_Timeout = 1; SDA timeout enabled.
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
4.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in
accordance with normal SMBus arbitration.
5.
Once the ADT7462 has responded to the alert response
address, the master must read the status registers, and
the SMBALERT is cleared only if the error condition has
gone away.
Bit 2 SDA_Timeout = 0; SDA timeout disabled (default).
Rev. 0 | Page 22 of 92
ADT7462
TEMPERATURE AND VOLTAGE MEASUREMENT
TEMPERATURE MEASUREMENT
The ADT7462 can measure its own ambient temperature and
the temperature of up to three remote thermal diodes. These
diodes can be discrete diode-connected 2N3904/6s or can be
located on a processor die. Figure 33 shows how to connect a
remote NPN or PNP transistor.
2N3906
D–
ADT7462
2N3904
Signal conditioning and measurement of the internal
temperature sensor are performed in the same manner.
D+
D–
05569-023
ADT7462
D+
The resulting ΔVBE waveforms are passed through a 65 kHz
low-pass filter to remove noise and then to a chopper-stabilized
amplifier. This amplifies and rectifies the waveform to produce
a dc voltage proportional to ΔVBE. The ADC digitizes this
voltage, and a temperature measurement is produced. To reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles for low conversion rates.
VCC
I
N1 × I
N2 × I
IBIAS
Figure 33. How to Measure Temperature Using Discrete Transistors
REMOTE
SENSING
TRANSISTOR
D+
VOUT+
C1*
TO ADC
D–
BIAS
DIODE
Remote Thermal Diode 2 connects to Pin 17 and Pin 18.
VOUT–
LOW-PASS FILTER
fC = 65kHz
*CAPACITOR C1 IS OPTIONAL. IT SHOULD ONLY BE USED IN NOISY ENVIRONMENTS.
Remote Thermal Diode 3 connects to Pin 19 and Pin 20.
05569-024
Remote Thermal Diode 1 connects to Pin 15 and Pin 16.
Figure 34. Input Signal Conditioning
A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor, operated at constant
current. Unfortunately, this technique requires calibration to
null out the effect of the absolute value of VBE, which varies
from device to device.
Temperature Measurement Results
The technique used in the ADT7462 is to measure the change
in VBE when the device is operated at three different currents.
Previous devices have used only two operating currents;
use of a third current allows automatic cancellation of any
resistances in series with the external temperature sensor.
Temperature Value
Local Temperature, LSB
Local Temperature, MSB
Remote 1 Temperature, LSB
Remote 1 Temperature, MSB
Remote 2 Temperature, LSB
Remote 2 Temperature, MSB
Remote 3 Temperature, LSB
Remote 3 Temperature, MSB
Figure 34 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the
collector is not grounded and should be linked to the base. To
prevent ground noise from interfering with the measurement, the
more negative terminal of the sensor is not referenced to
ground but is biased above ground by an internal diode at the
D− input. C1 can optionally be added as a noise filter
(recommended maximum value 1000 pF). However, a better
option in noisy environments is to add a filter, as described in
the Noise Filtering section.
To measure ΔVBE, the operating current through the sensor is
switched among three related currents. As shown in Figure 34,
N1 × I and N2 × I are different multiples of the Current I. The
currents through the temperature diode are switched between I
and N1 × I, giving ΔVBE1, and then between I and N2 × I, giving
ΔVBE2. The temperature can then be calculated using the two
ΔVBE measurements. This method can also be shown to cancel
the effect of any series resistance on the temperature
measurement.
The results of the local and remote temperature measurements
are stored in the local and remote temperature value registers
and are compared with limits programmed into the local and
remote high and low limit registers.
Table 12. Temperature Measurement Registers
Register Address
Register 0x88, Bits [7:6]
Register 0x89
Register 0x8A, Bits [7:6]
Register 0x8B
Register 0x8C, Bits [7:6]
Register 0x8D
Register 0x8E, Bits [7:6]
Register 0x8F
The temperature value is stored in two registers. The MSB has a
resolution of 1°C. Only two bits in the temperature LSB register
are used, Bit 7 and Bit 6, giving a temperature measurement a
resolution of 0.25°C. The temperature measurement range for
both local and remote measurements is from −64°C to +191°C.
However, the ADT7462 itself should never be operated outside
its operating temperature range, which is from −40°C to +125°C.
For the remote diode, the user should refer to the data sheet of
the diode.
Table 13. Temperature Data Format
Temperature Value
−64°C
−50.25°C
−25°C
0°C
+25°C
+50.25°C
+100°C
Rev. 0 | Page 23 of 92
MSB
0000 0000
0000 1110
0010 0111
0100 0000
0101 1001
0111 0010
1010 0100
LSB
0000 0000
0100 0000
0000 0000
0000 0000
0000 0000
0100 0000
0000 0000
ADT7462
When reading the full temperature value, the LSB should be
read first and then the MSB. Reading the LSBs causes the
current MSBs to be frozen until they are read. Reading the
MSBs only does not cause any register to be locked. This is
useful when a temperature reading with 1°C resolution is
required.
Table 14. Temperature Limit Registers
SERIES RESISTANCE CANCELLATION
Parasitic resistance in series with the remote diode D+ and D−
inputs can be caused by a variety of factors, including PCB track
resistance and track length. This series resistance appears as a
temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.8°C offset per ohm of
parasitic resistance in series with the remote diode.
The ADT7462 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result, without the need for user characterization of this
resistance. The ADT7462 is designed to automatically cancel
typically up to 2 kΩ of resistance. By using an advanced
temperature measurement method, the process is transparent to
the user. This feature also allows an RCR filter to be added to
the sensor path, allowing the part to be used accurately in noisy
environments.
Temperature Limits
Each temperature measurement channel has a high and low
temperature limit associated with it. The temperature measurements are compared with these limits, and the results of these
comparisons are stored in status registers. A Logic 0 indicates
an in-limit comparison, and a Logic 1 indicates an out-of-limit
comparison. The ADT7462 can generate an ALERT, if configured
to do so, once a status bit is set. For more information on the
status registers and ALERT, see the Status and Mask Registers
and ALERT section of this datasheet.
Each temperature channel also has a THERM1 and a THERM2
temperature limit associated with it. Once these temperature
limits are exceeded, the corresponding THERM pin is asserted
low (if THERM is configured as an output), and the fans are
boosted to full speed (if the boost bit is set). Table 14 shows
a complete list of all the temperature limits and their default
values.
Temperature Value
Local Low Temperature Limit
Remote 1 Low Temperature Limit
Remote 2 Low Temperature Limit
Remote 3 Low Temperature Limit
Local High Temperature Limit
Remote 1 High Temperature Limit
Remote 2 High Temperature Limit
Remote 3 High Temperature Limit
Local THERM1 Temperature Limit
Remote 1 THERM1 Temperature Limit
Remote 2 THERM1Temperature Limit
Remote 3 THERM1 Temperature Limit
Local THERM2 Temperature Limit
Remote 1 THERM2 Temperature Limit
Remote 2 THERM2 Temperature Limit
Remote 3 THERM2 Temperature Limit
Register
Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
Default
0x40
0x40
0x40
0x40
0x95
0x95
0x95
0x95
0xA4
0xA4
0xA4
0xA4
0xA4
0xA4
0xA4
0xA4
Offset Registers
The ADT7462 has temperature offset registers at Register 0x56
to Register 0x59 for the local, Remote 1, Remote 2, and Remote 3
temperature channels. By doing a one-time calibration of the
system, the user can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement, 8-bit reading to
every temperature measurement. The LSBs add 0.5°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to ±64°C with a resolution of 0.5°C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Register 0x56 Local Temperature Offset = 0x00 (0°C default)
Register 0x57 Remote 1 Temperature Offset = 0x00 (0°C default)
Register 0x58 Remote 2 Temperature Offset = 0x00 (0°C default)
Register 0x59 Remote 3 Temperature Offset = 0x00 (0°C default)
Rev. 0 | Page 24 of 92
ADT7462
Layout Considerations
Digital boards can be electrically noisy environments. The
ADT7462 measures very small voltages from the remote sensor,
so care must be taken to minimize noise induced at the sensor
inputs. The following precautions should be taken:
For really long distances (up to 100 feet), use shielded twisted
pair, such as Belden No. 8451 microphone cable. Connect the
twisted pair to D+ and D− and the shield to GND close to the
ADT7462. Leave the remote end of the shield unconnected to
avoid ground loops.
Place the ADT7462 as close as possible to the remote sensing
diode. Provided that the worst noise sources, such as clock
generators, data/address buses, and CRTs, are avoided, this
distance can be 4 inches to 8 inches.
• Because the measurement technique uses switched current
sources, excessive cable or filter capacitance can affect the
measurement. When using long cables, the filter capacitance
can be reduced or removed.
Route the D+ and D− tracks close together, in parallel, with
grounded guard tracks on each side. To minimize inductance
and reduce noise pick-up, a 5 mil track width and spacing is
recommended. If possible, provide a ground plane under the
tracks.
Noise Filtering
GND
5MIL
5MIL
D+
5MIL
For temperature sensors operating in noisy environments, the
industry-standard practice is to place a capacitor across the D+
and D− pins to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature
measurement, leading to a recommended maximum capacitor
value of 1000 pF. While this capacitor does reduce the noise,
it does not eliminate it, making it difficult to use the sensor in
a very noisy environment.
5MIL
5MIL
GND
5MIL
05569-025
5MIL
Figure 35. Typical Arrangement of Signal Tracks
Minimize the number of copper/solder joints that can cause
thermocouple effects. Where copper/solder joints are used,
make sure that they are in both the D+ and D− path and at
the same temperature.
• Thermocouple effects should not be a major problem because
1°C corresponds to about 200 mV, and thermocouple voltages
are about 3 mV/°C of temperature difference. Unless there
are two thermocouples with a big temperature differential
between them, thermocouple voltages should be much less
than 200 mV.
Place a 0.1 μF bypass capacitor close to the VDD pin. In
extremely noisy environments, an input filter capacitor can
be placed across D+ and D− close to the ADT7462. This
capacitance can affect the temperature measurement, so care
must be taken to ensure that any capacitance seen at D+ and
D− is a maximum of 1000 pF.
The ADT7462 has a major advantage over other devices when it
comes to eliminating the effects of noise on the external sensor.
The series resistance cancellation feature allows a filter to be
constructed between the external temperature sensor and the
device. The effect of any filter resistance seen in series with the
remote sensor is automatically cancelled from the temperature
result.
The construction of a filter allows the ADT7462 and the remote
temperature sensor to operate in noisy environments. Figure 36
shows a low-pass RCR filter, with the following values:
R = 100 Ω
C = 1 nF
This filtering reduces both common-mode noise and
differential noise.
This maximum value includes the filter capacitance, plus any
cable or stray capacitance between the pins and the sensor diode.
If the distance to the remote sensor is more than 8 inches, the
use of twisted pair cable is recommended. This works up to
about 6 feet to 12 feet.
Rev. 0 | Page 25 of 92
D+
100Ω
1nF
REMOTE
SENSOR
100Ω
D–
05569-026
D–
Figure 36. Filter Between Remote Sensor and the ADT7462
ADT7462
0.9V
The ADT7462 is capable of measuring up to 13 different voltage
inputs at one time. Table 15 is a list of the voltage measurement
inputs and the corresponding input pins. Each pin can be
configured to measure the desired voltage option using Pin
Configuration 1 (0x10) to Pin Configuration 4 (0x13) or the
easy configuration options.
8kΩ
92kΩ
GBIT,
FSB_VTT,
VCCP1 ,
VCCP2
1.25V
32kΩ
77kΩ
72kΩ
Voltage Measured
+12V1
+12V2
+3.3V
+2.5V/+1.8V
+1.25V/+0.9V
+5V
+12V3
VCCP1/+1.5V/+1.8V/+2.5V
VCCP2/+1.5V/+1.8V/+2.5V
+1.2V1 (GBIT)/+3.3V
+1.2V2 (FSB_VTT)/VBATT
+1.5V1 (ICH)
+1.5V2 (3GIO)
ICH,
3GIO,
1.5V
1.8V
2.5V
66kΩ
8pF
91kΩ
35pF
8kΩ
MUX
30kΩ
The internal structure for the voltage inputs is shown in Figure 37.
Each input circuit consists of an input protection diode; an
attenuator; plus a capacitor to form a first-order, low-pass filter
that gives the input immunity to high frequency noise.
5V
Rev. 0 | Page 26 of 92
5pF
100kΩ
16kΩ
Voltages with full-scale values greater than the reference are
divided down so that the full-scale value equals the reference
(2.25 V). All analog inputs are multiplexed into the on-chip,
successive approximation ADC. This ADC has a resolution of
ten bits. The basic input range is from 0 V to 2.25 V, but the
inputs have built-in attenuators to allow measurement of larger
and smaller voltages. To allow a tolerance for these voltages, the
ADC produces an output of 3/4 full scale (decimal 768 or
0x300) for the nominal input voltage and so has enough
headroom to cope with overvoltages.
5pF
76kΩ
39kΩ
12V
10pF
57kΩ
17kΩ
Input Circuit
10pF
51kΩ
72kΩ
3.3V
10pF
30kΩ
Table 15. Voltage Inputs
Pin
7
8
13
15
19
21
22
23
24
25
26
28
29
35pF
5pF
Figure 37. Voltage Input Structures
05569-027
VOLTAGE MEASUREMENT
ADT7462
A list of corresponding LSB and full-scale values for each input
voltage is shown in Table 16.
Similarly, the voltage, given the code in a particular channel, is
calculated as follows:
Table 16. Input Range Code Conversion
Nominal Input
Voltage (3/4 Scale)
+12V
+5V
VCCP1, VCCP2
VCCP1, when VIDs
are enabled
+3.3V
VBATT
+2.5V
+1.8V
+1.5V
+1.25V
+1.2V
+0.9V
Voltage = Code × 1 LSB
Pin
7, 8, 22
21
23, 24
23
1 LSB
Value
0.0625
0.026
0.00625
0.0125
Full
Scale
16 V
6.67 V
1.6 V
3.2 V
13, 25
26
15, 23, 24
15, 23, 24
23, 24, 28, 29
19
25, 26
19
0.0172
0.0156
0.013
0.0094
0.0078
0.0065
0.00625
0.00469
4.4 V
4V
3.33 V
2.4 V
2V
1.667 V
1.6 V
1.2 V
Example Calculations
Given the LSB value for each channel, the corresponding code
for each voltage (or vice versa) can be calculated.
Code =
where:
10 V is connected to the 12 V channel.
1 LSB = 0.0625.
Code = 160 decimal.
Voltage Measurement and Limit Registers
The corresponding register locations for voltage measurements
are listed in Table 17. Each voltage measurement channel has a
high and low voltage limit associated with it. The voltage
measurements are compared with these limits. The results of
these comparisons are stored in status registers. A Logic 0
indicates an in-limit condition, and a Logic 1 indicates an outof-limit condition. The ADT7462 can generate an ALERT, if
configured to do so, once a status bit is set. For more
information on the status registers and ALERT, see the Status
and Mask Registers and ALERT section of this datasheet. A
complete list of all the high and low voltage limits in the
ADT7462 and their default values is contained in Table 17.
Voltage
1 LSB
Example:
The code for 1.8 V in a 1.8 V channel is
Code =
1.8
(that
= 192
0.0094
is 3 scale
4
)
Table 17. Voltage Value and Limit Registers
Voltage Value
+12V1
+12V2
+3.3V
+1.8V or +2.5V
+1.25V or +0.9V
+5V
+12V3
VCCP1, +1.5V, +1.8V, +2.5V
VCCP2, +1.5V, +1.8V, +2.5V
+1.2V1 (GBIT) or +3.3V
+1.2V2 (FSB_VTT) or VBATT
+1.5V1 (ICH)
+1.5V2 (3GIO)
Pin
Pin 7
Pin 8
Pin 13
Pin 15
Pin 19
Pin 21
Pin 22
Pin 23
Pin 24
Pin 25
Pin 26
Pin 28
Pin 29
Value Register Address
0xA3
0xA5
0x96
0x8B
0x8F
0xA7
0xA9
0x90
0x91
0x92
0x93
0x94
0x95
Rev. 0 | Page 27 of 92
Low Limit
Register
Default
0x6D
0x00
0x6E
0x00
0x70
0x00
0x45
0x40
0x47
0x40
0x71
0x00
0x6F
0x00
0x72
0x20
0x73
0x00
0x74
0x00
0x75
0x80
0x76
0x00
0x77
0x00
High Limit
Register
Default
0x7C
0xFF
0x7D
0xFF
0x68
0xFF
0x49
0x95
0x4B
0x95
0x7E
0xFF
0x7F
0xFF
0x69
0xFF
0x6A
0xFF
0x6B
0xFF
0x6C
0xFF
0x50
0xA4
0x4C
0xA4
ADT7462
BATTERY MEASUREMENT INPUT (VBATT)
VBATT Input Battery Protection
The VBATT input allows the condition of a CMOS backup battery
to be monitored. This is typically a lithium coin cell, such as a
CR2032. The VBATT input is accurate only for voltages greater
than 1.2 V. Note that when Pin 26 is configured as a +1.2V
input, voltages lower than 1.2 V are not accurately measured.
Input voltage and corresponding voltage measured are shown in
Figure 22. Typically, the battery in a system is required to keep
some devices powered on when the system is in a powered-off
state. The VBATT measurement input is designed to minimize
battery drain. To reduce current drain from the battery, the
lower resistor of the VBATT attenuator is not connected, except
when a VBATT measurement is being made. The total current
drain on the VBATT pin is 80 nA typical (for a maximum VBATT
voltage = 4 V), so a CR2032 CMOS battery functions in a
system in excess of the expected 10 years. Note that when a
VBATT measurement is not being made, the current drain is
reduced to 6 nA typical. Under normal voltage measurement
operating conditions, all measurements are made in a roundrobin format, and each reading is actually the result of 16
digitally averaged measurements. However, averaging is not
carried out on the VBATT measurement to reduce measurement
time and, therefore, reduce the current drain from the battery.
In addition to minimizing battery current drain, the VBATT
measurement circuitry is specifically designed with battery
protection in mind. Internal circuitry prevents the battery from
being back-biased by the ADT7462 supply or through any other
path under normal operating conditions. In the unlikely event
of a catastrophic ADT7462 failure, the ADT7462 includes a
second level of battery protection, including a series 3 kΩ
resistor to limit current to the battery, as recommended by UL.
Thus, it is not necessary to add a series resistor between the
battery and the VBATT input; the battery can be connected
directly to the VBATT input to improve voltage measurement
accuracy.
The VBATT current drain when a measurement is being made is
calculated by
I=
T
V BATT
× PULSE
100 kΩ TPERIOD
where:
TPULSE is VBATT measurement time (~711 μs typical).
TPERIOD is the time required to measure all analog inputs.
Monitoring cycle time depends on the ADT7462 configuration.
Calculating the monitoring cycle time is described in more
detail in the ADC Information section.
Rev. 0 | Page 28 of 92
VBATT
49.5kΩ
3kΩ
DIGITAL
CONTROL
ADC
82.7kΩ
05569-028
4.5pF
3kΩ
Figure 38. Equivalent VBATT Input Protection Circuit
ADT7462
ADC INFORMATION
Single-Channel ADC Conversions
Round Robin
Setting Bit 2 of the EDO/single-channel enable register (0x16)
places the ADT7462 into single-channel mode. In this mode the
ADT7462 can be made to convert on a single voltage or
temperature channel only. The channel to be converted on is
selected by writing to Bits [7:3] of the EDO/single-channel
enable register (0x16). When the device is in single-channel
mode, the pin configuration option should not be changed.
Both temperature and voltage measurements are analog inputs
that are digitized using the on-board ADC. An internal
multiplexer switches between the different analog inputs and
digitizes them, in turn, in a round-robin manner. The total
conversion time depends upon how the ADT7462 is configured.
The conversion times for each measurement channel are shown
in Table 18. The complete conversion time is the sum of the time
for the voltage and temperature measurements.
For example, if the ADT7462 is configured as Easy Configuration
Option 1, the round-robin conversion time is calculated as follows:
Total Conversion Time = 1 × (Local Conversion Time) + 3 ×
(Remote Conversion Time) + 4 × (Voltage Measurement Time).
The TACH is not measured using the ADC and so is not part of
the round-robin monitoring cycle.
Table 18. Measurement Channel Conversion Times
Channel
Local Temperature
Remote Temperature
Voltage
Conversion Time
9.01 ms
38.36 ms
8.53 ms
For each ADC temperature and voltage measurement read from
their value registers, 16 readings have actually been made
internally and the results averaged before being placed in the
value register.
Bypass Voltage Attenuators
There are up to 13 voltage measurement channels on the
ADT7462. Each of these voltage measurement channels has an
input structure (see Figure 37 for input structures for each of
the voltage channels). Because the ADC has a voltage input
range from 0 V to 2.25 V, these input circuits attenuate the
voltage input using a resistor divider network to match the
input range of the ADC. However, the user may occasionally
want to remove the attenuators and directly apply a voltage of
between 0 V and 2.25 V to the ADC. These attenuators can be
disabled by setting relevant bits in the voltage attenuator
configuration registers. This feature also allows the user to
rescale the voltage inputs using an external attenuator circuit.
However, when the attenuators are disabled, the user should
ensure that the voltage on the pin never exceeds 2.25 V.
Note that when the Pin 26 voltage, which includes the VBATT
option, is selected in single-channel mode, this means that
voltage measurements are continuously made in the mode.
If a battery is connected to this input, then this results in an
excessive current drain on the battery. The specification of >10
years of battery life is valid only when the battery voltage is measured as part of the round robin and not in single-channel mode.
Table 20. Single-Channel Mode Options
Bits [7:3]
00 000
00 001
00 010
00 011
00100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
10 000
10 001
Table 19. Voltage Attenuator Configuration Registers
Register Name
Voltage Attenuator Configuration Register 1
Voltage Attenuator Configuration Register 2
Register
Address
0x18
0x19
Rev. 0 | Page 29 of 92
ADC Channel Selected
Pin 26
Remote 1 temperature
Remote 2 temperature
Remote 3 temperature
Local temperature
+12V1 voltage, Pin 7
+12V2 voltage, Pin 8
+12V3 voltage, Pin 22
+3.3V voltage, Pin 13
+2.5V/+1.8V voltage, Pin 15
+1.25V/0.9V voltage, Pin 19
+5V voltage, Pin 21
Pin 23 voltage
Pin 24 voltage
Pin 25 voltage
+1.5V1 voltage, Pin 28
+1.5V2 voltage, Pin 29
ADT7462
DYNAMIC VID MONITORING
VID CODE
The ADT7462 can be configured to monitor up to seven VID
inputs. The VID code is output on seven lines from the CPU
to tell the power controller what input voltage it requires. The
ADT7462 can monitor the VID code and the voltage applied to
the CPU to ensure that they match within an acceptable range.
This acceptable range is programmable in the ADT7462.
The VID lines are monitored by the ADT7462, and the VID
code is stored in the VID value register (0x97), which can be
read back over the SMBus.
VID monitoring is enabled by setting Bit 7 (VIDs) of Pin
Configuration Register 1 (0x10) to 1. See Table 21 and Table 22
for information on which pin should be connected to each VID
line. When VID monitoring is enabled, all seven pins are
automatically configured as VID inputs. It is not possible to select
six pins as VID inputs and use the remaining pin as their
alternate functions.
VID Value Register (0x97)
Bit 0 = VID0 (reflects the logic state of Pin 1)
Bit 2 = VID2 (reflects the logic state of Pin 3)
Bit 3 = VID3 (reflects the logic state of Pin 4)
Bit 4 = VID4 (reflects the logic state of Pin 31)
Bit 5 = VID5 (reflects the logic state of Pin 32)
Bit 6 = VID6 (reflects the logic state of Pin 28)
The ADT7462 supports both the VR10 and the VR11 specifications. The default option supports the VR10 specification.
To switch to the VR11 specification, set Bit 6 of Configuration
Register 0 (0x00) to 1. VR11 is defined as eight bits; the ADT7462
monitors only seven VID lines (see Table 21).
VID Number
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Pin
28
32
31
4
3
2
1
Voltage
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Table 22. VR10 VID Codes
VID Number
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Pin
28
32
31
4
3
2
1
Voltage
Unused, connect to GND
12.5 mV
400 mV
200 mV
100 mV
60 mV
25 mV
DYNAMIC VID MONITORING
The ADT7462 supports dynamic VID monitoring. The purpose
of the VID code is to tell the voltage controller what voltage,
VCCP, should be applied to the CPU. The VCCP voltage applied to
the processor changes as the power requirements of the
processor change. The VID is compared with VCCP1 only. Note
that when the VIDs are enabled, the LSB value for VCCP1
becomes 0.0125 V (see Table 16).
The VID values can represent voltages from 0.8375 V to 1.6 V.
The VID code is sampled by the ADT7462 every 11 μs and is
stored in Register 0x97. Once the VID code has been stable
(that is, does not change) for 55 μs, the measured VCCP is then
compared with the VID code. The comparison table used is
for either the VR10 or the VR11 specification (set by Bit 6 of
Register 0x00). If the VID code and the measured VCCP do not
match within a certain limit, then an ALERT is generated.
Bit 1 = VID1 (reflects the logic state of Pin 2)
Table 21. VR11 VID Codes
VR10 requires only six VID lines (see Table 22). Pin 28 should
be connected to ground when monitoring VR10 VID codes.
VID6 reports a 0.
The VID value decoded and the VCCP measurement must be
within a window controlled by the VID high and low limits.
The VID is compared with VCCP1 only. Register 0x78 holds
the 4-bit VID high and low limits. The high limit has a range
of 0 mV to +375 mV with a resolution of 25 mV (four bits). The
low limit has a range of 0 mV to −187.5 mV with resolution of
12.5 mV (four bits). The high limit is used in a greater-than
comparison, and the low limit is used in a less-than or equal-to
comparison. Note that if both limits are set to 0x00, then
because low limit is less than or equal to comparison, an
ALERT always results. Therefore, the minimum value for low
limit is 0x01.
If the VCCP voltage measured and the VID code do not match to
within the programmed limit, then Status Bit 6 of the digital
status register gets set (Register 0xBE). This, in turn, can
generate an ALERT if it is not masked.
Rev. 0 | Page 30 of 92
ADT7462
Example:
VID high limit: 100 mV (Register 0x78), four MSBs set to 0100.
VID low limit: 50 mV (Register 0x78), four LSBs set to 0100.
VID value equates to 1.1 V. This is the read VID decoded, using
either VR10 or VR11 tables.
VCCP1 must be in the window of 1.05 V to 1.2 V. If the VCCP1
value is outside this window, the status bit is set and an ALERT
is generated.
To clear an ALERT generated in this way, read the digital status
register. If the VID code and VCCP are now matching within the
programmed window (that is, the error condition that caused
the ALERT has gone away), then the status bit is reset and so is
the ALERT.
The VID to VCCP voltage tables for both VR10 and VR11 can be
found on the Intel website. See the VRM and EVRD 10.0 Design
Guidelines (Reg. 0.5), Page 18 and Page 19, for additional
information.
Rev. 0 | Page 31 of 92
ADT7462
STATUS AND MASK REGISTERS AND ALERT
Status Registers
HIGH LIMIT
Each measured temperature and voltage has an associated high
and low limit. The measured values are compared with these
programmable limits. The results of these comparisons are
stored in the status registers. A Logic 0 in the status register
represents an in-limit comparison, while a Logic 1 represents an
out-of-limit comparison.
Once a status bit is set, it remains set until the status register is
read by the SMBus master. Once read, the status bit clears if the
error condition has gone away. The status registers are duplicated
to accommodate situations where there are two SMBus masters.
If one master reads the host status registers and consequently
clears them, the second master has no way of knowing what bits
were set and what bits were cleared. The second SMBus master
can read from the duplicate BMC status registers for what status
bits were set.
Table 23 is a list of the status registers and corresponding
addresses.
Host Address
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
05569-029
STICKY
STATUS
BIT
Figure 39. ALERT and Status Bit Behavior
Figure 39 shows how the ALERT output and ‘‘sticky’’ status bits
behave. Once a limit is exceeded, the corresponding status bit is
set to 1. The status bit remains set until the error condition goes
away and the status register is read. The status bits are referred
to as sticky because they remain set until read by software. This
ensures that an out-of-limit event cannot be missed, if software
is polling the device periodically. Note that the ALERT output
remains low for the entire duration that a reading is out-of-limit
and until the status register has been read.
Mask Registers
Table 23. Status Registers
Register Name
Thermal Status Register 1
Thermal Status Register 2
Thermal Status Register 3
Voltage Status Register 1
Voltage Status register 2
Fan Status Register 1
Digital Status Register 1
GPIO Status Register
TEMPERATURE
BMC Address
0xC0
0xC1
0xC3
0xC4
0xC5
0xC6
The user has the option to mask out any of the individual status
bits that generate an ALERT. This is achieved by setting the
appropriate bit in the mask registers. The ALERT output is not
asserted on the setting of a status bit if it has been masked. The
status bit itself is not affected and continues to be set when an
out-of-limit condition exists.
Table 24 is a list of the mask registers and corresponding
addresses.
Table 24. Mask Registers
ALERT Output
The ADT7462 has an SMBus ALERT output that is asserted
when one of the status bits gets set. This is to alert the master
that an out-of-limit measurement has taken place or that there
is a fault on one of the fan channels.
An ALERT is generated as a result of a status bit being set in any
of the registers.
Register Name
Thermal Mask Register 1
Thermal Mask Register 2
Voltage Mask Register 1
Voltage Mask Register 2
Fan Mask Register 1
Digital Mask Register 1
GPIO Mask Register
Rev. 0 | Page 32 of 92
Register Address
0x30
0x31
0x32
0x33
0x34
0x35
0x36
ADT7462
FAN CONTROL
FAN DRIVE USING PWM CONTROL
Using the ADT7462 with 3-Wire Fans
The ADT7462 uses pulse width modulation (PWM) to control
fan speed. Control relies on varying the duty cycle (or on/off
ratio) of a square wave applied to the fan to vary the fan speed.
The advantage of using PWM control is that it uses a very
simple external circuit. The specific circuit used depends upon
the type of fan.
Figure 41 shows the most typical circuit used with a 3-wire fan.
For 2-wire and 3-wire fans, the low frequency PWM drive
signal should be selected. For 4-wire fans, the high frequency
PWM drive signal should be selected.
Using the ADT7462 with 2-Wire Fans
Figure 40 shows the most typical circuit used with a 2-wire
fan and illustrates how a 2-wire fan can be connected to the
ADT7462. The low frequency PWM mode must be selected
when using a 2-wire fan.
+V
ADT7462
3.3V
1N4148
5V OR
12V FAN
10kΩ
TYPICAL
Q1
NDT3055L
PWM
RSENSE
2Ω
TYPICAL
Figure 40. Driving a 2-Wire Fan
05569-030
0.01µF
TACH
12V
10kΩ
TACH/AIN
10kΩ
4.7kΩ
3.3V
12V
FAN
1N4148
ADT7462
10kΩ
PWM
Q1
NDT3055L
05569-031
There are three main fan types in use: 2-wire fans, 3-wire fans,
and 4-wire fans. The 2-wire fan has only power and ground
connections. The 3-wire fan has power and ground connections
and a TACH output to indicate the speed of the fan. The 4-wire
fan has power and ground connections, a TACH output, and a
PWM input. The PWM input is connected directly to the PWM
drive of the ADT7462 and is used to control the speed of the
fans.
12V
Figure 41. Driving a 3-Wire Fan
The external circuitry required is very simple. A MOSFET, such
as the NDT3055L, is used as the pass device. The specifications
of the MOSFET depend on the maximum current required by
the fan being driven. A typical PC fan can draw a nominal
current ranging from a few hundred milliamps to over an amp
of current. Depending on the current rating of the fan, a SOT
device can be used where board space is a concern. If you drive
several fans in parallel from a single PWM output or drive
larger server fans, the MOSFET must handle the higher current
requirements. The only other stipulation is that the MOSFET
should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM pins. VGS can be greater than 3.3 V as long as
the pull-up on the gate is tied to 5 V. The MOSFET should also
have a low on resistance to ensure that there is not significant
voltage drop across the FET, which would reduce the voltage
applied across the fan and reduce the full speed of the fan.
Figure 41 uses a 10 kΩ pull-up resistor for the TACH signal.
This assumes that the TACH signal is an open collector from
the fan. In all cases, the TACH signal from the fan must be kept
below 5 V maximum to prevent damaging the ADT7462. If in
doubt as to whether the fan used has an open-collector or
totem-pole TACH output, use one of the input signal
conditioning circuits shown in the Fan Speed Measurement
section of the data sheet.
Driving a 3-wire fan with a PWM signal makes the fan speed
measurement more difficult because the TACH signal is
chopped by the PWM drive signal. Pulse stretching is required
in this case to make accurate fan speed measurements. For
more information, see the Fan Speed Measurement section.
Rev. 0 | Page 33 of 92
ADT7462
Using the ADT7462 with 4-Wire Fans
Figure 42 shows the most typical circuit used with 4-wire fans.
12V 12V
12V, 4-WIRE FAN
TACH
10kΩ
4.7kΩ
ADT7462
TACH
VCC
TACH
3.3V
PWM
3.3V OR 5V
10kΩ
TYPICAL
2kΩ
TACH7
+V
3.3V
05569-032
PWM
ADT7462
Figure 42. Driving a 4-Wire Fan
10kΩ
TYPICAL
TACH3
Because the electronics in a 4-wire fan are powered continuously,
unlike previous PWM driven/powered fans, 4-wire fans tend to
perform better than 3-wire fans, especially for high frequency
applications. It also eliminates the requirement for pulse
stretching, because the TACH signal is always available.
+V
3.3V
TACH
5V OR
12V FAN
1N4148
TACH
5V OR
12V FAN
10kΩ
TYPICAL
PWM3
Q1
NDT3055L
Figure 43. Interfacing Two Fans in Parallel to a PWM Output
Using a Single N-Channel MOSFET
Driving Two Fans from Each PWM
Note that the ADT7462 has up to eight TACH inputs available
for fan speed measurement, but only four PWM drive outputs.
If all eight fans are being used in the system, two fans should be
driven in parallel from each PWM output. Figure 43 shows how
to drive two fans in parallel using the NDT3055L MOSFET.
This information is relevant for low frequency mode only
(2-wire and 3-wire fans), because the PWM and TACHs need to
be synchronized to obtain accurate fan speed measurements
using pulse stretching (see the Fan Speed Measurement with
Pulse Stretching section). In high frequency mode and when
using 4-wire fans, the TACH signal is always valid because the
fan is always powered on.
Rev. 0 | Page 34 of 92
05569-033
10kΩ
Note that because the MOSFET can handle up to 3.5 A, it is
simply a matter of connecting another fan directly in parallel
with the first. Care should be taken in designing drive circuits
with transistors and FETs to ensure that the PWM pins are not
required to source current and that they sink less than the 8 mA
maximum current specified on the data sheet.
ADT7462
FAN SPEED MEASUREMENT AND CONTROL
TACH INPUTS
Pin 1, Pin 2, Pin 3, Pin 4, Pin 7, Pin 8, Pin 21, and Pin 22 are
TACH inputs intended for fan speed measurement.
Signal conditioning in the ADT7462 accommodates the slow
rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even where VCC is less
than 5 V. In the event that these inputs are supplied from fan
outputs that exceed 0 V to 5 V, either resistive attenuation of the
fan signal or diode clamping must be included to keep inputs
within an acceptable range.
If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a
totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 46. Alternatively, a resistive
attenuator can be used, as shown in Figure 47. R1 and R2
should be chosen such that
2 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5 V
The fan inputs have an input resistance of nominally 160 kΩ to
ground, so this should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and a pull-up resistor of less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ.
This gives a high input voltage of 3.83 V.
If the fan TACH output has a resistive pull-up to VCC, it can be
connected directly to the fan input, as shown in Figure 44.
PULL-UP TYP
<1kΩ OR
TOTEM POLE
VCC
12V
R1
10kΩ
TACH
OUTPUT
TACH
OUTPUT
TACH
ADT7462
TACH
ZD1
ZENER*
FAN SPEED
COUNTER
ADT7462
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC.
FAN SPEED
COUNTER
Figure 46. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Clamped with a Zener Diode and Resistor
05569-034
PULL-UP
4.7kΩ
TYPICAL
VCC
5V OR 12V
FAN
05569-036
Figure 44 to Figure 47 show circuits for most common fan
TACH circuits.
VCC
12V
Figure 44. Fan with TACH Pull-Up to VCC
<1kΩ
R1*
TACH
OUTPUT
TACH
R2*
*SEE TEXT
FAN SPEED
COUNTER
ADT7462
05569-037
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V), the fan output can be clamped with a Zener
diode, as shown in Figure 45. The Zener diode voltage should
be chosen so that it is greater than VIH of the TACH input but
less than 5 V, allowing for the voltage tolerance of the Zener. A
value of between 3 V and 5 V is suitable.
Figure 47. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Attenuated with R1/R2
VCC
12V
FAN SPEED MEASUREMENT
TACH
OUTPUT
TACH
ZD1*
FAN SPEED
COUNTER
ADT7462
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC.
05569-035
PULL-UP
4.7kΩ
TYPICAL
Figure 45. Fan with TACH Pull-Up to Voltage > 5 V (Example, 12 V),
Clamped with Zener Diode
The method of fan speed measurement when using 3-wire fans
differs from that used with 4-wire fans. When 3-wire fans are in
use, power is continuously applied and removed from the fan,
thereby chopping the TACH information. As a result, every time
a fan speed measurement is to be made, the fan must be switched
on for a long enough period of time that a measurement can be
made. This is called pulse stretching. With 4-wire fans, power is
always applied to the fan, so fan speed measurements can be
made continuously, and there is no need for pulse stretching.
Pulse stretching is also not necessary when driving a 3-wire fan
with a dc input. The Fan Speed Measurement Without Pulse
Stretching section and the Fan Speed Measurement with Pulse
Stretching section describe how fan speed is measured both
when pulse stretching is required and when it is not.
Rev. 0 | Page 35 of 92
ADT7462
Fan Speed Measurement Without Pulse Stretching
Fan Speed Measurement Registers
Fan speed is measured by the ADT7462, and the result is stored
in the fan TACH value registers. The fan counter does not count
the fan TACH output pulses directly because the fan speed can
be less than 1000 rpm, and it would take several seconds to
accumulate a reasonably large and accurate count. Instead, the
period of the fan revolution is measured by gating an on-chip
90 kHz oscillator into the input of a 16-bit counter for N periods of
the fan TACH output (see Figure 48), so the accumulated count
is actually proportional to the fan tachometer period and inversely
proportional to the fan speed.
Fan speed measurement involves a 2-register read for each
measurement. The low byte should be read first. This causes the
high byte to be frozen until both high and low byte registers
have been read, preventing erroneous TACH readings. The fan
tachometer reading registers report back the number of 11.11 μs
period clocks (90 kHz oscillator) gated to the fan speed counter,
from the rising edge of the first fan TACH pulse to the rising
edge of the third fan TACH pulse (because two pulses per
revolution are being counted). Because the device is essentially
measuring the fan TACH period, the higher the count value the
slower the fan is actually running. A 16-bit fan tachometer
reading of 0xFFFF indicates either that the fan has stalled or is
running very slowly (<100 rpm).
To enable continuous measurement for 3-wire fans, set the
corresponding dc bit for the TACH input in the TACH configuration register. This bit is set automatically when the HF PWM
is in use with 4-wire fans.
Fan Speed Measurement with Pulse Stretching
The method for measuring fan speed for 3-wire fans requiring
pulse stretching is similar to the method described in the Fan
Speed Measurement Without Pulse Stretching section for
continuous measurements. The main difference is that the PWM
drive must be synchronized to the TACH input so that the
ADT7462 knows that pulse stretching is taking place while the
TACH is being measured.
PWM1 is synchronized with TACH1 and TACH5.
PWM2 is synchronized with TACH2 and TACH6.
PWM3 is synchronized with TACH3 and TACH7.
PWM4 is synchronized with TACH4 and TACH8.
When pulse stretching is enabled, the ADT7462 measures fan
speed once a second. The counter then counts up from the first
to the third TACH pulse; this value is stored in the TACH value
register. The PWM drive returns to its previous programmed value.
To enable fan speed measurements four times a second, set the
FAST bit (Bit 0) of Configuration Register 2 (0x02). When the
FAST bit is set, fan TACH readings are updated every 250 ms.
The actual fan TACH period is being measured; therefore, an
ALERT is generated if the reading falls below a fan TACH limit.
This sets the appropriate status bit and can be used to generate
an SMBALERT. The TACH limit is an 8-bit value that is
compared with the TACH high byte of the TACH reading.
Table 25. Tachometer Value and Limit Registers
TACH
TACH1
TACH2
TACH3
TACH4
TACH5
TACH6
TACH7
TACH8
Low Byte
Value Register
0x98
0x9A
0x9C
0x9E
0xA2
0xA4
0xA6
0xA8
High Byte
Value Register
0x99
0x9B
0x9D
0x9F
0xA3
0xA5
0xA7
0xA9
8-Bit Limit
Register
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Calculating Fan Speed
Assuming a fan with a two pulses/revolution (and two
pulses/revolution being measured), fan speed is calculated by
Fan Speed (rpm) = (freq × 60)/Fan Tachometer Reading
where:
Fan Tachometer Reading = a 16-bit fan tachometer reading.
freq = oscillator frequency, 90 kHz.
CLOCK
PWM
Example:
1
TACH1 high byte (Register 0x99) = 0x17
TACH1 low byte (Register 0x98) = 0xFF
2
3
4
05569-038
TACH
What is the speed of Fan 1 in rpm?
Figure 48. Fan Speed Measurement
Fan 1 Tachometer Reading = 0 × 17 FF = 6143 Decimal
RPM = ( f × 60)/Fan 1 Tachometer Reading
RPM = (90000 × 60)/6143
Fan Speed = 879 rpm
Rev. 0 | Page 36 of 92
ADT7462
If the fan is a 6-pole fan, the count value is representative of 2/3
of a revolution. Therefore, the result of the equation above
should be divided by 1.5. Similarly, if the fan used is an
8-pole fan, then the result should be divided by 2.
Fan Spin-Up
The ADT7462 has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are detected
on the TACH input. Once two TACH pulses have been detected,
the PWM duty cycle goes to the expected running value, for
example, 33%. The advantage of this process is that fans have
different spin-up characteristics and take different times to
overcome inertia. The ADT7462 runs the fans just fast enough
to overcome inertia and is quieter on spin-up than fans
programmed to spin up for a given spin-up time.
Fan Start-Up Timeout
To prevent false interrupts being generated as a fan spins up
(because it is below running speed), the ADT7462 includes a
fan start-up timeout function. During this time, the ADT7462
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated. Using Configuration
Register 1 (0x01), Bit 4, this functionality can be changed to
spinning the fans for a programmable time instead of two
TACH pulses.
The start-up timeout for each PWM drive is programmed by
Bits [2:0] in the PWMx configuration registers.
PWM1 Configuration Register = Register 0x21
PWM2 Configuration Register = Register 0x22
PWM Drive Frequency 2 is set using Bits [7:5] of the PWM1
and PWM2 frequency register (0x25).
PWM Drive Frequency 3 is set using Bits [4:2] of the PWM3
and PWM4 frequency register (0x26).
PWM Drive Frequency 4 is set using Bits [7:5] of the PWM3
and PWM4 frequency register (0x26).
Table 27. Low Frequency PWM Options
Bit
000
001
010
011
100
101
110
111
Frequency
11 Hz
14.7 Hz
22.1 Hz
29.4 Hz
35.3 Hz
44.1 Hz
58.8 Hz
88.2 Hz
In automatic fan speed control mode, fan speed is automatically
varied with temperature and without CPU intervention, once
initial parameters are set up. The advantage is that if the system
hangs, it is guaranteed that the system is protected from
overheating. The automatic fan speed control incorporates a
feature called dynamic TMIN calibration. This feature reduces the
design effort required to program the automatic fan speed
control loop. For more information on how to program the
automatic fan speed control loop and dynamic TMIN operation,
see the Programming the Automatic Fan Speed Control Loop
section.
Table 26. Fan Start-Up Timeout
Start-Up Timeout
No start-up timeout
100 ms
250 ms
400 ms
667 ms
1 sec
2 sec
4 sec
PWM LOGIC STATE
The PWM outputs can be programmed high for 100% duty
cycle (non-inverted) or low for 100% duty cycle (inverted). This
is programmed for each PWM drive in the PWMx Configuration
Registers using the INV bit (Bit 4).
1 = logic high for 100% PWM duty cycle.
PWM Drive Frequency 1 is set using Bits [4:2] of the PWM1
and PWM2 frequency register (0x25).
The ADT7462 controls fan speed using two different modes:
automatic and manual.
PWM4 Configuration Register = Register 0x24
0 = logic low for 100% PWM duty cycle.
The PWM drive frequency can be adjusted for the application.
The ADT7462 supports both high frequency and low frequency
PWM. High or low frequency PWM mode is selected in
Register 0x02, Bit 2. In high frequency mode, the PWM drive
frequency is always 22.5 kHz and cannot be changed. Register 0x25
and Register 0x26 configure the PWM frequency in low frequency mode for PWM1 to PWM4, respectively.
FAN SPEED CONTROL
PWM3 Configuration Register = Register 0x23
Bit
000
001
010
011
100
101
110
111
Low Frequency Mode PWM Drive Frequency
In manual fan speed control mode, the ADT7462 allows the
duty cycle of any PWM output to be manually adjusted. This is
useful if the user wants to change fan speed in the software or
adjust PWM duty cycle output for test purposes. Bits [7:5] of
Register 0x21 to Register 0x24 (PWM configuration registers)
control the behavior of each PWM output. Once under manual
control, each PWM output can be manually updated by writing to
Register 0xAA to Register 0xAD (PWM duty cycle registers).
Rev. 0 | Page 37 of 92
ADT7462
Programming the PWM Current Duty Cycle Registers
PWM Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
Register 0xAA PWM1 Duty Cycle = 0x00 (0% default)
The value to be programmed into the PWMMIN register is
given by
Register 0xAC PWM3 Duty Cycle = 0x00 (0% default)
Value (Decimal ) = PWM MIN 0.39
Example 1: For a PWM duty cycle of 50%,
Value (Decimal) = 50/0.39 = 128 Decimal
Value = 128 Decimal or 0x80
Register 0xAB PWM2 Duty Cycle = 0x00 (0% default)
Register 0xAD PWM4 Duty Cycle = 0x00 (0% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.
Example 2: For a PWM duty cycle of 33%,
Value (Decimal) = 33/0.39 = 85 Decimal
Value = 85 Decimal or 0x54
05569-039
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
Figure 49. Control PWM Duty Cycle Manually with a Resolution of 0.39%
Rev. 0 | Page 38 of 92
ADT7462
Note that to more efficiently understand the automatic fan
speed control loop, use of the ADT7462 evaluation board and
software is strongly recommended while reading this section.
This section provides the system designer with an understanding
of the automatic fan control loop and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize system characteristics, the designer
needs to carefully plan system configuration, including the
number of fans, where they are located, and what temperatures are
being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at the
beginning of the process.
Automatic Fan Control Overview
The ADT7462 can automatically control the speed of fans based
upon the measured temperature. This is done independently
from CPU intervention once initial parameters are set up.
The ADT7462 has a local temperature sensor and up to three
remote temperature channels that can be connected to a CPU
on-chip thermal diode (available on Intel Pentium class and
other CPUs/GPUs). These four temperature channels can be
used as the basis for automatic fan speed control to drive fans
using pulse-width modulation (PWM).
THERMAL CALIBRATION
Automatic fan speed control reduces acoustic noise by
optimizing fan speed according to accurately measured
temperature. Reducing fan speed can also decrease system
current consumption. The automatic fan speed control mode
is very flexible, owing to the number of programmable
parameters, including TMIN and TRANGE. The TMIN and TRANGE
values for a temperature channel and, therefore, for a given fan,
are critical because they define the thermal characteristics of the
system. The thermal validation of the system is one of the most
important steps in the design process, so these values should be
selected carefully.
Figure 50 gives a top-level overview of the automatic fan control
circuitry on the ADT7462. From a systems-level perspective, up
to four system temperatures can be monitored and used to
control four PWM outputs. The four PWM outputs can be used
to control up to eight fans. The ADT7462 allows the speed of
eight fans to be monitored. The Remote 1 and Remote 2
temperature channels have a thermal calibration block, allowing
the designer to individually configure the thermal characteristics of
those temperature channels. For example, the CPU fan can be
run when CPU temperature increases above 60°C and a chassis
fan can be run when the local temperature increases above
45°C. At this stage, the designer has not assigned these thermal
calibration settings to a particular fan drive (PWM) channel.
The right side of Figure 50 shows controls that are fan-specific.
The designer has individual control over parameters such as
minimum PWM duty cycle, fan speed failure thresholds, and
even ramp control of the PWM outputs. Automatic fan control,
then, ultimately allows graceful fan speed changes that are less
perceptible to the system user.
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
REMOTE 1
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
MUX
LOCAL
TEMP
REMOTE 2
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
TMIN
0%
PWM
MIN
100%
TRANGE
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
Figure 50. Automatic Fan Control Block Diagram
Rev. 0 | Page 39 of 92
PWM
GENERATOR
PWM
CONFIG
PWM
GENERATOR
PWM
CONFIG
PWM
GENERATOR
PWM1
TACH1
PWM2
TACH2
PWM3
TACH3
05569-040
PROGRAMMING THE AUTOMATIC FAN SPEED
CONTROL LOOP
ADT7462
The fastest speed calculated options pertain to controlling one
PWM output based on multiple temperature channels. The
thermal characteristics of the three temperature zones can be
set to drive a single fan. An example is the fan turning on when
the Remote 1 temperature exceeds 60°C or when the local
temperature exceeds 45°C.
STEP 1—CONFIGURING THE MUX
First, the user needs to decide how many temperature channels
are being measured and how many fans need to be controlled
and monitored. Once these decisions have been made, the fans
can be assigned to particular temperature channels. Not only
can fans be assigned to individual channels, but the behavior of
the fans is also configurable. For example, fans can be run under
automatic fan control; they can be run manually (under software
control); or they can be run at the fastest speed calculated by
multiple temperature channels. The MUX is the bridge between
temperature measurement channels and the three PWM outputs.
STEP 2—TMIN SETTINGS FOR THERMAL
CALIBRATION CHANNELS
TMIN is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at TMIN is
programmed later. The TMIN values chosen are temperature
channel-specific; for example, 25°C for ambient channel, 30°C
for VRM temperature, and 40°C for processor temperature.
Bits [7:5] (BHVR) of Register 0x21, Register 0x22, Register 0x23,
and Register 0x24 (PWM configuration registers) control the
behavior of the fans connected to the PWM1, PWM2, PWM3,
and PWM4 outputs. The values selected for these bits determine
how the MUX connects a temperature measurement channel to
a PWM output.
TMIN is an 8-bit value, either twos complement or Offset 64, that
can be programmed in 1°C increments. There is a TMIN register
associated with each temperature measurement channel: local,
Remote 1, Remote 2, and Remote 3. Once the TMIN value is
exceeded, the fan turns on and runs at the minimum PWM
duty cycle. The fan turns off once the temperature has dropped
below TMIN − THYST.
Automatic Fan Control MUX Options
Bits [7:5] (BHVR), Register 0x21, Register 0x22, Register 0x23,
and Register 0x24, control the behavior of the corresponding
PWM outputs (see Table 61).
MUX
PWM
MIN
100%
PWM
CONFIG
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
MUX
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
0%
PWM
MIN
100%
TRANGE
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
REMOTE 2 =
CPU TEMP
PWM
GENERATOR
PWM
CONFIG
PWM
GENERATOR
PWM
CONFIG
PWM1
TACH1
CPU FAN SINK
PWM2
TACH2
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REAR CHASSIS
Figure 51. Assigning Temperature Channels to Fan Channels
Rev. 0 | Page 40 of 92
05569-041
THERMAL CALIBRATION
ADT7462
To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Spin-Up section for
more details. In some cases, primarily for psycho-acoustic reasons,
the fan should never switch off below TMIN. The corresponding
bits in Register 0x25 and Register 0x26 should be set to keep the
fans running at the PWM minimum duty cycle, if the temperature
falls below TMIN.
TMIN Registers
Register 0x5C, Local Temperature TMIN = 0x9A (90°C)
PWM1 and PWM2 Frequency Register (0x25)
Bit 0 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 0 (MIN1) = 1. PWM1 runs at PWM1 minimum duty cycle
below TMIN − THYST.
Bit 1 (MIN2) = 0. PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 1 (MIN2) = 1. PWM2 runs at PWM2 minimum duty cycle
below TMIN − THYST.
Register 0x5D, Remote 1 Temperature TMIN = 0x9A (90°C)
PWM3 and PWM4 Frequency Register (0x26)
Register 0x5E, Remote 2 Temperature TMIN = 0x9A (90°C)
Bit 0 (MIN3) = 0. PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Register 0x5F, Remote 3 Temperature TMIN = 0x9A (90°C)
Bit 0 (MIN3) = 1. PWM3 runs at PWM3 minimum duty cycle
below TMIN − THYST.
Bit 1 (MIN4) = 0. PWM4 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 1 (MIN4) = 1. PWM4 runs at PWM4 minimum duty cycle
below TMIN − THYST.
PWM DUTYCYCLE
100%
0%
TMIN
PWM
MIN
100%
PWM
CONFIG
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
MUX
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
0%
PWM
MIN
100%
TRANGE
0%
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
PWM
GENERATOR
PWM
CONFIG
PWM
GENERATOR
PWM
CONFIG
PWM1
TACH1
CPU FAN SINK
PWM2
TACH2
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 52. Understanding the TMIN Parameter
Rev. 0 | Page 41 of 92
05569-042
THERMAL CALIBRATION
ADT7462
STEP 3—PWMMIN FOR EACH PWM (FAN) OUTPUT
PWMMIN is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above TMIN.
For maximum system acoustic benefit, PWMMIN should be as
low as possible. Depending on the fan used, the PWMMIN
setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.
Example 1: For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWMMIN Registers
Register 0x28, Minimum PWM1 Duty Cycle = 0x80 (50% default)
Register 0x29, Minimum PWM2 Duty Cycle = 0x80 (50% default)
Register 0x2A, Minimum PWM3 Duty Cycle = 0x80 (50% default)
PWMMIN
Register 0x2B, Minimum PWM4 Duty Cycle = 0x80 (50% default)
0%
Note on Fan Speed and PWM Duty Cycle
05569-043
TEMPERATURE
TMIN
Figure 53. PWMMIN Determines Minimum PWM Duty Cycle at TMIN
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan
characteristics can be set up differently. As a result, Fan 1,
driven by PWM1, can have a different PWMMIN value than that
of Fan 2 connected to PWM2. Figure 54 illustrates this as
PWM1MIN (the front fan) is turned on at a minimum duty cycle
of 20%, while PWM2MIN (the rear fan) turns on at a minimum
of 40% duty cycle. Note, however, that both fans turn on at
exactly the same temperature, defined by TMIN.
PWM DUTY CYCLE
100%
PW
M2
PW
PWM2MIN
The PWM duty cycle does not directly correlate to fan speed in
rpm. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %rpm generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in rpm approximates to
% fanspeed = PWM duty cycle × 10
STEP 4—PWMMAX FOR PWM (FAN) OUTPUTS
PWMMAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For
maximum system acoustic benefit, PWMMAX should be as low as
possible but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to 100%
for fail-safe cooling.
M1
There is one PWMMAX limit (Register 0x2C) for all fan channels.
PWM1MIN
100%
TEMPERATURE
Figure 54. Operating Two Different Fans from a Single Temperature Channel
Programming the PWMMIN Registers
The PWMMIN registers are 8-bit registers that allow the
minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWMMIN register is given by
Value (decimal ) = PWM MIN 0.39
Rev. 0 | Page 42 of 92
PWM DUTY CYCLE
TMIN
05569-044
0%
PWMMAX
PWMMIN
0%
TMIN
TEMPERATURE
Figure 55. PWMMAX Determines Maximum PWM Duty Cycle
Below the THERM Temperature Limit
05569-045
PWM DUTY CYCLE
100%
ADT7462
Programming the PWMMAX Register
The PWMMAX register (0x2C) is an 8-bit register that allows the
maximum PWM duty cycle for the outputs to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.
The TRANGE or fan control slope is determined by the following
procedure:
1.
Determine the maximum operating temperature for that
channel (for example, 70°C).
2.
Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worstcase operating points. (For example, 70°C is reached when
the fans are running at 50% PWM duty cycle.)
3.
Determine the slope of the required control loop to meet
these requirements.
4.
Using the ADT7462 evaluation software, you can
graphically program and visualize this functionality.
Ask your local Analog Devices representative for details.
The value to be programmed into the PWMMAX register is given
by
Value (decimal ) = PWM MAX 0.39
Example 1: For a maximum PWM duty cycle of 50%,
Value (decimal) − 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a maximum PWM duty cycle of 75%,
Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or 0xC0 (hex)
PWM DUTY CYCLE
100%
PWMMAX Register
Register 0x2C, Maximum PWM1 to PWM4 Duty Cycle =
0xC0 (75% default)
See the Note on Fan Speed and PWM Duty Cycle section for
more information.
50%
33%
0%
40°C
TRANGE is the range of temperature over which automatic fan
control occurs once the programmed TMIN temperature has
been exceeded. TRANGE is a temperature slope, not an arbitrary
value; that is, a TRANGE of 40°C holds true only for PWMMIN =
33%. If PWMMIN is increased or decreased, the effective TRANGE
changes.
TRANGE
TMIN
05569-047
30°C
STEP 5—TRANGE FOR TEMPERATURE CHANNELS
Figure 57. Adjusting PWMMIN Affects TRANGE
TRANGE is implemented as a slope, which means that as PWMMIN
is changed, TRANGE changes, but the actual slope remains the
same. The higher the PWMMIN value, the smaller the effective
TRANGE; that is, the fan reaches full speed (100%) at a lower
temperature.
100%
PWM DUTY CYCLE
PWMMIN
50%
33%
25%
10%
0%
TEMPERATURE
0%
30°C
40°C
Figure 56. TRANGE Parameter Affects Cooling Range
45°C
54°C
TMIN
Figure 58. Increasing PWMMIN Changes Effective TRANGE
Rev. 0 | Page 43 of 92
05569-048
TMIN
05569-046
PWM DUTY CYCLE
100%
ADT7462
For a given TRANGE value, the temperature at which the fan runs
at full speed for different PWMMIN values can be easily
calculated by
Example 4: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 50% duty cycle = 128 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE/170
TMAX = 30°C + (100% − 50%) × 40°C/170
TMAX = 30°C + (255 − 128) × 40°C/170
TMAX = 60°C (effective TRANGE = 30°C)
TMAX = TMIN + (Max DC − Min DC ) × TRANGE 170
where:
TMAX is the temperature at which the fan runs full speed.
TMIN is the temperature at which the fan turns on.
Max DC is the maximum duty cycle (100%) = 255 decimal.
Min DC is equal to PWMMIN.
TRANGE is the PWM duty cycle vs. temperature slope.
Selecting a TRANGE Slope
The TRANGE value can be selected for each temperature channel:
local, Remote 1, Remote 2, and Remote 3. Bits [7:4] (TRANGE) of
Register 0x60 to Register 0x63 define the TRANGE value for each
temperature channel (see Table 84).
Example 1: Calculate T, given that TMIN = 30°C, TRANGE = 40°C,
and PWMMIN = 10% duty cycle = 26 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE/170
TMAX = 30°C + (100% − 10%) × 40°C/170
TMAX = 30°C + (255 − 26) × 40°C/170
TMAX = 84°C (effective TRANGE = 54°C)
Example 2: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 25% duty cycle = 64 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE/170
TMAX = 30°C + (100% − 25%) × 40°C/170
TMAX = 30°C + (255 − 64) × 40°C/170
TMAX = 75°C (effective TRANGE = 45°C)
Example 3: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 33% duty cycle = 85 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE/170
TMAX = 30°C + (100% − 33%) × 40°C/170
TMAX = 30°C + (255 − 85) × 40°C/170
TMAX = 70°C (effective TRANGE = 40°C)
Summary of TRANGE Function
When using the automatic fan control function, the temperature
at which the fan reaches full speed can be calculated by
TMAX = TMIN + TRANGE
(1)
Equation 1 holds true only when PWMMIN is equal to 33% PWM
duty cycle.
Increasing or decreasing PWMMIN changes the effective TRANGE,
although the fan control still follows the same PWM duty cycle
to temperature slope. The effective TRANGE for different PWMMIN
values can be calculated using Equation 2
TMAX = TMIN + (Max DC − Min DC ) × TRANGE 170
(2)
where (Max DC − Min DC) × TRANGE/170 is the effective TRANGE
value.
Figure 59 shows PWM duty cycle vs. temperature for each
TRANGE setting. The lower graph shows how each TRANGE setting
affects fan speed vs. temperature. As can be seen from the
graph, the effect on fan speed is nonlinear.
Rev. 0 | Page 44 of 92
ADT7462
2.5°C
90
PWM DUTY CYCLE (%)
6.67°C
60
8°C
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
40°C
40
60
80
TEMPERATURE ABOVE TMIN
100
120
100
8°C
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
40°C
10
0
0
80°C
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
100
2°C
2.5°C
90
6.67°C
60
53.3°C
20
5°C
20
32°C
10
4°C
70
2.5°C
3.33°C
3.33°C
80
80
FAN SPEED (% OF MAX)
4°C
5°C
70
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
40°C
10
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
6.67°C
8°C
10°C
50
13.3°C
40
16°C
20°C
30
26.6°C
32°C
40°C
10
0
0
Figure 59. TRANGE vs. Actual Fan Speed Profile
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
Figure 60. TRANGE and % Fan Speed Slopes with PWMMIN = 20%
The graphs in Figure 59 assume that the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN,
needs to be factored in to see how the loop actually performs in
the system. Figure 60 shows how TRANGE is affected when the
PWMMIN value is set to 20%. It can be seen that the fan runs
about 45% fan speed when the temperature exceeds TMIN.
Example: Determining TRANGE for Each Temperature
Channel
The following example shows how the different TMIN and TRANGE
settings can be applied to three different thermal zones. In this
example, the following TRANGE values apply:
TRANGE = 80°C for ambient temperature
TRANGE = 53.3°C for CPU temperature
TRANGE = 40°C for VRM temperature
5°C
60
53.3°C
20
4°C
70
20
32°C
20
80°C
2°C
90
05569-049
PWM DUTY CYCLE (%)
5°C
20
FAN SPEED (% OF MAX)
3.33°C
80
4°C
70
0
0
2.5°C
90
3.33°C
80
0
0
2°C
100
2°C
This example uses the MUX configuration described in the
Step 1—Configuring the MUX section. Both CPU temperature
and VRM temperature drive the CPU fan connected to PWM1.
Ambient temperature drives the front chassis fan and rear
chassis fan connected to PWM2 and PWM3.
The front chassis fan is configured to run at PWMMIN = 20%.
The rear chassis fan is configured to run at PWMMIN = 30%.
The CPU fan is configured to run at PWMMIN = 10%.
Note on 4-Wire Fans
The control range for 4-wire fans is much wider than that of
2-wire or 3-wire fans. In many cases, 4-wire fans can start with
a PWM drive of as little as 20%.
Rev. 0 | Page 45 of 92
05569-050
100
ADT7462
100
Note that the TTHERM limits cannot be masked, and they affect
90
the fan speed no matter how the automatic fan control settings
are configured. This allows some flexibility because a TRANGE
value can be selected based on its slope, while a hard limit (such
as 70°C), can be programmed as TMAX (the temperature at which
the fan reaches full speed) by setting TTHERM to that limit (for
PWM DUTY CYCLE (%)
80
70
60
50
40
example, 70°C).
30
THERM Registers
20
Register 0x4C, Local THERM1 temperature limit = 0xA4
(100°C default)
10
0
0
10
20
30
40
50
60
70
TEMPERATURE ABOVE TMIN
80
90
100
Register 0x4D, Remote 1 THERM1 temperature limit = 0xA4
(100°C default)
100
90
Register 0x4E, Remote 2 THERM1 temperature limit = 0xA4
(100°C default)
FAN SPEED (% MAX RPM)
80
70
Register 0x4F Remote 3 THERM1 temperature limit = 0xA4
(100°C default)
60
50
Register 0x50, Local THERM2 temperature limit = 0xA4
(100°C default)
40
30
20
Register 0x51, Remote 1 THERM2 temperature limit = 0xA4
(100°C default)
0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE TMIN
05569-051
10
Register 0x52, Remote 2 THERM2 temperature limit = 0xA4
(100°C default)
Figure 61. TRANGE and % Fan Speed Slopes for VRM, Ambient,
and CPU Temperature Channels
Register 0x53 Remote 3 THERM2 temperature limit = 0xA4
(100°C default)
STEP 6—TTHERM FOR TEMPERATURE CHANNELS
TTHERM is the absolute maximum temperature allowed on a
temperature channel. Above this temperature, a component
such as the CPU or VRM might be operating beyond its safe
operating limit. When the measured temperature exceeds
TTHERM, all fans are driven at 100% PWM duty cycle (full speed)
to provide critical system cooling. The fans remain running at
100% until the temperature drops below TTHERM minus hysteresis,
where hysteresis is the number programmed into Local/Remote 1
Hysteresis Register 0x54 and Remote 2/Remote 3 Hysteresis
Register 0x55. The default hysteresis value is 4°C.
Hysteresis Registers
Register 0x54, Local/Remote 1 Temperature
Hysteresis Register
Bits [7:4], local temperature hysteresis (4°C default).
Bits [3:0], Remote 1 temperature hysteresis (4°C default).
Register 0x55, Remote 2/Remote 3 Temperature
Hysteresis Register
Bits [7:4], Remote 2 temperature hysteresis (4°C default).
The TTHERM limit should be considered as the maximum worst-
Bits [3:0], Remote 3 temperature hysteresis (4°C default).
case operating temperature of the system. Because exceeding
any TTHERM limit runs all fans at 100%, it has very negative
Because each hysteresis setting is four bits, hysteresis values are
programmable from 1°C to 15°C. It is not recommended that
hysteresis values ever be programmed to 0°C, because this
disables hysteresis. In effect, this would cause the fans to cycle
between normal speed and 100% speed, creating unsettling
acoustic noise.
acoustic effects. Ultimately, this limit should be set up as a failsafe, and it must not be exceeded under normal system
operating conditions.
Rev. 0 | Page 46 of 92
ADT7462
TRANGE
Dynamic TMIN Control Mode
In addition to the automatic fan speed control mode described
in the Automatic Fan Control Overview section, the ADT7462
has a mode that extends the basic automatic fan speed control
loop. Dynamic TMIN control allows the ADT7462 to intelligently
adapt the system’s cooling solution for best system performance
or lowest possible system acoustics, depending on user or design
requirements. Use of dynamic TMIN control alleviates the need
to design for worst-case conditions and significantly reduces
system design and validation time.
HYSTERESIS
PWM DUTY CYCLE
100%
TTHERM
TMIN
05569-052
0%
Figure 62. How TTHERM Relates to Automatic Fan Control
STEP 7—THYST FOR TEMPERATURE CHANNELS
THYST is the amount of extra cooling a fan provides after the
temperature measured has dropped back below TMIN before the
fan turns off. The premise for temperature hysteresis (THYST) is
that without it, the fan would merely chatter or cycle on and off
regularly whenever the temperature hovers near the TMIN
setting.
The THYST value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of THYST prevent the fans from chattering
on and off. The THYST default value is set at 4°C.
Hysteresis Register
Register 0x60, Bits [3:0] Local THYST
Register 0x61, Bits [3:0] Remote 1 THYST
Register 0x62, Bits [3:0] Remote 2 THYST
Register 0x63, Bits [3:0] Remote 3 THYST
In some applications, it is required that fans not turn off below TMIN
but remain running at PWMMIN. Bits [1:0] of the PWM1, PWM2
Frequency Register (0x25) and the PWM3, PWM4 Frequency
Register (0x26) allow the fans to be turned off or to be kept
spinning below TMIN. If the fans are always on, the THYST value has
no effect on the fan when the temperature drops below TMIN.
TRANGE
PWM DUTY CYCLE
100%
Designing for Worst-Case Conditions
System design must always allow for worst-case conditions.
In PC design, the worst-case conditions include, but are not
limited to, the following:
Worst-Case Altitude
A computer can be operated at different altitudes. Altitude
affects the relative air density, which alters the effectiveness of
the fan cooling solution. For example, when comparing 40°C
air temperature at 10,000 feet to 20°C air temperature at sea
level, relative air density is increased by 40%. This means that
the fan can spin 40% slower and make less noise at sea level
than at 10,000 feet while keeping the system at the same
temperature at both locations.
Worst-Case Fan
Due to manufacturing tolerances, fan speeds in rpm are
normally quoted with a tolerance of ±20%. The designer
must assume that the fan rpm can be 20% below tolerance.
This translates to reduced system airflow and elevated system
temperature. Note that fans 20% out of tolerance can negatively
impact system acoustics because they run faster and generate
more noise.
Worst-Case Chassis Airflow
The same motherboard can be used in a number of different
chassis configurations. The design of the chassis and the
physical location of fans and components determine the system’s
thermal characteristics. Moreover, for a given chassis, the
addition of add-in cards, cables, or other system configuration
options can alter the system airflow and reduce the
effectiveness of the system cooling solution. The cooling
solution can also be inadvertently altered by the end user.
(For example, placing a computer against a wall can block the
air ducts and reduce system airflow.)
VENTS
FAN
FAN
I/O CARDS
THYST
POWER
SUPPLY
I/O CARDS
VENTS
POWER
SUPPLY
TTHERM
GOOD CPU AIRFLOW
Figure 63. The THYST Value Applies to Fan On/Off Hysteresis
FAN
CPU
POOR CPU
AIRFLOW
DRIVE
BAYS
CPU
DRIVE
BAYS
VENTS
GOOD VENTING =
GOOD AIR EXCHANGE
POOR VENTING =
POOR AIR EXCHANGE
Figure 64. Chassis Airflow Issues
Rev. 0 | Page 47 of 92
05569-054
TMIN
05569-053
0%
ADT7462
Worst-Case Processor Power Consumption
This data sheet maximum does not necessarily reflect the
true processor power consumption. Designing for worst-case
CPU power consumption can result in a processor becoming
overcooled (generating excess system noise).
Worst-Case Peripheral Power Consumption
The tendency is to design to data sheet maximums for
peripheral components (again overcooling the system).
Worst-Case Assembly
Every system manufactured is unique because of manufacturing variations. Heat sinks may be loose fitting or slightly
misaligned. Too much or too little thermal grease may be used.
Variations in application pressure for thermal interface
material can affect the efficiency of the thermal solution.
Accounting for manufacturing variations in every system
is difficult; therefore, the system must be designed for the
worst case.
TA
THERMAL
INTERFACE
MATERIAL
TTIM
θCTIM
TC
θCA
θCS
θJA
θTIMC
PROCESSOR
TTIM
θJTIM
SUBSTRATE
EPOXY
THERMAL INTERFACE MATERIAL
TJ
05569-055
INTEGRATED
HEAT
SPREADER
TS
Figure 66 shows an overview of the parameters that affect the
operation of the dynamic TMIN control loop.
TEMPERATURE
TLOW
Figure 65. Thermal Model
Although a design usually accounts for worst-case conditions in
all these cases, the actual system is almost never operated at
worst-case conditions. The alternative to designing for the
worst case is to use the dynamic TMIN control function.
Dynamic TMIN Control Overview
Dynamic TMIN control mode builds upon the basic automatic
fan control loop by adjusting the TMIN value based on system
performance and measured temperature. This is important
because, instead of designing for the worst case, the system
thermals can be defined as operating zones. The ADT7462 can
self-adjust its fan control loop to maintain either an operating
zone temperature or a system target temperature. For example,
it can be specified that ambient temperature in a system be
maintained at 50°C. If the temperature is below 50°C, the fans
might not need to run or might run very slowly. If the
temperature is higher than 50°C, the fans need to throttle up.
The challenge presented by any thermal design is finding the
right settings to suit the system’s fan control solution. This can
involve designing for the worst case, followed by weeks of
system thermal characterization and, finally, fan acoustic
optimization (for psycho-acoustic reasons).
TMIN OPERATING THIGH TTHERM TRANGE
POINT
05569-056
θTIMS
Dynamic TMIN control mode is operated by specifying the
operating zone temperatures required for the system. Remote 1
and Remote 2 channels have dedicated operating point registers.
This allows the system thermal solution to be broken down into
distinct thermal zones. For example, CPU operating temperature
is 70°C, VRM operating temperature is 80°C, and ambient
operating temperature is 50°C. The ADT7462 dynamically
alters the control solution to maintain each zone temperature as
close as possible to its target operating point.
PWM DUTY CYCLE
θSA
HEAT
SINK
Getting the most benefit from the automatic fan control mode
involves characterizing the system to find the best TMIN and
TRANGE settings for the control loop and the best PWMMIN value
for the quietest fan speed setting. Using the ADT7462’s dynamic
TMIN control mode, however, shortens the characterization time
and alleviates tweaking the control loop settings, because the
device can self-adjust during system operation.
Figure 66. Dynamic TMIN Control Loop
Table 28 provides a brief description of each parameter.
Table 28. TMIN Control Loop Parameters
Parameter
TLOW
THIGH
TMIN
Operating
Point
TTHERM
TRANGE
Rev. 0 | Page 48 of 92
Description
If the temperature drops below the TLOW limit,
an error flag is set in a status register and an
SMBALERT interrupt can be generated.
If the temperature exceeds the THIGH limit, an error
flag is set in a status register and an SMBALERT
interrupt can be generated.
The temperature at which the fan turns on under
automatic fan speed control.
The maximum target temperature for a particular
temperature zone. The system attempts to
maintain system temperature around the
operating point by adjusting the TMIN parameter
of the control loop.
If the temperature exceeds this critical limit, the
fans can be run at 100% for maximum cooling.
Programs the PWM duty cycle vs. temperature
control slope.
ADT7462
DYNAMIC TMIN CONTROL PROGRAMMING
Because the dynamic TMIN control mode is a basic extension of
the automatic fan control mode, the automatic fan control mode
parameters should be programmed first (see Step 1—Configuring
the MUX through Step 8—Operating Points for Temperature
Channels). Then proceed with dynamic TMIN control mode
programming.
STEP 8—OPERATING POINTS FOR TEMPERATURE
CHANNELS
The operating point for each temperature channel is the optimal
temperature for that thermal zone. The hotter each zone is
allowed to be, the quieter the system, because the fans are not
required to run as fast. The ADT7462 increases or decreases fan
speeds as necessary to maintain the operating point temperature,
allowing for system-to-system variation and removing the need
for worst-case design. If a sensible operating point value is
chosen, any TMIN value can be selected in the system characterization. If the TMIN value is too low, the fans run sooner than
required, and the temperature is below the operating point. In
response, the ADT7462 increases TMIN to keep the fans off
longer and to allow the temperature zone to get closer to the
operating point. Likewise, too high a TMIN value causes the
operating point to be exceeded, and in turn, the ADT7462
reduces TMIN to turn the fans on sooner to cool the system.
Programming the Operating Point Registers
There are two operating point registers, one for the Remote 1
temperature channel and one for the Remote 2 temperature
channel. These 8-bit registers allow the operating point
temperatures to be programmed with 1°C resolution.
Operating Point Registers
Register 0x5A, Remote 1 Operating Point = 0xA4 (100°C default)
Register 0x5B, Remote 2 Operating Point = 0xA4 (100°C default)
Operating Point Hysteresis Register
The operating point hysteresis register sets the value below the
operating point at which TMIN begins to reduce.
Register 0x64, Bits [7:4], Operating Point Hysteresis = 0x40
(4°C default)
How Dynamic TMIN Control Works
The basic premise is as follows:
1.
Set the target temperature for the temperature zone, which
could be, for example, the Remote 1 thermal diode. This value
is programmed to the Remote 1 operating temperature register.
2.
As the temperature in that zone rises toward and exceeds
the operating point temperature minus hysteresis, TMIN is
reduced, and fan speed increases.
3.
As the temperature drops below the low limit value, TMIN is
increased, and the fan speed is reduced.
Short Cycle and Long Cycle
The ADT7462 implements two loops: a short (or decrease)
cycle and a long (or increase) cycle. The short cycle takes place
every n monitoring cycles. The long cycle takes place every 2n
monitoring cycles. The value of n is programmable for each
temperature channel. The bits are located at the following
register locations:
Dynamic TMIN Control Register 2 (0x0C)
Remote 1 = CYR1 = Bits [2:0]
Remote 2 = CYR2 = Bits [5:3]
Table 29. Cycle Bit Assignments
Code
000
001
010
011
100
101
110
111
Short Cycle
8 cycles
16 cycles
32 cycles
64 cycles
128 cycles
256 cycles
512 cycles
1024 cycles
1 sec
2 sec
4 sec
8 sec
16 sec
32 sec
64 sec
128 sec
Long Cycle
16 cycles
32 cycles
64 cycles
128 cycles
256 cycles
512 cycles
1024 cycles
2048 cycles
2 sec
4 sec
8 sec
16 sec
32 sec
64 sec
128 sec
256 sec
The cycle time must be chosen carefully. A long cycle time
means that TMIN is updated less often. If your system has very
fast temperature transients, the dynamic TMIN control loop is
always lagging. If you choose a cycle time that is too fast, the
full benefit of changing TMIN is not realized and needs to change
again on the next cycle. In effect, it is overshooting. It is necessary
to carry out some calibration to identify the most suitable
response time.
Figure 67 shows the steps taken during the short cycle.
STEP 9—HIGH AND LOW LIMITS FOR
TEMPERATURE CHANNELS
WAIT n
MONITORING
CYCLES
The low limit defines the temperature at which the TMIN value
starts to be increased, if temperature falls below this value. This
has the net effect of reducing the fan speed, allowing the system
to get hotter. An interrupt can be generated when the temperature drops below the low limit.
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
OPERATING
POINT
TEMPERATURE
OP1
PREVIOUS
TEMPERATURE
MEASUREMENT
T1 (n – 1)
IS T1(n) >
(OP1 – HYS)
NO
DO NOTHING
YES
IS T1(n) – T1(n – 1)
≤ 0.25°C
YES
DO NOTHING
(SYSTEM
COOLING IS OFF
OR CONSTANT)
Rev. 0 | Page 49 of 92
IS T1(n) – T1(n – 1) = 0.5 – 0.75°C
IS T1(n) – T1(n – 1) = 1.0 – 1.75°C
IS T1(n) – T1(n – 1) > 2.0°C
DECREASE T MIN BY 1°C
DECREASE T MIN BY 2°C
DECREASE T MIN BY 4°C
Figure 67. Short Cycle Steps
05569-058
NO
The high limit should be set above the operating point but
below the critical THERM point. An interrupt can be generated
when the temperature rises above the high limit.
ADT7462
Because neither the operating point minus the hysteresis
temperature nor the low temperature limit has been exceeded,
the TMIN value is not adjusted, and the fan runs at a speed
determined by the fixed TMIN and TRANGE values defined in the
automatic fan speed control mode.
Figure 68 shows the steps taken during the long cycle.
WAIT 2n
MONITORING
CYCLES
OPERATING
POINT
TEMPERATURE
OP1
IS T1(n) > OP1
YES
DECREASE T MIN
BY 1°C
Example 2: Operating Point Exceeded; TMIN Reduced
When the measured temperature is below the operating point
temperature minus the hysteresis, TMIN remains the same. Once
the temperature exceeds the operating temperature minus the
hysteresis (OP − Hyst), TMIN starts to decrease as illustrated in
Figure 70. This occurs during the short cycle (see Figure 67).
The rate at which TMIN decreases depends on the programmed
value of n. It also depends on how much the temperature has
increased between this monitoring cycle and the last monitoring
cycle; that is, if the temperature has increased by 1°C, then TMIN
is reduced by 2°C. Decreasing TMIN has the effect of increasing
the fan speed, thus providing more cooling to the system.
NO
IS T1(n) < LOW TEMP LIMIT
AND
TMIN < HIGH TEMP LIMIT YES
AND
TMIN < OP1
AND
T1(n) > TMIN
NO
INCREASE
TMIN BY 1°C
DO NOT
CHANGE
05569-059
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
Figure 68. Long Cycle Steps
The following examples illustrate some of the circumstances
that might cause TMIN to increase, decrease, or stay the same.
Example 1: Normal Operation—No TMIN Adjustment
1. If measured temperature never exceeds the programmed
operating point minus the hysteresis temperature, then
TMIN is not adjusted; that is, it remains at its current setting.
If measured temperature never drops below the low
temperature limit, TMIN is not adjusted.
Once the temperature exceeds the operating temperature, the
long cycle causes TMIN to be reduced by 1°C every long cycle
while the temperature remains above the operating temperature.
This takes place in addition to the decrease in TMIN that would
occur due to the short cycle. In Figure 69, because the
temperature is increasing at a rate ≤0.25°C per short cycle, no
reduction in TMIN takes place during the short cycle.
THERM LIMIT
HIGH TEMP
LIMIT
OPERATING
POINT
HYSTERESIS
ACTUAL
TEMP
LOW TEMP
LIMIT
TMIN
Figure 69. Temperature Between the Operating Point
and the Low Temperature Limit
05569-060
2.
If the temperature is slowly increasing only in the range (OP −
Hyst), that is, ≤0.25°C per short monitoring cycle, then TMIN
does not decrease. This allows small changes in temperature in
the desired operating zone without changing TMIN. The long
cycle makes no change to TMIN in the temperature range (OP −
Hyst), because the temperature has not exceeded the operating
temperature.
Once the temperature falls below the operating temperature,
TMIN stays the same. Even when the temperature starts to
increase slowly, TMIN stays the same, because the temperature
increases at a rate of ≤0.25°C per cycle.
Rev. 0 | Page 50 of 92
ADT7462
THERM
LIMIT
HIGH TEMP
LIMIT
OPERATING
POINT
HYSTERESIS
ACTUAL
TEMP
NO CHANGE IN TMIN HERE
DUE TO ANY CYCLE BECAUSE
T1(n) – T1 (n – 1) ≤ 0.25°C
AND T1(n) < OP = > TMIN
STAYS THE SAME
TMIN
LOW TEMP
LIMIT
DECREASE HERE DUE TO
LONG CYCLE ONLY
T1(n) – T1 (n – 1) ≤ 0.25°C
AND T1(n) > OP = > TMIN
DECREASES BY 1°C
EVERY LONG CYCLE
05569-061
DECREASE HERE DUE TO
SHORT CYCLE ONLY
T1(n) – T1 (n – 1) = 0.5°C
OR 0.75°C = > TMIN
DECREASES BY 1°C
EVERY SHORT CYCLE
Figure 70. Effect of Exceeding Operating Point Minus Hysteresis Temperature
When the temperature drops below the low temperature limit,
TMIN may increase, as shown in Figure 71. Increasing TMIN has
the effect of running the fan more slowly and, therefore, more
quietly. The long cycle diagram in Figure 68 shows the conditions
that need to be true for TMIN to increase. Here is a quick summary
of those conditions and the reasons they need to be true.
Figure 71 shows how TMIN increases when the current
temperature is above TMIN and below the low temperature limit,
and TMIN is below the high temperature limit and below the
operating point. Once the temperature rises above the low
temperature limit, TMIN stays the same.
THERM
LIMIT
HIGH TEMP
LIMIT
TMIN may increase, if
OPERATING
POINT
The measured temperature has fallen below the low
temperature limit. This means the user must choose the low
limit carefully. It should not be so low that the temperature
never falls below it, because TMIN would never increase and
the fans would run faster than necessary.
TMIN is below the high temperature limit. TMIN is never allowed
to increase above the high temperature limit. As a result, the
high limit should be sensibly chosen, because it determines
how high TMIN can go.
TMIN is below the operating point temperature. TMIN should never
be allowed to increase above the operating point temperature,
because the fans do not switch on until the temperature rises
above the operating point.
• The temperature is above TMIN. The dynamic TMIN control is
turned off below TMIN.
LOW TEMP
LIMIT
HYSTERESIS
ACTUAL
TEMP
TMIN
05569-062
Example 3: Temperature Below Low Limit, TMIN Increased
Figure 71. Increasing TMIN for Quieter Operation
Example 4: Preventing TMIN from Reaching Full Scale
Because TMIN is dynamically adjusted, it is undesirable for TMIN
to reach full scale (191°C), because the fan would never switch
on. As a result, TMIN is allowed to vary only within a specified
range.
• The lowest possible value for TMIN is −64°C .
• TMIN cannot exceed the high temperature limit.
• If the temperature is below TMIN, the fan is switched off or
is running at minimum speed, and dynamic TMIN control
is disabled.
Rev. 0 | Page 51 of 92
ADT7462
THERM
LIMIT
OPERATING
POINT
LOW TEMP
LIMIT
The operating point for the processor can be determined by
allowing the current temperature to be copied to the operating
point register when the PROCHOT output pulls the THERM
input low on the ADT7462. This gives the maximum
temperature at which the Pentium 4 can run before clock
modulation occurs.
HYSTERESIS
ACTUAL
TEMP
HIGH TEMP
LIMIT
TMIN PREVENTED
FROM INCREASING
Enabling the THERM Trip Point as the Operating Point
05569-063
TMIN
Figure 72. TMIN Adjustments Limited by High Temperature Limit
Enabling Dynamic TMIN Control Mode
Bits [1:0] of Dynamic TMIN Control Register 1 (0x0B)
enable/disable dynamic TMIN control on the temperature
channels (see Table 43).
Dynamic TMIN Control Register 1 (0x0B)
Bit (1) Remote 2 En = 1 enables dynamic TMIN control on the
Remote 2 temperature channel. The chosen TMIN value is
dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone.
Remote 2 En = 0 disables dynamic TMIN control. The TMIN value
chosen is not adjusted and the channel behaves as described in
the Automatic Fan Control Overview section.
Bit (0) Remote 1 En = 1 enables dynamic TMIN control on the
Remote 1 temperature channel. The chosen TMIN value is
dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone.
Remote 1 En = 0 disables dynamic TMIN control. The TMIN value
chosen is not adjusted, and the channel behaves as described in
the Automatic Fan Control Overview section.
STEP 10—MONITORING THERM
Using the operating point limit ensures that the dynamic TMIN
control mode is operating in the best possible acoustic position,
while ensuring that the temperature never exceeds the
maximum operating temperature. Using the operating point
limit allows TMIN to be independent of system-level issues
because of its self-corrective nature. In PC design, the operating
point for the chassis is usually the worst-case internal chassis
temperature.
Bits [5:2] of Dynamic TMIN Control Register 1 (0x0B)
enable/disable THERM monitoring to program the operating
point. Table 43 details how the remote temperatures can be
copied into the operating point registers on a THERM
assertion. Setting these bits to 1 uses the remote temperature as
the operating point temperature, overwriting the programmed
operating point value in the event of a THERM assertion.
Setting these bits to 0 ignores a THERM assertion, and the
operating point register remains at the programmed value.
ENHANCING SYSTEM ACOUSTICS
Automatic fan speed control mode reacts instantaneously to
changes in temperature; that is, the PWM duty cycle responds
immediately to temperature change. Any impulses in temperature
can cause an impulse in fan noise. For psycho-acoustic reasons,
the ADT7462 can prevent the PWM output from reacting
instantaneously to temperature changes. Enhanced acoustic
mode controls the maximum change in PWM duty cycle at a
given time. The objective is to prevent the fan from cycling up
and down, annoying the user.
Acoustic Enhancement Mode Overview
Figure 73 gives a top-level overview of the automatic fan control
circuitry on the ADT7462 and shows where acoustic enhancement
fits in. Acoustic enhancement is intended as a post-design tweak
made by a system or mechanical engineer evaluating best settings for the system. Having determined the optimal settings for
the thermal solution, the engineer can adjust the system acoustics.
The goal is to implement a system that is acoustically pleasing
without causing user annoyance due to fan cycling. It is
important to realize that although a system might pass an
acoustic noise requirement specification (for example, 36 dB),
if the fan is annoying, it fails the consumer test.
The optimal operating point for the processor is determined by
monitoring the thermal monitor in the Intel Pentium 4
processor. To do this, the PROCHOT output of the Pentium 4 is
connected to the THERM input of the ADT7462.
Rev. 0 | Page 52 of 92
ADT7462
ACOUSTIC
ENHANCEMENT
PWM
MIN
100%
PWM
CONFIG
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
0%
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
MUX
TMIN
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
0%
PWM
MIN
100%
TRANGE
TACHOMETER 1
MEASUREMENT
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
PWM
GENERATOR
PWM
CONFIG
PWM
GENERATOR
PWM
CONFIG
PWM1
TACH1
CPU FAN SINK
PWM2
TACH2
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
05569-064
THERMAL CALIBRATION
Figure 73. Acoustic Enhacement Smoothes Fan Speed Variations Under Automatic Fan Speed Control
Approaches to System Acoustic Enhancement
There are two different approaches to implementing system
acoustic enhancement: temperature-centric and fan-centric.
The temperature-centric approach involves smoothing transient
temperatures as they are measured by a temperature source (for
example, Remote 1 temperature). The temperature values used
to calculate the PWM duty cycle values are smoothed, reducing
fan speed variation. However, this approach causes an inherent
delay in updating fan speed and causes the thermal characteristics
of the system to change. It also causes the system fans to stay on
longer than necessary, because the fan’s reaction is merely
delayed. The user has no control over noise from different fans
driven by the same temperature source. Consider, for example,
a system in which control of a CPU cooler fan (on PWM1) and a
chassis fan (on PWM2) use Remote 1 temperature. Because the
Remote 1 temperature is smoothed, both fans are updated at
exactly the same rate. If the chassis fan is much louder than the
CPU fan, there is no way to improve its acoustics without
changing the thermal solution of the CPU cooling fan.
The fan-centric approach to system acoustic enhancement
controls the PWM duty cycle, driving the fan at a fixed rate
(for example, 6%). Each time the PWM duty cycle is updated, it
is incremented by a fixed 6%. As a result, the fan ramps
smoothly to its newly calculated speed. If the temperature starts
to drop, the PWM duty cycle immediately decreases by 6% at
every update. Therefore, the fan ramps smoothly up or down
without inherent system delay.
Consider, for example, controlling the same CPU cooler fan (on
PWM1) and chassis fan (on PWM2) using Remote 1 temperature.
The TMIN and TRANGE settings have already been defined in
automatic fan speed control mode; that is, thermal characterization of the control loop has been optimized. Now the chassis
fan is noisier than the CPU cooling fan. Using the fan-centric
approach, PWM2 can be placed into acoustic enhancement
mode independently of PWM1. The acoustics of the chassis fan
can, therefore, be adjusted without affecting the acoustic
behavior of the CPU cooling fan, even though both fans are
controlled by Remote 1 temperature. The fan-centric approach
is how acoustic enhancement works on the ADT7462.
Enabling Acoustic Enhancement for Each PWM Output
Enhance Acoustics Register 1 (0x1A)
Bit 0 = EA1_En = 1 enables acoustic enhancement on PWM1
output.
Bit 1 = EA2_En = 1 enables acoustic enhancement on PWM2
output.
Enhance Acoustics Register 2 (0x1B)
Bit 0 = EA3_En = 1 enables acoustic enhancement on PWM3
output.
Bit 1 = EA4_En = 1 enables acoustic enhancement on PWM4
output.
Rev. 0 | Page 53 of 92
ADT7462
Effect of Ramp Rate on Enhanced Acoustic Mode
The PWM signal driving the fan has a period, T, given by the
PWM drive frequency, f, because T = 1/f. For a given PWM
period, T, the PWM period is subdivided into 255 equal time
slots. One time slot corresponds to the smallest possible
increment in the PWM duty cycle. A PWM signal of 33% duty
cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3
× 255 time slots. Therefore, a 33% PWM duty cycle corresponds
to a signal that is high for 85 time slots and low for 170 time
slots.
PWM_OUT
33% DUTY
CYCLE
85
TIME SLOTS
STEP 11—RAMP RATE FOR ACOUSTIC
ENHANCEMENT
The optimal ramp rate for acoustic enhancement can be found
through system characterization after the thermal optimization
has been finished. The effect of each ramp rate should be logged, if
possible, to determine the best setting for a given solution.
Enhanced Acoustic Register 1 (0x1A)
Bits [4:2] RR1 select the ramp rate for PWM1.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots =3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
170
TIME SLOTS
05569-065
PWM OUTPUT
(ONE PERIOD)
= 255 TIME SLOTS
Figure 74. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable
from 1 to 8. The ramp rates are discrete time slots. For example,
if the ramp rate is 8, then eight time slots are added to the PWM
high duty cycle each time the PWM duty cycle needs to be
increased. If the PWM duty cycle value needs to be decreased, it
is decreased by eight time slots. Figure 75 shows how the
enhanced acoustics mode algorithm operates.
Bits [7:5] RR2 select the ramp rate for PWM2.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots =3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
Enhanced Acoustic Register 2 (0x1B)
Bits [4:2] RR3 selects the ramp rate for PWM3.
IS NEW PWM
VALUE >
PREVIOUS
VALUE?
NO
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
INCREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
05569-066
YES
Figure 75. Enhanced Acoustics Algorithm
The enhanced acoustics mode algorithm calculates a new PWM
duty cycle based on the temperature measured. If the new
PWM duty cycle value is greater than the previous PWM value,
the previous PWM duty cycle value is incremented by either 1,
2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of
the enhance acoustics registers. If the new PWM duty cycle
value is less than the previous PWM value, the previous PWM
duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots.
Each time the PWM duty cycle is incremented or decremented,
its value is stored as the previous PWM duty cycle for the next
comparison.
Bits [7:5] RR4 select the ramp rate for PWM4.
A ramp rate of 1 corresponds to one time slot, which is 1/255 of
the PWM period. In enhanced acoustics mode, incrementing or
decrementing by 1 changes the PWM output by 1/255 × 100%.
Rev. 0 | Page 54 of 92
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
ADT7462
Another way to view the ramp rates is to measure the time it
takes for the PWM output to ramp up from 0% to 100% duty
cycle for an instantaneous change in temperature. This can be
tested by putting the ADT7462 into manual mode and changing
the PWM output from 0% to 100% PWM duty cycle. The PWM
output takes 35 seconds to reach 100% when a ramp rate of
1 time slot is selected.
Figure 78 shows the PWM output response for a ramp rate of 2.
In this instance, the fan took about 17.6 seconds to reach full
running speed.
140
120
RTEMP (°C)
120
100
100
80
Figure 76 shows remote temperature plotted against PWM duty
cycle for enhanced acoustics mode. The ramp rate is set to 48,
which corresponds to the fastest ramp rate. Assume that a new
temperature reading is available every 115 ms. With these
settings, it takes approximately 0.76 seconds to go from 33%
duty cycle to 100% duty cycle (full speed). Even though the
temperature increases very rapidly, the fan ramps up to full
speed gradually.
80
40
40
0
TIME (s)
120
0
17.6
05569-069
20
20
0
140
60
PWM DUTY CYCLE (%)
60
Figure 78. Enhanced Acoustics Mode with Ramp Rate = 2
RTEMP (°C)
120
100
Figure 79 shows how the control loop reacts to temperature
with the slowest ramp rate. The ramp rate is set to 1, while all
other control parameters remain the same. With the slowest
ramp rate selected, it takes 35 seconds for the fan to reach full
speed.
100
80
80
60
60
PWM CYCLE (%)
40
140
120
40
RTEMP (°C)
20
0
0.76
TIME (s)
100
80
80
Figure 76. Enhanced Acoustics Mode with Ramp Rate = 48
60
40
20
20
0
140
TIME (s)
35
0
Figure 79. Enhanced Acoustics Mode with Ramp Rate = 1
RTEMP (°C)
120
100
As Figure 76 to Figure 79 show, the rate at which the fan reacts
to temperature change is dependent on the ramp rate selected in
the enhanced acoustics registers. The higher the ramp rate, the
faster the fan reaches the newly calculated fan speed.
100
80
PWM DUTY CYCLE (%)
80
60
60
40
40
20
20
TIME (s)
4.4
0
Figure 77. Enhanced Acoustics Mode with Ramp Rate = 8
05569-068
0
0
40
0
120
60
PWM DUTY CYCLE (%)
Figure 77 shows how changing the ramp rate from 48 to 8
affects the control loop. The overall response of the fan is
slower. Because the ramp rate is reduced, it takes longer for the
fan to achieve full running speed. In this case, it takes
approximately 4.4 seconds for the fan to reach full speed.
05569-070
0
0
120
100
05569-067
20
Figure 80 shows the behavior of the PWM output as temperature
varies. As the temperature increases, the fan speed ramps up.
Small drops in temperature do not affect the ramp-up function,
because the newly calculated fan speed is still higher than the
previous PWM value. Enhanced acoustics mode allows the
PWM output to be made less sensitive to temperature
variations. This is dependent on the ramp rate selected and
programmed into the enhanced acoustics registers.
Rev. 0 | Page 55 of 92
ADT7462
90
The freewheeling test procedure is as follows:
80
1.
PWM1 and PWM2 go to full speed, and PWM3 and PWM4
are switched off.
2.
After the spin-up time of PWM1 and PWM2 has elapsed,
the speed of Fan 1, Fan 2, Fan 3, and Fan 4 is measured.
3.
Once the speed of Fan 1 and Fan 2 is measured, PWM1 is
switched off and PWM3 is spun up. After the spin-up time for
PWM3 has elapsed, the speed of Fan 5 and Fan 6 is measured.
4.
After the speed of Fan 3 and Fan 4 is measured, PWM2 is
switched off and PWM4 is switched on. After the spin-up
time of PWM4 has elapsed, the speed of Fan 7 and Fan 8
is measured.
5.
Once the speed of all eight fans has been measured, the TACH
and PWM configurations go back to their previous values.
PWM DUTY CYCLE (%)
70
60
50
RTEMP (°C)
40
30
20
05569-071
10
0
Figure 80. How Fan Reacts to Temperature Variations
in Enhanced Acoustics Mode
Slower Ramp Rates
a. Fans must be in continuous mode for the freewheeling
test; that is, the dc bits must be set (Register 0x08).
The ADT7462 can be programmed for much longer ramp times
by slowing the ramp rates. Each ramp rate can be slowed by a
factor of 4.
b. To enable the freewheeling test, set the freewheeling test
enable register (0x1E) to a non-zero value. Set Bit 0 to 1
to enable the freewheeling test for Fan 1, and set Bit 1 for
Fan 2, all the way to Bit 7 for Fan 8. The freewheeling test
enable register should be programmed after the fans
present register is programmed. If the fans present register
is programmed first, then the values in the two registers do
not match, and the ADT7462 assumes that a fan is missing.
PWM1 Configuration Register (0x21)
PWM2 Configuration Register (0x22)
PWM3 Configuration Register (0x23)
PWM4 Configuration Register (0x24)
Setting Bit 3 (the SLOW bit) to 1 in the PWM1 to PWM4
registers slows the ramp rate for PWM4 by 4.
The following registers must be programmed for the fan
freewheeling test:
FAN FREEWHEELING TEST MODE
Fans Present Register (0x1D)
Set Bit 0 to 1 when a fan is connected to TACH1.
Set Bit 1 to 1 when a fan is connected to TACH2.
Set Bit 2 to 1 when a fan is connected to TACH3.
Set Bit 3 to 1 when a fan is connected to TACH4.
Set Bit 4 to 1 when a fan is connected to TACH5.
Set Bit 5 to 1 when a fan is connected to TACH6.
Set Bit 6 to 1 when a fan is connected to TACH7.
Set Bit 7 to 1 when a fan is connected to TACH8.
The fan freewheeling test mode is intended to diagnose whether
fans connected to the ADT7462 are working properly. It is
particularly useful in the situation where fans coupled in the
duct can affect the airflow of the other fan. If one fan has failed,
it may not be apparent, as moving air from other fans can cause
air to flow through the faulty fan, which in turn can cause the
faulty fan to rotate.
The fan freewheeling test is most useful in a system using
primary and redundant setup. In such a system the following
setup is recommended. The primary fans are Fan 1, Fan 2, Fan 3,
and Fan 4. The redundant fans are Fan 5, Fan 6, Fan 7, and Fan 8.
In this setup, each primary and redundant fan can be driven
separately because they are driven by different PWMs.
Set Bit 0 to 1 to enable the freewheeling test for Fan 1.
Set Bit 1 to 1 to enable the freewheeling test for Fan 2.
Set Bit 2 to 1 to enable the freewheeling test for Fan 3.
Set Bit 3 to 1 to enable the freewheeling test for Fan 4.
Set Bit 4 to 1 to enable the freewheeling test for Fan 5.
Set Bit 5 to 1 to enable the freewheeling test for Fan 6.
Set Bit 6 to 1 to enable the freewheeling test for Fan 7.
Set Bit 7 to 1 to enable the freewheeling test for Fan 8.
PWM 2
FAN 1
FAN 2
FAN 3
FAN 4
TACH CCT 1
TACH CCT 2
TACH CCT 3
TACH CCT 4
FAN 5
FAN 6
FAN 7
FAN 8
PWM 3
Fan Freewheeling Test Register (0x1C)
PWM 4
Figure 81. Fan Freewheeling Test Mode Setup
05569-072
PWM 1
Fan Freewheeling Test Enable Register (0x1E)
Both the fans present register (0x1D) and freewheeling test enable
register (0x1E) should be programmed before setting the
relevant bits in the freewheeling test register (0x1C). The host
fan status register (0xBD) should be read directly after completion
of the test.
Rev. 0 | Page 56 of 92
ADT7462
THERM I/O OPERATION
THERM Input
This section describes the operation of THERM1 and THERM2.
Pin 28 and Pin 29 can both be configured as THERM inputs or
outputs.
To configure THERM as an input, the Enable_THERM1_Timer
bit (Bit 0) in the THERM1 configuration register (0x0E) and the
Enable_THERM2_Timer bit (Bit 0) in the THERM2 configuration
register (0x0F) must be set to Logic 1. The ADT7462 can then
be used to detect when the THERM pins are asserted low. The
THERM pins can be connected to a trip point temperature
sensor or to the PROCHOT output of a CPU.
THERM Output
THERM is not enabled as an output by default on power-up,
but it can be enabled by setting the appropriate bits in
Register 0x0E (THERM1 configuration register) and
Register 0x0F (THERM2 configuration register). THERM1 and
THERM2 can be configured to assert whenever a specific
channel exceeds the specified THERM limit (see Table 30).
With processor core voltages reducing all the time, the threshold
for the AGTL+ PROCHOT output also reduces as new
processors become available.
Table 30. THERM O/P Channel Select and Limits
Channel
Enable
Configuration
THERM1,
THERM2,
Register 0x0E Register 0x0F
Bit 1 = 1
Bit 1 = 1
Bit 2 = 1
Bit 2 = 1
Bit 3 = 1
Bit 3 = 1
Bit 4 = 1
Bit 4 = 1
Local
Remote 1
Remote 2
Remote 3
Because the THERM input is typically an AGTL+ input, the
thresholds can be referenced to VCCP. By setting Bit 4 of
Configuration Register 3 (0x03) to 1, the THERM threshold is
2/3 × VCCP, the correct threshold for an AGTL+ signal. The
THERM assert bits in Host Thermal Status Register 2 (0xB9)
are set to Logic 1 whenever the THERM input is asserted low.
The THERM state bits in Host Thermal Status Register 2 (0xB9)
indicate that a high-to-low transition has taken place on the
THERM pin.
Limit Registers
THERM1
THERM2
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
As an output, THERM is asserted low to signal that the measured
THERM temperature has exceeded preprogrammed THERM
temperature limits. The output is automatically pulled high again
when the temperature falls below the (THERM − Hysteresis) limit.
The value of hysteresis for each channel is programmable in
Register 0x54 and Register 0x55, where 1 LSB = 1°C, and the
maximum hysteresis for each channel is 15°C.
THERM Timer
The ADT7462 can also measure assertion times on the THERM
inputs as a percentage of a timer window. The timer window for
the THERM1 input is programmed using Bits [4:2] of the
THERM configuration register (0x0D). The timer window for
the THERM2 input is programmed using Bits [7:5] of the THERM
configuration register (0x0D). Values of between 0.25 seconds
and 8 seconds are programmable (see Table 31).
TEMPERATURE
100°C
90°C
THERM LIMIT
80°C
HIGH TEMP LIMIT
70°C
Table 31. THERM Timer Window
THERM LIMIT–HYSTERESIS
60°C
50°C
40°C
RESET BY MASTER
ALERT
4
2
05569-073
1
THERM
3
Figure 82. THERM Behavior
Setting the THERM boost bits, Bit 0 and Bit 1, to logic zero
(default setting) in the THERM configuration register (0x0D),
sets the fans to full speed on an internal THERM event.
Code
000
001
010
011
100
101
110
111
Rev. 0 | Page 57 of 92
THERM Timer Window
0.25 sec
0.5 sec
1 sec
2 sec
4 sec
8 sec
8 sec
8 sec
ADT7462
The assertion time as a percentage of the time window is stored
in the THERM % on-time registers. This is a cumulative sum of
the percentage of time during the THERM timer window that
THERM is asserted. The % on-time and associated timer limit
registers are listed in Table 32.
Table 32. THERM On-Time and Timer Limit Register
Channel
THERM1
THERM2
% On-Time Register
0xAE
0xAF
% Timer Limit Register
0x80
0x81
Once the measured percentage exceeds the corresponding percentage limit, the THERM % bit in Thermal Status Register 2
gets asserted, and an ALERT is generated (that is, if the mask bit
is not set). If the limit is set to 0x00, an ALERT is generated on
the first assertion. If the Limit is set to FFh, an ALERT is never
generated because 0xFF corresponds to the THERM input
being asserted all the time.
When THERM is configured as an input only, setting Bits [1:4]
of the THERM zone in THERM1 configuration register (0x0E)
and THERM2 configuration register (0x0F) allows Pin 7 to
operate as an I/O.
THERM % Limit Register
The THERM % limit is programmed to Register 0x80 and
Register 0x81. If the THERM is asserted for longer than the
programmed percentage limit, then an ALERT is generated.
The limit is programmed as a percentage of the chosen THERM
timer window.
Example:
The THERM timer window is eight seconds, and an ALERT
should be generated if the THERM is asserted for more than
one second.
%Limit =
1
× 100 = 12.5%
8
The THERM % limit register is an 8 bit register.
0x00 = 0% 0xFF = 100%
Therefore, 1 LSB = 0.39%
12.5%
= 32dec = 0 x 20 = 00100000
0.39%
Once the time window has elapsed, if the THERM limit has
been exceeded, then an ALERT is generated.
Rev. 0 | Page 58 of 92
ADT7462
GENERAL-PURPOSE I/O PINS
The ADT7462 has eight open drain GPIO pins. GPIO1 to
GPIO4 can be configured to enable event driven outputs
(EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO
functionality is enabled. Two other GPIOs (GPIO 7 and GPIO 8)
are standard GPIO pins that are dedicated to general-purpose
logic input/output.
When the pin is configured as an output, this bit is automatically
masked to prevent the data written to the status bit from causing
an interrupt. When configured as inputs, the GPIO pins can be
connected to external interrupt sources such as temperature
sensors with digital output.
Each GPIO pin has five data bits associated with it: three bits in
a GPIO configuration register (0x09 and 0x0A), one in the
GPIO status register (0xBF), and one in the GPIO mask register
(0x38).
SETTING a direction bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin an output.
The ADT7462 has the added functionality that the assertion of
one of the four GPIOs (GPIO1 to GPIO4) can be used to latch
one of the two EDOs high or low. The ADT7462 has two EDO
event mask registers (0x37 and 0x38): one mask for each EDO.
See Table 33 for an explanation of event mask register
functionality.
CLEARING the direction bit to 0 makes the corresponding
GPIO an input.
The polarity of the EDOs is set in the GPIO configuration
registers (0x09 and 0x0A).
SETTING a polarity bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin active high.
SETTING a polarity bit to 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.
CLEARING the polarity bit to 0 makes the corresponding
GPIO active low.
CLEARING the polarity bit to 0 makes it active low.
EDO CIRCUITRY
GPIO1
When a GPIO pin is configured as an input, the corresponding
bit in the GPIO status registers is read only, and it is set when
the input is asserted (“asserted” can be high or low, depending
on the setting of the polarity bit).
EDO (GPIO 5)
GPIO2
LATCH
GPIO3
EVENT
MASK
EDO (GPIO 6)
05569-074
GPIO4
When a GPIO pin is configured as an output, the corresponding
bit in the GPIO status registers becomes read/write. Setting this
bit then asserts the GPIO output. (Again, “asserted” can be high
or low, depending on the setting of the polarity bit.) The effect
of a GPIO status register bit on the INT output can be masked
by setting the corresponding bit in one of the GPIO mask
registers.
Figure 83. EDO Circuit
Bits [7:5] of each event mask register allow the EDO output to be
driven high or low (depending on the polarity bit of the
configuration register) and latched (depending on the EDO latch
bit of the configuration register), if the ADT7462 detects an
overtemperature, an over/undervoltage, or a fan failure condition.
Table 33. EDO Control (Mask) Register 0x37 and Register 0x38
Bit 7: Over/Under Voltage
0 = Drive
Output X
1 = Ignore Event
Bit 6: THERM
0 = Drive
Output X
1 = Ignore Event
Bit5: Fan Fail
0 = Drive
Output X
1 = Ignore Event
Bit 3
Bit 2
Bit 1
Bit 0
Behavior: What Drives and Latches Output X
(G = GPIO)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G4 or G3 or G2 or G1
G4 or G3 or G2
G4 or G2 or G1
G4 or G3
G4 or G2 or G1
G4 or G2
G4 or G1
G4
G3 or G2 or G1
G3 or G2
G3 or G1
G3
G2 or G1
G2
G1
GPIO events Ignored by Output X
Rev. 0 | Page 59 of 92
ADT7462
Table 33 shows that any of the four designated GPIO pins can
be used to set or reset anyone of the two EDO outputs.
2
Using this functionality, it is possible to have the ADT7462
drive LEDs or signals based on rules. For example, if a GPIO1
(power fail), a GPIO2 (overcurrent), or an overtemperature
condition occurs, EDO1 (power supply fault LED) can be
latched. This does not require software handling and makes the
part more autonomous.
OTHER DIGITAL INPUTS
The ADT7462 contains other specific digital inputs that can be
found on PC motherboards. These inputs can be monitored and
configured for actions to occur on their assertion.
VR_HOT inputs
Pin 25 and Pin 26 can be configured as VR_HOT inputs. These
are specific digital signals from the CPU voltage regulator that
indicate an overtemperature. On assertion of these inputs, the
relevant status bits are set in the Thermal Status Register 2
(Host Register 0xB9 or BMC Register 0xC1). Assertion of these
inputs can also be used to boost the fans to full speed, thus
providing emergency cooling in the event of VR overtemperature.
This is set using Bit 3 and Bit 4 of Configuration Register 2
(0x02). There is also an associated mask bit in Register 0x31 to
mask the assertion of these inputs from the ALERT output.
SCSI_TERM inputs
Pin 16 and Pin 20 can be configured as SCSI_TERM inputs. An
assertion on the SCSI_TERM is recorded in Bit 4 and Bit 5 of
Digital Status Register 1 (Host Register 0xBE or BMC register
0xC6). There is also an associated mask bit in Register 0x35 to
mask the assertion of these inputs from the ALERT output.
RESET I/O
The ADT7462 includes an active low reset pin (Pin 14). The
RESET pin can be both a reset input and output. RESET
monitors the VCC input to the ADT7462. At power-up, RESET
is asserted (pulled low) until 180 ms after the power supply has
risen above the supply threshold. A power-on reset initializes all
registers to the default values.
VCC
1V
180ms
05569-075
RESET
Figure 84. Operation of RESET Output on Power-Up
The RESET pin can also function as a reset input. Pulling this
pin low externally resets the ADT7462. The user should wait at
least 180 ms after power-up before doing a hardware reset. The
reset pulse width should be greater than 0.8 ms to ensure that a
reset is registered.
the registers are re-initialized to the default values. For example,
limit registers are not all restored to the default values. This can
be useful if the user needs to reset the part but does not want to
completely reprogram the device. The Register Map shows which
registers are reset. Locked registers are not restored to default
values by a hardware reset.
Note that if two ADT7462 devices are used in one system, the
RESET pins should not be connected together between devices.
Doing so would cause one device to reset the other on a poweron reset.
Software Reset
The ADT7462 can be reset in software by setting Bit 7 of
Configuration Register 0 (0x00). The code 0x6D must be written to
Register 0x7B before setting the software reset bit. This register is
cleared to the power-on default after the software reset.
Note that not all registers are restored to their default values on
a reset. The same registers are reset by a hardware and software
reset. The Register Map section shows a complete reference of
registers that are reset.
CHASSIS INTRUSION INPUT
The chassis intrusion input is an active high input intended for
detection and signaling of unauthorized tampering with the
system. When this input goes high, the event is latched in Bit 7
of the digital status register (0xBE), and an interrupt is generated.
The bit remains set until cleared by writing a 1 to CI reset, Bit 5
of Configuration Register 3 (0x03). The CI reset bit itself is
cleared by writing a 0 to it.
The CI circuit is powered from the VBATT voltage channel. Pin 26
must be configured to monitor VBATT and a battery connected in
order to monitor CI events. CI monitoring is disabled if the
measured VBATT value (0x93) is less than the lower voltage limit
(0x75) of Pin 26.
The CI input detects chassis intrusion events even when the
ADT7462 is powered off (provided battery voltage is applied to
VBATT) but does not immediately generate an interrupt. Once a
chassis intrusion event is detected and latched, an interrupt is
generated when the system is powered on.
The actual detection of chassis intrusion is performed by an
external circuit that detects, for example, when the cover has
been removed. A wide variety of techniques can be used for the
detection. For example:
•
A microswitch that opens or closes when the cover is removed
•
A reed switch operated by a magnet affixed to the cover
•
A hall-effect switch operated by a magnet affixed to the cover
•
A phototransistor that detects light when the cover is
removed.
A hardware reset differs from a power-on reset in that not all of
Rev. 0 | Page 60 of 92
ADT7462
POWER-UP SEQUENCE
6.
The power-up sequence of the ADT7462 is as follows:
1.
The temperature of the thermal diode connected to Pin 17
and Pin 18 (only dedicated thermal diode channel) is
monitored immediately on power-up of the ADT7462.
Ideally, the hottest zone should be connected to this channel
so protection is provided immediately on power-up.
2.
VCCP1 is also monitored immediately on power-up. VCCP
is typically connected to a main power rail. The switching
on of the VCCP rail gates the fan’s quiet start-up counter.
3.
VBATT is monitored immediately on power-up before the
setup complete bit (Register 0x01, Bit 5) is set. The chassis
intrusion circuit (CI) is powered from VBATT. If the measured
VBATT reading is lower than the lower limit (default =
0x80), the CI circuit is turned off.
4.
PWM1, PWM3, and PWM4 are not on dedicated pins.
Because these pins are shared with inputs, they are allowed
to float high on power-up. This means that if a fan is
connected to these pins, it spins at full speed on power-up.
5.
PWM2 is switched off by default (because this is a
dedicated pin). If no SMBus communication takes place
within 4.6 seconds of the VCCP rail switching on, this PWM
drive is driven to full speed. If SMBus communication
does take place, this pin behaves as programmed.
No temperature or voltage (other than VCCP1 and Diode 2
and VBATT) are monitored until the setup complete bit (Bit 5)
is set in Configuration Register 1 (0x01). This allows the
user to program the ADT7462 as required before
monitoring of all channels is enabled, thereby not
generating false ALERTs. The setup complete bit should
not be set until the device is fully configured for the
desired monitoring functions.
The following steps describe how to set up the ADT7462:
1.
Power up the device.
2.
Choose the best-suited easy configuration option for the
application, changing pin functions as required.
3.
Program all appropriate limits for monitored inputs.
Program device parameters, fan control parameters, mask
bits, and anything else required for the application.
4.
Set the complete bit. Do not set the complete bit until the
device is fully set up.
Rev. 0 | Page 61 of 92
ADT7462
XOR TREE TEST
The ADT7462 includes an XOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying
stimulus to the pins included in the XOR test, it is possible to detect opens or shorts on the system board. Figure 85 shows the signals
exercised in the XOR tree test. The XOR tree test is invoked by setting Bit 6 (XOR tree test) of Configuration Register 3 (0x03).
Note that the digital inputs must be selected on multifunctional pins for the XOR tree test mode. Pin 13 is the open drain output of the
XOR tree test.
PIN 1
PIN 25
PIN 2
PIN 3
PIN 26
PIN 4
PIN 27
PIN 7
PIN 28
PIN 8
PIN 29
PIN 16
PIN 31
PIN 20
PIN 32
PIN 13
05569-076
PIN 21
PIN 22
Figure 85. XOR Tree Test
Rev. 0 | Page 62 of 92
ADT7462
REGISTER MAP
Table 34. Register Map
Bit 6
VID
Bit 5
#Byte
Bit 4
#Byte
Bit 3
#Byte
Bit 2
#Byte
Bit 1
#Byte
Bit 0
#Byte
Default
0x20
SW
Reset
Yes
Lockable
Yes
R/W
Bit 7
SW
Reset
RDY
Lock
SC
DFS
ALERT
Res
Res
Mon
0x81
Yes
Yes
R/W
R/W
R/W
R/W
#FP
Res
T8E
Res
#FP
XOR
T7E
Res
FMS
CI_R
T6E
Res
VB2
TT
T5E
Res
VB1
VID_T
T4E
DC 4/8
Yes
Yes
Yes
Yes
THERM Configuration
P4
P8
Res
Ver
TW2
D3
D7
P2R2
CYR2
TW2
P3
P7
P2R2
CYR2
TW1
D2
D6
P1R2
CYR2
TW1
Fast
GPIO
T1E
DC
1/5
P1
P5
R1
CYR1
B1
Yes
Yes
Yes
Yes
D4
D8
Res
Res
TW2
Res
SCL
T2E
DC
2/6
D1
D5
R2
CYR1
B2
0x40
0x00
0x00
0xE0
R/W
R/W
R/W
R/W
R/W
PWM
SDA
T3E
DC
3/7
P2
P6
P1R1
CYR1
TW1
0x00
0x00
0x00
0x40
0x00
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Conf_THERM1
R/W
Res
Res
Res
R3
R2
R1
Local
T1TE
0x00
Yes
Yes
Conf_THERM2
R/W
Res
Res
Res
R3
R2
R1
Local
T2E
0x00
Yes
Yes
0x10
0x11
0x12
0x13
0x14
0x16
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x21
0x22
0x23
0x24
0x25
0x26
0x28
0x29
0x2A
0x2B
0x2C
0x30
0x31
0x32
0x33
Pin Config 1
Pin Config 2
Pin Config 3
Pin Config 4
Easy Config
EDO Enable
Attenuators 1 En
Attenuators 2 En
Enhance Acoustics 1
Enhance Acoustics 2
Fan Free Wheel Test
Fans Present
Fan Free Wheel Test En
PWM1 Config
PWM2 Config
PWM3 Config
PWM4 Config
PWM1, PWM2 Freq
PWM3, PWM4 Freq
PWM1 Min
PWM2 Min
PWM3 Min
PWM4 Min
PWM1 to PWM4 Max
Thermal Mask 1
Thermal Mask 2
Voltage Mask 1
Voltage Mask 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Pin 1
Pin 19
Pin 25
Pin 29
Op5
CS
Pin 15
Pin 28
RR1
RR3
Fan 5
F5P
Fan 5
Inv
Inv
Inv
Inv
F1
F3
4
4
4
4
4
R3
T2A
P15
P25
Pin 2
Pin 21
Pin 26
Pin 31
Op4
CS
Pin 13
Res
RR1
RR3
Fan 4
F4P
Fan 4
Slow
Slow
Slow
Slow
F1
F3
3
3
3
3
3
R2
T2%
+3.3V
P24
Pin 3
Pin 22
Pin 26
Pin 32
Op3
SC
Pin 8
Pin 25
RR1
RR3
Fan 3
F3P
Fan 3
Spin
Spin
Spin
Spin
F1
F3
2
2
2
2
2
R1
T1S
+12V3
Res
Pin 4
Pin 23
Pin 27
Res
Op2
EDO2
Pin 7
Pin 24
En2
En4
Fan 2
F2P
Fan 2
Spin
Spin
Spin
Spin
Min 2
Min 4
1
1
1
1
1
Local
T1A
+12V2
Res
Pin 7
Pin 23
Res
Res
Op1
EDO1
Pin 5
Pin 23
En1
En3
Fan 1
F1P
Fan 1
Spin
Spin
Spin
Spin
Min 1
Min 3
0
0
0
0
0
Res
T1%
+12V1
Res
0x7F
0xCE
0x42
0xFC
0x01
0x00
0xFF
0x37
0x00
0x00
0x00
0x00
0x00
0x11
0x31
0x51
0x71
0x90
0x90
0x80
0x80
0x80
0x80
0xC0
0x00
0xC0
0x00
0x00
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Fan Mask
Digital Mask
R/W
R/W
D1
Pin 13
Pin 24
Pin 28
Res
CS
Pin 21
Res
RR2
RR4
Fan 7
F7P
Fan 7
Bhvr
Bhvr
Bhvr
Bhvr
F2
F4
6
6
6
6
6
R2D
VRD1
+5V
+1.5V2
(3GIO)
Fan 7
VID
D3
Pin 15
Pin 25
Pin 29
Res
CS
Pin 19
Pin 29
RR2
RR4
Fan 6
F6P
Fan 6
Bhvr
Bhvr
Bhvr
Bhvr
F2
F4
5
5
5
5
5
R1D
T2S
P19
P26
0x34
0x35
VID
Pin 8
Pin 24
Pin 28
Res
CS
Pin 22
Res
RR2
RR4
Fan 8
F8P
Fan 8
Bhvr
Bhvr
Bhvr
Bhvr
F2
F4
7
7
7
7
7
R3D
VRD2
P23
+1.5V1
(ICH)
Fan 8
CI
Fan 6
SCSI2
Fan 5
SCSI1
Fan 4
FAN2MAX
Fan 3
Res
Fan 2
Res
Fan 1
Res
0x00
0x38
Yes
Yes
No
No
0x36
0x37
0x38
0x3D
0x3E
0x3F
GPIO Mask
EDO Mask 1
EDO Mask 2
Device ID
Company ID
Revision Number
R/W
R/W
R/W
R
R
R
GPIO8
Volt
Volt
7
7
7
GPIO7
Temp
Temp
6
6
6
GPIO6
Fan
Fan
5
5
5
GPIO5
Res
Res
4
4
4
GPIO4
GPIO4
GPIO4
3
3
3
GPIO3
GPIO3
GPIO3
2
2
2
GPIO2
GPIO2
GPIO2
1
1
1
GPIO1
GPIO1
GPIO1
0
0
0
0x00
0x00
0x00
0x62
0x41
0x04
Yes
Yes
Yes
No
No
No
No
No
No
N/A
N/A
N/A
Addr
0x00
Description
Configuration 0
R/W
R/W
0x01
Configuration 1
0x02
0x03
0x07
0x08
Configuration 2
Configuration 3
TACH Enable
TACH Configuration
0x09
0x0A
0x0B
0x0C
0x0D
GPIO1_Bhvr
GPIO2_Bhvr
TMIN_Cal1
TMIN_Cal2
0x0E
0x0F
Rev. 0 | Page 63 of 92
ADT7462
Addr
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
Description
Local Low
Temp Limit
Remote 1/Pin +15V Low
Remote 2 Low limit
Remote 3/
Pin 19 Low
Local High
Remote1/
Pin15 High
Remote 2
High Limit
Remote 3/
Pin 19 High
Local THERM1/
+1.5V2 (3GIO) High
Remote 1
THERM1 Limit
Remote 2
THERM1 Limit
Remote 3
THERM1 Limit
R/W
R/W
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x40
SW
Reset
No
Lockable
No
R/W
R/W
R/W
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
0x40
0x40
0x40
No
No
No
No
No
No
R/W
R/W
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x95
0x95
No
No
No
No
R/W
7
6
5
4
3
2
1
0
0x95
No
No
R/W
7
6
5
4
3
2
1
0
0x95
No
No
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x50
Local THERM2/
+1.5V1 (ICH) High
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x51
Remote 1 THERM2 Limit
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x52
Remote 2 THERM2 Limit
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x53
Remote 3 THERM2 Limit
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x54
0x55
Local/Remote1 Hyst
Remote 2/
Remote 3 Hyst
Local Offset
Remote 1 Offset
Remote 2 Offset
Remote 3 Offset
Remote 1
Operating Point
Remote 2
Operating Point
Local TMIN
Remote 1 TMIN
Remote 2 TMIN
Remote 3 TMIN
Local TRANGE/Hys
Remote 1 TRANGE/Hys
Remote 2 TRANGE/Hys
Remote 3 TRANGE/Hys
Operating Point Hyst
+3.3V High Limit
Pin 23 Voltage High Limit
Pin 24 Voltage High Limit
Pin 25 Voltage High Limit
Pin 26 Voltage High Limit
+12V1 Low Limit
+12V2 Low Limit
+12V3 Low Limit
+3.3V Low Limit
+5V Low Limit
Pin 23 Voltage Low Limit
R/W
R/W
LH
RH2
LH
RH2
LH
RH2
LH
RH2
R1H
RH3
R1H
RH3
R1H
RH3
R1H
RH3
0x44
0x44
No
No
Yes
Yes
R/W
R/W
R/W
R/W
R/W
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
0x00
0x00
0x00
0x00
0xA4
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
R/W
7
6
5
4
3
2
1
0
0xA4
Yes
Yes
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
7
7
7
Range
Range
Range
Range
Hys
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
Range
Range
Range
Range
Hys
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
Range
Range
Range
Range
Hys
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
Range
Range
Range
Range
Hys
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
Hys
Hys
Hys
Hys
Res
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
Hys
Hys
Hys
Hys
Res
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
Hys
Hys
Hys
Hys
Res
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Hys
Hys
Hys
Hys
Res
0
0
0
0
0
0
0
0
0
0
0
0x9A
0x9A
0x9A
0x9A
0xC4
0xC4
0xC4
0xC4
0x40
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x20
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
Rev. 0 | Page 64 of 92
ADT7462
Addr
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
Description
Pin 24 Voltage Low Limit
Pin 25 Voltage Low Limit
Pin 26 Voltage Low Limit
+1.5V1 (ICH) Low Limit
+1.5V2 (3GIO) Low Limit
TACH1 Limit/VID
TACH2 Limit
TACH3 Limit
TACH4 Limit
TACH5/+12V1
High Limit
TACH6/+12V2
High Limit
TACH7/+5V
High Limit
TACH8/+12V3
High Limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
7
7
7
7
7
7
7
7
7
7
Bit 6
6
6
6
6
6
6
6
6
6
6
Bit 5
5
5
5
5
5
5
5
5
5
5
Bit 4
4
4
4
4
4
4
4
4
4
4
Bit 3
3
3
3
3
3
3
3
3
3
3
Bit 2
2
2
2
2
2
2
2
2
2
2
Bit 1
1
1
1
1
1
1
1
1
1
1
Bit 0
0
0
0
0
0
0
0
0
0
0
Default
0x00
0x00
0x80
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
SW
Reset
No
No
No
No
No
No
No
No
Yes
No
Lockable
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
THERM1
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
R
7
6
5
4
3
2
1
0
0x00
No
No
R
7
6
5
4
3
2
1
0
0x00
No
No
R
R
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x00
0x00
No
No
No
No
R
7
6
5
4
3
2
1
0
0x00
No
No
R
7
6
5
4
3
2
1
0
0x00
No
No
R
7
6
5
4
3
2
1
0
0x00
No
No
R
7
6
5
4
3
2
1
0
0x00
No
No
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
N/A
N/A
0xFF
0xFF
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
R
7
6
5
4
3
2
1
0
0xFF
No
No
Timer Limit
0x81
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
THERM2
Timer Limit
Local Temp
Value, LSBs
Local Temp
Value, MSBs
Remote 1 Temp, LSBs
Remote 1 Temp, MSBs,
Pin 15 Voltage
Remote 2
Temp, LSBs
Remote 2
Temp, MSBs
Remote 3
Temp, LSBs
Remote 3 Temp, MSBs,
Pin 19 Voltage
Pin 23 Voltage
Pin 24 Voltage
Pin 25 Voltage
Pin 26 Voltage
+1.5V1 (ICH) Voltage
+1.5V2 (3GIO) Voltage
+3.3V Voltage
VID Value
TACH1 Value, LSBs
TACH1 Value, MSBs
TACH2 Value, LSBs
TACH2 Value, MSBs
TACH3 Value, LSBs
TACH3 Value, MSBs
TACH4 Value, LSBs
TACH4 Value, MSBs
Unused
Unused
TACH5 Value, LSB
TACH5 MSB/+12V1
Voltage
TACH6 Value, LSB
Rev. 0 | Page 65 of 92
ADT7462
Addr
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
Description
TACH6 MSB/+12V2
Voltage
TACH7 Value, LSB
TACH7 MSB/+5V
Voltage
TACH8 Value, LSB
TACH8 MSB/+12V3
Voltage
PWM1 Duty Cycle
PWM2 Duty Cycle
PWM3 Duty Cycle
PWM4 Duty Cycle
R/W
R
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0xFF
SW
Reset
No
Lockable
No
R
R
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0xFF
0xFF
No
No
No
No
R
R
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0xFF
0xFF
No
No
No
No
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
No
No
No
No
No
No
No
No
No
No
THERM1 % On-Time
R/W
R/W
R/W
R/W
R
0xAF
THERM2 % On-Time
R
7
6
5
4
3
2
1
0
0x00
No
No
0xB8
0xB9
0xBA
0xBB
0xBC
Thermal Status 1, Host
Thermal Status 2, Host
Thermal Status 3, Host
Voltage Status 1, Host
Voltage Status 2, Host
R
R
R
R
R
R3
T2A
LT2
Pin 15
Pin 25
R2
T2%
R3T1
+3.3V
Pin 24
R1
T1S
R2T1
+12V3
Res
Local
T1A
R1T1
+12V2
Res
Res
T1%
LT1
+12V1
Res
0x00
0x00
0x00
0x00
0x00
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Fan Status, Host
Digital Status, Host
GPIO Status, Host
Thermal Status 1, BMC
Thermal Status 2, BMC
Voltage Status 1, BMC
Voltage Status 2, BMC
R
R
R/W
R
R
R
R
Fan 6
SCSI2
GPIO6
R1D
T2S
Pin 19
Pin 26
Fan 5
SCSI1
GPIO5
R3
T2A
Pin 15
Pin 25
Fan 4
Fan 2 Max
GPIO4
R2
T2%
+3.3V
Pin 24
Fan 3
Res
GPIO3
R1
T1S
+12V3
Res
Fan 2
Res
GPIO2
Local
T1A
+12V2
Res
Fan 1
Res
GPIO1
Res
T1%
+12V1
Res
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
0xC5
0xC6
Fan Status, BMC
Digital Status, BMC
R
R
R2D
VR1
R2T2
+5V
+1.5V2
(3GIO)
Fan 7
VID
GPIO7
R2D
VR1
5V
+1.5V2
(3GIO)
Fan 7
VID
R1D
T2S
R1T2
Pin 19
Pin 26
0xBD
0xBE
0xBF
0xC0
0xC1
0xC3
0xC4
R3D
VR2
R3T2
Pin 23
+1.5V1
(ICH)
Fan 8
CI
GPIO8
R3D
VR2
Pin 23
+1.5V1
(ICH)
Fan 8
CI
Fan 6
SCSI2
Fan 5
SCSI1
Fan 4
Fan 2 Max
Fan 3
Res
Fan 2
Res
Fan 1
Res
0x00
0x0
Yes
Yes
No
No
Rev. 0 | Page 66 of 92
ADT7462
Table 35. Register 0x00 Configuration Register 0 1
Bit
[5:0]
6
7
1
Name
#Bytes Block Read
VID Decoder
SW Reset
R/W
R/W
R/W
R/W
Description
These bits set the number of registers to be read in a Block Read. Default = 0x20.
0 = VR10 Decoding Spec; 1 = VR11 Decoding Spec. Default = 0.
Setting this bit to 1 restores all unlocked registers to their default values. Self clearing.
Write 0x6D to register 0x7B before setting this bit to get a software reset. Default = 0.
POR = 0x20, Lock = Y, SW Reset = Y.
Table 36. Register 0x01 Configuration Register 1 1
Bit
0
Name
Monitor
R/W
R/W
1
2
3
Reserved
Reserved
ALERT Mode
R/W
R/W
R/W
4
R/W
5
Fast Spin-Up
Disable
Setup Complete
6
Lock
Write
Once
7
RDY
R
1
R/W
Description
Setting this bit to 1 enables temperature and voltage measurements. When this bit is set to 0,
temperature and voltage measurements are disabled. Default = 1.
Reserved. Default = 0.
Reserved. Default = 0.
This bit sets the ALERT mode in the ADT7462. 1 = comparator mode, 0 SMBALERT mode (default).
Setting this bit to 1 disables the fast spin-up (for 2 TACH pulses) for the fan. Instead, the fans spin up
for the programmed fan start-up timeout. Default = 0.
Setting this bit to 1 tells the ADT7462 that setup is complete and that monitoring of all selected
channels should begin. Default = 0.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read only and cannot be modified until the ADT7462 is powered down and powered up again. This
prevents rogue programs, such as viruses, from modifying critical system limit settings. Lockable.
This bit is set to 1 to indicate that the ADT7462 is fully powered up and ready to start monitoring.
POR = 0x81, Lock = Y, SW Reset = Y.
Table 37. Register 0x02 Configuration Register 2 1
Bit
0
Name
Fast
R/W
R/W
1
2
Reserved
PWM Mode
R/W
R/W
3
VRD1 Boost
R/W
4
VRD2 Boost
R/W
5
[7:6]
Fans Full Speed
#TACH Pulses
R/W
R/W
1
Description
In low frequency, PWM fan speed measurements are made once a second. Setting this bit to 1
increases the frequency of the fan speed measurements to 4 times a second. Default = 0.
Reserved. Default = 0.
This bit sets the PWM frequency mode. 0 = low frequency PWM; frequency programmable
between 11 Hz and 88.2 Hz. Default = 35.3 Hz. 1 = high frequency mode, 22.5 kHz.
Setting this bit to 0 causes the fans to go to full speed on assertion of VRD1. Default = 0.
When this bit is set to 1, VRD1 assertions have no effect on the fan speed.
Setting this bit to 0 causes the fans to go to full speed on assertion of VRD2. Default = 0.
When this bit is set to 1, VRD2 assertions have no effect on the fan speed.
Setting this bit to 1 drives the fans to full speed. Default = 0.
In low frequency mode, the ADT7462 must pulse stretch to get an accurate fan speed measurement.
The speed is always measured between the 2nd rising edge and one × TACH pulses later. This bit
determines the last TACH pulse. Therefore, if the fan speed is to be measured between the second and
fourth TACH pulse, 01 is written to these bits.
x = 1 = 00
x = 2 = 01 (default)
x = 3 = 10
x = 4 = 11
POR = 0x40, Lock = Y, SW Reset = Y.
Rev. 0 | Page 67 of 92
ADT7462
Table 38. Register 0x03 Configuration Register 3 1
Bit
0
1
2
3
Name
GPIO_En
SCL_Timeout
SDA_Timeout
VID_Threshold
R/W
R/W
R/W
R/W
R/W
4
THERM
_Threshold
CI Reset
XOR Tree
V_Core_Low
R/W
5
6
7
1
R/W
R/W
R/W
Description
Setting this bit to 1 enables the GPIOs. Default = 0.
1 = SCL Timeout Enabled. 0 = SCL timeout disabled = default.
1 = SDA Timeout Enabled. 0 = SDA timeout disabled = default.
This bit sets the digital threshold for the VID’s digital inputs. 0 =default. 1 = low thresholds
selected = 0.65 V.
This bit sets the digital threshold for the THERM’s digital inputs. 0 =default. 1 = low thresholds
selected = 2/3 VCCP1 (Pin 23).
Setting this bit to 1 resets the chassis intrusion circuit. This bit clears itself. Default = 0.
Setting this bit to 1 enables the XOR tree test. Default = 0.
Setting this bit to 1 enables V_core_low. Default = 0.
POR = 0x00, Lock = Y, SW Reset = Y.
Table 39. Register 0x07 TACH Enable Register 1
Bit
0
1
2
3
4
5
6
7
1
Name
TACH1
TACH2
TACH3
TACH4
TACH5
TACH6
TACH7
TACH8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit to 1 enables the TACH1 measurement. Default = 0.
Setting this bit to 1 enables the TACH2 measurement. Default = 0.
Setting this bit to 1 enables the TACH3 measurement. Default = 0.
Setting this bit to 1 enables the TACH4 measurement. Default = 0.
Setting this bit to 1 enables the TACH5 measurement. Default = 0.
Setting this bit to 1 enables the TACH6 measurement. Default = 0.
Setting this bit to 1 enables the TACH7 measurement. Default = 0.
Setting this bit to 1 enables the TACH8 measurement. Default = 0.
POR = 0x00, Lock = Y, SW Reset = Y.
Table 40. Register 0x08 TACH Configuration Register 1
Bit
0
Name
DC1/5
R/W
R/W
1
DC2/6
R/W
2
DC3/7
R/W
3
DC4/8
R/W
[4:7]
RES
R
1
Description
Setting this bit to 1 enables continuous measurements on TACH1 and TACH5 in low frequency PWM mode.
Default = 0.
Setting this bit to 1 enables continuous measurements on TACH2 and TACH6 in low frequency PWM mode.
Default = 0.
Setting this bit to 1 enables continuous measurements on TACH3 and TACH7 in low frequency PWM mode.
Default = 0.
Setting this bit to 1 enables continuous measurements on TACH4 and TACH8 in low frequency PWM mode.
Default = 0.
Reserved for future use.
POR = 0xE0, Lock = Y, SW Reset = Y.
Table 41. Register 0x09 GPIO Configuration Register 1 1
Bit
0
1
2
3
4
5
6
7
1
Name
GPIO1_P
GPIO1_D
GPIO2_P
GPIO2_D
GPIO3_P
GPIO3_D
GPIO4_P
GPIO4_D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This bit sets the polarity of GPIO1. 0 = default = active low. 1= active high.
This bit sets the direction of GPIO1. 0 = default = input. 1= output.
This bit sets the polarity of GPIO2. 0 = default = active low. 1= active high.
This bit sets the direction of GPIO2. 0 = default = input. 1= output.
This bit sets the polarity of GPIO3. 0 = default = active low. 1= active high.
This bit sets the direction of GPIO3. 0 = default = input. 1= output.
This bit sets the polarity of GPIO4. 0 = default = active low. 1= active high.
This bit sets the direction of GPIO4. 0 = default = input. 1= output.
POR = 0x00, Lock = Y, SW Reset = Y.
Rev. 0 | Page 68 of 92
ADT7462
Table 42. Register 0x0A GPIO Configuration Register 2 1
Bit
0
1
2
3
4
5
6
7
1
Name
GPIO5_P
GPIO5_D
GPIO6_P
GPIO6_D
GPIO7_P
GPIO7_D
GPIO8_P
GPIO8_D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This bit sets the polarity of GPIO5. 0 = default = active low. 1= active high.
This bits sets the direction of GPIO5. 0 = default = input. 1= output.
This bit sets the polarity of GPIO6. 0 = default = active low. 1= active high.
This bits sets the direction of GPIO6. 0 = default = input. 1= output.
This bit sets the polarity of GPIO7. 0 = default = active low. 1= active high.
This bits sets the direction of GPIO7. 0 = default = input. 1= output.
This bit sets the polarity of GPIO8. 0 = default = active low. 1= active high.
This bits sets the direction of GPIO8. 0 = default = input. 1= output.
POR = 0x00, Lock = Y, SW Reset = Y.
Table 43. Register 0x0B Dynamic TMIN Control Register 1 1
Bit
0
1
2
Name
Remote 1 En
Remote 2 En
PH1_TR1
R/W
R/W
R/W
R/W
3
PH1_TR2
R/W
4
PH2_TR1
R/W
5
PH2_RT2
R/W
[7:6]
Reserved
R/W
1
Description
Setting this bit to 1 enables dynamic TMIN control for the Remote 1 channel. Default = 0.
Setting this bit to 1 enables dynamic TMIN control for the Remote 2 channel. Default = 0.
PH1_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register
if THERM1 gets asserted externally. This happens only if the current temperature is less than the
value in the operating point register. The operating point contains the temperature at which THERM1
is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 1
operating point register reflects its programmed value.
PH1_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register
if THERM1 gets asserted externally. This happens only if the current temperature is less than the value
in the operating point register. The operating point contains the temperature at which THERM1
is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 2
Operating Point Register reflects its programmed value.
PH2_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if
THERM2 gets asserted externally. This happens only if the current temperature is less than the value in
the operating point register. The operating point contains the temperature at which THERM2 is asserted.
PH2_TR1 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 1 operating point
register reflects its programmed value.
PH2_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if
THERM2 gets asserted externally. This happens only if the current temperature is less than the value in
the operating point register. The operating point contains the temperature at which THERM2 is asserted.
PH2_RT2 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 2 operating point
register reflects its programmed value.
Reserved for future use.
POR = 0x00, Lock = Y, SW Reset = Y.
Rev. 0 | Page 69 of 92
ADT7462
Table 44. Register 0x0C Dynamic TMIN Control Register 2 1
Bit
[2:0]
[5:3]
6
7
1
Name
CYR1
R/W
R/W
CYR2
Bits
000
001
010
011
100
101
110
111
R/W
Control
Loop Select
Reserved
Bits
000
001
010
011
100
101
110
111
R/W
R
Description
Three-bit Remote 1 cycle value. These three bits define the delay time between making subsequent TMIN
adjustments in the control loop for the Remote 1 temperature channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the response
of fans and the control loop.
Decrease cycle
Increase cycle
8 cycles (1 sec)
16 cycles (2 sec)
16 cycles (2 sec)
32 cycles (4 sec)
32 cycles (4 sec)
64 cycles (8 sec)
64 cycles (8 sec)
128 cycles (16 sec)
128 cycles (16 sec)
256 cycles (32 sec)
256 cycles (32 sec)
512 cycles (64 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
Three-bit Remote 2 cycle value. These three bits define the delay time between making subsequent TMIN
adjustments in the control loop for the Remote 2 temperature channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the response
of fans and the control loop.
Decrease cycle
Increase Cycle
8 cycles (1 sec)
16 cycles (2 sec)
16 cycles (2 sec)
32 cycles (4 sec)
32 cycles (4 sec)
64 cycles (8 sec)
64 cycles (8 sec)
128 cycles (32 sec)
128 cycles (16 sec)
256 cycles (32 sec)
256 cycles (32 sec)
1024 cycles (128 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
This bit allows the user to select between two control loops. 0 makes the control loop backwards-compatible
with ADT7463 and ADT7468. 1 = ADT7462 control loop (default).
Reserved for future use.
POR = 0x40, Lock = Y, SW Reset = Y.
Rev. 0 | Page 70 of 92
ADT7462
Table 45. Register 0x0D THERM Configuration Register 1
Bit
0
Name
Boost 1
R/W
R/W
1
Boost 2
R/W
[4:2]
THERM1 Timer
Window
R/W
Description
Setting this bit to 0 causes the fans to go to full speed on assertion of THERM1 as an output. Setting
this bit to 1 means that the fan speed is not affected when the THERM1 temperature limit is exceeded.
Default = 0.
Setting this bit to 0 causes the fans to go to full speed on assertion of THERM2 as an output. Setting
this bit to 1 means that the fan speed is not affected when the THERM2 temperature limit is exceeded.
Default = 0.
These bits set the timer window for measuring THERM1 assertions.
000 = 0.25 sec
001 = 0.5 sec
010 = 1 sec
011 = 2 sec
100 = 4 sec
101 = 8 sec
110 = 8 sec
111 = 8 sec
[7:5]
THERM2 Timer
Window
R/W
These bits set the timer window for measuring THERM2 assertions.
000 = 0.25 sec
001 = 0.5 sec
010 = 1 sec
011 = 2 sec
100 = 4 sec
101 = 8 sec
110 = 8 sec
111 = 8 sec
1
POR = 0x00, Lock = Y, SW Reset = Y.
Table 46. Register 0x0E THERM1 Configuration Register 1
Bit
0
Name
Enable THERM1 Timer
R/W
R/W
Description
Enables the THERM1 timer circuit. Default = 0.
1
THERM1_Local
R/W
2
THERM1_Remote 1
R/W
3
THERM1_Remote 2
R/W
4
THERM1_Remote 3
R/W
[7:5]
Reserved
R
Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the local temperature exceeds the Local THERM1 temperature limit. Default = 0.
Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 1 temperature exceeds the Remote 1 THERM1 temperature Limit. Default = 0.
Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 2 temperature exceeds the Remote 2 THERM1 temperature Limit. Default = 0.
Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever
the Remote 3 temperature exceeds the Remote 3 THERM1 temperature limit. Default = 0.
Reserved for future use.
1
POR = 0x00, Lock = Y, SW Reset = Y.
Rev. 0 | Page 71 of 92
ADT7462
Table 47. Register 0x0F THERM2 Configuration Register 1
Bit
0
Name
R/W
R/W
1
Enable THERM2 Timer
THERM2_Local
2
THERM2_Remote 1
R/W
3
THERM2_Remote 2
R/W
4
THERM2_Remote 3
R/W
[7:5]
Reserved
R
1
R/W
Description
Enables the THERM2 timer circuit. Default = 0
Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the local temperature exceeds the local THERM2 temperature limit. Default = 0.
Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 1 temperature exceeds the Remote 1 THERM2 temperature limit. Default = 0.
Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 2 temperature exceeds the Remote 2 THERM2 temperature limit. Default = 0.
Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever
the Remote 3 temperature exceeds the Remote 3 THERM2 temperature limit. Default = 0.
Reserved for future use.
POR = 0x00, Lock = Y, SW Reset = Y.
Table 48. Register 0x10 Pin Configuration Register 1 1
Bit
0
1
2
3
4
5
Name
Pin 7
Pin 4
Pin 3
Pin 2
Pin 1
Diode 3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
Diode 1
R/W
7
VIDs
R/W
1
Description
0 = +12V1, 1 = TACH5 input. Default =1.
0 = GPIO4; 1= TACH4 input (that is if the VIDs are not selected). Default = 1.
0 = GPIO3; 1= TACH3 input (that is if the VIDs are not selected). Default = 1.
0 = GPIO2; 1= TACH2 input (that is if the VIDs are not selected). Default = 1.
0 = GPIO1; 1= TACH1 input (that is if the VIDs are not selected). Default = 1.
1 enables the D3+ and D3− inputs on Pin 19 and Pin 20. 0 enables the voltage measurement
input and SCSI_Term input. Default = 1.
1 enables the D1+ and D1− inputs on Pin 15 and Pin 16. 0 enables the voltage measurement
input and SCSI_Term input. Default = 1.
Setting this bit to 1 enables the VIDs on Pin 1 to Pin 4, Pin 28, Pin 31, and Pin 32. Default = 0.
POR = 0x7F, Lock = Y, SW Reset = Y.
Table 49. Register 0x11 Pin Configuration Register 2 1
Bit
[1:0]
Name
Pin 23
R/W
R/W
2
3
4
5
6
7
Pin 22
Pin 21
Pin 19
Pin 15
Pin 13
Pin 8
R/W
R/W
R/W
R/W
R/W
R/W
1
Description
00 = VCCP1 selected.
01 = +2.5V.
10 = +1.8V (default).
11 = +1.5V.
0 = +12V3; 1 = TACH8. Default = 1.
0 = +5V; 1 = TACH7. Default = 1.
0 = 1.25V; 1 = +0.9V (that is, if RT3 is not selected). Default = 0.
0 = +2.5V, 1 = +1.8V (that is, if RT1 is not selected) . Default = 0.
0 = +3.3V; 1 = PWM4. Default = 1.
0 = +12V2; 1 = TACH6. Default = 1.
POR = 0xCE, Lock = Y, SW Reset = Y.
Rev. 0 | Page 72 of 92
ADT7462
Table 50. Register 0x12 Pin Configuration Register 3 1
Bit
0
1
Name
Res
Pin 27
R/W
R
R/W
Description
Reserved for future use
0 = FAN2MAX; 1 = chassis intrusion (default)
[3:2]
Pin 26
R/W
[5:4]
Pin 25
R/W
[7:6]
Pin 24
R/W
00 = VBATT selected (default)
01 = +1.2V2 (FSB_VTT)
10 = VR_Hot 2
11 = VR_Hot 2
00 = +3.3V selected (default)
01 = +1.2V1 (GBIT)
10 = VR_Hot 1
11 = VR_Hot 1
00 = VCCP2 selected
01 = +2.5V (default)
10 = +1.8V
11 = +1.5V
1
POR = 0x42, Lock = Y, SW Reset = Y.
Table 51. Register 0x13 Pin Configuration Register 4 1
Bit
[1:0]
2
3
[5:4]
Name
RES
Pin 32
Pin 31
Pin 29
(Pin 28, +1.5V Monitoring2)
R/W
R
R/W
R/W
R/W
Description
Reserved.
0 = GPIO6; 1 = PWM2 (Pin 32 is VID 5 if VIDs are selected). Default = 1.
0 = GPIO5; 1 = PWM1 (Pin 31 is VID4 if VIDs are selected). Default = 1.
00 = GPIO8.
01 = +1.5V (measured on Pin 28).
10 = THERM2.
11 = THERM2 (default).
(Pin 29 is VID6 if VIDs are selected.)
[7:6]
Pin 28
(Pin 29, +1.5V monitoring2)
R/W
00 = GPIO7.
01 = +1.5V (measured on Pin 29).
10 = THERM1.
11 = THERM1 (default).
1
2
POR = 0xFC, Lock = Y, SW Reset = Y.
+1.5V can be monitored on Pin 28 and Pin 29 only when both are configured as +1.5V inputs. This means that +1.5V is measured on both pins or on neither.
+1.5V monitoring cannot be combined with another function on the other pin. For example, if Pin 29 is configured as +1.5V, then THERM1 cannot be selected on
Pin 28, because they share the same selection bits.
Table 52. Register 0x14 Easy Configuration Options 1
Bit
0
1
2
3
4
[7:5]
1
Name
Easy Option 1 Select
Easy Option 2 Select
Easy Option 3 Select
Easy Option 4 Select
Easy Option 5 Select
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Setting this bit to 1 enables Easy Option 1.
Setting this bit to 1 enables Easy Option 2.
Setting this bit to 1 enables Easy Option 3.
Setting this bit to 1 enables Easy Option 4.
Setting this bit to 1 enables Easy Option 5.
Reserved for future use.
POR = 0x01, Lock = Y, SW Reset = Y.
Rev. 0 | Page 73 of 92
ADT7462
Table 53. Register 0x16 EDO/Single-Channel Enable 1
Bit
0
1
2
Name
EDO_En1
EDO_En2
Single-Channel
Mode Select
R/W
R/W
R/W
R/W
[7:3]
Channel Select
R/W
1
Description
Enable EDO on GPIO5. Default = 0.
Enable EDO on GPIO6. Default = 0.
Setting this bit to 1 places the ADT7462 in single-channel mode. This means that it converts on
one channel only. The channel it converts on is set using the channel select bits in this register.
Default = 0.
These bits are used to set the single channel that the ADT7462 measures in single-channel mode.
0000 0 = Pin 26 (default)
0000 1 = Remote 1 temperature
0001 0 = Remote 2 temperature
0001 1 = Remote 3 temperature
00100 = local temperature
0010 1 = +12V1
0011 0 = +12V2
0011 1 = +12V3
0100 0 = +3.3V
0100 1 = Pin 15 voltage
0101 0 = Pin 19 voltage
0101 1 = +5V
0110 0 = Pin 23 voltage
0110 1 = Pin 24 voltage
0111 0 = Pin 25 voltage
1000 0 = +1.5V2 (ICH) voltage
1000 1 = +1.5V1 (3GIO) voltage
POR = 0x00, Lock = Y, SW Reset = Y.
Table 54. Register 0x18 Voltage Attenuator Configuration 1 1
Bit
0
1
2
3
4
5
6
7
1
Name
Res
Attenuator Pin 7
Attenuator Pin 8
Attenuator Pin 13
Attenuator Pin 15
Attenuator Pin 19
Attenuator Pin 21
Attenuator Pin 22
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved for future use.
Setting this bit to 0 removes the attenuators for Pin 7. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 8. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin13. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 15. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 19. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 21. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 22. Default = 1 = attenuators enabled.
POR = 0xFF, Lock = Y, SW Reset = Y.
Table 55. Register 0x19 Voltage Attenuator Configuration 2 1
Bit
0
1
2
3
4
5
[7:6]
1
Name
Attenuator Pin 23
Attenuator Pin 24
Attenuator Pin 25
Unused
Attenuator Pin 28
Attenuator Pin 29
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit to 0 removes the attenuators for Pin 23. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 24. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 25. Default = 1 = attenuators enabled.
Default = 0.
Setting this bit to 0 removes the attenuators for Pin 28. Default = 1 = attenuators enabled.
Setting this bit to 0 removes the attenuators for Pin 29. Default = 1 = attenuators enabled.
Reserved for future use. Default = 00.
POR = 0x37, Lock = Y, SW Reset = Y.
Rev. 0 | Page 74 of 92
ADT7462
Table 56. Register 0x1A Enhance Acoustics Register 1 1
Bit
0
1
[4:2]
Name
EA1_En
EA2_En
Ramp Rate 1
R/W
R/W
R/W
R/W
[7:5]
Ramp Rate 2
R/W
1
Description
Setting this bit to 1 enables the enhance acoustics mode for PWM1; 0 disables it. Default = 0.
Setting this bit to 1 enables the enhance acoustics mode for PWM2; 0 disables it. Default = 0.
These bits set the ramp rate for the enhance acoustics mode for PWM1. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
These bits set the ramp rate for the enhance acoustics mode for PWM2. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
POR = 0x00, Lock = Y, SW Reset = Y.
Table 57. Register 0x1B Enhance Acoustics Register 2 1
Bit
0
1
[4:2]
Name
EA3_En
EA4_En
Ramp Rate 3
R/W
R/W
R/W
R/W
[7:5]
Ramp Rate 4
R/W
1
Description
Setting this bit to 1 enables the enhance acoustics mode for PWM3; 0 disables it. Default = 0.
Setting this bit to 1 enables the enhance acoustics mode for PWM4; 0 disables it. Default = 0.
These bits set the ramp rate for the enhance acoustics mode for PWM3. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
These bits set the ramp rate for the enhance acoustics mode for PWM4. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
POR = 0x00, Lock = Y, SW Reset = Y.
Rev. 0 | Page 75 of 92
ADT7462
Table 58. Register 0x1C Fan Freewheeling Test 1
Bit
0
1
2
3
4
5
6
7
1
Name
Test Fan 1
Test Fan 2
Test Fan 3
Test Fan 4
Test Fan 5
Test Fan 6
Test Fan 7
Test Fan 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Fan freewheeling test bit for Fan 1. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 2. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 3. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 4. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 5. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 6. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 7. This bit self clears once the test is complete.
Fan freewheeling test bit for Fan 8. This bit self clears once the test is complete.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Set this bit to 1 when Fan 1 is present.
Set this bit to 1 when Fan 2 is present.
Set this bit to 1 when Fan 3 is present.
Set this bit to 1 when Fan 4 is present.
Set this bit to 1 when Fan 5 is present.
Set this bit to 1 when Fan 6 is present.
Set this bit to 1 when Fan 7 is present.
Set this bit to 1 when Fan 8 is present.
POR = 0x00, Lock = Y, SW Reset = Y.
Table 59. Register 0x1D Fans Present 1
Bit
0
1
2
3
4
5
6
7
1
Name
Fan 1 Present
Fan 2 Present
Fan 3 Present
Fan 4 Present
Fan 5 Present
Fan 6 Present
Fan 7 Present
Fan 8 Present
POR = 0x00, Lock = Y, SW Reset = Y.
Table 60. Register 0x1E Fan Freewheeling Test Enable 1
Bit
0
1
2
3
4
5
6
7
1
Name
Test Fan 1
Test Fan 2
Test Fan 3
Test Fan 4
Test Fan 5
Test Fan 6
Test Fan 7
Test Fan 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit to 1 enables the fan freewheeling test for Fan 1.
Setting this bit to 1 enables the fan freewheeling test for Fan 2.
Setting this bit to 1 enables the fan freewheeling test for Fan 3.
Setting this bit to 1 enables the fan freewheeling test for Fan 4.
Setting this bit to 1 enables the fan freewheeling test for Fan 5.
Setting this bit to 1 enables the fan freewheeling test for Fan 6.
Setting this bit to 1 enables the fan freewheeling test for Fan 7.
Setting this bit to 1 enables the fan freewheeling test for Fan 8.
POR = 0x00, Lock = Y, SW Reset = Y.
Rev. 0 | Page 76 of 92
ADT7462
Table 61. PWM Configuration Registers 1
Register
Address
0x21
0x22
0x23
0x24
Bit
[2:0]
R/W Description
R/W PWM1 Configuration Register
R/W PWM2 Configuration Register
R/W PWM3 Configuration Register
R/W PWM4 Configuration Register
Name
Spin-Up Timeout
Power On
Default
0x11
0x31
0x51
0x71
R/W
R/W
3
SLOW
R/W
4
INV
R/W
[7:5]
BHVR
R/W
1
Description
These bits set the duration of the fan start-up timeout and the
timeout for the fan freewheeling test.
000 = no start-up timeout
001 = 100 ms
010 = 250 ms
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 32 sec
Setting this bit to 1 makes the ramp rate of the enhance
acoustics mode 4 times longer.
Setting this bit to 0, the PWM outputs are active high
Setting this bit to 1, the PWM outputs are active low.
These bits determine which temperature channel controls the
fans in the automatic fan speed control loop.
000 = local temperature
001 = Remote 1 temperature
010 = Remote 2 temperature
011 = Remote 3 temperature
100 = off
101 = maximum fan speed calculated by the local and Remote 3
temperature channels.
110 = maximum fan speed calculated by all 4 channels.
111 = manual mode.
Lock = Y, SW Reset = Y.
Rev. 0 | Page 77 of 92
ADT7462
Table 62. Register 0x25 PWM1, PWM2 Frequency 1
Bit
0
Name
Min 1
R/W
R/W
1
Min 2
R/W
[4:2]
Low Freq 1
R/W
[7:5]
Low Freq 2
R/W
1
Description
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or
at minimum PWM1 duty cycle when the controlling temperature is below its TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM1 duty cycle below TMIN − hysteresis.
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM2 is off (0% duty cycle) or
at minimum PWM2 duty cycle when the controlling temperature is below its TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM2 duty cycle below TMIN − hysteresis.
These bits set the frequency of PWM1 when configured in low frequency mode.
000 = 11 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
These bits set the frequency of PWM2 when configured in low frequency mode.
000 = 11 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
POR = 0x90, Lock = Y, SW Reset = Y.
Table 63. Register 0x26 PWM3, PWM4 Frequency 1
Bit
0
Name
Min 3
R/W
R/W
1
Min 4
R/W
[4:2]
Low Freq 3
R/W
[7:5]
Low Freq 4
R/W
1
Description
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM3 is off (0% duty cycle) or
at minimum PWM3 duty cycle when the controlling temperature is below its TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM3 duty cycle below TMIN − hysteresis.
When the ADT7462 is in automatic fan control mode, this bit defines whether PWM4 is off (0% duty cycle)
or at minimum PWM4 duty cycle when the controlling temperature is below its TMIN − hysteresis value.
0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM4 duty cycle below TMIN − hysteresis.
These bits set the frequency of PWM3 when configured in low frequency mode 000 = 11 Hz.
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
These bits set the frequency of PWM4 when configured in low frequency mode.
000 = 11 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
POR = 0x90, Lock = Y, SW Reset = Y.
Rev. 0 | Page 78 of 92
ADT7462
Table 64. Minimum PWMx Duty Cycle 1
Register Address
0x28
0x29
0x2A
0x2B
1
R/W
R/W
R/W
R/W
R/W
Description
Minimum PWM1 duty cycle
Minimum PWM2 duty cycle
Minimum PWM3 duty cycle
Minimum PWM4 duty cycle
POR Default
0x80
0x80
0x80
0x80
Lock = Y, SW Reset = Y.
Table 65. Register 0x2C Maximum PWM Duty Cycle 1
Bit
[7:0]
1
Name
Maximum PWM Duty Cycle
R/W
R/W
Description
This register sets the maximum % duty cycle output in automatic fan speed
control mode for all four PWM outputs.
POR = 0xC0, Lock = Y, SW Reset = Y.
Table 66. Register 0x30 Thermal Mask Register 1 1
Bit
0
1
Name
Reserved
Local Temp
R/W
R/W
R/W
Description
Reserved for future use.
A 1 masks ALERTs for an out-of-limit condition on the local temperature channel.
2
Remote 1 Temp
R/W
A 1 masks ALERTs for an out-of-limit condition on the Remote 1 temperature channel.
3
Remote 2 Temp
R/W
A 1 masks ALERTs for an out-of-limit condition on the Remote 2 temperature channel.
4
Remote 3 Temp
R/W
A 1 masks ALERTs for an out-of-limit condition on the Remote 3 temperature channel.
5
Diode 1 Error
R/W
A 1 masks ALERTs for an open or short condition on the Remote 1 channel.
6
Diode 2 Error
R/W
A 1 masks ALERTs for an open or short condition on the Remote 2 channel.
7
Diode 3 Error
R/W
A 1 masks ALERTs for an open or short condition on the Remote 3 channel.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 67. Register 0x31 Thermal Mask Register 2 1
Bit
0
Name
THERM1 %
R/W
R/W
Description
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1
THERM1 Assert
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
2
THERM1 State
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
3
THERM2 %
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
4
THERM2 Assert
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
5
THERM2 State
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
6
VRD1_Assert
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
7
VRD2_Assert
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1
POR = 0xC0, Lock = N, SW Reset = Y.
Rev. 0 | Page 79 of 92
ADT7462
Table 68. Register 0x32 Voltage Mask Register 1 1
Bit
0
Name
+12V1
R/W
R/W
Description
A 1 masks ALERTs for the corresponding interrupt status bit.
1
+12V2
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
2
+12V3
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
3
+3.3V
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
4
Pin 15 Voltage
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
5
Pin 19 Voltage
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
6
+5V
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
7
Pin 23 Voltage
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 69. Register 0x33 Voltage Mask Register 2 1
Bit
[2:0]
3
Name
Reserved
Pin 24 Voltage
R/W
R/W
R/W
Description
Reserved for future use.
A 1 masks ALERTs for the corresponding interrupt status bit.
4
Pin 25 Voltage
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
5
Pin 26 Voltage
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
6
+1.5V2 (3GIO)
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
7
+1.5V1 (ICH)
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 70. Register 0x34 Fan Mask Register 1 1
Bit
0
Name
Fan 1 Fault
R/W
R/W
Description
A 1 masks ALERTS for the corresponding interrupt status bit.
1
Fan 2 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
2
Fan 3 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
3
Fan 4 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
4
Fan 5 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
5
Fan 6 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
6
Fan 7 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
7
Fan 8 Fault
R/W
A 1 masks ALERTS for the corresponding interrupt status bit.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 71. Register 0x35 Digital Mask Register 1 1
Bit
[2:0]
3
Name
Reserved
FAN2MAX
R/W
R
R/W
Description
Reserved for future use.
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
4
SCSI_Term1
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
5
SCSI_Term2
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
6
VID Comparison
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
7
Chassis Intrusion
R/W
A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1
POR = 0x38, Lock = N, SW Reset = Y.
Rev. 0 | Page 80 of 92
ADT7462
Table 72. Register 0x36 GPIO Mask Register 1
Bit
0
Name
GPIO1
R/W
R/W
Description
A 1 masks ALERTs for the corresponding interrupt status bit.
1
GPIO2
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
2
GPIO3
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
3
GPIO4
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
4
GPIO5
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
5
GPIO6
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
6
GPIO7
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
7
GPIO8
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 73. Register 0x37 EDO 1 Mask Register 1
Bit
0
1
2
3
4
5
6
Name
GPIO1
GPIO2
GPIO3
GPIO4
Unused
Fan
Temp
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
A 1 masks GPIO1 from causing an EDO1 assertion.
A 1 masks GPIO2 from causing an EDO1 assertion.
A 1 masks GPIO3 from causing an EDO1 assertion.
A 1 masks GPIO4 from causing an EDO1 assertion.
Unused.
A 1 masks a fan fail condition from causing an EDO1 assertion.
A 1 masks a THERM condition from causing an EDO1 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 74. Register 0x38 EDO 2 Mask Register 1
Bit
0
1
2
3
4
5
6
Name
GPIO1
GPIO2
GPIO3
GPIO4
Unused
Fan
Temp
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
A 1 masks GPIO1 from causing an EDO2 assertion.
A 1 masks GPIO2 from causing an EDO2 assertion.
A 1 masks GPIO3 from causing an EDO2 assertion.
A 1 masks GPIO4 from causing an EDO2 assertion.
Unused.
A 1 masks a fan fail condition from causing an EDO2 assertion.
A 1 masks a THERM condition from causing an EDO2 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 75. Register 0x3D Device ID Register 1
Bit
[7:0]
1
Name
Device ID
R/W
R
Description
This register contains the device ID (0x62) for the ADT7462.
POR = 0x62.
Table 76. Register 0x3E Company ID Register 1
Bit
[7:0]
1
Name
Company ID
R/W
R
Description
This register contains the company ID (0x41) for the ADT7462.
POR = 0x41.
Rev. 0 | Page 81 of 92
ADT7462
Table 77. Register 0x3F Revision Register 1
Bit
[7:0]
1
Name
Revision ID
R/W
R
Description
This register contains the revision ID (0x03) for the ADT7462.
POR = 0x04.
Table 78. Temperature Limit Registers 1
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Local low temperature limit
Remote 1 low temperature/Pin 15 voltage low limit
Remote 2 low temperature limit
Remote 3 low temperature/Pin 19 voltage low limit
Local high temperature limit
Remote 1 high temperature/Pin 15 voltage high limit
Remote 2 high temperature limit
Remote 3 high temperature/Pin 19 voltage high limit
Local THERM1 temperature limit/+1.5V1 (ICH) voltage high limit
Lockable
No
No
No
No
No
No
No
No
Yes
POR Default
0x40
0x40
0x40
0x40
0x95
0x95
0x95
0x95
0xA4
0x4D
R/W
Yes
0xA4
0x4E
R/W
Remote 1 THERM1 temperature limit
Remote 2THERM1 temperature limit
Yes
0xA4
0x4F
R/W
Remote 3 THERM1 temperature limit
Yes
0xA4
0x50
R/W
0xA4
R/W
Local THERM2 temperature limit/+1.5V2 (3GIO) voltage high limit
Remote 1 THERM2 temperature limit
Yes
0x51
Yes
0xA4
0x52
R/W
0xA4
R/W
Remote 2 THERM2 temperature limit
Remote 3 THERM2 temperature limit
Yes
0x53
Yes
0xA4
1
SW Reset = N.
Table 79. Register 0x54 Local/Remote 1 Hysteresis 1
Bit
[3:0]
Name
Remote 1 Hystereis
R/W
R/W
[7:4]
Local Hysteresis
R/W
Description
These four bits set the Remote 1 THERM hysteresis value, 1 LSB = 1°C
These four bits set the local THERM hysteresis value, 1 LSB = 1°C
0000 = 0°C
0001 = 1°C
0010 = 2°C
0011 = 3°C
0100 = 4°C (default)
0101 = 5°C
0110 = 6°C
0111 = 7°C
1000 = 8°C
1001 = 9°C
1010 = 10°C
1011 = 11°C
1100 = 12°C
1101 = 13°C
1110 = 14°C
1111 = 15°C
1
POR = 0x44, Lock = Y, SW Reset = N.
Rev. 0 | Page 82 of 92
ADT7462
Table 80. Register 0x55 Remote 2/Remote 3 Hysteresis 1
Bit
[3:0]
Name
Remote 3 Hysteresis
R/W
R/W
Description
These four bits set the Remote 3 THERM hysteresis value,1 LSB = 1°C
[7:4]
Remote 2 Hysteresis
R/W
These four bits set the Remote 2 THERM hysteresis value,1 LSB = 1°C
0000 = 0°C
0001 = 1°C
0010 = 2°C
0011 = 3°C
0100 = 4°C (default)
0101 = 5°C
0110 = 6°C
0111 = 7°C
1000 = 8°C
1001 = 9°C
1010 = 10°C
1011 = 11°C
1100 = 12°C
1101 = 13°C
1110 = 14°C
1111 = 15°C
1
POR = 0x44, Lock = Y, SW Reset = N.
Table 81. Offset Registers 1
Register Address
0x56
0x57
0x58
0x59
1
R/W
R/W
R/W
R/W
R/W
Description
Local offset, resolution = 0.5°C
Remote 1 offset, resolution = 0.5°C
Remote 2 offset, resolution = 0.5°C
Remote 3 offset, resolution = 0.5°C
POR Default
0x00
0x00
0x00
0x00
R/W
R/W
R/W
Description
Remote 1 operating point
Remote 2 operating point
POR Default
0xA4
0xA4
R/W
R/W
R/W
R/W
R/W
Description
Local TMIN
Remote 1 TMIN
Remote 2 TMIN
Remote 3 TMIN
POR Default
0x9A
0x9A
0x9A
0x9A
Lock = Y, SW Reset = N.
Table 82. Operating Point Registers 1
Register Address
0x5A
0x5B
1
Lock = N, SW Reset = Y.
Table 83. Timing Registers 1
Register Address
0x5C
0x5D
0x5E
0x5F
1
Lock = Y, SW Reset = Y.
Rev. 0 | Page 83 of 92
ADT7462
Table 84. TRANGE/Hysteresis Registers 1
Register
Address
0x60
R/W
Description
R/W
0x61
R/W
0x62
R/W
0x63
R/W
Bit
[3:0]
Local TRANGE/
Hysteresis
Remote TRANGE/
Hysteresis
Remote
TRANGE/
Hysteresis
Remote
TRANGE/
Hysteresis
Name
Hysteresis
[7:4]
TRANGEe
1
POR
Default
0xC4
0xC4
0xC4
0xC4
R/W
R/W
R/W
Description
These four bits set the hysteresis in the automatic fan speed control loop and
in the dynamic TMIN control loop, 1 LSB = 1°C.
0000 = 0°C
0001 = 1°C
0010 = 2°C
0011 = 3°C
0100 = 4°C (default)
0101 = 5°C
0110 = 6°C
0111 = 7°C
1000 = 8°C
1001 = 9°C
1010 = 10°C
1011 = 11°C
1100 = 12°C
1101 = 13°C
1110 = 14°C
1111 = 15°C
These four bits set the TRANGE value, that is, the slope or rate of change of fan speed
with respect to temperature in the automatic fan speed control loop.
0000 = 2°C
0001 = 2.5°C
0010 = 3.3°C
0011 = 4°C
0100 = 5°C
0101 = 6.7°C
0110 = 8°C
0111 = 10°C
1000 = 13.3°C
1001 = 16°C
1010 = 20°C
1011 = 26.7°C
1100 = 32°C (default)
1101 = 40°C
1110 = 53.3°C
1111 = 80°C
Lock = Y, SW Reset = Y.
Rev. 0 | Page 84 of 92
ADT7462
Table 85. Register 0x64 Operating Point Hysteresis 1
Bit
[3:0]
[7:4]
1
Name
Reserved
Operating Point Hysteresis
R/W
R
R/W
Description
Reserved for future use.
These four bits set the operating point hysteresis for the dynamic TMIN control loop, 1 LSB = 1°C.
0000 = 0°C
0001 = 1°C
0010 = 2°C
0011 = 3°C
0100 = 4°C (default)
0101 = 5°C
0110 = 6°C
0111 = 7°C
1000 = 8°C
1001 = 9°C
1010 = 10°C
1011 = 11°C
1100 = 12°C
1101 = 13°C
1110 = 14°C
1111 = 15°C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
+3.3V high limit
Pin 23 voltage high limit
Pin 24 voltage high limit
Pin 25 voltage high limit
Pin 26 voltage high limit
+12V1 voltage low limit
+12V2 voltage low limit
+12V3 voltage low limit
+3.3V low limit
+5V low limit
Pin 23 voltage low limit
Pin 24 voltage low limit
Pin 25 voltage low limit
Pin 26 voltage low limit
+1.5V1 (ICH) voltage low limit
+1.5V2 (3GIO) voltage low limit
POR = 0x40, Lock = Y, SW Reset = Y.
Table 86. Voltage Limit Registers 1
Register Address
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
1
Lock = N, SW Reset = N.
Rev. 0 | Page 85 of 92
POR Default
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x20
0x00
0x00
0x80
0x00
0x00
ADT7462
Table 87. TACH Limit Registers 1
Register Address
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
TACH1 limit/VID limit
TACH2 limit
TACH3 limit
TACH4 limit
TACH5 limit/+12V1 voltage high limit
TACH6 limit/+12V2 voltage high limit
TACH7 limit/+5V voltage high limit
TACH8 limit/+12V3 voltage high limit
POR Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Description
THERM1 % Limit
THERM2 % Limit
POR Default
0xFF
Lock = Y, SW Reset = N.
Table 88. THERM Timer Limit 1
Register Address
0x80
R/W
R/W
0x81
R/W
1
Lock = Y, SW Reset = N.
Table 89. Temperature Value Registers 1
Register Address
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
1
R/W
R
R
R
R
R
R
R
R
Description
Bit [7:6] Local temperature value, LSBs
Local temperature value, MSBs
Bit [7:6] Remote 1 temperature value, LSBs
Remote 1 temperature value, MSBs/Pin 15 Voltage
Bit [7:6] Remote 2 temperature value, LSBs
Remote 2 temperature value, MSBs
Bit [7:6] Remote 3 temperature value, LSBs
Remote 3 temperature value, MSBs/Pin 19 voltage
Lock = N, SW Reset = N.
Table 90. Voltage Value Registers 1
Register Address
0x90
0x91
0x92
0x93
0x94
0x95
0x96
1
R/W
R
R
R
R
R
R
R
Description
Pin 23 voltage value
Pin 24 voltage value
Pin 25 voltage value
Pin 26 voltage value
+1.5V1 (ICH) voltage value
+1.5V2 (3GIO) voltage value
+3.3V voltage value
R/W
R
Description
This register reports the state of the 7 VID inputs.
Lock = N, SW Reset = N.
Table 91. VID Value Register 1
Register Address
0x97
1
Lock = N, SW Reset = N.
Rev. 0 | Page 86 of 92
0xFF
ADT7462
Table 92. TACH Value Registers 1
Register Address
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
1
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
TACH1, LSB
TACH1, MSB
TACH2, LSB
TACH2, MSB
TACH3, LSB
TACH3, MSB
TACH4, LSB
TACH4, MSB
TACH5, LSB
TACH5, MSB/+12V1 voltage value register
TACH6, LSB
TACH6, MSB/+12V2 voltage value register
TACH7, LSB
TACH7, MSB/+5V voltage value register
TACH8, LSB
TACH8, MSB/+12V3 voltage value register
Lock = N, SW Reset = N.
Table 93. Current PWM Duty Cycle Registers 1
Register Address
0xAA
0xAB
0xAC
0xAD
1
R/W
R/W
R/W
R/W
R/W
Description
PWM1 current duty cycle
PWM2 current duty cycle
PWM3 current duty cycle
PWM4 current duty cycle
Lock = N, SW Reset = N.
Table 94. THERM Timer Value Registers 1
Register Address
0xAE
R/W
R
0xAF
R
1
Description
THERM1 timer % on-time value
THERM2 timer % on-time value
POR Default
0x00
0x00
Lock = N, SW Reset = N.
Table 95. Register 0x0B8 Host Thermal Status Register 1 1
Register 0x0CO BMC Thermal Status Register 1 2
Bit
0
1
2
3
4
5
6
7
1
2
Name
Reserved
Local Temp
Remote 1 Temp
Remote 2 Temp
Remote 3 Temp
Diode 1 Error
Diode 2 Error
Diode 3 Error
R/W
R
R
R
R
R
R
R
R
Description
Reserved for future use.
A 1 indicates that a local temperature limit has been tripped.
A 1 indicates that a Remote 1 temperature limit has been tripped.
A 1 indicates that a Remote 2 temperature limit has been tripped.
A 1 indicates that a Remote 3 temperature limit has been tripped.
A 1 indicates that a Remote 1 diode error, either an open or a short, has occurred.
A 1 indicates that a Remote 2 diode error, either an open or a short, has occurred.
A 1 indicates that a Remote 3 diode error, either an open or a short, has occurred.
POR = 0x00, Lock = N, SW Reset = Y.
POR = 0x00, Lock = N, SW Reset = Y.
Rev. 0 | Page 87 of 92
ADT7462
Table 96. Register 0xB9 Host Thermal Status Register 2 1
Register 0xC1 BMC Thermal Status Register 21
Bit
0
Name
THERM1 %
R/W
R
1
THERM1 Assert
R
2
THERM1 State
R
3
THERM2 %
R
A 1 indicates that a transition from high to low has taken place on the THERM1 pin.
A 1 indicates that THERM2 has been asserted for longer than the programmed THERM2 timer limit.
4
THERM2 Assert
R
A 1 indicates that THERM2 is asserted.
5
THERM2 State
R
A 1 indicates that a transition from high to low has taken place on the THERM2 pin.
6
7
VRD1_Assert
VRD2_Assert
R
R
A 1 indicates that VRD1 is asserted.
A 1 indicates that VRD2 is asserted.
1
Description
A 1 indicates that THERM1 has been asserted for longer than the programmed THERM1 timer limit.
A 1 indicates that THERM1 is asserted.
POR = 0x00, Lock = N, SW Reset = Y.
Table 97. Register 0xBA Thermal Status Register 3 1
Bit
0
Name
Local THERM1
R/W
R
1
Remote 1 THERM1
Remote 2 THERM1
R
Remote 3 THERM1
Local THERM2
R
A 1 indicates that the Remote 2 THERM1 limit has been exceeded.
A 1 indicates that the Remote 3 THERM1 limit has been exceeded.
R
A 1 indicates that the Local THERM2 limit has been exceeded.
5
Remote 1 THERM2
R
A 1 indicates that the Remote 1 THERM2 limit has been exceeded.
6
Remote 2 THERM2
R
A 1 indicates that the Remote 2 THERM2 limit has been exceeded.
7
Remote 3 THERM2
R
A 1 indicates that the Remote 3 THERM2 limit has been exceeded.
2
3
4
1
R
Description
A 1 indicates that the local THERM1 limit has been exceeded.
A 1 indicates that the Remote 1 THERM1 limit has been exceeded.
POR = 0x00, Lock = N, SW Reset = Y.
Table 98. Register 0xBB Host Voltage Register 1 1
Register 0xC3 BMC Voltage Register 11
Bit
0
1
2
3
4
5
6
7
1
Name
+12V1
+12V2
+12V3
+3.3V
Pin 15 Voltage
Pin 19 Voltage
+5V
Pin 23 Voltage
R/W
R
R
R
R
R
R
R
R
Description
A 1 indicates that a +12V1 voltage limit has been tripped.
A 1 indicates that a +12V2 voltage limit has been tripped.
A 1 indicates that a +12V3 voltage limit has been tripped.
A 1 indicates that a +3.3V voltage limit has been tripped.
A 1 indicates that a Pin 15 voltage limit has been tripped.
A 1 indicates that a Pin 19 voltage limit has been tripped.
A 1 indicates that a +5V voltage limit has been tripped.
A 1 indicates that a Pin 23 voltage limit has been tripped.
POR = 0x00, Lock = N, SW Reset = Y.
Rev. 0 | Page 88 of 92
ADT7462
Table 99. Register 0xBC Host Voltage Status Register 2 1
Register 0xC4 BMC Voltage Status Register 21
Bit
[2:0]
3
4
5
6
7
1
Name
Reserved
Pin 24 Voltage
Pin 25 Voltage
Pin 26 Voltage
+1.5V2 (3GIO)
+1.5V1 (ICH)
R/W
R
R
R
R
R
R
Description
Reserved for future use.
A 1 indicates that a Pin 24 voltage limit has been tripped.
A 1 indicates that a Pin 25 voltage limit has been tripped.
A 1 indicates that a Pin 26 voltage limit has been tripped.
A 1 indicates that a +1.5V2 (3GIO) voltage limit has been tripped.
A 1 indicates that a +1.5V1 (ICH) voltage limit has been tripped.
POR = 0x00, Lock = N, SW Reset = Y.
Table 100. Register 0xBD Host Fan Status Register 1 1
Register 0xC5 BMC Fan Status Register 11
Bit
0
1
2
3
4
5
6
7
1
Name
Fan 1 Fault
Fan 2 Fault
Fan 3 Fault
Fan 4 Fault
Fan 5 Fault
Fan 6 Fault
Fan 7 Fault
Fan 8 Fault
R/W
R
R
R
R
R
R
R
R
Description
A 1 indicates a Fan 1 fault.
A 1 indicates a Fan 2 fault.
A 1 indicates a Fan 3 fault.
A 1 indicates a Fan 4 fault.
A 1 indicates a Fan 5 fault.
A 1 indicates a Fan 6 fault.
A 1 indicates a Fan 7 fault.
A 1 indicates a Fan 8 fault.
POR = 0x00, Lock = N, SW Reset = Y.
Table 101. Register 0xBE Host Digital Status Register 1 1
Register 0xC6 BMC Digital Status Register 11
Bit
[2:0]
3
Name
Reserved
FAN2MAX
R/W
R
R
Description
Reserved for future use.
A 1 indicates that the FAN2MAX has been asserted as an input.
4
5
6
7
SCSI_Term1
SCSI_Term2
VID Comparison
Chassis Intrusion
R
R
R
R
A 1 indicates that the SCSI_Term1 digital input has been asserted.
A 1 indicates that the SCSI_Term2 digital input has been asserted.
A 1 indicates a VID comparison fault.
A 1 indicates that the chassis intrusion digital input has been asserted.
1
POR = 0x00, Lock = N, SW Reset = Y.
Table 102. Register 0xBF GPIO Status Register 1
Bit
0
1
2
3
4
5
6
7
1
Name
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
A 1 indicates that GPIO1 is asserted.
A 1 indicates that GPIO2 is asserted.
A 1 indicates that GPIO3 is asserted.
A 1 indicates that GPIO4 is asserted.
A 1 indicates that GPIO5 is asserted.
A 1 indicates that GPIO6 is asserted.
A 1 indicates that GPIO7 is asserted.
A 1 indicates that GPIO8 is asserted.
POR = 0x00, Lock = N, SW Reset = Y.
Rev. 0 | Page 89 of 92
ADT7462
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADT7462ACPZ-500RL7 1
ADT7462ACPZ-REEL1
ADT7462ACPZ -REEL71
EVAL-ADT7462EB
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 90 of 92
Package Option
CP-32-2
CP-32-2
CP-32-2
ADT7462
NOTES
Rev. 0 | Page 91 of 92
ADT7462
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05569-0-1/06(0)
Rev. 0 | Page 92 of 92