800 MHz, 2:1 Analog Multiplexers ADV3219/ADV3220 Excellent ac performance −3 dB bandwidth 800 MHz (200 mV p-p) 730 MHz (2 V p-p) Slew rate: 2800 V/μs Low power: 75 mW, VS = ±5 V Excellent video performance >100 MHz, 0.1 dB gain flatness 0.02% differential gain/0.02° differential phase error (RL = 150 Ω) Gain = +1 (ADV3219) or gain = +2 (ADV3220) Low crosstalk of −82 dB @ 5 MHz and −60 dB @ 100 MHz High impedance output disable allows connection of multiple devices without loading the output bus 8-lead LFCSP FUNCTIONAL BLOCK DIAGRAM ADV3219 (ADV3220) IN0 1 8 SELECT 7 EN GND 2 IN1 3 G = +1 (G = +2) 6 OUT 5 V– V+ 4 08649-001 FEATURES Figure 1. APPLICATIONS Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, and RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications GENERAL DESCRIPTION The ADV3219 and ADV3220 are high speed, high slew rate, buffered, 2:1 analog multiplexers. They offer a −3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With −60 dB of crosstalk and −82 dB isolation (at 100 MHz), the ADV3219 and ADV3220 are useful in many high speed applications. The differential gain of less than 0.02% and the differential phase of less than 0.02°, together with 0.1 dB flatness beyond 100 MHz while driving a 75 Ω back terminated load, make the ADV3219 and ADV3220 ideal for all types of signal switching. The ADV3219/ADV3220 include an output buffer that can be placed into a high impedance state to allow multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3219 has a gain of +1, and the ADV3220 has a gain of +2; they both operate on ±5 V supplies while consuming less than 7.5 mA of idle current. The ADV3219/ADV3220 are available in the 8-lead LFCSP package over the extended industrial temperature range of −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADV3219/ADV3220 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Circuit Diagrams ............................................................................ 15 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 16 General Description ......................................................................... 1 Applications Information .............................................................. 17 Revision History ............................................................................... 2 Circuit Layout ............................................................................. 17 Specifications..................................................................................... 3 Termination................................................................................. 17 Absolute Maximum Ratings............................................................ 5 Capacitive Load .......................................................................... 17 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 18 Power Dissipation ......................................................................... 5 Ordering Guide .......................................................................... 18 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADV3219/ADV3220 SPECIFICATIONS VS = ±5 V, TA = 25°C, RL = 150 Ω, CL = 4 pF, ADV3219 at G = +1, ADV3220 at G = +2, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk Off Isolation, Input-Output Input Second-Order Intercept Input Third-Order Intercept Output 1 dB Compression Point Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching OUTPUT CHARACTERISTICS Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Drift Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) Conditions Min ADV3219 Typ Max Min ADV3220 Typ Max Unit 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 2 V p-p 1%, 2 V step 2 V step, peak 840 600 100 100 700 5 2200 800 730 100 100 650 5 2800 MHz MHz MHz MHz ps ns V/μs NTSC or PAL NTSC or PAL f = 100 MHz f = 5 MHz f = 100 MHz, one channel f = 70 MHz, ADV3220, RL = 100 Ω f = 70 MHz, ADV3220, RL = 100 Ω f = 70 MHz, ADV3220, RL = 100 Ω 10 MHz to 100 MHz 0.02 0.02 −70 −90 −83 0.02 0.02 −60 −82 −82 47 34 20 17 % Degrees dB dB dB dBm dBm dBm nV/√Hz 16 No load RL = 150 Ω Channel-to-channel, no load DC, enabled Disabled Disabled Disabled No load Load Short-circuit current 0.75 1 1 1.1 0.75 1 0.02 0.04 1 2.9 2.8 Worst case (all configurations) No load RL = 150 Ω Any switch configuration Output enabled Output enabled 1 50% SELECT to 1% settling IN0 to IN1 switching Rev. 0 | Page 3 of 20 1 1.1 Ω MΩ pF μA V V mA 1 1.0 2 ±3 ±3 50 ±5 ±10 ±3 ±3 0.6 10 5 15 20 70 2.9 2.75 21 1 12 1.2 2 ±3 ±3 50 ±5 ±10 ±1.5 ±1.5 0.6 10 6 15 20 100 % % % 21 12 mV μV/°C V V pF MΩ μA ns ns mV p-p ADV3219/ADV3220 Parameter POWER SUPPLIES Supply Current Conditions Supply Voltage Range PSR Min ADV3219 Typ Max ADV3220 Typ Max Unit V+, output enabled, no load V+, output disabled (EN high) 7 1.6 8 2.0 7.5 1.8 9 2.2 mA mA V−, output enabled, no load V−, output disabled (EN high) 7 1.6 8 2.0 7.5 1.8 9 2.2 mA mA ±5.5 V dB dB +85 °C °C/W ±4.5 f = 100 kHz f = 1 MHz TEMPERATURE Operating Temperature Range Operating Junction-to-Ambient Thermal Impedance, θJA Min Still air Still air ±5.5 ±4.5 −72 −62 −40 −69 −60 +85 85 −40 85 Table 2. Logic Levels VIH SELECT, EN VIL SELECT, EN IIH SELECT, EN IIL SELECT, EN +2.0 V minimum +0.8 V maximum ±2 μA maximum ±2 μA maximum Rev. 0 | Page 4 of 20 ADV3219/ADV3220 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 3. Rating 12 V V− to V+ 0 to V+ (V+ − 1 V) to (V− + 1 V) Momentary 50 mA −65°C to +150°C −40°C to +85°C 150°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead LFCSP θJA 85 θJC 23 Packaged in an 8-lead LFCSP, the ADV3219 and ADV3220 junction-to-ambient thermal impedance (θJA) is 85°C/W. For longterm reliability, the maximum allowed junction temperature of the die, TJ, should not exceed 125°C. Temporarily exceeding this limit can cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Figure 2 shows the range of the allowed internal die power dissipations that meet these conditions over the −40°C to +85°C ambient temperature range. When using Figure 2, do not include the external load power in the maximum power calculation, but do include the load current through the die output transistors. 1.5 TJ = 125°C MAXIMUM POWER (W) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The ADV3219/ADV3220 are operated with ±5 V supplies and can drive loads down to 150 Ω, resulting in a wide range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. 1.2 0.9 0.6 Unit °C/W 0.3 15 25 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 08649-002 Parameter Supply Voltage (V+ − V−) Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Output) Output Short-Circuit Duration Current Temperature Storage Temperature Range Operating Temperature Range Junction Temperature Figure 2. Maximum Die Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. 0 | Page 5 of 20 ADV3219/ADV3220 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN0 1 8 SELECT GND 2 ADV3219/ ADV3220 7 EN IN1 3 TOP VIEW (Not to Scale) 6 OUT 5 V– NOTES 1. CONNECT THE EXPOSED PAD TO GROUND. 08649-003 V+ 4 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic IN0 GND IN1 V+ V− OUT EN Descriptions Analog Input. Ground. Analog Input. Positive Power Supply. Negative Power Supply. Analog Output. Output Enable (Low True). 8 N/A 1 SELECT EP Logic Input for Analog Input Selection. Exposed Pad. Connect the exposed pad to ground. 1 N/A means not applicable. Table 6. Truth Table SELECT 0 1 0 1 EN OUT IN0 IN1 High-Z High-Z 0 0 1 1 Rev. 0 | Page 6 of 20 ADV3219/ADV3220 TYPICAL PERFORMANCE CHARACTERISTICS 4 3 2 1 0 –1 3 2 1 0 –1 4pF GAIN (dB) 0pF –2 –3 –4 –5 –6 –7 –8 2pF –9 –10 10pF 10 100 1k 10k FREQUENCY (MHz) 1 10 100 1k 10k FREQUENCY (MHz) Figure 7. ADV3220 Small Signal Frequency Response with Capacitive Loads, 200 mV p-p Output GAIN (dB) 4pF 0pF 10pF 10 100 1k 10k FREQUENCY (MHz) 4pF 2pF 0pF 10pF 1 10 100 1k 10k FREQUENCY (MHz) Figure 5. ADV3219 Large Signal Frequency Response with Capacitive Loads, 2 V p-p Output 0.2 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 08649-008 2pF 08649-005 Figure 8. ADV3220 Large Signal Frequency Response with Capacitive Loads, 2 V p-p Output 0.2 0pF 2pF 4pF 10pF 0.1 VOUT (V) 0.1 0pF 2pF 4pF 10pF 0 –0.1 –0.2 0 5 10 TIME (ns) 15 20 08649-006 –0.1 0 Figure 6. ADV3219 Small Signal Pulse Response vs. Capacitive Load, 200 mV p-p Output –0.2 0 5 10 TIME (ns) 15 20 08649-009 GAIN (dB) 10pF 4 1 VOUT (V) 0pF –11 –12 Figure 4. ADV3219 Small Signal Frequency Response with Capacitive Loads, 200 mV p-p Output 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 2pF –9 –10 –11 –12 1 4pF –2 –3 –4 –5 –6 –7 –8 08649-007 4 08649-004 GAIN (dB) VS = ±5 V, TA = 25°C, RL = 150 Ω, CL = 4 pF, ADV3219 at G = +1, ADV3220 at G = +2, unless otherwise noted. Figure 9. ADV3220 Small Signal Pulse Response vs. Capacitive Load, 200 mV p-p Output Rev. 0 | Page 7 of 20 ADV3219/ADV3220 2 2 0pF 2pF 4pF 10pF 1 VOUT (V) 0 0 –1 –1 0 5 10 15 –2 08649-010 –2 20 TIME (ns) 0 5 10 15 08649-013 VOUT (V) 1 0pF 2pF 4pF 10pF 20 TIME (ns) Figure 10. ADV3219 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p Output Figure 13. ADV3220 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p Output 3000 1.5 4000 2000 1.0 1.5 3000 1.0 0.5 dv/dt 0 0 –1000 –0.5 0.5 1000 dv/dt 0 0 VOUT (V) SLEW RATE (V/µs) 1000 VOUT (V) SLEW RATE (V/µs) 2000 –1000 –0.5 –2000 VOUT –2000 VOUT –1.0 –1.0 –3000 1.0 1.5 2.0 2.5 3.0 3.5 –1.5 4.0 –4000 TIME (ns) 0 2.0 2.5 3.0 3.5 4000 VOUT –1.5 4.0 1.5 3000 2000 1.0 SLEW RATE (V/µs) 1000 dv/dt 0 –1000 VOUT (V) 0.5 –0.5 1.0 VOUT 2000 0.5 1000 dv/dt 0 0 –1000 –0.5 –2000 –2000 –1.0 –1.0 –3000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –1.5 4.0 TIME (ns) –4000 Figure 12. ADV3219 Large Signal Falling Slew Rate with 4 pF Load, 2 V p-p Output 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –1.5 4.0 TIME (ns) Figure 15. ADV3220 Large Signal Falling Slew Rate with 4 pF Load, 2 V p-p Output Rev. 0 | Page 8 of 20 08649-015 –3000 08649-012 SLEW RATE (V/µs) 1.5 Figure 14. ADV3220 Large Signal Rising Slew Rate with 4 pF Load, 2 V p-p Output 1.5 0 1.0 TIME (ns) Figure 11. ADV3219 Large Signal Rising Slew Rate with 4 pF Load, 2 V p-p Output 3000 0.5 08649-014 0.5 VOUT (V) 0 08649-011 –3000 ADV3219/ADV3220 1.5 1.5 2.1 FALLING EDGE 1.0 1.9 2.1 FALLING EDGE 1.0 1.9 1.7 1.7 1.3 VOUT (V) 1.5 SELECT 0 –0.5 1.5 SELECT 0 1.3 –0.5 1.1 1.1 –1.0 0.9 –1.5 10 0.7 30 20 TIME (ns) 0.9 –1.5 08649-016 0 RISING EDGE 0 10 TIME (ns) Figure 16. ADV3219 Switching Time 0.5 0.7 30 20 Figure 19. ADV3220 Switching Time 0.5 6 0.4 6 0.4 5 5 4 3 OUTPUT 2 –0.1 –0.2 VOUT (V) 0.1 4 0.2 EN (V) 0.2 0 EN 0.3 0.1 3 OUTPUT 0 2 –0.1 –0.2 1 –0.3 EN (V) EN 0.3 1 –0.3 0 0 –0.4 10 20 30 40 –1 50 –0.5 TIME (ns) 0 10 30 40 Figure 20. ADV3220 Enable Glitch 3 2.1 2.1 EN EN 1.9 1.7 1.5 0 1.3 INPUT –1V –1 INPUT +0.5V 1 VOUT (V) INPUT +1V 1 1.9 2 EN (V) 2 –2 1.5 1.3 INPUT –0.5V –1 1.1 –2 10 20 TIME (ns) 0.7 30 08649-018 0.9 –3 1.7 0 1.1 0 –1 50 TIME (ns) Figure 17. ADV3219 Enable Glitch 3 20 EN (V) 0 08649-017 –0.5 08649-020 –0.4 Figure 18. ADV3219 Enable On Timing 0.9 –3 0 10 20 TIME (ns) Figure 21. ADV3220 Enable On Timing Rev. 0 | Page 9 of 20 0.7 30 08649-021 VOUT (V) 08649-019 RISING EDGE –1.0 VOUT (V) SELECT (V) 0.5 SELECT (V) VOUT (V) 0.5 ADV3219/ADV3220 1.5 1.5 2.1 INPUT +1V INPUT +0.5V 1.9 1.0 2.1 1.9 1.0 1.7 1.7 1.5 1.3 –0.5 1.5 EN 0 1.3 –0.5 1.1 1.1 –1.0 0.9 –1.5 10 20 0.7 40 30 TIME (ns) 0.9 –1.5 08649-022 0 INPUT –0.5V 0 20 0.7 40 30 TIME (ns) Figure 22. ADV3219 Disable Timing 100 10 Figure 25. ADV3220 Disable Timing 100 6 80 6 80 5 5 60 4 3 OUTPUT 0 2 –20 –40 20 VOUT (V) 20 3 OUTPUT 0 2 –20 –40 1 –60 4 40 SELECT (V) 40 1 –60 SELECT SELECT (V) 60 SELECT 0 0 –80 0 10 20 30 40 –1 50 –100 08649-023 –100 TIME (ns) 0 30 40 –1 50 Figure 26. ADV3220 Switching Glitch Rising Edge 100 6 SELECT 80 20 TIME (ns) Figure 23. ADV3219 Switching Glitch Rising Edge 100 10 08649-026 –80 6 SELECT 80 5 5 60 4 3 OUTPUT 0 2 –20 –40 20 VOUT (V) 20 4 40 SELECT (V) 40 3 OUTPUT 0 2 –20 –40 1 –60 SELECT (V) 60 1 –60 0 0 –80 –100 0 10 20 30 40 TIME (ns) –1 50 08649-024 –80 –100 Figure 24. ADV3219 Switching Glitch Falling Edge 0 10 20 30 40 TIME (ns) Figure 27. ADV3220 Switching Glitch Falling Edge Rev. 0 | Page 10 of 20 –1 50 08649-027 VOUT (V) 08649-025 INPUT –1V –1.0 VOUT (V) EN (V) EN 0 VOUT (V) 0.5 EN (V) VOUT (V) 0.5 ADV3219/ADV3220 5 5 1.25 1.25 INPUT 4 4 3 0.75 0.75 0.25 ERROR 0 –1 –0.25 ERROR (%) 1 1 0.25 ERROR 0 –1 –0.25 OUTPUT (V) 2 OUTPUT (V) 2 OUTPUT –2 –2 –3 –0.75 –3 –0.75 OUTPUT –4 0 1 2 3 4 5 6 7 8 9 –1.25 10 08649-028 –5 TIME (ns) –5 0 1 3 4 5 6 7 8 9 –1.25 10 TIME (ns) Figure 28. ADV3219 Settling Time 2 V Output Step Figure 31. ADV3220 Settling Time 2 V Output Step 10 10 0 0 –10 –10 –20 –20 –30 PSR (dB) PSR (dB) 2 08649-031 –4 PSR (V–) –40 –50 –30 PSR (V–) –40 –50 PSR (V+) –60 –60 –70 –70 –80 –80 10 100 1k 10k FREQUENCY (MHz) –90 0.1 1 Figure 29. ADV3219 PSR 180 160 160 140 140 NOISE (nV/ Hz) 200 180 120 100 80 10M 100M 80 40 20 20 10M FREQUENCY (Hz) 100M 08649-030 60 1M 10k 100 40 100k 1k 120 60 10k 100 Figure 32. ADV3220 PSR 200 0 1k 10 FREQUENCY (MHz) Figure 30. ADV3219 Noise vs. Frequency 0 1k 10k 100k 1M FREQUENCY (Hz) Figure 33. ADV3220 Noise vs. Frequency Rev. 0 | Page 11 of 20 08649-033 1 08649-029 –90 0.1 08649-032 PSR (V+) NOISE (nV/ Hz) ERROR (%) INPUT 3 –20 –20 –30 –30 –40 –40 –50 –50 CROSSTALK (dB) –70 –80 –60 –70 –80 –90 –90 –100 –100 10 100 1k 10k FREQUENCY (MHz) –110 1 –30 –30 –40 –40 FEEDTHROUGH (dB) FEEDTHROUGH (dB) –20 –50 –60 –70 –80 –60 –70 –80 –100 –100 –110 10k FREQUENCY (MHz) 08649-036 –90 1k –110 1 10 100 1k 10k FREQUENCY (MHz) Figure 35. ADV3219 Off Isolation vs. Frequency Figure 38. ADV3220 Off Isolation vs. Frequency 1M 1M 100k INPUT IMPEDANCE (Ω) 100k 10k 1k 100 10k 1k 100 10 1 1 10 100 1k FREQUENCY (MHz) 10 08649-041 DISABLED OUTPUT IMPEDANCE (Ω) 10k –50 –90 100 1k Figure 37. ADV3220 Crosstalk vs. Frequency –20 10 100 FREQUENCY (MHz) Figure 34. ADV3219 Crosstalk vs. Frequency 1 10 08649-039 1 08649-034 –110 08649-037 –60 1 10 100 1k FREQUENCY (MHz) Figure 36. ADV3219 Disabled Output Impedance vs. Frequency Figure 39. ADV3219/ADV3220 Input Impedance vs. Frequency Rev. 0 | Page 12 of 20 08649-040 CROSSTALK (dB) ADV3219/ADV3220 ADV3219/ADV3220 ENABLED OUTPUT IMPEDANCE (Ω) 10k 1k 100 10 1 0.1 1 10 100 1k FREQUENCY (MHz) 1k 100 10 1 0.1 0.01 1 10 08649-045 0.01 08649-042 ENABLED OUTPUT IMPEDANCE (Ω) 10k 1k 100 FREQUENCY (MHz) Figure 40. ADV3219 Enabled Output Impedance vs. Frequency Figure 43. ADV3220 Enabled Output Impedance vs. Frequency –10 5 5 –30 –40 –50 10 100 1k FREQUENCY (MHz) 3 2 OUTPUT 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 –4 –5 100 –5 08649-043 1 4 3 2 –60 –70 4 0 20 40 60 80 08649-046 OUTPUT VOLTAGE (V) INPUT S11 (dB) –20 INPUT VOLTAGE (V) INPUT TIME (ns) Figure 41. ADV3219/ADV3220, S11 (Measured on Evaluation Board) Figure 44. ADV3219 Overdrive Recovery 1M 0 1k 100 –20 –30 –40 –50 –60 –70 HD2 0dBm HD3 0dBm HD2 10dBm HD3 10dBm 10 –80 1 1 10 100 1k FREQUENCY (MHz) –90 10 100 1k INPUT FREQUENCY (MHz) Figure 42. ADV3220 Disabled Output Impedance vs. Frequency Figure 45. ADV3220 Harmonic Distortion, RL = 100 Ω, CL = 4 pF Rev. 0 | Page 13 of 20 08649-047 HARMONIC DISTORTION (dBc) 10k 08649-044 DISABLED OUTPUT IMPEDANCE (Ω) –10 100k ADV3219/ADV3220 60 35 30 25 20 15 10 5 1k INPUT FREQUENCY (MHz) 1.0 OUTPUT 1 0.5 0 0 –1 –0.5 –2 –1.0 –3 –1.5 –4 –2.0 –5 –2.5 100 0 20 40 60 80 TIME (ns) Figure 47. ADV3220 Overdrive Recovery OUTPUT P1dB GAIN COMPRESSION (dBm) 2 INPUT VOLTAGE (V) 1.5 100 1k 24 22 20 18 16 14 12 10 8 6 4 2 0 10 08649-049 OUTPUT VOLTAGE (V) 3 10 Figure 48. ADV3220 Input Second-Order Intercept, RL = 100 Ω, CL = 4 pF, 0 dBm Input 2.5 2.0 20 INPUT FREQUENCY (MHz) INPUT 4 30 0 10 Figure 46. ADV3220 Input Third-Order Intercept, RL = 100 Ω, CL = 4 pF, 0 dBm Input 5 40 100 INPUT FREQUENCY (MHz) 1k 08649-051 100 08649-048 0 10 50 08649-050 INPUT SECOND-ORDER INTERCEPT (dBm) INPUT THIRD-ORDER INTERCEPT (dBm) 40 Figure 49. ADV3220 Output P1dB Gain Compression, RL = 100 Ω, CL = 4 pF Rev. 0 | Page 14 of 20 ADV3219/ADV3220 CIRCUIT DIAGRAMS V+ IN 08649-052 1.0pF (ADV3219) 1.2pF (ADV3220) V– 08649-055 OUT 0.6pF Figure 53. ADV3219/ADV3220 Disabled Output Figure 50. ADV3219/ADV3220 Analog Input V+ OUT 1kΩ V– 08649-056 08649-053 SELECT, EN Figure 54. ADV3219/ADV3220 Logic Input Figure 51. ADV3219 Enabled Analog Output V+ OUT GND 08649-054 1kΩ SELECT, EN INx, OUT V– GND 08649-057 1kΩ Figure 55. ADV3219/ADV3220 ESD Schematic Figure 52. ADV3220 Enabled Analog Output Rev. 0 | Page 15 of 20 ADV3219/ADV3220 THEORY OF OPERATION The ADV3219/ADV3220 are dual-supply, high performance 2:1 analog multiplexers, optimized for switching between multiple video sources. High peak slew rates enable wide bandwidth operation for large input signals. Internal compensation provides for high phase margin, allowing low overshoot and fast settling for pulsed inputs. Low enabled and disabled power consumption make the ADV3219 and ADV3220 ideal for constructing larger arrays. The multiplexer is organized as two input transconductance stages tied in parallel with a single output transimpedance stage followed by a unity-gain buffer. Internal voltage feedback sets the gain. The ADV3219 is configured as a gain of 1, whereas the ADV3220 uses a resistive feedback network and ground buffer to realize gain-of-2 operation (see Figure 56). The ground reference for the ADV3220 is taken from the exposed pad of the package. To minimize spurious signals on the output, tie the exposed pad to a low inductance, quiet ground plane. When not in use, place the OUT pin in a low power, high impedance disabled mode via the EN logic input. This mode provides a wideband high impedance on the OUT pin that is useful when paralleling multiple ADV3219/ADV3220 devices in a system to create larger switching arrays. Switching between the inputs is controlled with the SELECT logic input, with IN0 selected when the SELECT line is a logical low and IN1 selected when the select line is a logical high. When EN is a logical low, the output is enabled and connected to one of the two inputs depending on the state of the SELECT pin. When EN is a logical high, the output is placed in a high impedance mode. When not in use, the output can be placed in a low power, high impedance disabled mode via the EN logic input. V+ IN0 ×1 OUT V– V+ IN1 V– 1kΩ V+ V– 08649-058 1kΩ GND Figure 56. Conceptual Diagram of ADV3220 Rev. 0 | Page 16 of 20 ADV3219/ADV3220 APPLICATIONS INFORMATION The ADV3219 and ADV3220 are very high speed muxes that can be used to switch video or RF signals. The low output impedance of the ADV3219/ADV3220 allows the output environment to be optimized for use in 75 Ω or 50 Ω systems by choosing the appropriate series termination resistor. For composite video applications, the ADV3220 (gain of +2) is typically used to provide compensation for the loss of the output termination. CIRCUIT LAYOUT Use of proper high speed design techniques is important to ensure optimum performance. Use a low inductance ground plane for power supply bypassing and to provide high quality return paths for the input and output signals. For best performance, it is recommended that power supplies be bypassed with 0.1 μF ceramic capacitors placed as close to the body of the device as possible. To provide stored energy for lower frequency, high current output driving, place 10 μF tantalum capacitors farther from the device. The input and output signal paths should be stripline or microstrip controlled impedance. Video systems typically use a 75 Ω characteristic impedance, whereas RF systems typically use 50 Ω. Various calculators are available to calculate the trace geometry that is required to produce the proper characteristic impedance. TERMINATION For a controlled impedance situation, termination resistors are required at the inputs and output of the device. The input termination should be a shunt resistor to ground with a value matching the characteristic impedance of the input trace. To reduce reflections, place the input termination resistor as close to the device input pin as possible. To minimize the input-toinput crosstalk, it is important to use a low inductance shield between input traces to isolate each input. Consideration of ground current paths must be taken to minimize loop currents in the shields to prevent them from providing a coupling medium for crosstalk. For proper matching, the output series termination resistor should be the same value as the characteristic impedance of the output trace and placed as close to the output of the device as possible. This placement reduces the high frequency effect of series parasitic inductance, which can affect gain flatness and −3 dB bandwidth. CAPACITIVE LOAD A high frequency output generally has difficulty when driving a capacitive load. The usual response is some peaking in the frequency domain or some overshoot in the time domain. If these effects become too large, oscillation can result. The response of the device under various capacitive loads is shown in Figure 4 to Figure 10 and in Figure 13. If a condition arises wherein excessive load capacitance is encountered and the overshoot is too great or the part oscillates, use a small series resistor of a few tens of ohms to improve the performance. Rev. 0 | Page 17 of 20 ADV3219/ADV3220 OUTLINE DIMENSIONS 2.54 2.44 2.34 3.10 3.00 SQ 2.90 0.50 BSC 8 5 1.80 1.70 1.60 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED 111809-A PIN 1 INDEX AREA Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-11) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV3219ACPZ ADV3219ACPZ-RL ADV3219ACPZ-R7 ADV3220ACPZ ADV3220ACPZ-RL ADV3220ACPZ-R7 ADV3219-EVALZ ADV3220-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead LFCSP_WD 8-Lead LFCSP_WD, 13” Tape and Reel 8-Lead LFCSP_WD, 7” Tape and Reel 8-Lead LFCSP_WD 8-Lead LFCSP_WD, 13” Tape and Reel 8-Lead LFCSP_WD, 7” Tape and Reel Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 Package Option CP-8-11 CP-8-11 CP-8-11 CP-8-11 CP-8-11 CP-8-11 Branding Code F0H F0H F0H F0J F0J F0J ADV3219/ADV3220 NOTES Rev. 0 | Page 19 of 20 ADV3219/ADV3220 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08649-0-4/10(0) Rev. 0 | Page 20 of 20