TI1 BQ7790400PW Open wire stackable lithium-ion battery protector Datasheet

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bq77904, bq77905
SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
bq77905, bq77904 3-5S Ultra Low-Power Voltage, Current, Temperature,
and Open Wire Stackable Lithium-ion Battery Protector
1 Features
3 Description
•
The bq77904 and bq77905 devices are low-power
battery pack protectors that implement a suite of
voltage, current, and temperature protections without
microcontroller (MCU) control. Protection thresholds
and delays are factory-programmed and available in
a variety of configurations. Separate overtemperature
and undertemperature thresholds for discharge (OTD
and UTD) and charge (OTC and UTC) are provided
for added flexibility.
1
•
•
•
•
•
•
Voltage Protection (Accuracy ±10 mV)
– Overvoltage: 3 V to 4.575 V
– Undervoltage: 1.2 V to 3 V
Open Cell and Open Wire Detection (OW)
Current Protection
– Overcurrent Discharge 1: –10 mV to –85 mV
– Overcurrent Discharge 2: –20 mV to 170 mV
– Short Circuit Discharge: –40 mV to 340 mV
– Accuracy ±20% for ≤ 20 mV, ±30% for > 20
mV across full temperature
Temperature Protection
– Overtemperature Charge: 45°C or 50°C
– Overtemperature Discharge: 65°C or 70°C
– Undertemperature Charge: –5°C or 0°C
– Undertemperature Discharge: –20°C or –10°C
Additional Features
– Independent Charge (CHG) and Discharge
(DSG) FET Drivers
– SimpleStack Interface for Easy Stacking
– 36-V Absolute Maximum Rating Per Cell Input
– Built-In-Self-Test Functions For High Reliability
Normal Mode: 6 µA (bq77904/bq77905)
Shutdown Mode: 0.5 µA Maximum
The device achieves pack protection via the
integrated independent CHG and DSG low-side
NMOS FET drivers, which may be disabled via two
control pins. These control pins may also be used to
achieve cell protection solutions for higher series (6S
and beyond) in a simple and economical manner. To
do this, simply cascade a higher device CHG and
DSG outputs to the immediate lower device control
pins. For reduced component count, all protection
faults use internal delay timers.
Device Information(1)
PART NUMBER
PACKAGE
bq77904
TSSOP (20)
bq77905
•
Power Tools, Garden Tools
Start-Stop Battery Packs
Lead-Acid (PbA) Replacement Batteries
Light Electric Vehicles
Energy Storage Systems, Uninterruptible Power
Supplies (UPS)
10.8 V to 72 V Packs
6.50 × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
BODY SIZE (NOM)
PACK+
VDD
VTB
VC5
TS
bq77094/5
LD
Vss
SRP
SRN
DSG
CHGU
CTRD
CTRC
VDD
VTB
VC5
TS
bq77094/5
LD
Vss
SRP
SRN
DSG
CHG
PACK-
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq77904, bq77905
SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 25
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application ................................................. 32
9.3 System Examples .................................................. 36
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
Changes from Original (June 2016) to Revision A
•
2
Page
Changed the device From: Product Preview To: Production ................................................................................................. 1
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SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
5 Device Comparison
DEVICE
NUMBER OF
CELLS
bq77904
3, 4
bq77905
3, 4, 5
PROTECTIONS
TYPICAL NORMAL
MODE CURRENT (µA)
PACKAGE
6
20-TSSOP
OV, UV, OW, OTD, OTC, UTD, UTC, OCD1,
OCD2, SCD, CTRC, CTRD
Unless specified, the devices in Table 1 and Table 2 are default with state comparator enabled with 2 mV
threshold. Filtered fault detection is used by default. Contact Texas Instruments for new configuration option or
device in preview.
Table 1. bq77904 Device Configuration
(1)
(2)
N
0
(disable)
Delay (s)
200
Threshold (mV)
1
Delay (ms)
Load Removal Recovery(Y/N)
2800
Current Fault
Recovery
SCD
Threshold (mV)
Hyst(mV)
100
OCD2
Delay (ms)
Delay(s)
1
OCD1
Threshold (mV)
Thresh (mV)
4225
Current(nA)
Hyst(mV)
OW
Delay(s)
Part Number
bq7790400 (2)
UV
Threshold(mV)
OV
Method
40
1420
80
700
160
0
Load Removal
Temperature (°C) (1)
OTD
OTC
UTD
OTC
70
50
-20
-5
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10kΩ resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
Product Preview
Table 2. bq77905 Device Configuration
Current Fault
Recovery
Load Removal Recovery(Y/N)
Current(nA)
Threshold (mV)
Delay (ms)
Threshold (mV)
Delay (ms)
Threshold (mV)
Delay (s)
Temperature (°C) (1)
Hyst(mV)
SCD
Delay(s)
OCD2
Thresh (mV)
OCD1
Hyst(mV)
OW
Delay(s)
UV
Threshold(mV)
OV
Method
OTD
OTC
UTD
OTC
bq7790500
4200
0.5
100
2600
1
400
Y
100
30
1420
50
700
120
1
Load Removal
+ Delay
70
50
-20
0
bq7790501 (2)
4200
0.5
100
2600
1
400
N
100
30
1420
50
700
120
1
Load Removal
+ Delay
70
50
-20
0
(2)
4250
1
200
2700
1
200
Y
100
85
700
120
350
240
—
Load Removal
70
50
-20
-5
bq7790503 (2)
4200
1
100
2700
2
400
Y
100
80
1420
160
350
320
1
Load Removal
+ Delay
70
50
-10
-5
bq7790504 (2)
4250
0.5
200
2700
1
200
Y
100
80
350
160
5
200
1
Load Removal
+ Delay
70
50
-10
-5
Part Number
bq7790502
(1)
(2)
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10kΩ resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
Product Preview
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6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
VDD
1
20
DVSS
AVDD
2
19
CTRD
VC5
3
18
CTRC
VC4
4
17
CCFG
VC3
5
16
VTB
VC2
6
15
TS
VC1
7
14
LD
AVSS
8
13
CHG
SRP
9
12
CHGU
SRN
10
11
DSG
Not to scale
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AVDD
2
O
Analog supply (only connect to a capacitor)
AVSS
8
P
Analog ground
CCFG
17
I
Cell in series-configuration input
CHG
13
O
CHG FET driver, use on a single device or on the bottom device of a stack
configuration
CHGU
12
O
CHG FET signal, use for upper device of a stack configuration to feed the CHG signal
to the CTRC pin of the lower device
CTRC
18
I
CTRD
19
I
DSG
11
O
DSG FET driver
DVSS
20
P
Digital ground
LD
14
I
PACK– load removal detection
SRN
10
I
Current sense input connecting to the pack– side of sense resistor
SRP
9
I
Current sense input connecting to the battery side of sense resistor
TS
15
I
Thermistor measurement input. Connect a 10kΩ resistor to AVSS pin if the function is
not used
VC1
7
I
VC2
6
I
VC3
5
I
VC4
4
I
VC5
3
I
Cell voltage sense inputs (pin 3 must be connected to pin 4 on bq77904)
VDD
1
P
Supply voltage
VTB
16
O
Thermistor bias output
(1)
4
CHG and DSG override inputs
Cell voltage sense inputs
I = Input, O = Output, P = Power
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). All values are referenced to VSS unless otherwise noted.
(1)
VDD, VC5, VC4, VC3, VC2, VC1, CCFG, CTRD, CTRC
VI
Input voltage
MAX
UNIT
36
V
LD
–30
20
V
SRN, SRP, TS, AVDD, CCFG
–0.3
3.6
V
DSG, CHGU
–0.3
20
V
CHG
–30
20
V
VTB
–0.3
VO
Output voltage range
II
Input current
LD, CHG
II
Input current
IO
IO
3.6
V
500
µA
CHGU, DSG
1
mA
Output current
CHG
1
mA
Output current
CHGU, DSG
1
mA
150
°C
Storage temperature, Tstg
(1)
MIN
–0.3
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±1000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) .
MIN
VBAT
VI
Supply voltage range
Input voltage range
Output voltage range
TSTG
Operating free-range temperature
MAX
3
25
VC5-VC4, VC4-VC3, VC3-VC2, VC2-VC1,
VC1-VSS
0
5
CTRD, CTRC
0
(VDD + 5)
0
AVDD
–0.2
0.8
CCFG
SRN, SRP
VO
NOM
VDD
LD
0
16
TS
0
VTB
CHG, CHGU, DSG
0
16
VTB, AVDD
0
3
–40
85
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UNIT
V
V
V
°C
5
bq77904, bq77905
SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
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7.4 Thermal Information
THERMAL METRIC
bq77904
bq77905
(1)
UNITS
PW (TSSOP)
16 PINS
θJA
Junction-to-ambient thermal resistance
TBD
θJCtop
Junction-to-case (top) thermal resistance
TBD
θJB
Junction-to-board thermal resistance
TBD
ψJT
Junction-to-top characterization parameter
TBD
ψJB
Junction-to-board characterization parameter
TBD
θJCbot
Junction-to-case (bottom) thermal resistance
TBD
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
Typical values stated at TA = 25ºC and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA =
–40ºC to 85ºC and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(POR)
POR threshold
VDD rising, 0 to 6 V
V(SHUT)
Shutdown threshold
VDD falling, 6 to 0 V
V(AVDD)
AVDD voltage
C(VDD) = 1 µF
2
2.1
4
V
3.25
V
2.5
3.25
V
9
µA
SUPPLY AND LEAKAGE CURRENT
ICC
Normal mode current
(bq77904/bq77905)
Cell1 through Cell5 = 4 V,
VDD = 20 V (bq77905)
6
I(CFAULT)
Fault condition current
State comparator on
8
IOFF
Shutdown mode current
VDD < VSHUT
ILKG(OW_DIS)
Input leakage current at VCx pins
All cell voltages = 4 V,
Open Wire disable configuration
ILKG(100nA)
Open-wire sink current at VCx
pins
ILKG(200nA)
ILKG(400nA)
12
µA
0.5
µA
–100
0
100
nA
All cell voltages = 4 V,
100 nA configuration
30
110
175
nA
Open-wire sink current at VCx
pins
All cell voltages = 4 V,
200 nA configuration
95
210
315
nA
Open-wire sink current at VCx
pins
All cell voltages = 4 V,
400 nA configuration
220
425
640
nA
PROTECTION ACCURACIES
VOV
Overvoltage programmable
threshold range
3000
4575
mV
VUV
Undervoltage programmable
threshold range
1200
3000
mV
TA = 25ºC, OV detection accuracy
–10
10
mV
TA = 25ºC, UV detection accuracy
–18
18
mV
TA = 0 to 60ºC
–28
26
mV
TA = –40 to 85ºC
–40
40
mV
V(VA)
OV, UV, detection accuracy
VHYS(OV)
OV hysteresis programmable
threshold range
0
400
mV
VHYS(UV)
UV hysteresis programmable
threshold range
200
800
mV
VOTD
Overtemperature in discharge
programmable threshold
(1)
6
Threshold for 65°C (1)
Threshold for 70°C
(1)
17.48
20.56
23.64
%VTB
15.49
18.22
20.95
%VTB
Based on a 10 KΩ pull-up and 103AT thermistor.
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Electrical Characteristics (continued)
Typical values stated at TA = 25ºC and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA =
–40ºC to 85ºC and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
VOTD(REC)
VOTC
VOTC(REC)
Overtemperature in charge
programmable threshold
Undertemperature in discharge
programmable threshold
VUTD(REC)
Undertemperature in discharge
recovery
VUTC(REC)
TYP
MAX
UNIT
22.20
26.12
30.04
%VTB
Recovery threshold at 60°C for
when VOTD is at 70°C (1)
19.72
23.2
26.68
%VTB
Threshold for 45°C (1)
28.00
32.94
37.88
%VTB
(1)
Threshold for 50°C
Overtemperature in charge
recovery
VUTD
VUTC
TEST CONDITIONS
Overtemperature in discharge
recovery
MIN
Recovery threshold at 55°C for
when VOTD is at 65°C (1)
24.97
29.38
33.79
%VTB
Recovery threshold at 35°C for
when VOTD is at 45°C (1)
34.82
40.97
47.12
%VTB
Recovery threshold at 40°C for
when VOTD is at 50°C (1)
31.30
36.82
42.34
%VTB
(1)
74.07
87.14
100.21
%VTB
Threshold for –10°C (1)
68.80
80.94
93.08
%VTB
Recovery threshold at –10°C for
when VUTD is at –20°C (1)
68.80
80.94
93.08
%VTB
Recovery threshold at 0°C for
when VUTD is at –10°C (1)
62.20
73.18
84.16
%VTB
Threshold for –5°C (1)
65.64
77.22
88.80
%VTB
Threshold for 0°C (1)
62.20
73.18
84.16
%VTB
Recovery threshold at 5°C for
when VUTC is at –5°C (1)
58.48
68.80
79.12
%VTB
Recovery threshold at 10°C for
when VUTC is at 0°C (1)
54.59
64.23
73.86
%VTB
Threshold for –20°C
Undertemperature in charge
programmable threshold
Undertemperature in Charge
Recovery
VOCD1
Overcurrent discharge 1 programmable threshold range,
(VSRP – VSRN)
–85
–10
mV
VOCD2
Overcurrent discharge 2 programmable threshold range,
(VSRP – VSRN)
–20
–170
mV
VSCD
Short circuit discharge programmable threshold range, (VSRP – VSRN)
–40
–340
mV
VCCAL
OCD1 detection accuracy at lower
VOCD1 > –20 mV
thresholds
–30%
30%
VCCAH
OCD1, OCD2, SCD detection
accuracy
VOCD1 ≤ –20 mV; all OCD2 and
SCD threshold ranges
–20%
20%
VOW
Open-wire fault voltage threshold
at VCx per cell with respect to
VCx-1
Voltage falling on VCx, 3.6 V to
0V
450
VOW(HYS)
Hysteresis for open wire fault
Voltage rising on VCx, 0 V to
3.6 V
500
550
100
mV
mV
CHARGE AND DISCHARGE FET DRIVERS
VDD ≥ 12 V, CL = 10 nF
11
VDD < 12 V, CL = 10 nF
VDD - 1
12
14
V
VDD
V
0.5
V
V(FETON)
CHG/CHGU/DSG on
V(FETOFF)
CHG/CHGU/DSG off
R(CHGOFF)
CHG off resistance
CHG off for > tCHGPDN and pin
held at 2V
0.5
R(DSGOFF)
CHGU/DSG off resistance
CHGU/DSG off and pin held at 2V
10
16
Ω
ICHG(CLAMP)
CHG clamp current
CHG off and pin held at 18 V
450
µA
VCHG(CLAMP)
CHG clamp voltage
ICHG(CLAMP) = 300 µA
18
20.5
V
tCHGON
CHG on rise time
CL = 10 nF, 10% to 90%
50
150
µs
tDSGON
CHGU/DSG on rise time
CL = 10 nF, 10% to 90%
2
75
µs
tCHGOFF
CHG off fall time
CL = 10 nF, 90% to 10%
15
30
µs
tDSGOFF
CHGU/DSG off fall time
CL = 10 nF, 90% to 10%
5
15
µs
No load when CHG/CHGU/DSG is
off
16
kΩ
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Electrical Characteristics (continued)
Typical values stated at TA = 25ºC and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA =
–40ºC to 85ºC and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CTRC AND CTRD CONTROL
VCTR1
Enable FET driver (VSS)
With respect to VSS. Enabled <
MAX
VCTR2
Enable FET driver (Stacked)
Enabled > MIN
VCTR(DIS)
Disable FET driver
Disabled between MIN and MAX
VCTR(MAXV)
CTRC and CTRD clamp voltage
ICTR = 600nA
0.6
VDD + 2.2
V
2.04
VDD + 2.8
V
VDD + 4
VDD + 0.7
V
VDD + 5
V
tCTRDEG_ON)
(2)
CTRC and CTRD de-glitch for ON
signal
7
ms
tCTRDEG_OFF
(2)
CTRC and CTRD de-glitch for
OFF signal
7
ms
CURRENT STATE COMPARATOR
V(STATE_D1)
Discharge qualification threshold1
Measured at SRP-SRN
-3
–2
-1
mV
V(STATE_C1)
Charge qualification threshold1
Measured at SRP-SRN
1
2
3
mV
1.2
ms
tSTATE
(2)
State detection qualification time
LOAD REMOVAL DETECTION
VLD(CLAMP)
LD clamp voltage
I(LDCLAMP) = 300 µA
ILD(CLAMP)
LD clamp current
V(LDCLAMP) = 18 V
16
VLDT
LD threshold
Load removed < when VLDT
1.25
RLD(INT)
LD input resistance when enabled
Measured to VSS
tLD_DEG
LD detection de-glitch
18
20.5
V
450
µA
1.3
1.35
V
160
250
375
kΩ
1
1.5
2.3
ms
10
%AVDD
100
%AVDD
45
%AVDD
CCFG PIN
V(CCFGL)
CCFG threshold low (ratio of
VAVDD)
3 cell configuration
V(CCFGH)
CCFG threshold high (ratio of
VAVDD)
4 cell configuration
65
V(CCFGHZ)
CFG threshold high-Z (ratio of
VAVDD)
5 cell configuration, CCFG
floating, internally biased
25
tCCFG_DEG
(2)
CCFG de-glitch
33
6
ms
CUSTOMER TEST MODE
V(CTM)
Customer test mode entry voltage
at VDD
VDD > VC5 + V(CTM), TA = 25°C
8.5
50
10
V
tCTM_ENTRY
(3)
Delay time to enter and exit
customer test mode
VDD > VC5 + V(CTM), TA = 25°C
tCTM_DELAY
(3)
Delay time of faults while in
customer test mode
TA = 25°C
200
ms
Fault recovery time of OCD1,
OCD2, and SCD faults while in
customer test mode
1 s and 8 s options, TA = 25°C
100
ms
tCTM_OC_REC
(2)
(3)
8
(3)
ms
Not production tested parameters. Specified by design
Device is in no fault state prior to entering Customer Test Mode.
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7.6 Timing Requirements
MIN
TYP
MAX
0.5 s Delay Option
0.4
0.5
0.8
1 s Delay Option
0.8
1
1.4
2 s Delay Option
1.8
2
2.7
UNIT
PROTECTION DELAYS (1)
tOVn_DELAY
Overvoltage detection delay time
4.5 s Delay Option
tUVn_DELAY
Undervoltage detection delay time
4
4.5
5.2
1 s Delay Option
0.8
1
1.5
2 s Delay Option
1.8
2
2.7
4.5 s Delay Option
4
4.5
5.5
9 s Delay Option
8
9
10.2
s
s
tOWn_DELAY
Open-wire detection delay time
3.6
4.5
5.3
s
tOTC_DELAY
Overtemperature charge detection
delay time
3.6
4.5
5.3
s
tUTC_DELAY
Undertemperature charge detection
delay time
3.6
4.5
5.3
s
tOTD_DELAY
Overtemperature discharge
detection delay time
3.6
4.5
5.3
s
tUTD_DELAY
Undertemperature discharge
detection delay time
3.6
4.5
5.3
s
10 ms delay option
8
10
15
20 ms delay option
17
20
26
45 ms delay option
36
45
52
90 ms delay option
78
90
105
180 ms delay option
155
180
205
350 ms delay option
320
350
405
700 ms delay option
640
700
825
1420 ms delay option
1290
1420
1620
4
5
8
10 ms delay option
8
10
15
20 ms delay option
17
20
26
45 ms delay option
36
45
52
90 ms delay option
78
90
105
180 ms delay option
155
180
205
350 ms delay option
320
350
405
tOCD1_DELAY
Overcurrent 1 detection delay time
5 ms delay option
tOCD2_DELAY
tSCD_RELAY
tCD_REC
(1)
Overcurrent 2 detection delay time
700 ms delay option
640
700
825
Short-circuit detection delay time
360 µs delay option
220
400
610
Overcurrent 1, Overcurrent 2, and
Short-circuit recovery delay time
1 s option
0.8
1
1.4
9 s option
8
9
10.2
ms
ms
µs
s
Not production tested parameters. Specified by design
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7.7 Typical Characteristics
7.5
0.25
0.2
Shutdown Current (PA)
Normal Mode Current (PA)
7
6.5
6
5.5
5
0.15
0.1
0.05
4.5
4
-40
-15
10
35
Temperature (qC)
60
0
-40
85
-15
Figure 1. Normal Mode Current
60
85
D002
Figure 2. Shutdown Current
15
10
10
5
UV Error (mV)
5
0
-5
-10
0
-5
-10
-15
-15
-20
-40
-15
10
35
Temperature (qC)
60
-20
-40
85
-15
10
35
Temperature (qC)
D003
Figure 3. OV Error at 4.25 V Threshold
85
D004
Figure 4. UV Error at 2.8 V Threshold
0.2
0.1
60
4.0
2.5
0.05
3.5
0.0
2
±0.2
-0.1
±0.4
-0.15
-0.2
±0.6
-0.25
Error (in mV)
Error (in %)
-0.3
-0.35
±40
±20
0
20
40
60
2.5
1.5
2.0
1
1.5
1.0
Error (in mV)
Error (in %)
0
±1.0
±40
±20
0
20
40
60
0.5
0.0
80
Temperature (ºC)
C001
Figure 5. OCD1 Error at 40 mV Threshold
10
3.0
0.5
±0.8
80
Temperature (ºC)
OCD2 Error (mV)
-0.05
OCD1 Error (%)
OCD1 Error (mV)
0
OCD2 Error (%)
OV Error (mV)
10
35
Temperature (qC)
D001
C002
Figure 6. OCD2 Error at 60 mV Threshold
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Typical Characteristics (continued)
1.6
2.5
1.4
1.2
1.0
1.5
0.8
1
0.6
SCD Error(%)
SCD Error (mV)
2
0.4
0.5
Error (in mV)
Error (in %)
0
±40
±20
0
20
40
60
0.2
0.0
80
Temperature (ºC)
C003
Figure 7. SCD Error at 160 mV Threshold
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8 Detailed Description
8.1 Overview
The bq77904 and bq77905 families are full-feature stackable primary protectors for Li-ion/Li-polymer batteries.
The devices implement a suite of protections including:
• Cell voltage: overvoltage, undervoltage
• Current: Overcurrent discharge 1 and 2, short circuit discharge
• Temperature: overtemperature and undertemperature in charge and discharge
• PCB: cell open wire connection
• FET body diode protection
Protection thresholds and delays are factory-programmed and available in a variety of configurations.
The bq77904 supports 3S-to-4S cell configuration and bq77905 supports 3S-to-5S cell configuration. Up to 4
devices can be stacked to support ≥6S cell configuration, providing protections up to 20S cell configuration.
The device has built-in CHG and DSG drivers for low-side N-channel FET protection, which automatically opens
up the CHG and/or DSG FETs after protection delay time when a fault is detected. A set of CHG/DSG override is
provided to allow disabling of CHG and/or DSG driver externally. Although host system can use this function to
disable the FETs control, the main usage of these pins is to channel down the FET control signal from the upper
device to the lower device in a cascading configuration in ≥6S battery pack.
8.1.1 Device Functionality Summary
For brevity, in this and subsequent sections, a number of abbreviations will be used to identify specific fault
conditions. The fault descriptor abbreviations and their meanings are defined in Table 3.
Table 3. Device Functionality Summary
FAULT DESCRIPTOR
OV
FAULT DETECTION THRESHOLD and DELAY OPTIONS
FAULT RECOVERY METHOD and SETTING OPTIONS
Overvoltage
3 V to 4.575 V (25 mV step)
0.5, 1, 2, 4.5 s
Hysteresis
0, 100, 200, 400 mV
UV
Undervoltage
1.2 V to 3 V
(100 mV step for < 2.5 V,
50 mV step for ≥ 2.5 V)
1, 2, 4.5, 9 s
Hysteresis, OR
Hysteresis + Load Removal
200, 400 mV
OW
Open Wire (cell to pcb
disconnection)
0 (disabled), 100, 200, or 400
nA
4.5 s
Restore bad VCx to pcb connection
VCx > VOW
OTD (1)
Overtemperature during
Discharge
65°C or 70°C
4.5 s
Hysteresis
10°C
OTC (1)
Overtemperature during
Charge
45°C or 50°C
4.5 s
Hysteresis
10°C
UTD (1)
Undertemperature during
Discharge
-20°C or -10°C
4.5 s
Hysteresis
10°C
Undertemperature during
Charge
-5°C or 0°C
4.5s
Hysteresis
10°C
Delay, OR
Delay + Load Removal , OR
Load Removal
1 s or 9 s
UTC
(1)
OCD1
Overcurrent1 during
Discharge
10 mV to 85 mV (5 mV step)
10, 20, 45, 90, 180, 350, 700,
1420 ms
OCD2
Overcurrent1 during
Discharge
20 mV to 170 mV (10 mV step)
5, 10, 20, 45, 90, 180, 350, 700
ms
SCD
Short Circuit Discharge
40 mV to 340 mV (20 mV step)
360 µs
tCTRDEG_ON
Enable via external control or via CHGU
signal from the upper device in stack
configuration
tCTRDEG_OFF
tCTRDEG_ON
Enable via external control or via DSG
signal from the upper device in stack
configuration
tCTRDEG_OFF
CTRC
CHG signal override control
Disable via external control or
via CHGU signal from the
upper device in stack
configuration
CTRD
DSG signal override control
Disable via external control or
via DSG signal from the upper
device in stack configuration
(1)
12
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
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8.2 Functional Block Diagram
VDD
CCFG
BG
REFERENCE
BIAS
CONFIG
LOGIC
AVDD
VDIG
REGULATOR
AND
SHUTDOWN
VTB
POR
TS
VC5
VC4
EEPROM
COMPARE
1
MUX
VC3
CTRC
VC2
STACK
INTERFACE
CTRD
VC1
EQUINOX
CONTROL
LOGIC (ECL)
OPEN
WIRE
CHG
CHG
DRIVER
CHGU
MUX
COMPARE
2
DSG
DRIVER
DSG
LOAD
DETECTION
LD
SRP
STATE
COMPARE
SRN
CLOCK
and
WDT
AVSS
DVSS
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Figure 8. bq77904 and bq77905 Block Diagram
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8.3 Feature Description
8.3.1 Protection Summary
The bq77904 and bq77905 have two comparators. Both are time multiplexed to detect all protection fault
conditions. Each of the comparators runs on a time-multiplexed schedule and cycles through the assigned
protection-fault checks. Comparator 1 checks for OV, UV, and OW protection faults. Comparator 2 checks for
OCD1, OCD2, SCD, OTC, OTD, UTC, and UTD protection faults. For OV, UV, and OW protection faults, every
cell is checked individually in round-robin fashion starting with cell 1 and ending with the highest-selected cell.
The number of the highest cell is configured using the CCFG pin.
Devices can be ordered with various timing and hysteresis settings. Refer to the Device Comparison Table
section for a summary of options available per device type.
Check OV VCELL1
Check OV VCELL2
Check OV VCELLn
n = the highest call
configured by CCFG pin
Time to check
UV?
NO
Time to check
OT?
YES
Check UV VCELL1
NO
YES
Time to check
UT?
NO
YES
Check OT
Time to check
OW?
NO
YES
Check OW VCELLx,
x = x +1
Check UT
Check UV VCELL2
x starts
from 1
at POR
Reset x = 1, if x >
the highest cell
configured via
CCFG pin
Check UV VCELLn
Figure 9. Comparator 1 Flow Chart
Check SCD
Time to check
OCD1?
YES
Check
OCD1
NO
Time to check
OCD2?
NO
YES
Check
OCD2
Figure 10. Comparator 2 Flow Chart
14
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Feature Description (continued)
8.3.2 Fault Operation
8.3.2.1 Operation in OV
An OV fault detection is when at least one of the cell voltages is measured above the OV threshold, VOV. The
CHG pin is turned off if the fault condition lasts for a duration of OV Delay, tOVn_DELAY. The OV fault recovers
when the voltage of the cell in fault is below the (OV threshold - OV hysteresis, VHYS_OV) for a time of OV Delay.
The bq77904, ba779055 assumes OV fault after device reset.
8.3.2.2 Operation in UV
An UV fault detection is when at least one of the cell voltages is measured below the UV threshold, VUV. The
DSG is turned off if the fault condition lasts for a duration of UV Delay, tUVn_DELAY. The UV fault recovers when:
• the cell voltage in fault is above the (UV threshold + UV hysteresis, VHYS_UV) for a time of UV Delay only, OR
• the cell voltage in fault is above the (UV threshold + UV hysteresis) for a time of UV Delay AND Load removal
is detected
If load removal is enabled as part of UV recovery requirement, The CHG FET RGS value should change to
around 3 MΩ. Refer to the Using Load Detect For UV Fault Recovery section of this document for more detail.
This requirement applies to load removal enabled for UV recovery only. Hence, if load removal is selected for
current fault recovery but not for the UV recovery, a lower CHG FET RGS value (typical of 1MΩ) can be used to
reduce the CHG FET turn off time.
To minimize supply current, the device disables all overcurrent detection blocks anytime the DSG FET has been
turned off (due to a fault or CTRD being driven to the DISABLED state). Upon recovery from fault or when CTRD
is no longer externally driven, all overcurrent detection blocks reactivate before the DSG FET turns back on.
8.3.2.3 Operation in OW
An OW fault detection is when at least one of the cell voltages is measured below the OW threshold, VOW. Both
CHG and DSG are turned off if the fault condition lasts for a duration of OW Delay, tOWn_DELAY. The OW Fault
recovers when the cell voltage in fault is above the OW threshold + OW hysteresis, VOW_HYS for a time of OW
Delay.
The tOWn_DELAY time starts when voltage at a given cell is detected below VOW threshold and is not from the time
that the actual event of open wire occurs. During an open wire event, it is common that the device detects an
undervoltage and/or overvoltage fault before detecting an open wire fault. This may happen due to the
differences in fault thresholds, fault delays, and the VCx pin filter capacitor values. To ensure both CHG and
DSG return to normal operation mode, the OW, OV and UV faults recovery conditions must be met.
8.3.2.4 Operation in OCD1
An OCD1 fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN),
is measured below the OCD1 voltage threshold, VOCD1. Both CHG and DSG are turned off if the fault condition
lasts for a duration of OCD1 Delay, tOCD1_DELAY.
The OCD1 Fault recovers when:
• Load removal detected only, VLD < VLDT, OR
• Overcurrent Recovery Timer, tCD_REC, expiration only , OR
• Overcurrent Recovery Timer expiration and load removal detected
8.3.2.5 Operation in OCD2
An OCD2 fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN),
is measured below the OCD2 voltage threshold, VOCD2. Both CHG and DSG are turned off if the fault condition
lasts for a duration of OCD2 Delay, tOCD2_DELAY.
The OCD2 Fault recovers when:
• Load removal detected only, VLD < VLDT, OR
• Overcurrent Recovery Timer, tCD_REC, expiration only , OR
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Feature Description (continued)
•
Overcurrent Recovery Timer expiration and load removal detected
8.3.2.6 Operation in SCD
An SCD fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN), is
measured below the SCD voltage threshold, VSCD. Both CHG and DSG are turned off if the fault condition lasts
for a duraiton of SCD Delay, tSCD_DELAY.
The SCD Fault recovers when:
• Load removal detected only, VLD < VLDT, OR
• Overcurrent Recovery Timer, tCD_REC, expiration only , OR
• Overcurrent Recovery Timer expiration and load removal detected
8.3.2.7 Overcurrent Recovery Timer
The timer expiration method simply activates an internal recovery timer as soon as the initial fault condition
exceeds the OCD1/OCD2/SCD time. When the recovery timer reaches its limit, both CHG and DSG drivers are
turned back on. If the combination option of timer expiration AND load removal is used, then the load removal
condition is only evaluated upon expiration of the recovery timer, which can have an expiration period of tCD_REC.
8.3.2.8 Load Removal Detection
The load removal detection feature is implemented with the LD pin (see Table 4). When no undervoltage fault
and current fault conditions are present, the LD pin is held in an open drain state. Once any UV, OCD1, OCD2,
or SCD fault occurs and load removal is selected as part of the recovery conitions, a high impedance pull-down
path to VSS is enabled on the LD pin. With an external load still present, the LD pin will be externally pulled
high – it is internally clamped to VLDCLAMP and should also be resistor-limited via RLD externally to avoid
conducting excessive current. If the LD pin exceeds VLDT, this is interpreted as a load present condition. When
the load is eventually removed, the internal high-impedance path to VSS should be sufficient to pull the LD pin
below VLDT for tLD_DEG – this is interpreted as a load removed condition and is one of the recovery mechanisms
selectable for undervoltage and overcurrent faults.
PACK+
bq77094/5
Load Detect
block
When load detect is
enabled, the LD pin is
connected to Vss via the
RLD_INT.
VLDT
LD
pin
RLD_INT
RLD
LOAD
The load, RLD and RLD_INT
create a resister divider,
which the load detect
circuit is used to detect
when the load is removed.
PACKFigure 11. Load Detection Circuit For Current Faults Recovery
16
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Table 4. Load State
LD PIN
LOAD STATE
≥ VLDT
Load present
< VLOT for tLD_DEG
Load removed
8.3.2.9 Load Removal Detection in UV
During UV fault, only the DSG FET driver is turned off while the CHG FET driver remains on. When load removal
is selected as part of the UV recovery condition, the active CHG FET driver would alter the resistor divider ratio
of the load detection circuit. To ensure the load status can still be detected properly, it is required to increase the
CHG FET external RGS value to about 3 MΩ. Refer to the Using Load Detect For UV Fault Recovery section of
this document for more detail. Note that if load removal is only selected for the current fault recovery (and is not
used for UV recovery), it is not required to use a larger CHG FET RGS value.
8.3.2.10 Operation in OTC
An OTC Fault occurs when the temperature increases such that the voltage across an NTC thermistor goes
below the OTC voltage threshold, VOTC. CHG is turned off if the fault condition lasts for an OTC Delay time,
tOTC_DELAY. The state comparator is turned on when CHG is turned off. If a discharge current is detected, the
device immediately switchs the CHG back on. The response time of the state comparator is typically in 700 µs
and should not pose any disturbance in the discharge event. The OTC fault recovers when the voltage across
thermistor gets above OTC recovery threshold, VOTC_REC for OTC delay time.
8.3.2.11 Operation in OTD
An OTD fault is when the temperature increases such that the voltage across an NTC thermistor goes below the
OTD voltage threshold, VOTD. Both CHG and DSG are turned off if the fault condition lasts for an OTD Delay
time, tOTD_DELAY. The OTD fault recovers when the voltage across thermistor gets above OTD recovery threshold,
VOTD_REC, a time of OTD Delay.
8.3.2.12 Operation in UTC
A UTC fault occurs when the temperature decreases such that the voltage across an NTC thermistor gets above
the UTC voltage threshold, VUTC. CHG is turned off if the fault condition lasts for a time of UTC Delay, tUTC_DELAY.
The state comparator is turned on when CHG is turned off. If a discharge current is detected, the device will
immediately switch the CHG back on. The response time of the state comparator is typically in 700 µs and
should not pose any disturbance in the discharge event. The UTC fault recovers when the voltage across
thermistor gets below UTC recovery threshold, VUTC_REC, a time of UTC Delay.
8.3.2.13 Operation in UTD
A UTD fault occurs when the temperature decreases such that the voltage across an NTC thermistor goes above
the UTD voltage threshold, VUTD. Both CHG and DSG are turned off if the fault condition lasts for a UTD Delay
time. The UTD Fault recovers when the voltage across thermistor gets below UTD recovery threshold, VUTD_REC,
a time of UTD Delay.
8.3.3 Protection Response and Recovery Summary
Table 5 summarize how each fault condition affects the state of the DSG and CHG output signals, as well as the
recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output drivers
are enabled only when no respective fault conditions are present. When multiple simultaneous faults (such as an
OV and OTD) are present, all faults must be cleared before the FET can resume operation.
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Table 5. Fault Condition, State, and Recovery Methods
FAULT
FAULT TRIGGER
CONDITION
CHG
DSG
RECOVERY METHOD
RECOVERY
DELAY
TRIGGER DELAY
CTRC disabled
CTRC disabled for delgitch
delay time
OFF
—
CTRC must be enabled for delgitch delay time
tCTRDLY
CTRD disabled
CTRD disabled for delgitch
delay time
—
OFF
CTRD must be enabled for delgitch delay time
tCTRDLY
OV
V(Cell) rises above VOV for
delay time
OFF
—
V(Cell) drops below VOV – VHYS_OV for delay
tOVn_DELAY
UV
V(Cell) drops below VUV for
delay time
—
OFF
V(Cell) rises above VUV + VHYS_UV for delay
tUVn_DELAY
OW
VCX – VCX-1 < VOW for delay
time
OFF
OFF
Bad VCX recovers such that VCX – VCX-1 > VOW +
VOW_HYS for delay
tOWn_DELAY
OCD1, OCD2,
SCD
(VSRP - VSRN) < VOCD1,
VOCD2, or VSCD for delay
time
OFF
OFF
Recovery delay expires, OR
LD detects < VLDT, OR
Recovery delay expires + LD detects < VLDT
OTC (1)
Temperature rises above
TOTC for delay time
OFF
—
Temp drops below TOTC – TOTC_REC for delay
tOTC_DELAY
OTD (1)
Temperature rises above
TOTD for delay time
OFF
OFF
Temp drops below TOTD – TOTD_REC for delay
tOTD_DELAY
UTC (1)
Temperature drops below
TUTC for delay time
OFF
—
Temperature rises above TUTC + TUTC_REC for
delay
tUTC_DELAY
UTD (1)
Temp drops below TUTD for
delay time
OFF
OFF
Temp rises above TUTD + TUTD_REC for delay
tUTD_DELAY
(1)
tOCD1_DELAY,
tOCD2_DELAY,
tSCD_DELAY,
tCD_REC
TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected
thermistor resistance.
For bq77904 and bq77905 devices to prevent CHG FET damage, there are times when the CHG FET may be
enabled even though an OV, UTC, OTC or CTRC low event has occurred. See the State Comparator section for
details.
8.3.4 Configuration CRC Check And Comparator Built-In-Self-Test
To improve reliability, the device has built in CRC check for all the factory-programmable configuration, such as
the thresholds and delay time setting. When the device is set up in the factory, a corresponding CRC value is
also programmed to the memory. During normal operation, the device compares the configuration setting against
the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the CRC fault
counter. The digital reset forces the device to reload the configuration as an attempt to correct the configurations.
A correct CRC check reduces the CRC fault counter. Three CRC faults counts will turn off both the CHG and
DSG drivers. If FETs are opened due to CRC error, only a POR can recover the FET state and reset the CRC
fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, each comparator is checked for a period of time. If a fault is detected for the entire check period, the
particular comparator is considered at fault, and both the CHG and DSG FETs is turned off. The BIST continuous
to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver resumes
normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not specific
indication when a CRC or BIST error is detected besides turning off both CHG and DSG drivers. If there is no
voltage, current or temperature fault condition present, but CHG and DSG drivers remain off, it is possible either
CRC or BIST error is detected. User can POR the device to reset the device.
18
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8.3.5 Fault Detection Method
8.3.5.1 Filtered Fault Detection
The device detects a fault once the applicable fault is triggered after accumulating sufficient trigger sample
counts. The filtering scheme is based on a simple add/subtract. Starting with the Triggered Sample Count
cleared, the counts go up for a sample that is taken across the tested condition (for example, above the fault
threshold when looking for a fault) and the counts go down for a sample that is taken before the tested condition
(that is, below the fault threshold). Figure 12 shows an example of a signal that triggers a fault when
accumulating 5 counts above the Fault Threshold. Once a fault has been triggered, the trigger sample counts
reset and counts are incremented for every sample that is found to be below the Recovery Threshold.
Note that with filtered detection, when the input signal falls below the fault threshold, the sample count does not
reset but only counts down as shown in Figure 12. Therefore, it is normal to observe a longer delay time if a
signal is right at the detection threshold. The noise can push the delay count to be counting up and down,
resulting a longer time for the delay counter to reach its final accumulated trigger target.
Based on Fault Trigger After 5 Counts
Fault Threshold
Recovery Threshold
FAULT
FAULT
Sample
Triggered Sample Count
0 1 2 3 4 3 2 1 2 3 4 5 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 2 3 4 5 0 0 0
Looking for a Fault
Looking for a Recovery
Looking for a Fault
Figure 12. Fault Trigger Filtering
8.3.6 State Comparator
A small, low-offset analog State comparator monitors the sense-resistor voltage (SRP-SRN) to determine when
the pack is in a discharge state less than a minimum threshold, VSTATE_D or charge state greater than a
maximum threshold, VSTATE_C. The State comparator is used to turn the CHG FET on to prevent damage or
overheating during discharge in fault states that call for having only the CHG FET off, and vice versa for the DSG
FET during charging in fault that call for having only the DSG FET off.
Table 6 summarizes when the State comparator is operational. The State comparator is only on during faults
detected that call for only one FET driver to be turned off.
Table 6. State Comparator Operation Summary
STATE COMP
CHG
DSG
OFF
ON
ON
Normal
MODE
VSTATE_C Detection
ON
OFF
UV, CTRD
VSTATE_D Detection
OFF
ON
OV, UTC, OTC, CTRC
OFF
OFF
OFF
OCD1, OCD2, SCD, UTD, OTD, OW
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PACK IS CHARGING
PACK IS DISCHARGING
SRP - SRN
VSTATE_D
0V
VSTATE_C
Figure 13. State Comparator Thresholds
8.3.7 DSG FET Driver Operation
The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, and CTRD
disabled) are present. It is a fast switching driver with a target on resistance of about 15-20 Ω and an off
resistance of RDSGOFF. It is designed to allow customer to select the optimized RGS value to archive the desirable
FET rise and fall time per the application requirement and the choice of FET characteristics. When the DSG FET
is turned off, the DSG pin drives low, all overcurrent protection (OCD1, OCD2, SCD) is disabled to better
conserve power. These resume operation when the DSF FET is turned on. The device provides FET body diode
protection via the state comparator if one FET driver is on and the other FET driver is off.
The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge
inhibit fault condition is present. This is done via the state comparator. The state comparator (with VSTATE_C
threshold) remains on for the entire duration of a DSG fault with no CHG fault event.
• If (SRP - SRN) ≤ VSTATE_C, no charge event is detected, the DSG FET output will remain OFF due to the
present of a DSG fault
• If (SRP - SRN) > VSTATE_C, a charge event is detected, the DSG FET output will turn ON for body diode
protection
See the State Comparator section for detail.
The presence of any related faults as shown in Figure 14 results in the DSGFET_OFF signal.
DSGFET_OFF_UVn
DSGFET_OFF_OCD1
DSGFET_OFF_OCD2
DSGFET_OFF_SCD
DSGFET_OFF
DSGFET_OFF_UTD
DSGFET_OFF_OTD
OWn
CTRD
Figure 14. Faults That Can Qualify DSGFET_OFF
8.3.8 CHG FET Driver Operation
The CHG and CHGU pin are driven high only when no related faults (OV, OW, OTC, UTC, OTD, UTD, OCD1,
OCD2, SCD, and CTRC are disabled) are present or the pack has a discharge current where (SRP-SRN) <
VSTATE_D1 . The CHG pin drives the CHG FET, which is for use on the single device configuration or by the
bottom device in a stack configuration. The CHGU pin has the same logic state as the CHG pin and is for use in
the upper device (in a multi-stack configuration) to provide the drive signal to the CTRC pin of the lower device
and should never connect to the CHG FET directly.
20
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Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG pin is designed to
switch on quickly and the target on resistance is about 2 kΩ. When the pin is turned off, the CHG driver pin is
actively driven low and will together with PACK- voltage below ground.
The CHG FET may be turned on to protect the FET's body diode if the pack is discharging, even if a charging
inhibit fault condition is present. This is done via the state comparator. The State comparator (with VSTATE_D
threshold) remains on for the entire duration of a DSG fault with no CHG fault event.
• If (SRP - SRN) > VSTATE_D, no discharge event is detected, the CHG FET output will remain OFF due to
the present of a CHG fault
• If (SRP - SRN) ≤ VSTATE_D, a charge event is detected, the CHG FET output will turn ON for body diode
protection
The CHGFET_OFF signal is a result of the presence of any related faults as shown in Figure 15.
CHGFET_OFF_OVn
CHGFET_OFF_UTC
CHGFET_OFF_OTC
CHGFET_OFF_OCD1
CHGFET_OFF_OCD2
CHGFET_OFF
CHGFET_OFF_SCD
CHGFET_OFF_UTD
CHGFET_OFF_OTD
OWn
CTRC
Figure 15. Faults That Can Qualify CHGFET OFF
8.3.9 External Override of CHG and DSG Drivers
The device allows direct disabling of the CHG and DSG drivers via the CTRC and CTRD pins respectively. The
operation of CTRC and CTRD pins is shown in Figure 16. To support the SimpleStack solution for higher-cell
count packs, these pins are designed to operate above the device’s VDD level. Simply connect a 10 MΩ resistor
between a lower device CTRC and CTRD input pins to an upper device CHGU and DSG output pins (see
schematics in Stacking Implementations.
CTRC only enables or disables the CHG pin, while CTRD only enables or disables the DSG pin. When the CTRx
pin is in the DISABLED region, the respective FET pin will be off, regardless of the state of the protection
circuitry. When the CTRx pin is in either ENABLED region, the protection circuitry determines the state of the
FET driver.
Both CTRx pins apply the fault-detection filtered method to improve the robustness of the signal detection; a
counter counts up if an ENABLED signal is sampled; the counter counts down if a DISABLED signal is sampled.
When the counter counts up from 0% to > 70% of its full range, which take about 7 ms typical of a solid signal,
the CTRx pins take the signal as ENABLED. If the counter counts down from 100% to < 30%, of its full range,
which take about 7 ms typical of a solid signal, the CTRx pins take the signal as DISABLED. From a 0 count
counter (solid DISABLE), a solid ENABLE signal takes about tCTRDEG_ON time to deglitch. From a 100% count
(solid ENABLE), a solid DISABLE signal takes about tCTRDEG_OFF time to deglitch. Although such a filter scheme
provides a certain level of noise tolerance, it is highly recommended to shield the CTRx traces and keep the
traces as short as possible in the PCB layout design. The CTRx deglitch time will add onto the FET response
timing on OV, UV, and OW faults in a stack configuration. The tCTRDEG_OFF time adds an additional delay to the
fault detection timing and the tCTRDEG_ON time adds an additional delay to the fault recovery timing.
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ENABLED
VCTR2
VCTRDIS (max)
VDD
DISABLED
(FET OFF)
VCTRDIS (min)
VCTR1
ENABLED
VSS
CHG driver set by CTRC
DSG driver set by CTRD
Figure 16. External Override of CHG and DSG Drivers
8.3.10 Configuring 3S, 4S, or 5S Mode
The bq77904 supports 3S and 4S packs, while the bq77905 supports 3S, 4S, and 5S packs. In order to avoid
accidentally detecting a UV fault on unused (shorted) cell inputs, the device must be configured for the specific
cell count of the pack. This is set with the configuration pin, CCFG, which is mapped as in Table 7. The device
periodically checks the CCFG status and takes tCCFG_DEG time to detect the pin status.
Table 7. CCFG Configurations
CCFG
CONFIGURATION
CONNECT TO
< VCCFGL for tCCFG_DEG
3 cells
AVSS
Within VCCFGM for tCCFG_DEG
4 cells
AVDD
> VCCFGH for tCCFG_DEG
5 cells
Floating
The CCFG pin should be tied to the recommended net from Table 7. The device compares the CCFG input
voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is
for 5S, leave the CCFG pin floating. The internal pin bias is approximately 30% of the AVDD voltage for 5S
configuration. Note that the bq77904 should be configured in 5S mode as this results in a permanent UV fault.
8.3.11 Stacking Implementations
Higher than 5S cell packs may be supported by daisy-chaining multiple devices. Each device will ensure OV, UV,
OTC OTD, UTC, and UTD protections, of its directly monitored cells, while any fault conditions automatically
disable the global CHG and/or DSG FET driver. Note that upper devices do not provide OCD1, OCD2, or SCD
protections, as these are based on pack current. For bq77904 and bq77905 used on the upper stack, the SRP
and SRN pins should be shorted to prevent false detection.
Table 8. Stacking Implementation Configurations
CONFIGURATION
CHG PIN
CHGU PIN
Bottom or single device
Connect to CHG FET
Leave unconnected
Upper stack
Leave unconnected
Connect to CTRC of the lower device
To configure higher-cell packs, follow this procedure:
• Each device must have a connection on at least three lowest-cell input pins.
• It is recommended to connect higher-cell count to the upper devices (for example, for a 7S configuration,
connect 4 cells on the upper device and 3 cells on the bottom device). This is to provide stronger CRTx signal
to the bottom device.
• Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (three, four, or
five cells).
22
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•
•
•
•
SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
For the bottom device, the CHG pin should be used to drive the CHG FET and leave the CHGU pin
unconnected. For the upper device, the CHGU pin should be used to connect to lower device’s CTRC pin
with a RCTRx and leave the CHG pin unconnected.
Connect the upper DSG pins with a RCTRx to the immediate lower device CTRD pin
All upper devices should have the SRP and SRN to its AVSS pin.
If load removal is not used for UV recovery, connect the upper device LD pin to its AVSS pin shown in
Figure 17 and Figure 18. Otherwise, refer to Figure 25 for proper LD connection.
PACK+
RVDD
CVDD
CVDD
RIN
CIN
RIN
DVSS
CTRD
VC5
CTRC
VC4
CCFG
VC3
CIN
RIN
VDD
AVDD
bq77905
VC2
RIN
CIN
RIN
RTS
TS
VC1
CIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
CIN
RVDD
CVDD
CVDD
RIN
CIN
RIN
RIN
RIN
RIN
VC3
CIN
VC2
VC1
CIN
CIN
bq77905
RCTRD
RCTRC
RTS_PU
VTB
RTS
TS
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS_DSG
RGS_CHG
RSNS
PACK-
Figure 17. 10S Pack Using Two bq77905 Devices
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PACK+
RVDD
CVDD
RIN
CVDD
CIN
RIN
CIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
RIN
CIN
bq77905
VC2
CIN
RIN
CIN
RTS
TS
VC1
RIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RVDD
CVDD
CVDD
RIN
CIN
RIN
DVSS
CTRD
VC5
CTRC
VC4
CCFG
VTB
VC3
CIN
RIN
VDD
AVDD
bq77905
VC2
CIN
RIN
RTS_PU
RTS
LD
AVSS
RIN
RCTRC
TS
VC1
CIN
RCTRD
CHG
SRP
CHGU
SRN
DSG
CIN
RVDD
CVDD
CVDD
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VTB
VC3
VC2
RIN
RIN
RIN
VC1
CIN
CIN
bq77905
RCTRD
RCTRC
RTS_PU
RTS
TS
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS
RGS
RSNS
PACK-
Figure 18. 13S Pack Using Three bq77905 Devices
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8.3.12 Zero-Volt Battery Charging Inhibition
Once the device is powered up, it can pull the CHG pin up if the VDD ≥ VSHUT, which varies from about 1 V per
cell on a 3S configuration to about 0.6 V per cell on a 5S configuration. If the battery stack voltage falls below
VSHUT, the device is in SHUTDOWN mode and the CHG driver is not longer active and charging is not allowed
unless VDD rises above VPOR again.
8.4 Device Functional Modes
8.4.1 Power Modes
8.4.1.1 Power On Reset (POR)
The device powers up when VDD ≥ VPOR. At POR, the following events occur:
• A typical 5-ms hold-off delay applies to both CHG and DSG drivers, keeping both drivers in the OFF state.
This provides time for the internal LDO voltage to ramp up.
• CTRC and CTRD de-glitch occurs. During the de-glitch time, the CHG and DSG driver remains off. Note that
de-glitch time basically mask out the 5-ms hold-off delay.
• Device assumes OV fault at POR, hence, the CHG driver is off for OV recovery time if all the cell voltages are
< (VOV – VHYS_OV). The OV recovery time start after the 5-ms hold-off delay. If device reset occurs when any
cell voltage is above the OV hysteresis range, the CHG driver will remain off until an OV recovery condition is
met.
8.4.1.2 FAULT Mode
If any configured protection fault is detected, the device enters the FAULT mode. In this mode, the CHG and/or
DSG driver can be turned off depending on the fault. Refer to the Fault Response Summary for detail. When one
of the FET drivers (either CHG or DSG) is turned off, while the other FET driver is still on, the state comparator is
activated for FET body diode protection.
8.4.1.3 SHUTDOWN Mode
This is the lowest power consumption state of the device when VDD falls below VSHUT. In this mode, all fault
detections, CHG and DSG drivers are disabled. The device will wake up and enter NORMAL Mode when VDD
rises above VPOR.
8.4.1.4 Customer Fast Production Test Modes
The bq7790x device supports the ability to greatly reduce production test time by cutting down on protection fault
delay times. To shorten fault times, place the bq7790x device into Customer Test Mode (CTM). CTM is triggered
by raising VDD to VCTM voltage above the highest cell input pin (that is, VC5) for tCTM_ENTRY time.
The CTM is expected to be used in single-chip designs only. CTM is not supported for stacked designs. Once
the device is in CTM, all fault delay and non-current fault's recovery delay times reduce to a value of tCTM_DELAY.
The fault recovery time for overcurrent faults (OCD1, OCD2, and SCD) is reduced to tCTM_OC_REC.
Verification of protection fault functionality can be accomplished in a reduced time frame in CTM. Reducing the
VDD voltage to the same voltage applied to the highest-cell input pin for tCTM_ENTRY will exit CTM.
In CTM, with reduced time for all internal delays, qualification of all faults will be reduced to a single instance.
Thus in this mode, fault condition qualification is more susceptible to transients, so take care to have fault
conditions clearly and cleanly applied during test mode to avoid false triggering of fault conditions during CTM.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq77904/5 is low power stackable battery pack protector with integrated low-side NMOS FET driver. The
bq77904/5 provides voltage, current, temperature and open wire protections. All the devices protect and recover
without a MCU control. The following section highlights several recommended implementation when using these
devices.
9.1.1 Recommended System Implementation
9.1.1.1 CHG and DSG FET Rise And Fall Time
The CHG and DSG FET driver are designed to have fast switching time. Customer should select a proper gate
resistor (RCHG and RDSG in the reference schematic) to set to the desired rise/fall time.
DSG
CHG
Select proper gate
resistor to adjust
the desired rise/
fall time
RCHG
RDSG
RGS_DSG
RGS_CHG
Q2 Q1
RSNS
PACK-
Figure 19. Select Proper Gate Resistor For FET Rise And Fall Time
The CHG FET fall time is generally slower because it is connected to the PACK- terminal. The CHG driver will
pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or
Vgsth, the PACK- will start to fall below ground, the CHG signal will follow suit in order to turn off the CHG FET.
This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel, and
the value of gate-source resistor (RGS_CHG).
26
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Application Information (continued)
Strong pull down by the CHG driver
when the device is initially signaled to
turn off CHG.
Once the CFET gate voltage reach PACK-, PACKvoltage starts to fall below ground. The gate
voltage is then relying on RGS_CHG to fall with
PACK- to keep the CHG FET off.
Figure 20. CHG FET Fall Time
9.1.1.2 Protecting CHG And LD
Since both CHG and LD are connected to PACK- terminal, these pins are specially designed to sustain an
absolute max of -30 V. However, the device can be used in a wide variety of application, it is possible to expose
the pins lower than -30 V absolute max rating.
To protect the pins, it is recommended to put a PMOS FET in series of the CHG pin and a diode in series of the
LD pin as shown below.
DSG
CHG
LD
Q3 and the LD pin diode are used to
keep CHG and LD away from any
voltages below VSS. Apply these
components when CHG and LD pins can
be exposed beyond the absolute -30V.
Q3
RDSG
RCHG
RLD
RGS_DSG
RGS_CHG
Q2
Q3 will allow RGS_CHG to keeps Q1 OFF,
since all voltages below this FET can
^(}oo}Á_ W <- as it goes below VSS.
Q1
RSNS
PACK-
Figure 21. Protect CHG and LD Go Below Absolute Minimum
9.1.1.3 Protecting CHG FET
When CHG driver is off, CHG is pulled to VSS, the PACK- terminal can be pull up to PACK+ level when a load is
connected. This can put the gate-source voltage above the absolute max of the MOSFET rating. Hence, it is
common to place a Zener diode across the CHG FET’s gate-source to protect the CHG FET. Additional
components are added when a Zener is used to limit current going into the CHG pin as well as reducing the
impact on rise time. See Figure 22 for details.
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Application Information (continued)
DSG
CHG
RDSG
This diode allows CHG to
pull the Q1 gate high,
bypassing the path through
RCHG and RGS_CHG which will
divide down the CHG ON
voltage
RCHG drops the voltage and limits the
current going into the CHG pin when
RCHG PACK- is pulled high and zener across Q1
(1MŸ ) Vgs is used.
RGS_CHG
(>=1MŸ)
RGS_DSG
Q2
This zener clamp may be
needed to prevent the Vgs of Q1
excesses absolute max rating.
Q1
16V
RSNS
PACK-
Figure 22. Protect CHG FET from High Voltage on PACK–
DSG
LD
CHG
Q3
RCHG
(1MŸ )
RDSG
RGS_DSG
Q2
Q1
RLD
RGS_CHG
(>=1MŸ)
16V
RSNS
PACK-
Figure 23. Optional Components Combining Figure 21 and Figure 22 Protections
9.1.1.4 Using Load Detect For UV Fault Recovery
A larger CHG FET gate-source resistor is required if load removal is enabled as part of the UV recovery criteria.
When the load removal circuit is enabled, the device is internally connected to Vss. Since in UV fault, the CHG
driver remains on, it creates a resistor divider path to the load detect circuit.
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Application Information (continued)
PACK+
bq77094/5
Load Detect
block
VLDT
LD
pin
RLD_INT
FET driver
block
VFETON
LOAD
CHG
pin
RCHG
RLD
16V
CFET
RGS_CHG
PACKFigure 24. Load Detect Circuit During UV Fault
To ensure load removal is detected properly during UV fault, it is recommended to use 3.3 MΩ for RGS_CHG
(instead of a typical of 1 MΩ when load removal is NOT required for UV recovery). RCHG can stay in 1 MΩ as
recommended when using CHG FET protection components. The CHG FET rise time impact is minimized as
described in the “Protecting CHG FET” section. On a stacked configuration, connect the LD pin as shown in
Figure 25 if load removal is used for UV fault recovery. If load detection is not required for UV fault recovery, a
larger value of RGS_CHG can be used (that is, 10 MΩ) and there LD pin on the upper devices can be left floating.
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Application Information (continued)
bq77094/5
LD
pin
Upper
device
Vss
pin
Ra is used to keep the LD pin pull
down when load detect circuit is
not activated
Ra
(1M)
Must have block
diode on the upper
device.
RLD
bq77094/5
LD
pin
Bottom
device
Vss
pin
RLD
Diode for the bottom
device is optional.
Use if the LD pin will
be exposed lower
than -30V.
PACKFigure 25. Simplified Circuit: LD Connection On Upper Device When Using For UV Fault Recovery
9.1.1.5 Temperature Protection
The device detects temperature by checking the voltage divided by RTS_PU and RTS, with the assumption of using
10 KΩ RTS_PU and 103AT NTC for RTS. System designer should always check the thermistor resistance
characteristic and refer to the temperature protection threshold specification in the Electrical Characteristic table
to determine if a different pull up resistor should be used. If a different temperature trip pint is required, it is
possible to scale the threshold using this equation: Temperature Protection Threshold = RTS/(RTS + RTS_PU).
Example: Scale OTC trip points from 50°C to 55°C
The OTC protection can be set to 45°C or 50°C. When the device's OTC threshold is set to 50°C, it is referred to
configure the VOTC parameter to 29.38% of VTB (typical), with the assumption of RTS_PU = 10KΩ and RTS =
103AT or similar NTC (which the NTC resistance at 50°C = 4.16KΩ). The VOTC specification is simply the resistor
divider ratio of RTS_PU and RTS.
The VOTC, VOTD, VUTC and VUTD configuration options are fixed in the device. Hence, the actual temperature trip
point can only adjust by using a different B-value NTC and/or using a different RTS_PU.
In this example, the 103AT NTC resistance at 55°C is 3.536 KΩ. By changing the RTS_PU from 10 KΩ to 8.5 KΩ,
we can scale the actual OTC temperature trip point from 50°C to 55°C. Because the RTS_PU value is smaller, this
change affects all the other temperature trip points and scales OTD, UTC and UTD to ~5°C higher as well.
9.1.1.6 Adding Filter To Sense Resistor
Current fault is sense through voltage across sense resistor. Optional RC filters can be added to the sense
resistor to improve stability.
30
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Application Information (continued)
SRP
0.1 µF
SRN
0.1 µF
100 Ÿ
0.1 µF
100 Ÿ
R SNS
PACK-
Figure 26. Optional Filters Improve Current Measurement
9.1.1.7 Using State Comparator In Application
The state comparator does not have built-in hysteresis. It is normal to observe the FET body diode protection
toggling on and off with the VSTATE_C1 or VSTATE_D1 accuracy range. In a typical application, the sense resistor is
selected according to the application current, which usually is not close to the state comparator threshold.
9.1.1.7.1 Examples
For example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor is
mostly 3 mΩ or less.
The typical current to turn on the FET body diode protection is 667 mA using this example. Since there is no
built-in hysteresis, noise can reset the state comparator counter and toggle off the FET body diode protection
and vice versa. Hence, it is normal to observe the device toggles the FET body diode protection on or off within 1
mV to 3 mV range. With a 3mohm sense resistor, it is about 330 mA to 1 A. As this behavior is due to noise from
the system, the FET toggling behavior is usually occurs right at the typical 2mV state comparator threshold, as
current increases or decreases from the typical value, the detection is more solid and has less frequent FET
toggling. Using this example, either charge or discharge should provide a solid FET body diode protection
detection.
Look at the device behavior during an OV event (and no other fault is detected). In an OV event, CHG FET is off
and DSG FET is on. If a discharge of >1 A occurs, the device would turn on the CHG FET immediate to allow the
full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery level, the OV
fault is recovered and CHG driver turns on (or remains on in this scenario) and the state comparator is turned off.
If the discharge current is < 1 A when the device is still in OV fault, the CHG FET may toggle on and off until the
overcharged cell voltage is reduced down to the OV recovery level. When OV fault recovered, the CHG FET will
be solidly turned on and the state comparator is off.
Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can
only pass through the CHG FET body diode until the OV fault is recovered. This increase the risk of damaging
the CHG FET if the MOSFET is not rate to sustain such current through its body diode. It also increases the FET
temperature as current is now carry through the body diode.
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9.2 Typical Application
PACK+
RVDD
CVDD
CVDD
RIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
CIN
VC2
RIN
RIN
RIN
bq77905
bq77904
CIN
RTS
TS
VC1
CIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS
RGS
RSNS
PACKCopyright © 2016, Texas Instruments Incorporated
Figure 27. bq77904 and bq77905 with 4 Cells
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 9.
Table 9. Design Parameters
PARAMETER
DESCRIPTION
VALUES
RIN
Cell voltage sensing (VCx pins) filter resistor
1 kΩ ±5%
CIN
Cell voltage sensing (VCx pins) filter capacitor
RVDD
Supply voltage filter resistor
1 kΩ ±5%
CVDD
Supply voltage filter capacitor
1 µF ±20%
RTS
NTC thermistor
RTS_PU
Thermistor pullup resistor to VTB pin, assuming using 103AT NTC or NTC with similar
resistance-temperature characteristic
RGS_CHG
CHG FET gatesource resistor
RGS_DSG
DSG FET gate-source resistor
RCHG
CHG gate resistor
0.1 µF ±10%
103AT, 10 kΩ ±3%
10 kΩ ±1%
Load removal is enabled for UV recovery
3.3 MΩ ±5%
Load removal is disabled for UV recovery
1 MΩ ±5%
1 MΩ ±5%
system designer should adjust this parameter to meet the
desirable FET rise/fall time
1 kΩ ±5%
If additional components are used to protect the CHG FET
and/or to enable load removal detection for UV recovery
1 MΩ ±5%
RDSG
DSG gate resistor, system designer should adjust this parameter to meet the
desirable FET rise/fall time
RCRTC and RCTRD
CTRC and CTRD current limit resistor
10 MΩ ±5%
RLD
LD resistor for load removal detection
450 KΩ ±5%
RSNS
Current sense resistor for current protection , system designer should change this
parameter according to the application current protection requirement
32
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4.5 kΩ ±5%
1 mΩ ±1%
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SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
9.2.2 Detailed Design Procedure
The following is the detailed design procedure.
1. Based on the application current, select the proper sense resistor value. The sense resistor should allow
detection of the highest current protection, short circuit current.
2. Temperature protection is set with the assuming of using 103AT NTC (or NTC with similar specification). If a
different type of NTC is used, a different RTS_PU may be used for the application. Refer to the actual
temperature detection threshold voltage to determine the RTS_PU value.
3. Connect the CCFG pin correctly based on the number of cell in series.
4. Review the Recommended Application Implementation to determine if optional components should be added
to the schematic.
9.2.2.1 Design Example
To design the protection for a 36 V Li-ion battery pack using 4.2 V LiCoO2 cells with the following protection
requirements.
Voltage Protection
• OV at 4.3V, recover at 4.1V
• UV at 2.6V, recover at 3V and when load is removed
Current Protection
• OCD1 at 40A with 300-400ms delay
• OCD2 at 80A with the shortest delay option
• SCD at 100A with <500us delay
• Requires load removal for recovery
Temperature Protection
• Charge - OTC at 50°C, UTC at -5°C
• Discharge - OTD at 70°C, UTD at -10°C
To start the design:
1. Start the schematic
– A 36 V pack using LiCoO2 cells requires 10S configuration. Hence, two bq77905 devices in stackable
configuration is needed.
– Follow the 10S reference schematic in this document. Follow the recommended desgin parameters list in
the Design Requirements section of this document.
– The power FET uses in this type of application usually has an absolute of 20 V Vgs. For a 36 V pack
design, it is recommended to use the additional components to protect the CHG FET Vgs. Refer to the
Using Load Detect For UV Fault Recovery section for detail.
– Since load removal for UV recovery is required, a 3 MΩ RGS_CHG should be used for the schematic.
2. Decide the value of the sense resistor, RSNS
– When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available
current protection threshold range.
– In this example, select RSNS = 1 mΩ (any value ≤ 2 mΩ will work in this example).
3. Determine all the bq77905 protection configuration, see Table 10.
4. Review the available release or preview device in the Device Option Tables to determine if a suitable option
is available. If not, contact TI representative for further assistant.
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Table 10. Design Example Configuration
Protection
Threshold
Hystersis
Delay
Recovery Method
OV
4.3 V
200 mV
1 s (default setting)
Hysteresis
UV
2.6 V
400 mV
1 s (default setting)
Hysteresis + load removal
OW
100 nA
(default setting)
-
-
(VCx - VCx-1) > 600 mV (typical)
OCD1
40 mV
-
350 ms
Load removal only
OCD2
80 mV
-
5 ms
Load removal only
SCD
100 mV
-
Fixed at 360us
Load removal only
OTC
50°C
10°C
4.5 s
Hysteresis
OTD
70°C
10°C
4.5 s
Hysteresis
UTC
-5°C
10°C
4.5 s
Hysteresis
UTD
-10°C
10°C
4.5 s
Hysteresis
34
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9.2.3 Application Curves
DSG remains on
DSG remains on
CHG recovers after
2nd OV fault is removed
CHG falls due to
detection of 1st OV fault
Figure 28. OV Fault Protection
State comparator detects discharge and
turns CHG back on even OV fault is present
2nd Fault removed
1st Fault removed
1st OV Fault
Figure 29. OV Fault Recovery
Device is set to recovery after
current recovery delay. Both
CHG/DSG turns back on, but
device detects OCD2 fault and
turns off both FET driver again
Both CHG/DSG are
off in OCD2 fault
CHG falls due to OV fault.
State comparator is on to detect any
discharge activity
OV fault
OCD2 fault inserted
Figure 31. Detect OTC Fault While in 30A Discharge
Figure 30. OV and OCD2 Faults Protection
DSG falls due to
UV fault on VC2
DSG falls after ~ 1s due to
UV fault on VC2
In real application, OV and UV are usually
triggered first in an open wire event, masking out
the OW protection. This capture is to demonstrate
the OW protection by observing the CHG delay
time
CHG falls after
~5s due to OW
CHG falls after ~ 1s due to
OV fault on VC3
Relay opens ± open cell2 to pcb connection
VC2 ramped to 0V, while other cell
voltages stay in normal
In real application, an open wire event will deplete the filter
capacitor connects to the device cell voltage sensing pin. The
depleted capacitor will trigger the UV fault. It also causes the upper
cell voltage sensing pin to see a sum of 2 cell voltages, which will
trigger an OV fault.
OV and UV delays are shorter than OW delay, hence, the OV and
UV will triggered before OW protection activates.
Figure 32. OW Fault Protection - Open Cell2 To PCB
Connection
Figure 33. OW Fault Protection - Ramping Down Cell2
Voltage
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9.3 System Examples
PACK+
RVDD
CVDD
RIN
RIN
RIN
RIN
RIN
CVDD
CIN
CIN
CIN
CIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
VTB
bq77905
VC2
TS
VC1
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RTS_PU
RTS
RCHG
RDSG
RLD
CIN
RGS
RSNS
RGS
PACKCopyright © 2016, Texas Instruments Incorporated
Figure 34. bq77905 with 5 Cells
10 Power Supply Recommendations
The recommended cell voltage range is up to 5 V. If 3 cells in series is connecting to bq77905, the unused VCx
pins should be shorted to the highest unused VCx pin. The recommended VDD range is from 3 V to 25 V. This
implies the device is still operational when cell voltage is depleted down to ~1.5 V range.
36
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SLUSCM3A – JUNE 2016 – REVISED JUNE 2016
11 Layout
11.1 Layout Guidelines
1. Match SRN and SRP trace.
2. RIN filters, VDD, AVDD filters and CVDD capacitor should be placed close to the device pins.
3. Separating device ground plane (low current ground) from the high current path. Filter capacitors should
reference to the low current ground path or device Vss.
4. In a stack configuration, the RCTRD and RCTRC should be placed closer to the lower device CTRD and CTRC
pins.
5. RGS should be placed near the FETs
11.2 Layout Example
High current Path
Please filters
close to IC pins VDD
DVSS
Connect AVSS and DVSS
to device ground plane
AVDD
RC
Filters
PACK+
VC5
:
:
Low current, local
ground for each device
VC1
AVSS
AVSS
CHGU
DSG
Connect the device ground at
šZ o}Á Œ oo[• oo- on each
cell group
Please filters
close to IC pins VDD
AVDD
RC
Filters
VC5
:
:
DVSS
DVSS
CTRD
Please CTRs
resistors close to
the lower device
CTRC
VC1
AVSS
AVSS
Connect the bottom
device ground at BAT-.
Using BAT- as the mutual
point to connect high
and low current path
Low current, local
device ground.
Separate from high
power path
PACK-
Figure 35. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq77904
Click here
Click here
Click here
Click here
Click here
bq77905
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ7790400PW
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
BQ7790400PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
BQ7790500PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790500
BQ7790500PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790500
BQ7790501PW
PREVIEW
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790501
BQ7790501PWR
PREVIEW
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790501
BQ7790502PW
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
BQ7790502PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
BQ7790503PW
PREVIEW
TSSOP
PW
20
1050
TBD
Call TI
Call TI
-40 to 85
BQ7790503PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ7790500PWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ7790500PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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