PSoC® 3: CY8C32 Family
Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 3 is a true ystem level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces,
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Single cycle 8051 CPU core
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
1.024 V ±0.9-percent internal voltage reference across –40°C
to +85°C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
One 8-bit, 8-Msps IDAC or 1-Msps VDAC
Two comparators with 95 ns response time
CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
4-KB instruction trace buffer
2
Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
DC to 50 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V through 1.8-V to
5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
low-voltage detect (LVD) interrupt
• 200-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs[2])
Any GPIO to any digital or analog peripheral routability
[2]
LCD direct drive from any GPIO, up to 46×16 segments
®
[3]
CapSense support from any GPIO
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
16 to 24 programmable PLD based universal digital
blocks (UDB)
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 106 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 30, 2011
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PSoC® 3: CY8C32 Family
Data Sheet
Contents
1. Architectural Overview ..................................................... 3
2. Pinouts ............................................................................... 5
3. Pin Descriptions .............................................................. 10
4. CPU ................................................................................... 11
4.1 8051 CPU ................................................................. 11
4.2 Addressing Modes .................................................... 11
4.3 Instruction Set .......................................................... 12
4.4 DMA and PHUB ....................................................... 16
4.5 Interrupt Controller ................................................... 18
5. Memory ............................................................................. 22
5.1 Static RAM ............................................................... 22
5.2 Flash Program Memory ............................................ 22
5.3 Flash Security ........................................................... 22
5.4 EEPROM .................................................................. 22
5.5 Nonvolatile Latches (NVLs) ...................................... 23
5.6 External Memory Interface ....................................... 24
5.7 Memory Map ............................................................ 24
6. System Integration .......................................................... 26
6.1 Clocking System ....................................................... 26
6.2 Power System .......................................................... 29
6.3 Reset ........................................................................ 33
6.4 I/O System and Routing ........................................... 34
7. Digital Subsystem ........................................................... 40
7.1 Example Peripherals ................................................ 41
7.2 Universal Digital Block .............................................. 44
7.3 UDB Array Description ............................................. 47
7.4 DSI Routing Interface Description ............................ 47
7.5 USB .......................................................................... 49
7.6 Timers, Counters, and PWMs .................................. 49
7.7 I2C ............................................................................ 49
8. Analog Subsystem .......................................................... 51
8.1 Analog Routing ......................................................... 52
8.2 Delta-sigma ADC ...................................................... 54
8.3 Comparators ............................................................. 55
8.4 LCD Direct Drive ...................................................... 57
8.5 CapSense ................................................................. 57
Document Number: 001-56955 Rev. *J
8.6 Temp Sensor ............................................................ 57
8.7 DAC .......................................................................... 58
9. Programming, Debug Interfaces, Resources ................ 59
9.1 JTAG Interface ......................................................... 59
9.2 Serial Wire Debug Interface ..................................... 59
9.3 Debug Features ........................................................ 59
9.4 Trace Features ......................................................... 59
9.5 Single Wire Viewer Interface .................................... 60
9.6 Programming Features ............................................. 60
9.7 Device Security ........................................................ 60
10. Development Support ................................................... 61
10.1 Documentation ....................................................... 61
10.2 Online ..................................................................... 61
10.3 Tools ....................................................................... 61
11. Electrical Specifications ............................................... 62
11.1 Absolute Maximum Ratings .................................... 62
11.2 Device Level Specifications .................................... 63
11.3 Power Regulators ................................................... 67
11.1 Inputs and Outputs ................................................. 71
11.2 Analog Peripherals ................................................. 79
11.3 Digital Peripherals .................................................. 91
11.4 Memory .................................................................. 94
11.5 PSoC System Resources ..................................... 100
11.6 Clocking ................................................................ 102
12. Ordering Information ................................................... 106
12.1 Part Numbering Conventions ............................... 108
13. Packaging ..................................................................... 109
14. Acronyms ..................................................................... 112
15. Reference Documents ................................................. 113
16. Document Conventions .............................................. 114
16.1 Units of Measure .................................................. 114
17. Revision History .......................................................... 115
18. Sales, Solutions, and Legal Information ................... 119
Page 2 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Quadrature Decoder
UDB
Sequencer
Usage Example for UDB
IMO
I2C
Universal Digital Block Array ( 24 x UDB)
8- Bit
Timer
UDB
UDB
UDB
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 Ω
12- Bit SPI
UDB
UDB
UDB
UDB
8- Bit
Timer
Logic
UDB
8- Bit SPI
I2C Slave
Master/
Slave
16- Bit PRS
UDB
UDB
FS USB
2.0
4x
Timer
Counter
PWM
Logic
UDB
UDB
UDB
UART
UDB
USB
PHY
GPIOs
GPIOs
Clock Tree
32.768 KHz
( Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4- 33 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
System Bus
GPIOs
EEPROM
EMIF
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
FLASH
Program
Debug &
Trace
PHUB
DMA
ILO
Program &
Debug
GPIOs
WDT
and
Wake
Memory System
Boundary
Scan
Power Management
System
Analog System
LCD Direct
Drive
ADC
POR and
LVD
SMP
Temperature
Sensor
CapSense
Del Sig
ADC
DAC
+
2x
CMP
-
GPIOs
1.71 to
5.5V
Sleep
Power
1.8V LDO
GPIOs
SIOs
Clocking System
0. 5 to 5.5V
( Optional)
Figure 1-1 illustrates the major components of the CY8C32
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Digital subsystem
Analog subsystem
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C32 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
and FS USB.
For more details on the peripherals see the “Example
Peripherals” section on page 41 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 40 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.9-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
ADC
DAC
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
A high-speed voltage or current DAC supports 8-bit output
signals at an update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO
pin. You can create higher resolution voltage PWM DAC outputs
using the UDB array. This can be used to create a pulse width
modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The
digital DACs in each UDB support PWM, PRS, or delta-sigma
algorithms with programmable widths.
In addition to the ADC and DAC, the analog subsystem provides
multiple comparators.
See the “Analog Subsystem” section on page 51 of this
datasheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection. Up
to 2 KB of byte-writeable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[4], CapSense[5], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow Voh to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All of the features of the PSoC I/Os are covered
in detail in the “I/O System and Routing” section on page 34 of
this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1-percent accuracy at 3 MHz. The IMO can
be configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 50 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power Internal Low-Speed Oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C32 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V.
Notes
4. This feature on select devices only. See Ordering Information on page 106 for details.
5. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
This enables the device to be powered directly from a single
battery or solar cell. In addition, you can use the boost converter
to generate other voltages required by the device, such as a
3.3-V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 29 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for “printf” style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4-KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 59 of this datasheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1
through Figure 2-4. Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins. On the 68 pin and 100 pin devices each
set of Vddio associated pins may sink up to 100 mA. The 48-pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
Figure 2-1. 48-pin SSOP Part Pinout
(SIO ) P12[2]
(SIO ) P12[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(Extref0, GPIO) P0[3]
Vddio0
(GPIO) P0[4]
(GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(GPIO) P0[7]
Vccd
Vssd
Vddd
(GPIO) P2[3]
(GPIO) P2[4]
Vddio2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
Vssb
Ind
Vboost
Vbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Lines show
Vddio to I/O
supply
association
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
[6]
P15[7] (USBIO, D-, SW DCK)
[6]
P15[6] (USBIO, D+, SW DIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SW V)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SW DCK)
P1[0] (GPIO, TMS, SW DIO)
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
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48
47
46
45
44
43
42
41
40
39
38
37
P2[5] (GPIO)
Vddio2
P2[4] (GPIO)
P2[3] (GPIO)
Vddd
Vssd
Vccd
P0[7] (GPIO)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO)
Vddio0
Figure 2-2. 48-pin QFN Part Pinout[8]
(GPIO) P2[6]
(GPIO) P2[7]
1
2
Vssb
Ind
Vboost
Vbat
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, Configurable XRES) P1[2]
(GPIO, TDO, SWV) P1[3]
(GPIO, TDI) P1[4]
(GPIO, nTRST) P1[5]
3
4
5
6
QFN
( Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P0[3] (Extref0, GPIO)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
Vddio1
(GPIO) P1[6]
(GPIO) P1[7]
[7]
(USBIO, D+, SWDIO) P15[6]
[7]
(USBIO, D-, SWDCK) P15[7]
Vddd
Vssd
Vccd
(GPIO, MHz XTAL: Xo) P15[0]
(GPIO, MHz XTAL: Xi) P15[1]
Vddio3
(SIO, I2C1: SCL) P12[0]
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
Lines show
Vddio to I/O
supply
association
Notes
7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
8. PPins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P0[5] (GPIO)
P0[4] (GPIO)
Vddio0
53
52
P0[7] (GPIO)
P0[6] (GPIO, IDAC0)
55
54
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
Vddd
Vssd
Vccd
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
63
62
61
60
59
64
Vddio2
P2[4] (GPIO)
P2[3] (GPIO)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show Vddio
to I/O supply
association
QFN
P0[3] (GPIO, Extref0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
34
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
Vddio3
(GPIO) P3[5]
(GPIO) P3[3]
(GPIO) P3[4]
28
29
30
(MHz XTAL: Xi, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(Extref1, GPIO) P3[2]
31
32
33
24
25
26
27
Vddd
Vssd
Vccd
(MHz XTAL: Xo, GPIO) P15[0]
20
21
22
23
(GPIO) P1[6]
18
19
(Top View)
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
Vddio1
66
65
68
67
P2[5] (GPIO)
Figure 2-3. 68-pin QFN Part Pinout[10]
Notes
9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
Document Number: 001-56955 Rev. *J
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Data Sheet
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO)
47
48
49
50
(GPIO) P3[5]
Vddio3
46
43
44
45
36
37
38
[11] (USBIO, D-, SWDCK) P15[7]
Vddd
Vssd
Vccd
NC
NC
(MHz XTAL: Xo, GPIO) P15[0]
(MHz XTAL: Xi, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(Extref1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
42
32
33
34
35
54
53
52
51
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
[11]
(USBIO, D+, SWDIO) P15[6]
39
40
41
77
76
79
78
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO)
Vccd
P4[7] (GPIO)
P4[6] (GPIO)
85
84
83
82
81
80
Vddd
Vssd
87
86
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
95
94
93
92
91
96
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
98
97
28
29
30
TQFP
31
Vddio1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Lines show Vddio
to I/O supply
association
26
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
100
99
Vddio2
Figure 2-4. 100-pin TQFP Part Pinout
Vddio0
P0[3] (GPIO,Extref0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two layer board.
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on
page 29. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *J
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Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
Vddd
Vddd
C1
1 uF
Vddd
C2
0.1 uF
U2
CY8C55xx
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vdda
Vddd
Vddio0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0out, P0[1]
OA2out, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
kHzXin, P15[3]
kHzXout, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3out, P3[7]
OA1out, P3[6]
Vddio1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
Vddd
Vssd
Vccd
NC
NC
P15[0], MHzXout
P15[1], MHzXin
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
Vddio3
Vssd
Vddd
C12
0.1 uF
Vssd
Vddd
Vccd
Vssd
Vssd
C15
1 uF
C16
0.1 uF
C8
0.1 uF
C17
1 uF
Vssd
Vssd
Vssd
Vdda
Vssa
Vcca
Vssa
Vdda
C9
1 uF
C10
0.1 uF
Vssa
C11
0.1 uF
C13
10 uF, 6.3 V
Vssa
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vddd
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P32 47
48
49
50
Vssd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vssd
Vddio2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
Vddd
Vssd
Vccd
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
Vssd
Vddd
100
99
98
97
96
95
94
93
92
91
90
89
Vddd
88
Vssd
87
86
85
84
83
82
81
80
79
78
77
76
Vccd
C6
0.1 uF
C14
0.1 uF Vssd
Vssa
Vssd
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-6 on page 10.
Document Number: 001-56955 Rev. *J
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Data Sheet
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Vssa
Vddd
Vssd
Vdda
Vssa
Plane
Vssd
Plane
3. Pin Descriptions
nTRST
IDAC0
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
Low resistance output pin for high current DAC (IDAC).
SIO
Extref0, Extref1
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
External reference input to the analog system.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense.
I2C0: SCL, I2C1: SCL
SWDCK
Serial wire debug clock programming and debug port
connection.
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
SWDIO
I2C0: SDA, I2C1: SDA
SWV.
2
I C SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25- MHz crystal oscillator pin.
Document Number: 001-56955 Rev. *J
Serial wire debug input and output programming and debug port
connection.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
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Data Sheet
USBIO, D+
4. CPU
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are Do Not Use (DNU) on devices
without USB.
4.1 8051 CPU
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are No Connect (NC) on devices without
USB.
Vboost
Power sense connection to boost pump.
Vbat
Battery supply to boost pump.
The CY8C32 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C32 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
Vcca
Programmable nested vector interrupt controller
Output of analog core regulator and input to analog core.
Requires a 1-µF capacitor to VSSA. Regulator output not for
external use.
Direct memory access (DMA) controller
Vccd
External memory interface (EMIF)
Output of digital core regulator and input to digital core. The two
VCCD pins must be shorted together, with the trace between
them as short as possible, and a 1-µF capacitor to VSSD; see
Power System on page 29. Regulator output not for external use.
4.2 Addressing Modes
Vdda
Supply for all analog peripherals and analog core regulator.
Vdda must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
Vddd
Supply for all digital peripherals and digital core regulator. VDDA
must be less than or equal to VDDA.
Vssa
Ground for all analog peripherals.
Vssb
Ground connection for boost pump.
Vssd
Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3
Supply for I/O pins. See pinouts for specific I/O pin to Vddio
mapping. Each Vddio must be tied to a valid operating voltage
(1.71 V to 5.5 V), and must be less than or equal to Vdda. If the
I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used
then that Vddio should be tied to ground (Vssd or Vssa).
Peripheral HUB (PHUB)
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the data
pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
XRES (and configurable XRES)
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 23.
Document Number: 001-56955 Rev. *J
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4.3 Instruction Set
4.3.1 Instruction Set Summary
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
4.3.1.1 Arithmetic Instructions
Arithmetic instructions
Logical instructions
Data transfer instructions
Boolean instructions
Arithmetic instructions support the direct, indirect, register,
immediate constant, and register-specific instructions.
Arithmetic modes are used for addition, subtraction,
multiplication, division, increment, and decrement operations.
Table 4-1 Table 4-1 on page 12lists the different arithmetic
instructions.
Program branching instructions
Table 4-1. Arithmetic Instructions
Mnemonic
Description
Bytes
Cycles
ADD
A,Rn
Add register to accumulator
1
1
ADD
A,Direct
Add direct byte to accumulator
2
2
ADD
A,@Ri
Add indirect RAM to accumulator
1
2
ADD
A,#data
Add immediate data to accumulator
2
2
ADDC A,Rn
Add register to accumulator with carry
1
1
ADDC A,Direct
Add direct byte to accumulator with carry
2
2
ADDC A,@Ri
Add indirect RAM to accumulator with carry
1
2
ADDC A,#data
Add immediate data to accumulator with carry
2
2
SUBB A,Rn
Subtract register from accumulator with borrow
1
1
SUBB A,Direct
Subtract direct byte from accumulator with borrow
2
2
SUBB A,@Ri
Subtract indirect RAM from accumulator with borrow
1
2
SUBB A,#data
Subtract immediate data from accumulator with borrow
2
2
INC
A
Increment accumulator
1
1
INC
Rn
Increment register
1
2
INC
Direct
Increment direct byte
2
3
INC
@Ri
Increment indirect RAM
1
3
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
2
DEC
Direct
Decrement direct byte
2
3
DEC
@Ri
Decrement indirect RAM
1
3
INC
DPTR
Increment data pointer
1
1
MUL
Multiply accumulator and B
1
2
DIV
Divide accumulator by B
1
6
DAA
Decimal adjust accumulator
1
3
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4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2Table 4-2 on page 13
shows the list of logical instructions and their description.
Table 4-2. Logical Instructions
Mnemonic
Description
Bytes
Cycles
ANL
A,Rn
AND register to accumulator
1
1
ANL
A,Direct
AND direct byte to accumulator
2
2
ANL
A,@Ri
AND indirect RAM to accumulator
1
2
ANL
A,#data
AND immediate data to accumulator
2
2
ANL
Direct, A
AND accumulator to direct byte
2
3
ANL
Direct, #data
AND immediate data to direct byte
3
3
ORL
A,Rn
OR register to accumulator
1
1
ORL
A,Direct
OR direct byte to accumulator
2
2
ORL
A,@Ri
OR indirect RAM to accumulator
1
2
ORL
A,#data
OR immediate data to accumulator
2
2
ORL
Direct, A
OR accumulator to direct byte
2
3
ORL
Direct, #data
OR immediate data to direct byte
3
3
XRL
A,Rn
XOR register to accumulator
1
1
XRL
A,Direct
XOR direct byte to accumulator
2
2
XRL
A,@Ri
XOR indirect RAM to accumulator
1
2
XRL
A,#data
XOR immediate data to accumulator
2
2
XRL
Direct, A
XOR accumulator to direct byte
2
3
XRL
Direct, #data
XOR immediate data to direct byte
3
3
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumulator left
1
1
RLC
A
Rotate accumulator left through carry
1
1
RR
A
Rotate accumulator right
1
1
RRC A
Rotate accumulator right though carry
1
1
SWAP A
Swap nibbles within accumulator
1
1
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4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
addressing mode. Table 4-3 lists the various data transfer
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Table 4-4 on
page 15Table 4-4 lists the available Boolean instructions.
Table 4-3. Data Transfer Instructions
Mnemonic
Description
Bytes
Cycles
MOV
A,Rn
Move register to accumulator
1
1
MOV
A,Direct
Move direct byte to accumulator
2
2
MOV
A,@Ri
Move indirect RAM to accumulator
1
2
MOV
A,#data
Move immediate data to accumulator
2
2
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn,Direct
Move direct byte to register
2
3
MOV
Rn, #data
Move immediate data to register
2
2
MOV
Direct, A
Move accumulator to direct byte
2
2
MOV
Direct, Rn
Move register to direct byte
2
2
MOV
Direct, Direct
Move direct byte to direct byte
3
3
MOV
Direct, @Ri
Move indirect RAM to direct byte
2
3
MOV
Direct, #data
Move immediate data to direct byte
3
3
MOV
@Ri, A
Move accumulator to indirect RAM
1
2
MOV
@Ri, Direct
Move direct byte to indirect RAM
2
3
MOV
@Ri, #data
Move immediate data to indirect RAM
2
2
MOV
DPTR, #data16
Load data pointer with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative to DPTR to accumulator
1
5
MOVC A, @A + PC
Move code byte relative to PC to accumulator
1
4
MOVX A,@Ri
Move external RAM (8-bit) to accumulator
1
4
MOVX A, @DPTR
Move external RAM (16-bit) to accumulator
1
3
MOVX @Ri, A
Move accumulator to external RAM (8-bit)
1
5
MOVX @DPTR, A
Move accumulator to external RAM (16-bit)
1
4
PUSH Direct
Push direct byte onto stack
2
3
POP
Direct
Pop direct byte from stack
2
2
XCH
A, Rn
Exchange register with accumulator
1
2
XCH
A, Direct
Exchange direct byte with accumulator
2
3
XCH
A, @Ri
Exchange indirect RAM with accumulator
1
3
Exchange low order indirect digit RAM with accumulator
1
3
XCHD A, @Ri
Document Number: 001-56955 Rev. *J
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Table 4-4. Boolean Instructions
Mnemonic
Description
Bytes
Cycles
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
3
SETB C
Set carry
1
1
SETB bit
Set direct bit
2
3
CPL
C
Complement carry
1
1
CPL
bit
Complement direct bit
2
3
ANL
C, bit
AND direct bit to carry
2
2
ANL
C, /bit
AND complement of direct bit to carry
2
2
ORL C, bit
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to carry
2
2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C
Move carry to direct bit
2
3
JC
Jump if carry is set
2
3
rel
JNC rel
Jump if no carry is set
2
3
JB
Jump if direct bit is set
3
5
JNB bit, rel
Jump if direct bit is not set
3
5
JBC bit, rel
Jump if direct bit is set and clear bit
3
5
bit, rel
Document Number: 001-56955 Rev. *J
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4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A + DPTR
JZ rel
JNZ rel
CJNE A,Direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn,rel
DJNZ Direct, rel
NOP
Description
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if accumulator is zero
Jump if accumulator is nonzero
Compare direct byte to accumulator and jump if not equal
Compare immediate data to accumulator and jump if not equal
Compare immediate data to register and jump if not equal
Compare immediate data to indirect RAM and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Bytes
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
Cycles
4
4
4
4
3
4
3
5
4
4
5
4
4
5
4
5
1
4.4 DMA and PHUB
Simultaneous CPU and DMA access to peripherals located on
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
Simultaneous DMA source and destination burst transactions
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Document Number: 001-56955 Rev. *J
different spokes
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, USB, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
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4.4.2 DMA Features
24 DMA channels
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
shown in Table 4-7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
Table 4-7. Priority Levels
Priority Level
% Bus Bandwidth
0
100.0
1
100.0
2
50.0
3
25.0
4
12.5
5
6.2
6
3.1
7
1.5
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64k bytes
TDs may be nested and/or chained for complex transactions
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-1. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
B
ADDR 16/32
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA (A)
DATA
READY
Basic DMA Read Transfer without wait states
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
Document Number: 001-56955 Rev. *J
Basic DMA Write Transfer without wait states
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.4.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
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4.4.4.5 Scatter Gather DMA
4.5 Interrupt Controller
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
4.4.4.6 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.7 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Thirty two interrupt vectors
Jumps directly to ISR anywhere in code space with dynamic
vector addresses
Multiple sources for each vector
Flexible interrupt to vector matching
Each interrupt vector is independently enabled or disabled
Each interrupt can be dynamically assigned one of eight
priorities
Eight level nestable interrupts
Multiple I/O interrupt vectors
Software can send interrupts
Software can clear pending interrupts
When an interrupt is pending, the current instruction is
completed and the program counter is pushed onto the stack.
Code execution then jumps to the program address provided by
the vector. After the ISR is completed, a RETI instruction is
executed and returns execution to the instruction following the
previously interrupted instruction. To do this the RETI instruction
pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Figure 4-2 on page 19 represents typical flow of events when an
interrupt triggered. Figure 4-3 on page 20 shows the interrupt
structure and priority polling.
Document Number: 001-56955 Rev. *J
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Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
S
CLK
Arrival of new Interrupt
INT_INPUT
S
Pend bit is set on next system clock active edge
POST and PEND bits cleared after IRQ is sleared
PEND
S
Interrupt is posted to ascertain the priority
POST
S
Interrupt request sent to core for processing
IRQ
ACTIVE_INT_NUM
(#10)
NA
NA
INT_VECT_ADDR
0x0010
IRQ cleared after receiving IRA
S
S
The active interrupt
number is posted to core
The active interrupt ISR
address is posted to core
0x0000
S
S
NA
S
IRA
S
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
Complete ISR and return
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Document Number: 001-56955 Rev. *J
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Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupts form Fixed
function blocks, DMA and
UDBs
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 30
from UDBs
0
Interrupts 0 to 30
from Fixed
Function Blocks
1
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 31
sources
Interrupt 2 to 29
Interrupts 0 to
30 from DMA
Individual
Enable Disable
bits
0 to 30
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
30
Global Enable
disable bit
Document Number: 001-56955 Rev. *J
Lowest Priority
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Data Sheet
Table 4-8. Interrupt Vector Table
#
Fixed Function
DMA
UDB
0
LVD
phub_termout0[0]
udb_intr[0]
1
ECC
phub_termout0[1]
udb_intr[1]
2
Reserved
phub_termout0[2]
udb_intr[2]
3
Sleep (Pwr Mgr)
phub_termout0[3]
udb_intr[3]
4
PICU[0]
phub_termout0[4]
udb_intr[4]
5
PICU[1]
phub_termout0[5]
udb_intr[5]
6
PICU[2]
phub_termout0[6]
udb_intr[6]
7
PICU[3]
phub_termout0[7]
udb_intr[7]
8
PICU[4]
phub_termout0[8]
udb_intr[8]
9
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10] udb_intr[10]
11
PICU[12]
phub_termout0[11] udb_intr[11]
12
PICU[15]
phub_termout0[12] udb_intr[12]
13
Comparators
Combined
phub_termout0[13] udb_intr[13]
14
Reserved
phub_termout0[14] udb_intr[14]
15
I2C
phub_termout0[15] udb_intr[15]
16
Reserved
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
USB SOF Int
phub_termout1[5]
udb_intr[21]
22
USB Arb Int
phub_termout1[6]
udb_intr[22]
23
USB Bus Int
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
USB Endpoint Data phub_termout1[9]
udb_intr[25]
26
Reserved
27
LCD
phub_termout1[11] udb_intr[27]
28
Reserved
phub_termout1[12] udb_intr[28]
29
Decimator Int
phub_termout1[13] udb_intr[29]
30
PHUB Error Int
phub_termout1[14] udb_intr[30]
31
EEPROM Fault Int
phub_termout1[15] udb_intr[31]
phub_termout1[10] udb_intr[26]
Document Number: 001-56955 Rev. *J
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5. Memory
5.1 Static RAM
CY8C32 Static RAM (SRAM) is used for temporary data storage.
Up to 8 KB of SRAM is provided and can be accessed by the
8051 or the DMA controller. See Memory Map on page 24.
Simultaneous access of SRAM by the 8051 and the DMA
controller is possible if different 4-KB blocks are accessed.
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
64 KB of user program space.
Up to an additional 8 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected.
Flash is read in units of rows; each row is 9 bytes wide with 8
bytes of data and 1 byte of ECC data. When a row is read, the
data bytes are copied into an 8-byte instruction buffer. The CPU
fetches its instructions from this buffer, for improved CPU
performance.
Flash programming is performed through a special interface and
preempts code execution out of flash. The flash programming
interface performs flash erasing, programming and setting code
protection levels. Flash in-system serial programming (ISSP),
typically used for production programming, is possible through
both the SWD and JTAG interfaces. In-system programming,
typically used for bootloaders, is also possible using serial
interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data. A total of up to 256 blocks is provided on
64-KB flash devices.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
Document Number: 001-56955 Rev. *J
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security” section on page 60). For more information
about how to take full advantage of the security features in
PSoC, see the PSoC 3 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C32 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each.
The CPU can not execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
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5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-2.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
PRT15RDM[1:0]
DIG_PHS_DLY[3:0]
ECCEN
DPS[1:0]
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See “Reset Configuration” on page 40. All pins of the port 01b - high impedance digital
are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
0 (default for 68-pin and 100-pin parts) - GPIO
Controls whether pin P1[2] is used as a GPIO or as an
external reset. See “Pin Descriptions” on page 10, XRES 1 (default for 48-pin parts) - external reset
description.
DPS{1:0]
Controls the usage of various P1 pins as a debug port.
See “Programming, Debug Interfaces, Resources” on
page 59.
ECCEN
Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled
configuration and data storage. See “Flash Program
1 - ECC enabled
Memory” on page 22.
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
00b - 5-wire JTAG
01b (default) - 4-wire JTAG
10b - SWD
11b - debug ports disabled
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see “Nonvolatile Latches (NVL))” on page 95.
Document Number: 001-56955 Rev. *J
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5.6 External Memory Interface
CY8C32 provides an external memory interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C32
supports only one type of external memory device at a time.
External memory can be accessed via the 8051 xdata space; up
to 24 address bits can be used. See “xdata Space” section on
page 26. The memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
IO
PORTs
Data Signals
External_ MEM_ DATA[15:0]
IO
PORTs
Control Signals
IO
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
5.7 Memory Map
5.7.2 Internal Data Space
The CY8C32 8051 memory map is very similar to the MCS-51
memory map.
The CY8C32 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in Static RAM on page
22) and a 128-byte space for Special Function Registers (SFRs).
See Figure 5-2. The lowest 32 bytes are used for 4 banks of
registers R0-R7. The next 16 bytes are bit-addressable.
5.7.1 Code Space
The CY8C32 8051 code space is 64 KB. Only main flash exists
in this space. See the “Flash Program Memory” section on
page 22.
Document Number: 001-56955 Rev. *J
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Figure 5-2. 8051 Internal Data Space
0x00
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 11
4 Banks, R0-R7 Each
0x1F
0x20
Bit-Addressable Area
0x2F
0x30
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x7F
0x80
Upper Core RAM Shared
with Stack Space
(indirect addressing)
0xFF
SFR
Special Function Registers
(direct addressing)
5.7.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
0×F8
SFRPRT15DR
SFRPRT15PS
SFRPRT15SEL
–
–
–
–
–
0×F0
B
–
SFRPRT12SEL
–
–
–
–
–
0×E8
SFRPRT12DR
SFRPRT12PS
MXAX
–
–
–
–
–
0×E0
ACC
–
–
–
–
–
–
–
0×D8
SFRPRT6DR
SFRPRT6PS
SFRPRT6SEL
–
–
–
–
–
0×D0
PSW
–
–
–
–
–
–
–
0×C8
SFRPRT5DR
SFRPRT5PS
SFRPRT5SEL
–
–
–
–
–
0×C0
SFRPRT4DR
SFRPRT4PS
SFRPRT4SEL
–
–
–
–
–
0×B8
–
–
–
–
–
–
–
–
0×B0
SFRPRT3DR
SFRPRT3PS
SFRPRT3SEL
–
–
–
–
–
0×A8
IE
–
–
–
–
–
–
–
0×A0
P2AX
–
SFRPRT1SEL
–
–
–
–
–
0×98
SFRPRT2DR
SFRPRT2PS
SFRPRT2SEL
–
–
0×90
SFRPRT1DR
SFRPRT1PS
–
DPX0
0×88
–
SFRPRT0PS
SFRPRT0SEL
–
0×80
SFRPRT0DR
SP
DPL0
DPH0
The CY8C32 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C32
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C32 family.
XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
Document Number: 001-56955 Rev. *J
–
–
–
DPX1
–
–
–
–
–
–
DPL1
DPH1
DPS
–
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
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Table 5-5. XDATA Data Address Map (continued)
I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 34.
Address Range
Purpose
0×01 0000 – 0×01 FFFF Digital Interconnect configuration
0×05 0220 – 0×05 02F0
Debug controller
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
0×08 0000 – 0×08 1FFF
Flash ECC bytes
Each SFR supported I/O port provides three SFRs:
6. System Integration
SFRPRTxDR sets the output data state of the port (where x is
port number and includes ports 0 – 6, 12 and 15).
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
5.7.3.1 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 24.
Table 5-5. XDATA Data Address Map
Address Range
Purpose
0×80 0000 – 0×FF FFFF External Memory Interface
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±1 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. All of the system clock sources can be used to generate
other clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent PSoC.
Key features of the clocking system include:
0×00 0000 – 0×00 1FFF
SRAM
Seven general purpose clock sources
0×00 4000 – 0×00 42FF
Clocking, PLLs, and oscillators
0×00 4300 – 0×00 43FF
Power management
0×00 4400 – 0×00 44FF
Interrupt controller
3- to 24-MHz IMO, ±1 percent at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 29
DSI signal from an external I/O pin or other logic
24- to 50- MHz fractional PLL sourced from IMO, MHzECO,
or DSI
Clock Doubler
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
0×00 4500 – 0×00 45FF
Ports interrupt control
0×00 4700 – 0×00 47FF
Flash programming interface
0×00 4900 – 0×00 49FF
I2C controller
0×00 4E00 – 0×00 4EFF Decimator
0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs
0×00 5000 – 0×00 51FF
I/O ports control
0×00 5400 – 0×00 54FF
External Memory Interface (EMIF)
control registers
0×00 5800 – 0×00 5FFF
Analog Subsystem interface
0×00 6000 – 0×00 60FF
USB controller
0×00 6400 – 0×00 6FFF
UDB configuration
0×00 7000 – 0×00 7FFF
PHUB configuration
0×00 8000 – 0×00 8FFF
EEPROM
Document Number: 001-56955 Rev. *J
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the bus clock
Dedicated 4-bit divider for the CPU clock
Automatic clock configuration in PSoC Creator
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Table 6-1. Oscillator Summary
Source
IMO
Fmin
3 MHz
Tolerance at Fmin
±1% over voltage and temperature
Fmax
24 MHz
Tolerance at Fmax
±4%
Startup Time
10 µs max
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
12 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
50 MHz
50 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Figure 6-1. Clocking Subsystem
3-24 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-50 MHz
32 kHz ECO
1,33,100 kHz
ILO
12-48 MHz
Doubler
CPU
Clock
CPU Clock Divider
4 bit
24-50 MHz
PLL
System
Clock Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
6.1.1 Internal Oscillators
6.1.1.2 Clock Doubler
6.1.1.1 Internal Main Oscillator
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
In most designs the IMO is the only clock source required, due
to its ±1-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1 percent at 3 MHz, up to ±4-percent at
24 MHz. The IMO, in conjunction with the PLL, allows generation
of CPU and system clocks up to the device's maximum
frequency (see Phase-locked Loop)
The IMO provides clock outputs at 3, 6, 12, and 24 MHz.
Document Number: 001-56955 Rev. *J
6.1.1.3 Phase-locked Loop
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
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The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 50 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate to generate the CPU and system clocks
up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low-power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
Xi
(Pin P15[1])
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
Xo
(Pin P15[0])
4 – 25 MHz
crystal
External
Components
Capacitors
6.1.2.2 32.768-kHz ECO
The 32.768-kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Figure 6-3. 32kHzECO Block Diagram
The 100-kHz clock (CLK100K) works as a low-power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel.
The fast timewheel is a 100-kHz, 5-bit counter clocked by the ILO
that can also be used to wake the system. The fast timewheel
settings are programmable, and the counter automatically resets
when the terminal count is reached. This enables flexible,
periodic wakeups of the CPU at a higher rate than is allowed
using the central timewheel. The fast timewheel can generate an
optional interrupt each time the terminal count is reached.
XCLK_MHZ
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
“Phase-locked Loop” section on page 27). The GPIO pins
connecting to the external crystal and capacitors are fixed.
MHzECO accuracy depends on the crystal chosen.
Document Number: 001-56955 Rev. *J
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
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Data Sheet
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus Clock 16-bit divider uses the system clock to generate the
system's bus clock used for data transfers. Bus clock is the
source clock for the CPU clock divider.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
Timer/Counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, system clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(Vccd) and analog (Vcca) supplies for the internal core logic. The
output pins of the regulators (Vccd and Vcca) and the Vddio pins
must have capacitors connected as shown in Figure 6-4. The
two Vccd pins must be shorted together, with as short a trace as
possible, and connected to a 1-µF ±10-percent X5R capacitor.
The power system also contains a sleep regulator, an I2C
regulator, and a hibernate regulator.
components that require clocking, such as ADC. The analog
clock dividers include skew control to ensure that critical analog
events do not occur simultaneously with digital switching
events. This is done to reduce analog system noise.
Document Number: 001-56955 Rev. *J
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Data Sheet
Figure 6-4. PSoC Power System
Vddd
1 µF
Vddio2
Vddd
I/ O Supply
Vssd
Vccd
Vddio2
Vddio0
0.1µF
0.1µF
I/O Supply
Vddio0
0.1µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
Vdda
Vdda
Vcca
Analog
Regulator
Digital
Regulators
Vssd
0.1µF
1 µF
.
Vssa
Analog
Domain
0.1µF
I/O Supply
Vddio3
Vddd
Vssd
I/O Supply
Vccd
Vddio1
Hibernate
Regulator
0.1µF
0.1µF
Vddio1
Vddd
Vddio3
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-6.
Document Number: 001-56955 Rev. *J
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6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes.
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source
Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset,
peripherals available (program- manual register
mable)
entry
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Alternate
Active
Manual register
Similar to Active mode, and is
entry
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Hibernate
All subsystems automatically
Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Only hibernate regulator
active.
Manual register
entry
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
Active
–
1.2 mA[12]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
<15 µs
1 µA
No
I2C
Comparator
ILO/kHzECO
Comparator,
PICU, I2C, RTC,
CTW, LVD
XRES, LVD,
WDR
<100 µs
200 nA
No
None
None
None
PICU
XRES
Sleep
Hibernate
Note
12. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 63.
Document Number: 001-56955 Rev. *J
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6.2.1.5 Wakeup Events
Figure 6-5. Power Mode Transitions
Active
Manual
Sleep
Hibernate
Buzz
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Firmware enabled interrupt sources include internally
generated interrupts, power supervisor, central timewheel, and
I/O interrupts. Internal interrupt sources can come from a variety
of peripherals, such as analog comparators and UDBs. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES), WDT, and Precision Reset (PRES).
6.2.2 Boost Converter
Alternate
Active
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
Applications that use a supply voltage of less than 1.71 V, such
as solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
0.5 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage from 0.5 V to 5.5 V
(VBAT), and can start up with VBAT as low as 0.5 V. The converter
provides a user configurable output voltage of 1.8 to 5.0 V
(VBOOST). VBAT is typically less than VBOOST; if VBAT is greater
than or equal to VBOOST, then VBOOST will be the same as VBAT.
The block can deliver up to 50 mA (IBOOST) depending on
configuration.
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
Four pins are associated with the boost converter: VBAT, VSSB,
VBOOST, and Ind. The boosted output voltage is sensed at the
VBOOST pin and must be connected directly to the chip’s supply
inputs. An inductor is connected between the VBAT and Ind pins.
You can optimize the inductor value to increase the boost
converter efficiency based on input voltage, output voltage,
current and switching frequency. The External Schottky diode
shown in Figure 6-6 is required only in cases when
VBOOST > 3.6 V.
6.2.1.3 Sleep Mode
Figure 6-6. Application for Boost Converter
6.2.1.2 Alternate Active Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
Document Number: 001-56955 Rev. *J
Vboost
Optional
Schottky Diode
Only required
Vboost >3.6 V
Vdda Vddd Vddio
Ind
10 µH
22 µF
SMP
PSoC
22 µF 0. 1 µF
Vbat
Vssb
Vssa
Vssd
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The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,
or 32 kHz to optimize efficiency and component cost. The
100 kHz, 400 kHz, and 2 MHz switching frequencies are
generated using oscillators internal to the boost converter block.
When the 32-kHz switching frequency is selected, the clock is
derived from a 32 kHz external crystal oscillator. The 32-kHz
external clock is primarily intended for boost standby mode.
At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz
Vboost is limited to 4 × Vbat.
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low-power, low-current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption. Table 6-4 lists the boost power modes
available in different chip power modes.
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software – The device can be reset under program control.
Figure 6-7. Resets
Vddd Vdda
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Chip – Active mode
Boost Power Modes
Boost can be operated in either active
or standby mode.
Chip – Sleep mode
Boost can be operated in either active
or standby mode. However, it is recommended to operate boost in standby
mode for low-power consumption
Chip – Hibernate mode Boost can only be operated in active
mode. However, it is recommended not
to use boost in chip hibernate mode
due to high current consumption in
boost active mode
If the boost converter is not used in a given application, tie the
VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin
unconnected.
6.3 Reset
CY8C32 has multiple internal and external reset sources
available. The reset sources are:
Power source monitoring – The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External – The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must all
have voltage applied before the part comes out of reset.
Watchdog timer – A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
Document Number: 001-56955 Rev. *J
The term device reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power-on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
IPOR – Initial Power-on Reset
At initial power-on, IPOR monitors the power voltages VDDD
and VDDA, both directly at the pins and at the outputs of the
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the
voltage is high enough for PRES to release, the IMO starts.
PRES – Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
Page 33 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
services and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt,
Analog High Voltage Interrupt
Interrupt circuits are available to detect when VDDA and VDDD
go outside a voltage range. For AHVI, VDDA is compared to a
fixed trip level. For ALVI and DLVI, VDDA and VDDD are
compared to trip levels that are programmable, as listed in
Table 6-5. ALVI and DLVI can also be configured to generate
a device reset instead of an interrupt.
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Normal
Voltage
Range
VDDD 1.71 V –
5.5 V
Interrupt Supply
DLVI
ALVI
AHVI
VDDA 1.71 V –
5.5 V
VDDA 1.71 V –
5.5 V
Available Trip Accuracy
Settings
1.70 V – 5.45 V
in 250 mV
increments
1.70 V – 5.45 V
in 250 mV
increments
5.75 V
±2%
±2%
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both GPIO and Special I/O (SIO) provide
similar digital functionality. The primary differences are their
analog capability and drive strength. Devices that include USB
also provide two USBIO pins that support specific USB
functionality as well as limited GPIO capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense, and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
Features supported by both GPIO and SIO:
User programmable port reset state
Separate I/O supplies and voltages for up to four groups of I/O
Digital peripherals use DSI to connect the pins
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
Dedicated port interrupt vector for each port
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
Special functionality on a pin by pin basis
Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices
CapSense
Analog input and output capability
Continuous 100 µA clamp current capability
Standard drive strength down to 1.7 V
Additional features only provided on SIO pins:
Higher drive strength than GPIO
Hot swap capability (5 V tolerance at any operating VDD)
Programmable and regulated high input and output drive
levels down to 1.2 V
No analog input, CapSense, or LCD capability
Over voltage tolerance up to 5.5 V
SIO can act as a general purpose analog comparator
USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
±2%
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wake up
sequence. The interrupt is then recognized and may be
serviced.
6.3.1.2 Other Reset Sources
XRES – External Reset
PSoC 3 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
The external reset is active low. It includes an internal pull-up
resistor. XRES is active during sleep and hibernate modes.
SRES – Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
WRES – Watchdog Timer Reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power-on reset event.
Document Number: 001-56955 Rev. *J
6.4 I/O System and Routing
Page 34 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 6-8. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
Digital System Output
In
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
Capsense Global Control
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-56955 Rev. *J
5
Page 35 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
Driver
Vhigh
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SYNC_OUT
D+ pin only
USBIO_CR1[7]
USB or I/O
USB SIE Control for USB Mode
USBIO_CR1[4,5]
Digital System Output
PRT[x]BYP
Vddd
0
1
In
Drive
Logic
Vddd
5k
Vddd Vddd
1.5 k
PIN
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
Document Number: 001-56955 Rev. *J
D+ 1.5 k
D+D- 5 k
Open Drain
Page 36 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are
used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight
drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is
selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For
example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the
pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
Pin
1. High Impedance
Digital
DR
PS
Pin
2. Resistive
Pull-Up
Vddio
DR
PS
4. Open Drain,
Drives Low
Pin
DR
PS
Vddio
DR
PS
Pin
3. Resistive
Pull-Down
Vddio
Pin
5. Open Drain,
Drives High
DR
PS
Vddio
Pin
6. Strong Drive
DR
PS
Pin
7. Resistive
Pull-Up and Pull-Down
Table 6-6. Drive Modes
Diagram
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedence analog
Drive Mode
0
0
0
High Z
High Z
1
High Impedance digital
0
0
1
High Z
High Z
2
Resistive pull-up[13]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[13]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[13]
1
1
1
Res High (5K)
Res Low (5K)
Note
13. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Resistive pull-up or resistive pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull-up and pull-down
are not available with SIO in regulated output mode.
Open Drain, Drives High and Open Drain, Drives Low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
Strong Drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pull-up and pull-down are not
available with SIO in regulated output mode.
6.4.2 Pin Registers
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
Document Number: 001-56955 Rev. *J
6.4.3 Bidirectional Mode
High-speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRT×DM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRT×SLW registers.
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.7 I/O Power Supplies
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature allows
users to provide different I/O voltage levels for different pins on
the device. Refer to the specific device package pinout to
determine VDDIO capability for a given port and pin.
The SIO port pins support an additional regulated high output
capability, as described in Adjustable Output Level.
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Data Sheet
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, one select pin provides direct connection to the high
current DAC.
Figure 6-12. SIO Reference for Input and Output
Input Path
Digital
Input
Vinref
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders. See the
“CapSense” section on page 57 for more information.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 57 for details.
Reference
Generator
SIO_Ref
PIN
Voutref
Output Path
Driver
Vhigh
6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to output
either the standard VDDIO level or the regulated output, which is
based on an internally generated reference. Typically the voltage
DAC (VDAC) is used to generate the reference (see Figure
6-12). The “DAC” section on page 58 has more details on VDAC
use and reference routing to the SIO pins. Resistive pull-up and
pull-down drive modes are not available with SIO in regulated
output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO. The
reference sets the pins voltage threshold for a high logic level
(see Figure 6-12). Available input thresholds are:
0.5 × Vddio
0.4 × Vddio
0.5 × VREF
VREF
Typically the voltage DAC (VDAC) generates the VREF
reference. The “DAC” section on page 58 has more details on
VDAC use and reference routing to the SIO pins.
Document Number: 001-56955 Rev. *J
Digital
Output
Drive
Logic
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in Figure 6-9 on page 36 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
Page 39 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage tolerance feature at any
operating VDD.
There are no current limitations for the SIO pins as they present a
high impedance load to the external circuit where VDDIO < VIN <
5.5 V.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply where VDDIO < VIN < VDDA.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8 V, and
an external device could run from 5 V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated VDDIO supply
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull-down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull-down or pull-up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
6.4.17 Low-Power Functionality
In all low-power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low-power modes.
Analog
High current IDAC output
External reference inputs
6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
I/O pins for board level test.
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture. You
do not need to interact directly with the programmable digital
system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The main components of the digital programmable system are:
Universal Digital Blocks (UDB) – These form the core
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
Universal Digital Block Array – UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
Digital System Interconnect (DSI) – Digital signals from
Universal Digital Blocks (UDBs), fixed function peripherals, I/O
pins, interrupts, DMA, and other system core signals are
attached to the Digital System Interconnect to implement full
featured device connectivity. The DSI allows any digital function
to any pin or other feature routability when used with the
Universal Digital Block Array.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in Pinouts on page 5. The special features
are:
Digital
4- to 25- MHz crystal oscillator
32.768-kHz crystal oscillator
2
Wake from sleep on I C address match. Any pin can be used
for I2C if wake from sleep is not required.
JTAG interface pins
SWD interface pins
SWV interface pins
External reset
Document Number: 001-56955 Rev. *J
Page 40 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 7-1. CY8C32 Digital Programmable Architecture
IO Port
IO Port
Digital Core System
and Fixed Function Peripherals
DSI Routing Interface
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
Current
Voltage
PWM
Comparators
7.1.3 Example System Function Components
7.1 Example Peripherals
The flexibility of the CY8C32 family’s Universal Digital Blocks
(UDBs) and Analog Blocks allow the user to create a wide range
of components (peripherals). The most common peripherals
were built and characterized by Cypress and are shown in the
PSoC Creator component catalog, however, users may also
create their own custom components using PSoC Creator. Using
PSoC Creator, users may also create their own components for
reuse within their organization, for example sensor interfaces,
proprietary algorithms, and display interfaces.
The number of components available through PSoC Creator is
too numerous to list in the datasheet, and the list is always
growing. An example of a component available for use in
CY8C32 family, but, not explicitly called out in this datasheet is
the UART component.
7.1.1 Example Digital Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
I2C
UART
SPI
Functions
EMIF
PWMs
Timers
Counters
Logic
NOT
OR
XOR
AND
Document Number: 001-56955 Rev. *J
Delta-sigma
IO Port
Digital Core System
and Fixed Function Peripherals
ADC
DACs
DSI Routing Interface
Communications
The following is a sample of the analog components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (routing, RAM, flash) used by a component
varies with the features selected in PSoC Creator for the
component.
UDB
UDB Array
UDB
UDB
IO Port
UDB Array
UDB
7.1.2 Example Analog Components
The following is a sample of the system function components
available in PSoC Creator for the CY8C32 family. The exact
amount of hardware resources (UDBs, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
CapSense
LCD Drive
LCD Control
7.1.4 Designing with PSoC Creator
7.1.4.1 More Than a Typical IDE
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
Page 41 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 7-2. PSoC Creator Framework
Document Number: 001-56955 Rev. *J
Page 42 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
7.1.4.2 Component Catalog
7.1.4.4 Software Development
Figure 7-3. Component Catalog
Figure 7-4. Code Editor
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADC and DAC, and communication
protocols, such as I2C, and USB. See Example Peripherals on
page 41 for more details about available peripherals. All content
is fully characterized and carefully documented in datasheets
with code examples, AC/DC specifications, and user code ready
APIs.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
7.1.4.5 Nonintrusive Debugging
Figure 7-5. PSoC Creator Debugger
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion.
Breakpoints and code execution commands are all readily
available from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and
peripherals—make for an unparalleled level of visibility into the
system.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
Clock and Reset Module – This block provides the UDB clocks
and reset selection and control.
7.2.1 PLD Module
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, lookup tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
PT4
PT5
PT6
PT7
Figure 7-7. PLD 12C4 Structure
PT3
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
to provide a way for CPU firmware to interact and synchronize
with UDB operation.
PT2
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
Status and Control Module – The primary role of this block is
PT1
7.2 Universal Digital Block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
PT0
PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
Figure 7-6. UDB Block Diagram
PLD
Chaining
Clock
and Reset
Control
Status and
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Datapath
Datapath
Chaining
SELIN
(carry in)
OUT0
MC0
T
T
T
T
T
T
T
T
OUT1
MC1
T
T
T
T
T
T
T
T
OUT2
MC2
T
T
T
T
T
T
T
T
OUT3
MC3
T
T
T
T
T
T
T
T
SELOUT
(carry out)
Routing Channel
The main component blocks of the UDB are:
PLD blocks – There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
Datapath Module – This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
Document Number: 001-56955 Rev. *J
AND
Array
OR
Array
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
Page 44 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
Figure 7-8. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
F0
D1
Data Registers
A0
A1
D0
D1
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
6
Datapath Control
Input from
Programmable
Routing
Control Store RAM
8 Word X 16 Bit
FIFOs
Input
Muxes
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.1 Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumulators or ALU. Each FIFO is four
bytes deep.
Document Number: 001-56955 Rev. *J
7.2.2.2 Dynamic Datapath Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the
8-word × 16-bit configuration RAM, which stores eight unique
16-bit wide configurations. The address input to this RAM
controls the sequence, and can be routed from any block
connected to the UDB routing matrix, most typically PLD logic,
I/O pins, or from the outputs of this or other datapath blocks.
ALU
The ALU performs eight general purpose functions. They are:
Increment
Decrement
Add
Subtract
Logical AND
Logical OR
Logical XOR
Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
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Data Sheet
Independent of the ALU operation, these functions are available:
7.2.2.7 Chaining
Shift left
Shift right
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
Nibble swap
7.2.2.8 Time Multiplexing
Bitwise OR mask
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.3 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.4 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.5 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic
Redundancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Figure 7-9. Example FIFO Configurations
System Bus
D0/D1
A0/A1/ALU
System Bus
F1
A0/A1/ALU
A0/A1/ALU
F0
F0
F1
D0
A0
D1
A1
F1
System Bus
System Bus
TX/RX
Dual Capture
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-10. Status and Control Registers
System Bus
8-bit Status Register
(Read Only)
7.2.2.6 Input/Output FIFOs
F0
7.2.2.9 Datapath I/O
Document Number: 001-56955 Rev. *J
Dual Buffer
8-bit Control Register
(Write/Read)
Routing Channel
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.1 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
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PSoC® 3: CY8C32 Family
Data Sheet
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3 UDB Array Description
Figure 7-11 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Figure 7-11. Digital System Interface Structure
HV
A
Figure 7-12. Function Mapping Example in a Bank of UDBs
8-Bit
Timer
Quadrature Decoder
UDB
UDB
HV
A
HV
A
16-Bit PYRS
UDB
UDB
HV
A
HV
B
UDB
8-Bit
Timer Logic
UDB
8-Bit SPI
12-Bit SPI
UDB
HV
B
16-Bit
PWM
HV
B
UDB
UDB
I2C Slave
System Connections
HV
B
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Sequencer
7.2.3.2 Clock Generation
UDB
HV
B
UDB
HV
A
UDB
HV
B
HV
A
Logic
UDB
UDB
HV
A
UDB
HV
B
UDB
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
HV
B
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
UDB
UART
UDB
UDB
12-Bit PWM
7.4 DSI Routing Interface Description
HV
A
UDB
HV
A
UDB
HV
B
System Connections
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Signals in this category include:
Interrupt requests from all digital peripherals in the system.
7.3.1 UDB Array Programmable Resources
DMA requests from all digital peripherals in the system.
Figure 7-12 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Connection to analog system digital signals.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 7-13. Digital System Interconnect
Tim ers
C ounters
Interrupt
C ontroller
I2C
DMA
C ontroller
IO Port
Pins
G lobal
C locks
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
D igital System R outing I/F
DO
UDB ARRAY
DI
D igital System R outing I/F
Figure 7-16. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
G lobal
C locks
I/O Port
Pins
EM IF
D el-Sig
D AC
C om parators
Interrupt and DMA routing is very flexible in the CY8C32
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-14 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
DO
PIN 0
DO
PIN1
DO
PIN2
Fixed Function IRQs
0
1
IRQs
UDB Array
2
Edge
Detect
Interrupt
Controller
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
Port i
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
DO
PIN3
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
3
DRQs
DMA termout (IRQs)
4 IO Control Signal Connections from
UDB Array Digital System Interface
0
Fixed Function DRQs
1
Edge
Detect
DMA
Controller
2
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
Document Number: 001-56955 Rev. *J
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
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Data Sheet
7.5 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
Routing” section on page 34.
USB includes the following features:
Eight unidirectional data endpoints
One bidirectional control endpoint 0 (EP0)
Shared 512-byte buffer for the eight data endpoints
Dedicated 8-byte buffer for EP0
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
16-bit Timer/Counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Three memory modes
Manual Memory Management with No DMA Access
Manual Memory Management with Manual DMA Access
Automatic Memory Management with Automatic DMA
Access
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Timer capture mode
Internal 3.3 V regulator for transceiver
Count while enable signal is asserted mode
Internal 48 MHz main oscillator mode that auto locks to USB
Free run mode
bus clock, requiring no external crystal for USB (USB equipped
parts only)
Interrupts on bus and each endpoint event, with device wakeup
USB Reset, Suspend, and Resume operations
Bus powered and self powered modes
Figure 7-18. USB
System Bus
Arbiter
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
Interrupts
External 22 Ω
Resistors
USB
I/O
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
Figure 7-19. Timer/Counter/PWM
Clock
Reset
Enable
Capture
Kill
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
7.7 I2C
D–
48 MHz
IMO
7.6 Timers, Counters, and PWMs
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows you to choose the timer, counter, and PWM
features that they require. The tool set utilizes the most optimal
resources available.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
Document Number: 001-56955 Rev. *J
The I2C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I2C serial
communication bus. The bus is compliant with Philips ‘The I2C
Specification’ version 2.1. Additional I2C interfaces can be
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
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Data Sheet
I2C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to the
two special sets of SIO pins.
2
I C features include:
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
Data transfers follow the format shown in Figure 7-20. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
Figure 7-20. I2C Complete Transfer Timing
SDA
1-7
SCL
START
Condition
ADDRESS
8
9
R/W
ACK
Document Number: 001-56955 Rev. *J
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
Page 50 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
8. Analog Subsystem
High resolution delta-sigma ADC.
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
One 8-bit DAC that provides either voltage or current output.
Two comparators with optional connection to configurable LUT
outputs.
CapSense subsystem to enable capacitive touch sensing.
Precision reference for generating an accurate analog voltage
for internal analog blocks.
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
A
N
A
L
O
G
GPIO
Port
DelSig
ADC
Figure 8-1. Analog Subsystem Block Diagram
A
N
A
L
O
G
Precision
Reference
DAC
Comparators
R
O
U
T
I
N
G
CMP
R
O
U
T
I
N
G
CMP
CapSense Subsystem
Analog
Interface
DSI
Array
Clock
Distribution
Config &
Status
Registers
PHUB
GPIO
Port
CPU
Decimator
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and
various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that
allow you to configure the various analog blocks to perform application specific functions. The tool also generates API interface
libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory.
Document Number: 001-56955 Rev. *J
Page 51 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
8.1 Analog Routing
The CY8C32 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
8.1.1 Features
Flexible, configurable analog routing architecture
16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Each GPIO is connected to one analog global and one analog
Eight analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C32 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C32, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
mux bus
Document Number: 001-56955 Rev. *J
Page 52 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
Figure 8-2. CY8C32 Analog Interconnect
*
*
GPIO
P3[5]
GPIO
P3[4]
GPIO
P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
* P15[1]
GPXT
* P15[0]
3210 76543210
*
cmp0_vref
(1.024V)
in1
5
out1
comp0
+
-
cmp1_vref
refbufl_
cmp
*
swout
ExVrefR
swin
comp1 +
-
COMPARATOR
vref_cmp1
(0.256V)
bg_vda_res_en
cmp1_vref
bg_vda_swabusl0
CAPSENSE
out
ref
in refbufl
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
refbufr
out
ref
in
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
Vssa
vssa
* P15[7]
VIDAC
USB IO
* P15[6]
36
+
DSM0
-
DSM
vcm
refs
qtz_ref
vref_vss_ext
ExVrefL
refmux[2:0]
ExVrefR
01 23456 7 0123
3210 76543210
*
13
*
XRES
Vbat
Vssd
Ind
Vssb
Vboost
*
Document Number: 001-56955 Rev. *J
*
Large ( ~200 Ohms)
*
Switch Resistance
Small ( ~870 Ohms )
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
AGR[0]
AGR[3]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
AGL[3]
AGL[2]
AGL[1]
AGL[0]
AMUXBUSL
Notes:
* Denotes pins on all packages
LCD signals are not shown.
AMUXBUSR
LPF
*
Connection
VBE
Vss ref
*
*
Mux Group
Switch Group
TS
ADC
AGR[3]
AGR[2]
AGR[1]
AGL[1]
AGL[2]
AGL[3]
:
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
*
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
Vddio1
AMUXBUSL
28
*
en_resvda
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
* P1[7]
GPIO
* P1[6]
*
dsm0_qtz_vref2 (1.2V)
dsm0_qtz_vref1 (1.024V)
Vdda
Vdda/4
vssa
*
vpwra
vpwra/2
dsm0_vcm_vref1
(0.8V)
dsm0_vcm_vref2 (0.7V)
*
*
Vddio2
USB IO
v0
DAC0
i0
vcmsel[1:0]
en_resvpwra
Vssd
Vddd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
*
*
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
ABUSL0
ABUSL1
ABUSL2
ABUSL3
Vccd
*
*
Vssd
AGR[4]
AMUXBUSR
Vdda
Vdda/2
Vccd
cmp0_vref
(1.024V)
90
cmp_muxvn[1:0]
AGR[7]
AGR[6]
AGR[5]
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
LPF
out0
swin
refbufr_
cmp
in0
swout
i0
cmp1_vref
*
*
*
AGL[6]
AGL[7]
44
01 2 3 4 56 7 0123
*
*
ExVrefL2
*
*
*
*
AGR[6]
AGR[7]
AGL[7]
AGL[4]
AGL[5]
*
*
*
AGR[4]
AGR[5]
AGL[4]
AGL[5]
AGL[6]
ExVrefL
ExVrefL1
*
*
*
*
AMUXBUSR
AMUXBUSL
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
AMUXBUSL
Vssd
Vcca
Vssa
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinp
*
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
swinn
Rev #51
2-April-2010
Page 53 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C32,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
modulator/decimator frequency response is [(sin x)/x]4; a typical
frequency response is shown in Figure 8-5.
Figure 8-4. Delta-sigma ADC Block Diagram
Positive
Input Mux
8.2 Delta-sigma ADC
The CY8C32 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for measurement applications. The
converter can be configured to output 12-bit resolution at data
rates of up to 192 ksps. At a fixed clock rate, resolution can be
traded for faster data rates as shown in Table 8-1 and Figure 8-3.
(Analog Routing)
Input
Buffer
Negative
Input Mux
Delta
Sigma
Modulator
Decimator
12 to 20 Bit
Result
EOC
SOC
Figure 8-5. Delta-sigma ADC Frequency Response,
Normalized to Output, Sample Rate = 48 kHz
Table 8-1. Delta-sigma ADC Performance
Bits
Maximum Sample Rate
(sps)
SINAD (dB)
12
192 k
66
-10
8
384 k
43
-20
0
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
1,000,000
100,000
frequency Response. dB
-30
-40
-50
-60
-70
-80
-90
-100
100
1,000
10,000
100,000
1,000,000
Input Frequency, Hz
Sample rates, sps
Input frequency, Hz
10,000
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
1,000
Continuous
Multi-Sample
Resolution, bits
8.2.2 Operational Modes
100
7
8
9
10
11
12
13
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in Figure 8-4. The signal from the input
Document Number: 001-56955 Rev. *J
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continous, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
Page 54 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
8.2.2.1 Single Sample
8.2.3 Start of Conversion Input
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
8.2.2.2 Continuous
8.3 Comparators
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.2.3 Multi Sample
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
More information on output formats is provided in the Technical
Reference Manual.
Document Number: 001-56955 Rev. *J
8.2.4 End of Conversion Output
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
The CY8C32 family of devices contains two comparators in a
device. Comparators have these features:
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (VSSA to VDDA)
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
Comparator outputs can be routed to lookup tables to perform
simple logic functions and then can also be routed to digital
blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO or DAC output
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Page 55 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
Figure 8-6. Analog Comparator
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
_
From
Analog
Routing
4
LUT3
UDBs
8.3.2 LUT
The CY8C32 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Document Number: 001-56955 Rev. *J
Table 8-2. LUT Function vs. Program Word and Inputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
0111b
1000b
A OR B
A NOR B
1001b
1010b
1011b
1100b
1101b
1110b
1111b
A XNOR B
NOT B
A OR (NOT B)
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
Page 56 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
8.4 LCD Direct Drive
8.4.1 LCD Segment Pin Driver
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C32 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.4.2 Display Data Flow
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
Key features of the PSoC LCD segment system are:
8.4.3 UDB and LCD Segment Control
LCD panel direct driving
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
Type A (standard) and Type B (low-power) waveform support
Wide operating voltage range support (2 V to 5 V) for LCD
panels
Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
Internal bias voltage generation through internal resistor ladder
Up to 62 total common and segment outputs
Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
Up to 62 front plane/segment outputs for direct drive
Drives up to 736 total segments (16 backplane × 46 front plane)
Up to 64 levels of software controlled contrast
Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
Adjustable LCD refresh rate from 10 Hz to 150 Hz
Ability to invert LCD display for negative image
Three LCD driver drive modes, allowing power optimization
Figure 8-7. LCD System
LCD
DAC
Global
Clock
UDB
LCD Driver
Block
DMA
8.4.4 LCD DAC
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
8.5 CapSense
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in each CapSense component in
PSoC Creator.
A capacitive sensing method using a delta-sigma modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
8.6 Temp Sensor
PIN
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
Display
RAM
PHUB
Document Number: 001-56955 Rev. *J
Page 57 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
8.7 DAC
Source and sink option for current output
The CY8C32 parts contain a Digital to Analog Converter (DAC).
The DAC is 8-bit and can be configured for either voltage or
current output. The DAC supports CapSense, power supply
regulation, and waveform generation. The DAC has the following
features:
8 Msps conversion rate for current output
Adjustable voltage or current output in 255 steps
Programmable step size (range selection)
1 Msps conversion rate for voltage output
Monotonic in nature
Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
Dedicated low-resistance output pin for high-current mode
Eight bits of calibration to correct ± 25 percent of gain error
Figure 8-8. DAC Block Diagram
I
Reference
Source
Scaler
source Range
1x , 8x , 64x
Vout
R
Iout
3R
I sink Range
1x , 8x , 64x
8.7.1 Current DAC
8.7.2 Voltage DAC
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be
configured to source or sink current.
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
Document Number: 001-56955 Rev. *J
Page 58 of 119
[+] Feedback
PSoC® 3: CY8C32 Family
Data Sheet
9. Programming, Debug Interfaces,
Resources
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device. Permanently
disabling interfaces is not recommended in most applications
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
Debug and Trace Configuration
All debug and trace disabled
JTAG
SWD
SWV
SWD + SWV
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D– pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or programming the flash memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
9.3 Debug Features
Using the JTAG or SWD interface, the CY8C32 supports the
following debug features:
Halt and single-step the CPU
View and change CPU and peripheral registers, and RAM
addresses
Eight program address breakpoints
One memory access breakpoint—break on reading or writing
any memory address and data value
Break on a sequence of breakpoints (non recursive)
Debugging at the full speed of the CPU
Debug operations are possible while the device is reset, or in
GPIO Pins Used
0
4 or 5
2
1
3
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit
transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,
whichever is least. By default, the JTAG pins are enabled on new
devices but the JTAG interface can be disabled, allowing these
pins to be used as General Purpose I/O (GPIO) instead. The
JTAG interface is used for programming the flash memory,
debugging, I/O scan chains, and JTAG device chaining.
Document Number: 001-56955 Rev. *J
9.2 Serial Wire Debug Interface
low-power modes
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG programming and debugging interfaces make
CY8C32 compatible with other popular third-party tools (for
example, ARM / Keil)
9.4 Trace Features
The CY8C32 supports the following trace features when using
JTAG or SWD:
Trace the 8051 program counter (PC), accumulator register
(ACC), and one SFR / 8051 core RAM register
Trace depth up to 1000 instructions if all registers are traced,
or 2000 instructions if only the PC is traced (on devices that
include trace memory)
Program address trigger to start tracing
Trace windowing, that is, only trace when the PC is within a
given range
Two modes for handling trace buffer full: continuous (overwriting
the oldest trace data) or break when trace buffer is full
Page 59 of 119
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Data Sheet
9.5 Single Wire Viewer Interface
The SWV interface is closely associated with SWD but can also
be used independently. SWV data is output on the JTAG
interface’s TDO pin. If using SWV, you must configure the device
for SWD, not JTAG. SWV is not supported with the JTAG
interface.
SWV is ideal for application debug where it is helpful for the
firmware to output data similar to 'printf' debugging on PCs. The
SWV is ideal for data monitoring, because it requires only a
single pin and can output data in standard UART format or
Manchester encoded format. For example, it can be used to tune
a PID control loop in which the output and graphing of the three
error terms greatly simplifies coefficient tuning.
The following features are supported in SWV:
32 virtual channels, each 32 bits long
Simple, efficient packing and serializing protocol
Supports standard UART format (N81)
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. You can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 3 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0×50536F43) to a Write Once Latch (WOL).
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0×50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
Document Number: 001-56955 Rev. *J
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0×50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security” on
page 22). However, after setting the values in the WOL, a user
still has access to the part until it is reset. Therefore, a user can
write the key into the WOL, program the flash protection data,
and then reset the part to lock it.
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out via Serial Wire Debug
(SWD) port to electrically identify protected parts. The user can
write the key in WOL to lock out external access only if no flash
protection is set. For more information on how to take full
advantage of the security features in PSoC see the PSoC 3
TRM.
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Page 60 of 119
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Data Sheet
10. Development Support
The CY8C32 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
10.1 Documentation
A suite of documentation, supports the CY8C32 family to ensure
that you can find answers to your questions quickly. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Document Number: 001-56955 Rev. *J
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C32 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
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PSoC® 3: CY8C32 Family
Data Sheet
11. Electrical Specifications
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC
Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example
Peripherals” section on page 41 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Higher storage temperatures
reduce NVL data retention time.
Recommended storage temperature is +25 °C ±25 °C. Extended
duration storage temperatures
above 85 °C degrade reliability.
–55
25
100
°C
Analog supply voltage relative to
VSSA
–0.5
–
6
V
VDDD
Digital supply voltage relative to
VSSD
–0.5
–
6
V
VDDIO
I/O supply voltage relative to VSSD
–0.5
–
6
V
VCCA
Direct analog core voltage input
–0.5
–
1.95
V
VCCD
Direct digital core voltage input
–0.5
–
1.95
V
VSSA
Analog ground voltage
VSSD –0.5
–
VSSD +
0.5
V
VGPIO[14]
DC input voltage on GPIO
Includes signals sourced by VDDA
and routed internal to the pin
VSSD –0.5
–
VDDIO +
0.5
V
VSIO
DC input voltage on SIO
Output disabled
VSSD –0.5
–
7
V
Output enabled
VSSD –0.5
–
6
V
TSTG
Storage temperature
VDDA
VIND
Voltage at boost converter input
VBAT
Boost converter supply
Ivddio
Current per VDDIO supply pin
Vextref
ADC external reference inputs
Pins P0[3], P3[2]
current[15]
0.5
–
5.5
V
VSSD –0.5
–
5.5
V
–
–
100
mA
–
–
2
V
LU
Latch up
–140
–
140
mA
ESDHBM
Electrostatic discharge voltage
Human body model
750
–
–
V
ESDCDM
Electrostatic discharge voltage
Charge device model
500
–
–
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Notes
14. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA.
15. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Document Number: 001-56955 Rev. *J
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11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Min
Typ
Max
Units
VDDA
Parameter
Analog supply voltage and input to Analog core regulator enabled
analog core regulator
Description
1.8
–
5.5
V
VDDA
Analog supply voltage, analog
regulator bypassed
Analog core regulator disabled
1.71
1.8
1.89
V
VDDD
Digital supply voltage relative to
VSSD
Digital core regulator enabled
1.8
–
VDDA[16]
V
VDDD
Digital supply voltage, digital
regulator bypassed
Digital core regulator disabled
1.71
1.8
1.89
V
VDDIO[17]
I/IO supply voltage relative to VSSIO
1.71
–
VDDA[16]
V
VCCA
Direct analog core voltage input
(Analog regulator bypass)
Analog core regulator disabled
1.71
1.8
1.89
V
VCCD
Direct digital core voltage input
(Digital regulator bypass)
Digital core regulator disabled
1.71
1.8
1.89
V
IDD[18]
Active Mode, VDD = 1.71 V–5.5 V
T = –40 °C
–
–
–
mA
T = 25 °C
–
0.8
–
mA
T = 85 °C
–
–
–
mA
Bus clock off. Execute from CPU
instruction buffer. See “Flash
Program Memory” on page 22.
Conditions
CPU at 3 MHz
CPU at 6 MHz
CPU at 12 MHz
CPU at 24 MHz
–
–
–
mA
–
1.2
–
mA
T = 85 °C
–
–
–
mA
T = –40 °C
–
–
–
mA
T = 25 °C
–
2.0
–
mA
T = 85 °C
–
–
–
mA
T = –40 °C
–
–
–
mA
T = 25 °C
–
3.5
–
mA
T = 85 °C
–
–
–
mA
T = –40 °C
–
–
–
mA
T = 25 °C
–
6.6
–
mA
T = 85 °C
–
–
–
mA
CPU at 3 MHz
–
1.4
–
mA
CPU at 6 MHz
–
2.2
–
mA
CPU at 12 MHz
–
3.6
–
mA
CPU at 24 MHz
–
6.4
–
mA
CPU at 48 MHz
–
11.8
–
mA
CPU at 48 MHz
VDD = 3.3 V, T = 25 °C, IMO and bus
clock enabled, ILO = 1 kHz, CPU
executing from flash and accessing
SRAM, all other blocks off, all I/Os
tied low.
T = –40 °C
T = 25 °C
Notes
16. The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies.
17. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA.
18. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
Document Number: 001-56955 Rev. *J
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Table 11-2. DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
T = –40 °C
–
–
–
µA
T = 25 °C
–
–
–
µA
T = 85 °C
–
–
–
µA
[20]
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in
low-power mode)
Sleep timer = ON (= ILO ON at
1 kHz)[21]
WDT = OFF
I2C Wake = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 4.5–5.5 V
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
I2C Wake = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7–3.6 V
T = –40 °C
–
–
–
µA
T = 25 °C
–
1
–
µA
T = 85 °C
–
–
–
µA
–
–
–
µA
T = 25 °C
–
–
–
µA
T = 85 °C
–
–
–
µA
VDD = VDDIO = 2.7–3.6V
T = 25 °C
–
–
–
µA
VDD = VDDIO = 2.7–3.6V
T= 25 °C
–
–
–
µA
VDD = VDDIO = 4.5–5.5 V
T = –40 °C
–
–
–
nA
T = 25 °C
–
–
–
nA
T = 85 °C
–
–
–
nA
VDD = VDDIO = 1.71–1.95 V T = –40 °C
Hibernate Mode[20]
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7–3.6 V
T = –40 °C
–
–
–
nA
T = 25 °C
–
200
–
nA
T = 85 °C
–
–
–
nA
–
–
–
nA
T = 25 °C
–
–
–
nA
T = 85 °C
–
–
–
nA
VDD = VDDIO = 1.71–1.95 V T = –40 °C
Notes
19. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
20. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
21. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Document Number: 001-56955 Rev. *J
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Data Sheet
Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V,
Temperature = 25 °C
Figure 11-2. Active Mode Current vs Temperature and FCPU,
VDD = 3.3 V
Figure 11-3. Active Mode Current vs VDD and Temperature,
FCPU = 24 MHz
Document Number: 001-56955 Rev. *J
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Data Sheet
Table 11-3. AC Specifications[22]
Parameter
Description
Conditions
Min
Typ
Max
Units
FCPU
CPU frequency
1.71 V ≤ VDDD ≤ 5.5 V
DC
–
50.01
MHz
FBUSCLK
Bus frequency
1.71 V ≤ VDDD ≤ 5.5 V
DC
–
50.01
MHz
Svdd
VDD ramp rate
–
–
1
V/ns
TIO_INIT
Time from VDDD/VDDA/VCCD/VCCA
≥ IPOR to I/O ports set to their reset
states
–
–
10
µs
TSTARTUP
Time from VDDD/VDDA/VCCD/VCCA VCCA/VCCD = regulated from
≥ PRES to CPU executing code at VDDA/VDDD, no PLL used, IMO
reset vector
boot mode (12 MHz typ.)
–
–
66
µs
TSLEEP
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
–
–
15
µs
THIBERNATE
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
–
–
100
µs
Figure 11-4. FCPU vs. VDD
Vdd Voltage
5.5 V
Valid Operating Region
3.3 V
1.71 V
Valid Operating Region with SMP
0.5 V
0V
DC
1 MHz
10 MHz
50 MHz
CPU Frequency
Note
22. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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11.3 Power Regulators
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDD
Output voltage
VCCD
Regulator output capacitor
Conditions
±10%, X5R ceramic or better. The two
VCCD pins must be shorted together, with
as short a trace as possible, see Power
System on page 29
Figure 11-5. Regulators VCC vs VDD
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-6. Digital Regulator PSRR vs Frequency and VDD
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDA
Output voltage
VCCA
Regulator output capacitor
Conditions
±10%, X5R ceramic or better
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-7. Analog Regulator PSRR vs Frequency and VDD
Document Number: 001-56955 Rev. *J
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Data Sheet
11.3.3 Inductive Boost Regulator.
Table 11-6. Inductive Boost Regulator DC Specifications
Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 µH,
CBOOST = 22 µF || 0.1 µF
Parameter
VBAT
IOUT
Description
Min
Typ
Max
Units
T=-35 °C to +65 °C
0.5
–
3.6
V
Over entire temperature range
0.68
–
3.6
V
VBAT = 1.6 – 3.6 V, VOUT = 3.6 – 5.0 V,
external diode
–
–
50
mA
VBAT = 1.6 – 3.6 V, VOUT = 1.6 – 3.6 V,
internal diode
–
–
75
mA
VBAT = 0.8 – 1.6 V, VOUT = 1.6 – 3.6 V,
internal diode
–
–
30
mA
VBAT = 0.8 – 1.6 V, VOUT = 3.6 – 5.0 V,
external diode
–
–
20
mA
VBAT = 0.5 – 0.8 V, VOUT = 1.6 – 3.6 V,
internal diode
–
–
15
mA
–
–
700
mA
Boost active mode
–
200
–
µA
Boost standby mode, 32 khz external crystal
oscillator, IOUT < 1 ìA
–
12
–
µA
1.8 V
1.71
1.80
1.89
V
1.9 V
1.81
1.90
2.00
V
2.0 V
1.90
2.00
2.10
V
2.4 V
2.28
2.40
2.52
V
2.7 V
2.57
2.70
2.84
V
3.0 V
2.85
3.00
3.15
V
3.3 V
3.14
3.30
3.47
V
3.6 V
3.42
3.60
3.78
V
4.75
5.00
5.25
V
–
–
3.8
%
Input voltage
Includes startup
Load current
[23, 24]
ILPK
Inductor peak current
IQ
Quiescent current
VOUT
Conditions
Boost voltage range[25, 26]
5.0 V
RegLOAD
Load regulation
RegLINE
Line regulation
η
Efficiency
External diode required
–
–
4.1
%
LBOOST = 10 µH
70
85
–
%
LBOOST = 22 µH
82
90
–
%
Notes
23. For output voltages above 3.6 V, an external diode is required.
24. Maximum output current applies for output voltages ≤ 4x input voltage.
25. Based on device characterization (Not production tested).
26. At boost frequency of 2 MHz, VOUT is limited to 2 x VBAT. At 400 kHz, VOUT is limited to 4 x VBAT.
Document Number: 001-56955 Rev. *J
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Table 11-7. Inductive Boost Regulator AC Specifications
Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 2.7 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 µH,
CBOOST = 22 µF || 0.1 µF.
Parameter
Description
VRIPPLE
Ripple voltage (peak-to-peak)
FSW
Switching frequency
Conditions
Min
VOUT = 1.8 V, FSW = 400 kHz, IOUT = 10 mA
Typ
Max
Units
–
–
100
mV
–
0.1, 0.4,
or 2
–
MHz
Table 11-8. Recommended External Components for Boost Circuit
Parameter
LBOOST
Description
Conditions
Boost inductor
[27]
CBOOST
Filter capacitor
IF
External Schottky diode
average forward current
External Schottky diode is required for
VOUT > 3.6 V
VR
Min
Typ
Max
Units
4.7
10
47
µH
10
22
47
µF
1
–
–
A
20
–
–
V
Note
27. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Figure 11-8. Efficiency vs VOUT
IOUT = 30 mA, VBAT ranges from 0.7 V to VOUT, LBOOST = 22 µH
Figure 11-9. Efficiency vs VBAT
IOUT = 30 mA, VOUT = 3.3 V, LBOOST = 22 µH
Figure 11-10. Efficiency vs IOUT
VBAT = 2.4 V, VOUT = 3.3 V
Figure 11-11. Efficiency vs IOUT
VBAT ranges from 0.7 V to 3.3 V, LBOOST = 22 µH
Figure 11-12. Efficiency vs Switching Frequency
VOUT = 3.3 V, VBAT = 2.4 V, IOUT = 40 mA
Document Number: 001-56955 Rev. *J
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11.1 Inputs and Outputs
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
11.1.1 GPIO
Table 11-9. GPIO DC Specifications
Parameter
Description
VIH
Input voltage high threshold
VIL
Input voltage low threshold
VIH
Input voltage high threshold
Conditions
CMOS Input, PRT[×]CTL = 0
CMOS Input, PRT[×]CTL = 0
LVTTL Input, PRT[×]CTL =
1, VDDIO < 2.7 V
LVTTL Input, PRT[×]CTL =
1, VDDIO ≥ 2.7V
LVTTL Input, PRT[×]CTL =
1, VDDIO < 2.7 V
LVTTL Input, PRT[×]CTL =
1, VDDIO ≥ 2.7V
IOH = 4 mA at 3.3 VDDIO
IOH = 1 mA at 1.8 VDDIO
IOL = 8 mA at 3.3 VDDIO
IOL = 4 mA at 1.8 VDDIO
VIH
Input voltage high threshold
VIL
Input voltage low threshold
VIL
Input voltage low threshold
VOH
Output voltage high
VOL
Output voltage low
Rpullup
Rpulldown
IIL
CIN
VH
Idiode
Pull-up resistor
Pull-down resistor
Input leakage current (absolute value)[29]
25 °C, VDDIO = 3.0 V
Input capacitance[29]
Input voltage hysteresis (Schmitt-Trigger)[29]
Current through protection diode to VDDIO and
VSSIO
Resistance pin to analog global bus
25 °C, VDDIO = 3.0 V
Resistance pin to analog mux bus
25 °C, VDDIO = 3.0 V
Rglobal
Rmux
Figure 11-13. GPIO Output High Voltage and Current
Min
0.7 × VDDIO
–
0.7 × VDDIO
Typ
–
–
–
Max
–
0.3 × VDDIO
–
Units
V
V
V
2.0
–
–
V
–
–
0.3 × VDDIO
V
–
–
0.8
V
VDDIO – 0.6
VDDIO – 0.5
–
–
3.5
3.5
–
–
–
–
–
–
–
–
5.6
5.6
–
–
40
–
–
–
0.6
0.6
8.5
8.5
2
7
–
100
V
V
V
V
kΩ
kΩ
nA
pF
mV
µA
–
–
320
220
–
–
Ω
Ω
Figure 11-14. GPIO Output Low Voltage and Current
Note
28. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
Table 11-10. GPIO AC Specifications
Parameter
Description
TriseF
Rise time in Fast Strong Mode[29]
TfallF
TriseS
TfallS
Fgpioout
Fgpioin
Conditions
3.3 V VDDIO Cload = 25 pF
Min
–
Typ
–
Max
12
Units
ns
Fall time in Fast Strong Mode[29]
Rise time in Slow Strong Mode[29]
Fall time in Slow Strong Mode[29]
GPIO output operating frequency
2.7 V < VDDIO < 5.5 V, fast strong drive mode
1.71 V < VDDIO < 2.7 V, fast strong drive mode
3.3 V < VDDIO < 5.5 V, slow strong drive mode
1.71 V < VDDIO < 3.3 V, slow strong drive mode
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
–
–
–
–
–
–
12
60
60
ns
ns
ns
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
–
–
–
–
–
–
–
–
33
20
7
3.5
MHz
MHz
MHz
MHz
GPIO input operating frequency
1.71 V < VDDIO < 5.5 V
90/10% VDDIO
–
–
50
MHz
Figure 11-15. GPIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-16. GPIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Note
29. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
11.1.2 SIO
Table 11-11. SIO DC Specifications
Parameter
Description
Vinmax
Maximum input voltage
Vinref
Input voltage reference (Differential input mode)
Conditions
Min
Typ
Max
Units
–
–
5.5
V
0.5
–
0.52 × VDDIO
V
VDDIO > 3.7
1
–
VDDIO – 1
V
VDDIO < 3.7
1
–
VDDIO – 0.5
V
All allowed values of Vddio and
Vddd, see Section 11.2.1
Output voltage reference (Regulated output mode)
Voutref
Input voltage high threshold
VIH
0.7 × VDDIO
–
–
V
SIO_ref + 0.2
–
–
V
CMOS input
–
–
0.3 × VDDIO
V
Hysteresis disabled
–
–
SIO_ref – 0.2
V
GPIO mode
CMOS input
Differential input mode[30]
Hysteresis disabled
Input voltage low threshold
VIL
GPIO mode
Differential input
mode[30]
Output voltage high
VOH
Unregulated mode
IOH = 4 mA, VDDIO = 3.3 V
VDDIO – 0.4
–
–
V
Regulated mode[30]
IOH = 1 mA
SIO_ref – 0.65
–
SIO_ref + 0.2
V
IOH = 0.1 mA
SIO_ref – 0.3
–
SIO_ref + 0.2
V
Regulated
mode[30]
Output voltage low
VOL
VDDIO = 3.30 V, IOL = 25 mA
–
–
0.8
V
VDDIO = 1.80 V, IOL = 4 mA
–
–
0.4
V
Rpullup
Pull-up resistor
3.5
5.6
8.5
kΩ
Rpulldown
Pull-down resistor
3.5
5.6
8.5
kΩ
IIL
Input leakage current (absolute
value)[31]
VIH < Vddsio
25 °C, Vddsio = 3.0 V, VIH = 3.0 V
–
–
14
nA
VIH > Vddsio
25 °C, Vddsio = 0 V, VIH = 3.0 V
–
–
10
µA
–
–
7
pF
Single ended mode (GPIO mode)
–
40
–
mV
Differential mode
–
35
–
mV
–
–
100
µA
CIN
Input Capacitance[31]
VH
Input voltage hysteresis
(Schmitt-Trigger)[31]
Idiode
Current through protection diode
to VSSIO
Notes
30. See Figure 6-9 on page 36 and Figure 6-12 on page 39 for more information on SIO reference
31. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
Figure 11-17. SIO Output HighVoltage and Current,
Unregulated Mode
Figure 11-18. SIO Output Low Voltage and Current,
Unregulated Mode
Figure 11-19. SIO Output High Voltage and Current,
Regulated Mode
Table 11-12. SIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Description
Rise time in Fast Strong Mode
(90/10%)[32]
Fall time in Fast Strong Mode
(90/10%)[32]
Rise time in Slow Strong Mode
(90/10%)[32]
Fall time in Slow Strong Mode
(90/10%)[32]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
–
Typ
–
Max
12
Units
ns
Cload = 25 pF, VDDIO = 3.3 V
–
–
12
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
60
ns
Note
32. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
Table 11-12. SIO AC Specifications (continued)
Parameter
Fsioout
Fsioin
Description
SIO output operating frequency
2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast
strong drive mode
1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast
strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow
strong drive mode
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 5.5 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 2.7 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
Min
Typ
Max
Units
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
16
MHz
90/10% VDDIO into 25 pF
–
–
5
MHz
90/10% VDDIO into 25 pF
–
–
4
MHz
Output continuously switching
into 25 pF
–
–
20
MHz
Output continuously switching
into 25 pF
–
–
10
MHz
Output continuously switching
into 25 pF
–
–
2.5
MHz
90/10% VDDIO
–
–
50
MHz
Figure 11-20. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Document Number: 001-56955 Rev. *J
Figure 11-21. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Page 75 of 119
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Data Sheet
11.1.3 USBIO
For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 63.
Table 11-13. USBIO DC Specifications
Parameter
Rusbi
Description
USB D+ pull-up resistance
Min
Typ
Max
Units
With idle bus
Conditions
0.900
–
1.575
kΩ
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
kΩ
Vohusb
Static output high
15 kΩ ±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 kΩ ±5% to Vss, internal pull-up
enabled
–
–
0.3
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD ≥ 3 V
2.4
–
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD ≥ 3 V
–
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
–
–
0.2
V
Vcm
Differential input common mode
range
–
0.8
–
2.5
V
0.8
–
2
V
3
–
7
kΩ
21.78
(–1%)
22
22.22
(+1%)
Ω
28
–
44
Ω
Vse
Single ended receiver threshold
–
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
External USB series resistor
In series with each USB pin
Zo
USB driver output impedance
Including Rext
CIN
USB transceiver input capacitance –
–
–
20
pF
IIL
Input leakage current (absolute
value)
–
–
2
nA
Rext
25 °C, VDDD = 3.0 V
Figure 11-22. USBIO Output High Voltage and Current, GPIO
Mode
Document Number: 001-56955 Rev. *J
Figure 11-23. USBIO Output Low Voltage and Current, GPIO
Mode
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Data Sheet
Table 11-14. USBIO AC Specifications
Parameter
Description
Tdrate
Full-speed data rate average bit rate
Tjr1
Tjr2
Tdj1
Tdj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Fgpio_out
Tr_gpio
Tf_gpio
Conditions
Receiver data jitter tolerance to next
transition
Receiver data jitter tolerance to pair
transition
Driver differential jitter to next
transition
Driver differential jitter to pair transition
Source jitter for differential transition to
SE0 transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential transition
GPIO mode output operating
3 V ≤ VDDD ≤ 5.5 V
frequency
VDDD = 1.71 V
Rise time, GPIO mode, 10%/90%
VDDD > 3 V, 25 pF load
VDDD
VDDD = 1.71 V, 25 pF load
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Min
12 – 0.25%
Typ
12
Units
MHz
–
Max
12 +
0.25%
8
–8
–5
–
5
ns
–3.5
–
3.5
ns
–4
–2
–
–
4
5
ns
ns
160
82
–
–
–
–
175
–
14
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
20
6
12
40
12
40
MHz
MHz
ns
ns
ns
ns
Min
–
–
90%
Typ
–
–
–
Max
20
20
111%
Units
ns
ns
1.3
–
2
V
ns
Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode,
VDDD = 3.3 V, 25 pF Load
Table 11-15. USB Driver AC Specifications
Parameter
Description
Tr
Transition rise time
Tf
Transition fall time
TR
Rise/fall time matching
Vcrs
Output signal crossover voltage
Document Number: 001-56955 Rev. *J
Conditions
VUSB_5, VUSB_3.3, see USB DC
Specifications on page 93
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Data Sheet
11.1.4 XRES
Table 11-16. XRES DC Specifications
Parameter
Description
VIH
Input voltage high threshold
VIL
Input voltage low threshold
Rpullup
CIN
VH
Idiode
Conditions
Pull-up resistor
Input capacitance[33]
Input voltage hysteresis
(Schmitt-Trigger)[33]
Current through protection diode to
VDDIO and VSSIO
Min
0.7 × VDDIO
–
Typ
–
–
Units
V
V
5.6
3
100
Max
–
0.3 ×
VDDIO
8.5
–
–
3.5
–
–
–
–
100
µA
Min
1
Typ
–
Max
–
Units
µs
kΩ
pF
mV
Table 11-17. XRES AC Specifications
Parameter
Description
Reset pulse width
TRESET
Document Number: 001-56955 Rev. *J
Conditions
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Data Sheet
11.2 Analog Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.2.1 Delta-sigma ADC
Unless otherwise specified, operating conditions are:
Operation in continuous sample mode
fclk = 6.144 MHz
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
Table 11-18. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Ge
Gain error
Gd
Gain drift
Vos
Input offset voltage
TCVos
INL12
DNL12
INL8
DNL8
Rin_Buff
Temperature coefficient, input offset
voltage
Input voltage range, single ended[34]
Input voltage range, differential unbuffered[34]
Input voltage range, differential,
buffered[34]
Integral non linearity[34]
Differential non linearity[34]
Integral non linearity[34]
Differential non linearity[34]
ADC input resistance
Rin_ADC12 ADC input resistance
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V
Buffered, 16-bit mode, VDDA = 2.7 V,
25 °C
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Input buffer used
Input buffer bypassed, 12 bit,
Range = ±1.024 V
ADC external reference input voltage, see
also internal reference in Voltage
Pins P0[3], P3[2]
Reference on page 81
Current Consumption
IDD_12
Current consumption, 12 bit[34]
192 ksps, unbuffered
IBUFF
Buffer current consumption[34]
Vextref
Min
8
Typ
–
Units
bits
–
Max
12
No. of
GPIO
No. of
GPIO/2
–
–
–
–
–
–
–
–
±0.2
%
–
–
50
ppm/°C
–
–
±0.1
mV
–
–
55
µV/°C
VSSA
–
VDDA
V
VSSA
–
VDDA
V
VSSA
–
VDDA – 1
V
–
–
–
–
10
–
–
–
–
–
±1
±1
±1
±1
–
LSB
LSB
LSB
LSB
MΩ
–
148[35]
–
kΩ
0.9
–
1.3
V
–
–
–
–
1.4
2.5
mA
mA
–
–
–
Notes
34. Based on device characterization (Not production tested).
35. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional
to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
Document Number: 001-56955 Rev. *J
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Data Sheet
Table 11-19. Delta-sigma ADC AC Specifications
Parameter
Description
Conditions
Startup time
Total harmonic distortion[36]
THD
Min
Typ
Max
Units
–
–
4
Samples
Buffer gain = 1, 16 bit,
Range = ±1.024 V
–
–
0.0032
%
12-Bit Resolution Mode
SR12
Sample rate, continuous, high power[36]
Range = ±1.024 V, unbuffered
4
–
192
ksps
BW12
Input bandwidth at max sample rate[36]
Range = ±1.024 V, unbuffered
–
44
–
kHz
SINAD12int
Signal to noise ratio, 12-bit, internal
reference[36]
Range = ±1.024 V, unbuffered
66
–
–
dB
Range = ±1.024 V, unbuffered
8
–
384
ksps
Range = ±1.024 V, unbuffered
–
88
–
kHz
Range = ±1.024 V, unbuffered
43
–
–
dB
8-Bit Resolution Mode
Sample rate, continuous, high power[36]
SR8
rate[36]
BW8
Input bandwidth at max sample
SINAD8int
Signal to noise ratio, 8-bit, internal
reference[36]
Table 11-20. Delta-sigma ADC Sample Rates, Range = ±1.024 V
Continuous
Multi-Sample
Resolution,
Bits
Min
Max
Min
Max
8
8000
384000
1911
91701
9
6400
307200
1543
74024
10
5566
267130
1348
64673
11
4741
227555
1154
55351
12
4000
192000
978
46900
Figure 11-25. Delta-sigma ADC IDD vs sps, Range = ±1.024 V,
Continuous Sample Mode, Input Buffer Bypassed
Note
36. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
11.2.2 Voltage Reference
Table 11-21. Voltage Reference Specifications
See also ADC external reference specifications in Section 11.2.1.
Parameter
VREF
Description
Conditions
Precision reference voltage
Initial trim
Min
Typ
Max
Units
1.014 (–1%)
1.024
1.034 (+1%)
V
11.2.3 Analog Globals
Table 11-22. Analog Globals Specifications
Parameter
Rppag
Description
Conditions
Resistance pin-to-pin through analog global[37]
Rppmuxbus Resistance pin-to-pin through analog mux
bus[37]
Min
Typ
Max
Units
VDDA = 3.0 V
–
939
1461
Ω
VDDA = 3.0 V
–
721
1135
Ω
11.2.4 Comparator
Table 11-23. Comparator DC Specifications
Parameter
Conditions
Min
Max
Units
Input offset voltage in fast mode
Description
Factory trim, Vdda > 2.7 V,
Vin ≥ 0.5 V
–
10
mV
Input offset voltage in slow mode
Factory trim, Vin ≥ 0.5 V
–
9
mV
Custom trim
–
–
4
mV
Custom trim
–
–
4
mV
–
±12
–
mV
VOS
VOS
Input offset voltage in fast
mode[38]
Input offset voltage in slow mode[38]
Typ
VOS
Input offset voltage in ultra low-power
mode
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
High current / fast mode
VSSA
–
VDDA – 0.1
V
Low current / slow mode
VSSA
–
VDDA
V
Ultra low power mode
VSSA
–
VDDA – 0.9
CMRR
Common mode rejection ratio
–
50
–
dB
ICMP
High current mode/fast mode[39]
–
–
400
µA
Low current mode/slow mode[39]
–
–
100
µA
Ultra low-power mode[39]
–
6
–
µA
Table 11-24. Comparator AC Specifications
Parameter
Description
Response time, high current
Tresp
mode[39]
Response time, low current mode[39]
Response time, ultra low-power
mode[39]
Conditions
Min
Typ
Max
Units
50 mV overdrive, measured pin-to-pin
–
50 mV overdrive, measured pin-to-pin
–
75
110
ns
155
200
ns
50 mV overdrive, measured pin-to-pin
–
55
–
µs
Notes
37. The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended
38. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
39. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
11.2.5 Current Digital-to-analog Converter (IDAC)
See the IDAC component datasheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-25. IDAC DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–
–
8
bits
Range = 2.048 mA, code = 255,
VDDA ≥ 2.7 V, Rload = 600 Ω
–
2.048
–
mA
Range = 2.048 mA, High mode,
code = 255, VDDA ≤ 2.7 V, Rload =
300 Ω
–
2.048
–
mA
Range = 255 µA, code = 255, Rload
= 600 Ω
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600 Ω
–
31.875
–
µA
–
–
Yes
Resolution
IOUT
Output current at code = 255
Monotonicity
Ezs
Zero scale error
Eg
Gain error
TC_Eg
INL
DNL
Vcompliance
Temperature coefficient of gain
error
Integral nonlinearity
Differential nonlinearity
Dropout voltage, source or sink
mode
Document Number: 001-56955 Rev. *J
–
0
±1
LSB
Range = 2.048 mA, 25 °C
–
–
±2.5
%
Range = 255 µA, 25 ° C
–
–
±2.5
%
Range = 31.875 µA, 25 ° C
–
–
±3.5
%
Range = 2.048 mA
–
–
0.04
% / °C
Range = 255 µA
–
–
0.04
% / °C
Range = 31.875 µA
–
–
0.05
% / °C
Sink mode, range = 255 µA, Codes
8 – 255, Rload = 2.4 kΩ, Cload =
15 pF
–
±0.9
±1
LSB
Source mode, range = 255 µA,
Codes 8 – 255, Rload = 2.4 kΩ,
Cload = 15 pF
–
±1.2
±1.5
LSB
Sink mode, range = 255 µA, Rload
= 2.4 kΩ, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 255 µA,
Rload = 2.4 kΩ, Cload = 15 pF
–
±0.3
±1
LSB
Voltage headroom at max current,
Rload to Vdda or Rload to Vssa,
Vdiff from Vdda
1
–
–
V
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Table 11-25. IDAC DC Specifications (continued)
Parameter
IDD
Description
Operating current, code = 0
Conditions
Min
Typ
Max
Units
Slow mode, source mode, range =
31.875 µA
–
44
100
µA
Slow mode, source mode, range =
255 µA,
–
33
100
µA
Slow mode, source mode, range =
2.04 mA
–
33
100
µA
Slow mode, sink mode, range =
31.875 µA
–
36
100
µA
Slow mode, sink mode, range =
255 µA
–
33
100
µA
Slow mode, sink mode, range =
2.04 mA
–
33
100
µA
Fast mode, source mode, range =
31.875 µA
–
310
500
µA
Fast mode, source mode, range =
255 µA
–
305
500
µA
Fast mode, source mode, range =
2.04 mA
–
305
500
µA
Fast mode, sink mode, range =
31.875 µA
–
310
500
µA
Fast mode, sink mode, range =
255 µA
–
300
500
µA
Fast mode, sink mode, range =
2.04 mA
–
300
500
µA
Figure 11-26. IDAC INL vs Input Code, Range = 255 µA,
Source Mode
Document Number: 001-56955 Rev. *J
Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Sink
Mode
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Figure 11-28. IDAC DNL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Sink
Mode
Figure 11-30. IDAC INL vs Temperature, Range = 255 µA, Fast
Mode
Figure 11-31. IDAC DNL vs Temperature, Range = 255 µA,
Fast Mode
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Figure 11-32. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Source Mode
Figure 11-33. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Sink Mode
Figure 11-34. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Source Mode
Figure 11-35. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Sink Mode
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Table 11-26. IDAC AC Specifications
Parameter
Description
FDAC
Update rate
TSETTLE
Settling time to 0.5 LSB
Conditions
Min
–
Range = 31.875 µA or 255 µA, full
scale transition, fast mode, 600 Ω
15-pF load
–
Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0,
255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V
Typ
Max
Units
–
8
Msps
–
125
ns
Figure 11-37. IDAC Glitch Response, Codes 0x7F - 0x80,
255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V
Figure 11-38. IDAC PSRR vs Frequency
Document Number: 001-56955 Rev. *J
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11.2.6 Voltage Digital to Analog Converter (VDAC)
See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-27. VDAC DC Specifications
Parameter
Description
Conditions
Resolution
8
–
bits
±2.5
LSB
1 V scale
–
±0.3
±1
LSB
1 V scale
–
4
–
kΩ
4 V scale
–
16
–
kΩ
1 V scale
–
1
–
V
–
4
–
V
–
–
Yes
–
Differential nonlinearity
Rout
Output resistance
VOUT
Output voltage range, code = 255
1 V scale
4 V scale, Vdda = 5 V
Monotonicity
Gain error
TC_Eg
IDD
Operating current
Units
±2.1
DNL1
Zero scale error
Max
–
Integral nonlinearity
Eg
Typ
–
INL1
VOS
Min
–
0
±0.9
LSB
1 V scale
–
–
±2.5
%
4 V scale
–
–
±2.5
%
Temperature coefficient, gain error 1 V scale
–
–
0.03
%FSR / °C
Figure 11-39. VDAC INL vs Input Code, 1 V Mode
Document Number: 001-56955 Rev. *J
4 V scale
–
–
0.03
%FSR / °C
Slow mode
–
–
100
µA
Fast mode
–
–
500
µA
Figure 11-40. VDAC DNL vs Input Code, 1 V Mode
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Figure 11-41. VDAC INL vs Temperature, 1 V Mode
Figure 11-42. VDAC DNL vs Temperature, 1 V Mode
Figure 11-43. VDAC Full Scale Error vs Temperature, 1 V
Mode
Figure 11-44. VDAC Full Scale Error vs Temperature, 4 V
Mode
Figure 11-45. VDAC Operating Current vs Temperature, 1V
Mode, Slow Mode
Figure 11-46. VDAC Operating Current vs Temperature, 1 V
Mode, Fast Mode
Document Number: 001-56955 Rev. *J
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Table 11-28. VDAC AC Specifications t
Parameter
FDAC
Description
Update rate
Conditions
Min
Typ
Max
Units
1 V scale
–
–
1000
ksps
4 V scale
–
–
250
ksps
–
0.45
1
µs
TsettleP
Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF
75%
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
TsettleN
Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF
25%
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Figure 11-47. VDAC Step Response, Codes 0x40 - 0xC0, 1 V
Mode, Fast Mode, Vdda = 5 V
Figure 11-48. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V
Mode, Fast Mode, Vdda = 5 V
Figure 11-49. VDAC PSRR vs Frequency
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11.2.7 Temperature Sensor
Table 11-29. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
Typ
Max
Units
–
±5
–
°C
11.2.8 LCD Direct Drive
Table 11-30. LCD Direct Drive DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
ICC
LCD system operating current
Device sleep mode with wakeup at
400-Hz rate to refresh LCDs, bus
clock = 3 Mhz, Vddio = Vdda = 3 V,
4 commons, 16 segments, 1/4 duty
cycle, 50 Hz frame rate, no glass
connected
–
38
–
μA
ICC_SEG
Current per segment driver
Strong drive mode
–
260
–
µA
VBIAS
LCD bias range (VBIAS refers to the VDDA ≥ 3 V and VDDA ≥ VBIAS
main output voltage(V0) of LCD DAC)
2
–
5
V
VDDA ≥ 3 V and VDDA ≥ VBIAS
–
9.1 × VDDA
–
mV
Drivers may be combined
–
500
5000
pF
LCD bias step size
LCD capacitance per
segment/common driver
Long term segment offset
IOUT
Output drive current per segment
driver)
Vddio = 5.5V, strong drive mode
–
–
20
mV
355
–
710
µA
Min
10
Typ
50
Max
150
Units
Hz
Table 11-31. LCD Direct Drive AC Specifications
Parameter
Description
LCD frame rate
fLCD
Document Number: 001-56955 Rev. *J
Conditions
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11.3 Digital Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.3.1 Timer
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for
more information, see the Timer component datasheet in PSoC Creator.
Table 11-32. Timer DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
3 MHz
Min
Typ
Max
Units
–
–
–
µA
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
50.01
MHz
Capture pulse width (Internal)
21
–
–
ns
Capture pulse width (external)
42
–
–
ns
Timer resolution
21
–
–
ns
Table 11-33. Timer AC Specifications
Parameter
Description
Conditions
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
11.3.2 Counter
The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in
UDBs; for more information, see the Counter component datasheet in PSoC Creator.
Table 11-34. Counter DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit counter, at listed input clock
frequency
3 MHz
12 MHz
50 MHz
Min
–
Typ
–
Max
–
Units
µA
–
–
–
15
60
260
–
–
–
µA
µA
µA
Min
DC
21
21
21
42
21
42
21
42
Typ
–
–
–
–
–
–
–
–
–
Max
50.01
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Table 11-35. Counter AC Specifications
Parameter
Description
Operating frequency
Capture pulse
Resolution
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Document Number: 001-56955 Rev. *J
Conditions
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11.3.3 Pulse Width Modulation
The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented
in UDBs; for more information, see the PWM component datasheet in PSoC Creator..
Table 11-36. PWM DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
DC
–
50.01
MHz
Pulse width
21
–
–
ns
Pulse width (external)
42
–
–
ns
Kill pulse width
21
–
–
ns
Kill pulse width (external)
42
–
–
ns
Table 11-37. Pulse Width Modulation (PWM) AC Specifications
Parameter
Description
Conditions
Operating frequency
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
Min
Typ
Max
Units
11.3.4 I2C
Table 11-38. Fixed I2C DC Specifications
Parameter
Description
Block current consumption
Conditions
Enabled, configured for 100 kbps
–
–
250
µA
Enabled, configured for 400 kbps
–
–
260
µA
Wake from sleep mode
–
–
30
µA
Min
Typ
Max
Units
–
–
1
Mbps
Typ
–
Max
200
Table 11-39. Fixed I2C AC Specifications
Parameter
Description
Conditions
Bit rate
Controller Area Network[40]
Table 11-40. CAN DC Specifications
Parameter
Description
Block current consumption
IDD
Conditions
Min
–
Units
µA
Conditions
Min
Typ
Max
Units
–
–
1
Mbit
Table 11-41. CAN AC Specifications
Parameter
Description
Bit rate
Minimum 8 MHz clock
Note
40. Refer to ISO 11898 specification for details.
Document Number: 001-56955 Rev. *J
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11.3.5 USB
Table 11-42. USB DC Specifications
Parameter
Min
Typ
Max
Units
USB configured, USB regulator
enabled
4.35
–
5.25
V
VUSB_3.3
USB configured, USB regulator
bypassed
3.15
–
3.6
V
VUSB_3
USB configured, USB regulator
bypassed[41]
2.85
–
3.6
V
IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz
mode, bus clock and IMO = 24 MHz V
DDD = 3.3 V, FCPU = 1.5 MHz
–
10
–
mA
–
8
–
mA
IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB
mode
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 5 V, disconnected from
USB host
–
0.3
–
mA
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 3.3 V, disconnected from
USB host
–
0.3
–
mA
VUSB_5
Description
Device supply for USB operation
Conditions
11.3.6 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-43. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
50.01
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
50.01
MHz
–
–
50.01
MHz
–
–
50.01
MHz
Datapath Performance
FMAX_CRC
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C, Vddd ≥ 2.7 V
out, see Figure 11-50.
–
20
25
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-50.
and pin selection
–
–
55
ns
Note
41. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 77.
Document Number: 001-56955 Rev. *J
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Figure 11-50. Clock to Output Performance
11.4 Memory
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.4.1 Flash
Table 11-44. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Min
–
–
–
–
–
–
Typ
15
10
5
–
–
–
Max
20
13
7
35
15
5
Units
ms
ms
ms
ms
ms
seconds
20
–
–
years
10
–
–
Min
1.71
Typ
–
Max
5.5
Table 11-45. Flash AC Specifications
Parameter
Description
Row write time (erase + program)
TWRITE
Row erase time
TERASE
Row program time
Bulk erase time (16 KB to 64 KB)
TBULK
Sector erase time (8 KB to 16 KB)
Total device program time, including
JTAG or SWD, and other overhead
Flash data retention time, retention
period measured from last erase cycle
Conditions
Average ambient temp.
TA ≤ 55 °C, 100 K erase/program
cycles
Average ambient temp.
TA ≤ 85 °C, 10 K erase/program
cycles
11.4.2 EEPROM
Table 11-46. EEPROM DC Specifications
Parameter
Description
Erase and program voltage
Document Number: 001-56955 Rev. *J
Conditions
Units
V
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Table 11-47. EEPROM AC Specifications
Parameter
Description
Conditions
Single row erase/write cycle time
TWRITE
EEPROM data retention time, retention Average ambient temp, TA ≤ 25 °C,
period measured from last erase cycle 1M erase/program cycles
Average ambient temp, TA ≤ 55 °C,
100 K erase/program cycles
Average ambient temp.
TA ≤ 85 °C, 10 K erase/program
cycles
Min
–
20
Typ
2
–
Max
20
–
20
–
–
10
–
–
Units
ms
years
11.4.3 Nonvolatile Latches (NVL))
Table 11-48. NVL DC Specifications
Parameter
Description
Erase and program voltage
Min
Typ
Max
Units
VDDD pin
Conditions
1.71
–
5.5
V
Conditions
Programmed at 25 °C
Min
1K
Typ
–
Max
–
Programmed at 0 °C to 70 °C
100
–
–
Programmed at 25 °C
Programmed at 0 °C to 70 °C
20
20
–
–
–
–
Units
program/
erase
cycles
program/
erase
cycles
years
years
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
50.01
MHz
Table 11-49. NVL AC Specifications
Parameter
Description
NVL endurance
NVL data retention time
11.4.4 SRAM
Table 11-50. SRAM DC Specifications
Parameter
VSRAM
Description
Conditions
SRAM retention voltage
Table 11-51. SRAM AC Specifications
Parameter
FSRAM
Description
SRAM operating frequency
Document Number: 001-56955 Rev. *J
Conditions
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11.4.5 External Memory Interface
Figure 11-51. Asynchronous Read Cycle Timing
Tcel
EM_ CEn
Taddrv
EM_ Addr
Taddrh
Address
Toel
EM_ OEn
EM_ WEn
Tdoesu
Tdoeh
EM_ Data
Data
Table 11-52. Asynchronous Read Cycle Specifications
Parameter
Description
T
EMIF clock period[42]
Tcel
EM_CEn low time
Taddrv
Taddrh
Toel
Conditions
Vdda ≥ 3.3 V
Min
Typ
Max
Units
30.3
–
–
nS
2T – 5
–
2T+ 5
nS
EM_CEn low to EM_Addr valid
–
–
5
nS
Address hold time after EM_Wen high
T
–
–
nS
EM_OEn low time
2T – 5
–
2T + 5
nS
Tdoesu
Data to EM_OEn high setup time
T + 15
–
–
nS
Tdoeh
Data hold time after EM_OEn high
3
–
–
nS
Note
42. Limited by GPIO output frequency, see Table 11-10 on page 72.
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Figure 11-52. Asynchronous Write Cycle Timing
Taddrv
Taddrh
EM_ Addr
Address
Tcel
EM_ CEn
Twel
EM_ WEn
EM_ OEn
Tdweh
Tdcev
EM_ Data
Data
Table 11-53. Asynchronous Write Cycle Specifications
Parameter
Description
period[43]
T
EMIF clock
Tcel
EM_CEn low time
Taddrv
Taddrh
Twel
EM_WEn low time
Tdcev
EM_CEn low to data valid
Tdweh
Data hold time after EM_WEn high
Conditions
Vdda ≥ 3.3 V
Min
Typ
Max
Units
30.3
–
–
nS
T–5
–
T+5
nS
EM_CEn low to EM_Addr valid
–
–
5
nS
Address hold time after EM_WEn high
T
–
–
nS
T–5
–
T+5
nS
–
–
7
nS
T
–
–
nS
Note
43. Limited by GPIO output frequency, see Table 11-10 on page 72.
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Figure 11-53. Synchronous Read Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-54. Synchronous Read Cycle Specifications
Parameter
Description
period[44]
Conditions
Vdda ≥ 3.3 V
Min
Typ
Max
Units
30.3
–
–
nS
T/2
–
–
nS
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
nS
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
nS
Taddrv
EM_Addr valid to EM_Clock high
Taddriv
EM_Clock high to EM_Addr invalid
Toeld
Toehd
5
–
–
nS
T/2 – 5
–
–
nS
EM_OEn low to EM_Clock high
5
–
–
nS
EM_Clock high to EM_OEn high
T
–
–
nS
Tds
Data valid before EM_OEn high
T + 15
–
–
nS
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
nS
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
nS
Note
44. Limited by GPIO output frequency, see Table 11-10 on page 72.
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Figure 11-54. Synchronous Write Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tdh
Tds
Data
EM_ Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-55. Synchronous Write Cycle Specifications
Parameter
Description
Period[45]
Conditions
Vdda ≥ 3.3 V
Min
Typ
Max
Units
30.3
–
–
nS
T/2
–
–
nS
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
nS
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
nS
Taddrv
EM_Addr valid to EM_Clock high
5
–
–
nS
Taddriv
EM_Clock high to EM_Addr invalid
T/2 – 5
–
–
nS
Tweld
EM_WEn low to EM_Clock high
5
–
–
nS
Twehd
EM_Clock high to EM_WEn high
T/2 – 5
–
–
nS
Tds
Data valid before EM_Clock high
5
–
–
nS
Tdh
Data invalid after EM_Clock high
T
–
–
nS
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
nS
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
nS
Note
45. Limited by GPIO output frequency, see Table 11-10 on page 72.
Document Number: 001-56955 Rev. *J
Page 99 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
11.5 PSoC System Resources
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 POR with Brown Out
For brown out detect in regulated mode, VDDD and VDDA must be ≥ 2.0 V. Brown out detect is not available in externally regulated
mode.
Table 11-56. Precise Power-on Reset (PRES) with Brown Out DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
1.64
–
1.68
V
1.62
–
1.66
V
Min
Typ
Max
Units
–
–
0.5
µs
–
5
–
V/sec
Min
Typ
Max
Units
1.68
1.89
2.14
2.38
2.62
2.87
3.11
3.35
3.59
3.84
4.08
4.32
4.56
4.83
5.05
5.30
5.57
1.73
1.95
2.20
2.45
2.71
2.95
3.21
3.46
3.70
3.95
4.20
4.45
4.70
4.98
5.21
5.47
5.75
1.77
2.01
2.27
2.53
2.79
3.04
3.31
3.56
3.81
4.07
4.33
4.59
4.84
5.13
5.37
5.63
5.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
Typ
Max
Units
–
–
1
µs
Precise POR (PPOR)
PRESR
Rising trip voltage
PRESF
Falling trip voltage
Factory trim
Table 11-57. Power-on Reset (POR) with Brown Out AC Specifications
Parameter
Description
Conditions
PRES_TR Response time
VDDD/VDDA droop rate
Sleep mode
11.5.2 Voltage Monitors
Table 11-58. Voltage Monitors DC Specifications
Parameter
Description
LVI
Trip voltage
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
Conditions
Table 11-59. Voltage Monitors AC Specifications
Parameter
Description
Response time
Document Number: 001-56955 Rev. *J
Conditions
Page 100 of 119
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Data Sheet
11.5.3 Interrupt Controller
Table 11-60. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
Min
Typ
Max
Units
–
–
25
Tcy CPU
11.5.4 JTAG Interface
Figure 11-55. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Table 11-61. JTAG Interface AC Specifications[46]
Parameter
f_TCK
Description
TCK frequency
Conditions
3.3 V ≤ VDDD ≤ 5 V
1.71 V ≤ VDDD < 3.3 V
T_TDI_setup
TDI setup before TCK high
T_TMS_setup
TMS setup before TCK high
T_TDI_hold
TDI, TMS hold after TCK high
T = 1/f_TCK max
Min
Typ
Max
Units
–
–
14[47]
MHz
–
–
7[47]
MHz
(T/10) – 5
–
–
ns
T/4
–
–
T/4
–
–
T_TDO_valid
TCK low to TDO valid
T = 1/f_TCK max
–
–
2T/5
T_TDO_hold
TDO hold after TCK high
T = 1/f_TCK max
T/4
–
–
Notes
46. Based on device characterization (Not production tested).
47. f_TCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. *J
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Data Sheet
11.5.5 SWD Interface
Figure 11-56. SWD Interface Timing
(1/f_SWDCK)
SWDCK
T_SWDI_setup T_SWDI_hold
SWDIO
(PSoC 3 reading on SWDIO)
T_SWDO_hold
T_SWDO_valid
SWDIO
(PSoC 3 writing to SWDIO)
Table 11-62. SWD Interface AC Specifications[48]
Parameter
f_SWDCK
Description
SWDCLK frequency
Conditions
3.3 V ≤ VDDD ≤ 5 V
1.71 V ≤ VDDD < 3.3 V
1.71 V ≤ VDDD < 3.3 V,
SWD over USBIO pins
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold SWDIO input hold after SWDCK high
T = 1/f_SWDCK max
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max
Min
–
–
–
Typ
–
–
–
Max
14[49]
7[49]
5.5[49]
Units
MHz
MHz
MHz
T/4
T/4
–
T/4
–
–
–
–
–
–
2T/5
–
Min
Typ
Max
Units
–
–
33
Mbit
11.5.6 SWV Interface
Table 11-63. SWV Interface AC Specifications[22]
Parameter
Description
Conditions
SWV mode SWV bit rate
11.6 Clocking
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.6.1 32 kHz External Crystal
Table 11-64. 32 kHz External Crystal DC Specifications[22]
Parameter
ICC
Description
Operating current
Conditions
Low-power mode
Min
Typ
Max
Units
–
0.25
1.0
µA
CL
External crystal capacitance
–
6
–
pF
DL
Drive level
–
–
1
µW
Min
Typ
Max
Units
–
32.768
–
kHz
–
1
–
s
Table 11-65. 32 kHz External Crystal AC Specifications
Parameter
Description
F
Frequency
TON
Startup time
Conditions
High power mode
Notes
48. Based on device characterization (Not production tested).
49. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. *J
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Data Sheet
11.6.2 Internal Main Oscillator
Table 11-66. IMO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
With oscillator locking to USB bus
–
–
500
µA
24 MHz – non USB mode
–
–
300
µA
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Conditions
Min
Typ
Max
Units
–4
–
4
%
With oscillator locking to USB bus
–0.25
–
0.25
%
12 MHz
–3
–
3
%
6 MHz
–2
–
2
%
–1
–
1
%
–
–
12
µs
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
1.6
–
ns
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
12
–
ns
Supply current
24 MHz – USB mode
Figure 11-57. IMO Current vs. Frequency
Table 11-67. IMO AC Specifications
Parameter
Description
IMO frequency stability (with factory trim)
24 MHz – Non USB mode
FIMO
24 MHz – USB mode
3 MHz
Startup time[50]
From enable (during normal system
operation) or wakeup from
low-power state
Jitter (peak to peak)[50]
Jp-p
Jitter (long term)[50]
Jperiod
Note
50. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *J
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Data Sheet
Figure 11-58. IMO Frequency Variation vs. Temperature
Figure 11-59. IMO Frequency Variation vs. VCC
11.6.3 Internal Low-Speed Oscillator
Table 11-68. ILO DC Specifications
Parameter
Description
Min
Typ
Max
Units
FOUT = 1 kHz
–
0.3
1.7
µA
FOUT = 33 kHz
–
1.0
2.6
µA
FOUT = 100 kHz
–
1.0
2.6
µA
Power down mode
–
2.0
15
nA
Min
Typ
Max
Units
–
–
2
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
100 kHz
30
100
300
kHz
1 kHz
0.3
1
3.5
kHz
Operating current
ICC
Leakage current
Conditions
Table 11-69. ILO AC Specifications
Parameter
Description
Startup time, all frequencies
Conditions
Turbo mode
ILO frequencies (trimmed)
FILO
ILO frequencies (untrimmed)
Figure 11-60. ILO Frequency Variation vs. Temperature
Document Number: 001-56955 Rev. *J
Figure 11-61. ILO Frequency Variation vs. VDD
Page 104 of 119
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Data Sheet
11.6.4 External Crystal Oscillator
Table 11-70. ECO AC Specifications
Parameter
F
Description
Conditions
Crystal frequency range
Min
Typ
Max
Units
4
–
25
MHz
Min
Typ
Max
Units
11.6.5 External Clock Reference
Table 11-71. External Clock Reference AC Specifications[51]
Parameter
Description
Conditions
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.1
–
–
V/ns
Min
Typ
Max
Units
–
200
–
µA
Min
Typ
Max
Units
11.6.6 Phase–Locked Loop
Table 11-72. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Conditions
In = 3 MHz, Out = 24 MHz
Table 11-73. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
1
–
48
MHz
1
–
3
MHz
PLL output frequency[52]
24
–
50
MHz
Lock time at startup
–
–
250
µs
(rms)[51]
–
–
250
ps
PLL intermediate frequency[53]
Fpllout
Conditions
frequency[52]
Jperiod-rms Jitter
Output of prescaler
Notes
51. Based on device characterization (Not production tested).
52. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
53. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
Document Number: 001-56955 Rev. *J
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PSoC® 3: CY8C32 Family
Data Sheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision
oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,
and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you
in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.
All CY8C32 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.
Table 12-1. CY8C32 Family with Single Cycle 8051
I/O[55]
JTAG ID[56]
USBIO
SIO
GPIO
Total I/O
CAN 2.0b
Package
FS USB
16-bit Timer/PWM
UDBs[54]
CapSense
DFB
Opamps
Digital
SC/CT Analog Blocks
Comparator
DAC
ADC
LCD Segment Drive
Analog
EEPROM (KB)
SRAM (KB)
Flash (KB)
Part Number
CPU Speed (MHz)
MCU Core
16 KB Flash
CY8C3244AXI-153
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
70
62
8
0
100-pin TQFP
0×1E099069
CY8C3244LTI-130
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
46
38
8
0
68-pin QFN
0×1E082069
CY8C3244LTI-123
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin QFN
0×1E07B069
CY8C3244PVI-155
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin SSOP
0×1E09B069
CY8C3244AXI-146
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
72
62
8
2
100-pin TQFP
0×1E092069
CY8C3244LTI-168
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
48
38
8
2
68-pin QFN
0×1E0A8069
CY8C3244LTI-152
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
31
25
4
2
48-pin QFN
0×1E098069
CY8C3244PVI-165
50
16
2
0.5
–
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
31
25
4
2
48-pin SSOP
0×1E0A5069
CY8C3244AXI-143
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
70
62
8
0
100-pin TQFP
0×1E08F069
CY8C3244LTI-127
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
46
38
8
0
68-pin QFN
0×1E07F069
0×1E087069
CY8C3244LTI-135
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin QFN
CY8C3244PVI-133
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin SSOP
0×1E085069
CY8C3244AXI-159
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
72
62
8
2
100-pin TQFP
0×1E09F069
CY8C3244LTI-151
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
48
38
8
2
68-pin QFN
0×1E097069
CY8C3244LTI-161
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
31
25
4
2
48-pin QFN
0×1E0A1069
CY8C3244PVI-126
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
✔
–
31
25
4
2
48-pin SSOP
0×1E07E069
32 KB Flash
CY8C3245AXI-158
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
70
62
8
0
100-pin TQFP
0×1E09E069
CY8C3245LTI-163
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
46
38
8
0
68-pin QFN
0×1E0A3069
0×1E08B069
CY8C3245LTI-139
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin QFN
CY8C3245PVI-134
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin SSOP
0×1E086069
CY8C3245AXI-166
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
72
62
8
2
100-pin TQFP
0×1E0A6069
0×1E07C069
CY8C3245LTI-124
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
48
38
8
2
68-pin QFN
CY8C3245LTI-144
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin QFN
0×1E090069
CY8C3245PVI-167
50
32
4
1
–
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin SSOP
0×1E0A7069
CY8C3245AXI-148
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
70
62
8
0
100-pin TQFP
0×1E094069
CY8C3245LTI-142
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
46
38
8
0
68-pin QFN
0×1E08E069
Notes
54. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 41 for more information on how UDBs can be used.
55. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 34 for details on the functionality of each of
these types of I/O.
56. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-56955 Rev. *J
Page 106 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Table 12-1. CY8C32 Family with Single Cycle 8051 (continued)
I/O[58]
JTAG ID[59]
USBIO
SIO
GPIO
Total I/O
CAN 2.0b
Package
FS USB
16-bit Timer/PWM
UDBs[57]
CapSense
DFB
Opamps
Digital
SC/CT Analog Blocks
Comparator
DAC
ADC
LCD Segment Drive
Analog
EEPROM (KB)
SRAM (KB)
Flash (KB)
Part Number
CPU Speed (MHz)
MCU Core
CY8C3245LTI-164
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin QFN
0×1E0A4069
CY8C3245PVI-157
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin SSOP
0×1E09D069
0×1E09A069
CY8C3245AXI-154
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
72
62
8
2
100-pin TQFP
CY8C3245LTI-129
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
48
38
8
2
68-pin QFN
0×1E081069
CY8C3245LTI-160
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin QFN
0×1E0A0069
CY8C3245PVI-150
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin SSOP
0×1E096069
64 KB Flash
CY8C3246AXI-137
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
70
62
8
0
100-pin TQFP
0×1E089069
CY8C3246LTI-149
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
46
38
8
0
68-pin QFN
0×1E095069
CY8C3246LTI-136
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin QFN
0×1E088069
CY8C3246PVI-141
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin SSOP
0×1E08D069
0×1E08C069
CY8C3246AXI-140
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
72
62
8
2
100-pin TQFP
CY8C3246LTI-145
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
48
38
8
2
68-pin QFN
0×1E091069
CY8C3246LTI-121
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin QFN
0×1E079069
CY8C3246PVI-147
50
64
8
2
–
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin SSOP
0×1E093069
CY8C3246AXI-131
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
70
62
8
0
100-pin TQFP
0×1E083069
CY8C3246LTI-156
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
46
38
8
0
68-pin QFN
0×1E09C069
CY8C3246LTI-162
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin QFN
0×1E0A2069
CY8C3246PVI-122
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin SSOP
0×1E07A069
CY8C3246AXI-138
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
72
62
8
2
100-pin TQFP
0×1E08A069
CY8C3246LTI-128
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
48
38
8
2
68-pin QFN
0×1E080069
CY8C3246LTI-125
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin QFN
0×1E07D069
CY8C3246PVI-132
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin SSOP
0×1E084069
Notes
57. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 41 for more information on how UDBs can be used.
58. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 34 for details on the functionality of each
of these types of I/O.
59. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-56955 Rev. *J
Page 107 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
12.1 Part Numbering Conventions
PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
a: Architecture
ef: Package code
3: PSoC 3
5: PSoC 5
Two character alphanumeric
AX: TQFP
LT: QFN
PV: SSOP
b: Family group within architecture
2: CY8C32 family
4: CY8C34 family
6: CY8C36 family
8: CY8C38 family
g: Temperature range
C: commercial
I: industrial
A: automotive
c: Speed grade
xxx: Peripheral set
4: 50 MHz
6: 67 MHz
d: Flash capacity
Three character numeric
No meaning is associated with these three characters.
4: 16 KB
5: 32 KB
6: 64 KB
Example
CY8C
3 2 4 6 P V
I
-
x x x
Cypress Prefix
3: PSoC 3
2: CY8C32 Family
Architecture
Family Group within Architecture
4: 50 MHz
Speed Grade
6: 64 KB
Flash Capacity
PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
Document Number: 001-56955 Rev. *J
Page 108 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25.00
85
°C
TJ
Operating junction temperature
–40
–
100
°C
Tja
Package θJA (48-pin SSOP)
–
45.16
–
°C/Watt
Tja
Package θJA (48-pin QFN)
–
15.94
–
°C/Watt
Tja
Package θJA (68-pin QFN)
–
11.72
–
°C/Watt
Tja
Package θJA (100-pin TQFP)
–
30.52
–
°C/Watt
Tjc
Package θJC (48-pin SSOP)
–
27.84
–
°C/Watt
Tjc
Package θJC (48-pin QFN)
–
7.05
–
°C/Watt
Tjc
Package θJC (68-pin QFN)
–
6.32
–
°C/Watt
Tjc
Package θJC (100-pin TQFP)
–
9.04
–
°C/Watt
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak
Temperature
48-pin SSOP
260 °C
30 seconds
48-pin QFN
260 °C
30 seconds
68-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
48-pin SSOP
MSL 3
48-pin QFN
MSL 3
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
Document Number: 001-56955 Rev. *J
Page 109 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 13-1. 48-pin (300 mil) SSOP Package Outline
.020
24
1
0.395
0.420
0.292
0.299
25
DIMENSIONS IN INCHES MIN.
MAX.
48
0.620
0.630
0.088
0.092
SEATING PLANE
0.095
0.110
0.005
0.010
.010
GAUGE PLANE
0.004
0.025
BSC
0°-8°
0.008
0.016
0.008
0.0135
0.024
0.040
51-85061-*D
Figure 13-2. 48-pin QFN Package Outline
SIDE VIEW
TOP VIEW
BOTTOM VIEW
1.00 MAX.
7.00±0.10
5.6±0.10
0.05 MAX.
48
37
36
1
PIN 1 ID
0.23±0.05
0.20 REF.
37
48
36
1
PIN 1 DOT
LASER MARK
SOLDERABLE
EXPOSED
PAD
7.00±0.10
5.6±0.10
12
25
13
0.40±0.10
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LT48D
LEAD FREE
Document Number: 001-56955 Rev. *J
12
25
24
24
5.55 REF
13
0.50±0.10
0.08
C
5.55 REF
001- 45616 *B
Page 110 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.900±0.100
5.7±0.10
8.000±0.100
0.200 REF
5
1
PIN 1 DOT
8.000±0.100
LASER MARK
1
7
0.20±0.05
3
0.400±0.1005
0.05 MAX
C
0.08
NOTES:
1.
SEATING PLANE
3
4
1
8
1
SOLDERABLE
EXPOSED
PAD
5.7±0.10
3
5
6
8
5
2
6.40 REF
5
1
1
PIN1 ID
R 0.20
0.400 PITCH
5
2
6
8
3
4
1
8
1
7
6.40 REF
HATCH AREA IS SOLDERABLE EXPOSED METAL.
001-09618 *C
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.17g
4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
51-85048 *E
Document Number: 001-56955 Rev. *J
Page 111 of 119
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Data Sheet
14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Table 14-1. Acronyms Used in this Document
Acronym
Description
Acronym
Description
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
IC
integrated circuit
ALU
arithmetic logic unit
IDAC
current DAC, see also DAC, VDAC
AMUXBUS
analog multiplexer bus
IDE
integrated development environment
application programming interface
I2C,
API
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
common-mode rejection ratio
IPOR
initial power-on reset
CPU
central processing unit
IPSR
interrupt program status register
CRC
cyclic redundancy check, an error-checking
protocol
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
Document Number: 001-56955 Rev. *J
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
Page 112 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PHUB
peripheral hub
SOF
start of frame
PHY
physical layer
SPI
PICU
port interrupt control unit
Serial Peripheral Interface, a communications
protocol
PLA
programmable logic array
SR
slew rate
PLD
programmable logic device, see also PAL
SRAM
static random access memory
PLL
phase-locked loop
SRES
software reset
PMDD
package material declaration datasheet
SWD
serial wire debug, a test protocol
POR
power-on reset
SWV
single-wire viewer
PRES
precise power-on reset
TD
transaction descriptor, see also DMA
PRS
pseudo random sequence
THD
total harmonic distortion
PS
port read data register
TIA
transimpedance amplifier
PSoC®
Programmable System-on-Chip™
TRM
technical reference manual
PSRR
power supply rejection ratio
TTL
transistor-transistor logic
PWM
pulse-width modulator
TX
transmit
RAM
random-access memory
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
RX
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
remote transmission request
VDAC
voltage DAC, see also DAC, IDAC
receive
WDT
watchdog timer
SAR
successive approximation register
WOL
write once latch, see also NVL
SC/CT
switched capacitor/continuous time
WRES
watchdog timer reset
2C
serial clock
SCL
I
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
Document Number: 001-56955 Rev. *J
XRES
external reset I/O pin
XTAL
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
Page 113 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
16. Document Conventions
Table 16-1. Units of Measure (continued)
Symbol
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
kΩ
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
megaohms
Msps
megasamples per second
µA
microamperes
Document Number: 001-56955 Rev. *J
Unit of Measure
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
Ω
ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Page 114 of 119
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Data Sheet
17. Revision History
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
Orig. of
Rev.
ECN No. Submission
Description of Change
Date
Change
**
2796903
11/04/09
MKEA
New datasheet
*A
2824546
12/09/09
MKEA
Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC
and DC specs); also added Shottky Diode specs. Changed current for
sleep/hibernate mode to include SIO; Added footnote to analog global specs.
Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3
(Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO
AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated
description of VDDA spec in Table 11-1 and removed GPIO Clamp Current
parameter. Updated number of UDBs on page 1.
Moved FILO from ILO DC to AC table.
Added PCB Layout and PCB Schematic diagrams.
Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec
table. Added note for Sleep and Hibernate modes and Active Mode specs in Table
11-2. Linked URL in Section 10.3 to PSoC Creator site.
Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast
FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table.
Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC
ADC. Updated Boost Converter section.
Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode)
in Table 11-10.
Updated VBAT condition and deleted Vstart parameter in Table 11-6.
Added 'Bytes' column for Tables 4-1 to 4-5.
*B
2873322
02/04/10
MKEA
Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification.
Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt
Vector table, Updated Sales links. Updated JTAG and SWD specifications.
Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer
in Table 11-2. Updated ILO AC and DC specifications. Added Resolution
parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values.
Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup
specification from Table 11-1. Updated DAC details
Document Number: 001-56955 Rev. *J
Page 115 of 119
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Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
*C
2903576
04/01/10
MKEA
Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table.
Updated ICC parameter in LCD Direct Drive DC Specs table.
In page 1, updated internal oscillator range under Prescision programmable
clocking to start from 3 MHz.
Updated IOUT parameter in LCD Direct Drive DC Specs table.
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section 12
Rem
oved some references to footnote [1].
Changed INC_Rn cycles from 3 to 2 (Table 4-1).
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout).
Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for VDDA
and VDDD pins.
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level
Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.
Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64.
Updated VREF specs in Table 11-19.
Updated IDAC uncompensated gain error in Table 11-23.
Updated Delay from Interrupt signal input to ISR code execution from ISR code
in Table-71. Removed other line in table.
Added sentence to last paragraph of section 6.1.1.3.
Updated Tresp, high and low-power modes, in Table 11-22.
Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59.
Updated SNR condition in Table 11-18.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= VDDD < 3.3 V, SWD over USBIO pins value to Table 11-59.
Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3,
Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs
in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed
PPOR to PRES), Table 11-53 (changed title, values TBD), and Table 11-54
(changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1.
Changed IDD values on page 1, page 5, and Table 11-2.
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Changed sample rate row in Table 11-18.
Removed VDDA = 1.65 V rows and changed BWag value in Table 11-20.
Changed Vioff values and changed CMRR value in Table 11-21.
Changed INL max value in Table 11-25.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-41.
Changed max response time value in Tables 11-54 and 11-56.
Change the Startup time in Table 11-64.
Added condition to intermediate frequency row in Table 11-70.
Added row to Table 11-54.
Added brown out note to Section 11.8.1.
Document Number: 001-56955 Rev. *J
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Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
*D
2938381
05/27/10
MKEA
Replaced VDDIO with VDDD in USBIO diagram and specification tables, added text
in USBIO section of Electrical Specifications.
Added Table 13-2 (Package MSL)
Modified Tstorag condition and changed max spec to 100
Added bullet (Pass) under ALU (section 7.2.2.2)
Added figures for kHzECO and MHzECO in the External Oscillator section
Updated Figure 6-1(Clocking Subsystem diagram)
Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection
Updated PSoC Creator Framework image
Updated SIO DC Specifications (VIH and VIL parameters)
Updated bullets in Clocking System and Clocking Distribution sections
Updated Figure 8-2
Updated Table 11-10
Updated PCB Layout and Schematic, updated as per MTRB review comments
Updated Table 6-3 (power changed to current)
In 32kHZ EC DC Specifications table, changed ICC Max to 0.25
In IMO DC Specifications table, updated Supply Current values
Updated GPIO DC Specs table
Modified to support a maximum 50MHz CPU speed
*E
2958674
06/22/10
SHEA
Minor ECN to post datasheet to external website
*F
2989685
08/04/10
MKEA
Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram
Added to Table 6-6 a footnote and references to same.
Added sentences to the resistive pull-up and pull-down description bullets.
Added sentence to Section 6.4.11, Adjustable Output Level.
Updated section 5.5 External Memory Interface
Updated Table 11-73 JTAG Interface AC Specifications
Updated Table 11-74 SWD Interface AC Specifications
*G
3078568
11/04/10
MKEA
Updated “Current Digital-to-analog Converter (IDAC)” on page 82
Updated “Voltage Digital to Analog Converter (VDAC)” on page 87
Updated Table 11-2, “DC Specifications,” on page 63
*H
3107314 12/10/2010
MKEA
Updated delta-sigma tables and graphs.
Updated Flash AC specs
Formatted table 11.2.
Updated interrupt controller table
Updated transimpedance amplifier section
Updated SIO DC specs table
Updated Voltage Monitors DC Specifications table
Updated LCD Direct Drive DC specs table
Updated ESDHBM value.
Updated IDAC and VDAC sections
Removed ESO parts from ordering information
Changed USBIO pins from NC to DNU and removed redundant USBIO pin
description notes
Updated POR with brown out DC and AC specs
Updated 32 kHz External Crystal DC Specifications
Updated XRES IO specs
Updated Inductive boost regulator section
Delta sigma ADC spec updates
Updated comparator section
Removed buzz mode from Power Mode Transition diagram
*I
3179219
02/22/2011
MKEA
Updated conditions for flash data retention time.
Updated 100-pin TQFP package spec.
Updated EEPROM AC specifications.
Document Number: 001-56955 Rev. *J
Page 117 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
*J
3200146
03/28/2011
MKEA
Removed Preliminary status from the data sheet.
Updated JTAG ID
Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table
Updated JTAG Interface AC Specifications and SWD Interface Specifications
tables
Updated USBIO DC specs
Added 0.01 to max speed
Updated Features on page 1
Added Section 5.5, Nonvolatile Latches
Updated Flash AC specs
Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables
Add reference to application note AN58304 in section 8.1
Updated 100-pin TQFP package spec
Added oscillator, I/O, VDAC, regulator graphs
Updated JTAG/SWD timing diagrams
Updated GPIO and SIO AC specs
Updated POR with Brown Out AC spec table
UpdatedIDAC graphs
Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing
diagrams
Added full chip performance graphs
Changed MHzECO range.
Added “Solder Reflow Peak Temperature” table.
Document Number: 001-56955 Rev. *J
Page 118 of 119
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PSoC® 3: CY8C32 Family
Data Sheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56955 Rev. *J
®
®
®
®
Revised March 30, 2011
Page 119 of 119
®
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
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