AD AD7938BCP 8-channel, 1.5 msps, 12-bit and 10-bit parallel adcs with a sequencer Datasheet

FEATURES
Fast throughput rate: 1.5 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
8 mW max at 1.5 MSPS with 3 V supplies
16 mW max at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo-differential inputs
7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
Wide input bandwidth
70 dB SNR at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 1 µA max
32-lead LFCSP and TQFP package
GENERAL DESCRIPTION
The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) ADCs. The parts
operate from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.5 MSPS. The parts contain a low noise,
wide bandwidth, differential track-and-hold amplifier that can
handle input frequencies up to 20 MHz.
The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allow a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudodifferential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is also initiated at
this point.
The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
AD7938/AD7939
VREFIN/
VREFOUT
2.5V
VREF
VIN0
I/P
MUX
CLKIN
12-/10-BIT
SAR ADC
AND
CONTROL
T/H
CONVST
BUSY
VIN7
SEQUENCER
VDRIVE
PARALLEL INTERFACE/CONTROL REGISTER
DB0 DB11
CS RD WR W/B
DGND
03715-0-001
Preliminary Technical Data
8-Channel, 1.5 MSPS, 12-Bit and 10-Bit
Parallel ADCs with a Sequencer
AD7938/AD7939
Figure 1.
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control register
allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
High throughput with low power consumption.
Eight analog inputs with a channel sequencer.
Accurate on-chip 2.5 V reference.
Software configurable analog inputs. Single-ended, pseudodifferential, or fully differential analog inputs that are
software selectable.
Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of VDD.
No pipeline delay.
Accurate control of the sampling instant via a CONVST
input and once off conversion control.
Rev. PrN
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7938/AD7939
Preliminary Technical Data
TABLE OF CONTENTS
AD7938—Specifications.................................................................. 3
Analog Inputs.............................................................................. 20
AD7939—Specifications.................................................................. 5
Analog Input Selection .............................................................. 22
Timing Specifications....................................................................... 7
Reference Section ....................................................................... 23
Absolute Maximum Ratings............................................................ 8
Parallel Interface......................................................................... 25
ESD Caution.................................................................................. 8
Power Modes of Operation....................................................... 28
Pin Function Description ................................................................ 9
Power vs. Throughput Rate....................................................... 29
Terminology .................................................................................... 11
Microprocessor Interfacing....................................................... 29
Typical Performance Characteristics ........................................... 13
Application Hints ........................................................................... 31
On-Chip Registers .......................................................................... 16
Grounding and Layout .............................................................. 31
Circuit Information ........................................................................ 18
PCB Design Guidelines for Chip Scale Package .................... 31
Converter Operation.................................................................. 18
Evaluating the AD7938/AD7939 Performance ...................... 31
ADC Transfer Function............................................................. 18
Outline Dimensions ....................................................................... 32
Typical Connection Diagram ................................................... 19
Ordering Guide .......................................................................... 32
Analog Input Structure.............................................................. 19
REVISION HISTORY
8/04—Revision PrN: Preliminary Version
Rev. PrN | Page 2 of 32
Preliminary Technical Data
AD7938/AD7939
AD7938—SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel to Channel Isolation
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2, 3
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Total Unadjusted Error
Single-Ended and Pseudo-Differential Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Single-Ended Input Range
Pseudo-Differential Input Range: VIN+
VIN−
Fully Differential Input Range: VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current5
Input Capacitance
REFERENCE INPUT/OUTPUT
VREF Input Voltage6
DC Leakage Current
VREF Input Impedance
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
VREF Noise
B Version1
Unit
70
70
−75
−75
dB min
dB min
dB max
dB max
−85
−85
−85
5
50
20
2.5
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
12
±1
±0.95
TBD
Bits
LSB max
LSB max
LSB max
±4.5
±0.5
±2
±0.6
LSB max
LSB max
LSB max
LSB max
±2
±0.6
±3
±1
±2
±0.6
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to VREF or 0 to 2 × VREF
0 to VREF or 2 × VREF
−0.1 to +0.4
VCM ± VREF/2
VCM ± VREF
±1
45
10
V
V
V
V
V
µA max
pF typ
pF typ
2.5
±1
10
2.5
15
10
130
V
µA max
kΩ typ
V
ppm/°C typ
µV typ
µV typ
Test Conditions/Comments
FIN = 50 kHz sine wave
−80 dB typ
−82 dB typ
fa = 40.1 kHz, fb = 51.5 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Twos complement output coding
Rev. PrN | Page 3 of 32
Depending on RANGE bit setting
Depending on RANGE bit setting
VCM = common-mode voltage4 = VREF/2
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
When in track
When in hold
±1% for specified performance
±0.1% @ 25°C
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
AD7938/AD7939
Parameter
VREF Output Impedance
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD7
Normal Mode(Static)
Normal Mode (Operational)
Auto-Standby Mode
Auto-Shutdown Mode
Full Shutdown Mode
Power Dissipation
Normal Mode (Operational)
Auto-Standby Mode (Static)
Auto-Shutdown Mode (Static)
Full Shutdown Mode
Preliminary Technical Data
B Version1
10
15
25
Unit
Ω typ
pF typ
pF typ
2.4
0.8
±1
10
V min
V max
µA max
pF max
2.4
0.4
±10
10
Straight (Natural) Binary
Twos Complement
V min
V max
µA max
pF max
t2 + 13 tclk + t20
135
1.5
ns
ns max
MSPS max
2.7/5.25
2.7/5.25
V min/max
V min/max
0.5
3.2
2.6
1.55
90
1
1
1
mA typ
mA max
mA max
mA typ
µA max
mA typ
µA max
µA max
Digital I/Ps = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 250 kSPS
(Static)
FSAMPLE = 250 kSPS
(Static)
SCLK on or off
16
8
450
270
5
3
5/3
mW max
mW max
µW max
µW max
µW max
µW max
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V/3 V
Test Conditions/Comments
When in track
When in hold
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA
ISINK = 200 µA
CODING bit = 0
CODING bit = 1
1
Full-scale step input
Temperature ranges as follows: B Versions: −40°C to +85°C.
See the Terminology section.
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4
For full common-mode range see Figure 28 and Figure 29.
5
Sample tested during initial release to ensure compliance.
6
This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.
See the Reference Section for more information.
7
Measured with a midscale dc input.
2
3
Rev. PrN | Page 4 of 32
Preliminary Technical Data
AD7938/AD7939
AD7939—SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, Internal/External VREF = 2.5V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel to Channel Isolation
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2, 3
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Total Unadjusted Error
Single-Ended and Pseudo-Differential Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Single-Ended Input Range
Pseudo-Differential Input Range: VIN+
VIN−
Fully Differential Input Range: VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current5
Input Capacitance
REFERENCE INPUT/OUTPUT
VREF Input Voltage6
DC Leakage Current5
VREF Input Impedance
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
VREF Noise
B Version1
Unit
60
60
−73
−73
dB min
dB min
dB max
dB max
−75
−75
−75
5
50
20
2.5
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
10
±0.5
±0.5
TBD
Bits
LSB max
LSB max
LSB max
±4.5
±0.5
±2
±0.6
LSB max
LSB max
LSB max
LSB max
±2
±0.6
±3
±1
±2
±0.6
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0 to VREF or 0 to 2 × VREF
0 to VREF or 2 × VREF
−0.1 to +0.4
VCM ± VREF/2
VCM ± VREF
±1
45
10
V
V
V
V
V
µA max
pF typ
pF typ
2.5
±1
10
2.5
15
10
130
V
µA max
kΩ
V
ppm/°C typ
µV typ
µV typ
Test Conditions/Comments
FIN = 50 kHz sine wave
fa = 40.1 kHz, fb = 51.5 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 10 bits
Straight binary output coding
Twos complement output coding
Rev. PrN | Page 5 of 32
Depending on RANGE bit setting
Depending on RANGE bit setting
VCM = common-mode voltage4 = VREF/2
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
When in track
When in hold
±1% for specified performance
±0.1% @ 25°C
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
AD7938/AD7939
Parameter
VREF Output Impedance
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD7
Normal Mode(Static)
Normal Mode (Operational)
Auto-Standby Mode
Auto-Shutdown Mode
Full Shutdown Mode
Power Dissipation
Normal Mode (Operational)
Auto-Standby Mode (Static)
Auto-Shutdown Mode (Static)
Full Shutdown Mode
Preliminary Technical Data
B Version1
10
15
25
Unit
Ω typ
pF typ
pF typ
2.4
0.8
±1
10
V min
V max
µA max
pF max
2.4
0.4
±10
10
Straight (Natural) Binary
Twos Complement
V min
V max
µA max
pF max
t2 + 13 tclk + t20
135
1.5
ns
ns max
MSPS max
2.7/5.25
2.7/5.25
V min/max
V min/max
0.5
3.2
2.6
1.55
90
1
1
1
mA typ
mA max
mA max
mA typ
µA max
mA typ
µA max
µA max
Digital I/Ps = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 250 kSPS
(Static)
FSAMPLE = 250 kSPS
(Static)
SCLK on or off
16
8
450
270
5
3
5
3
mW max
mW max
µW max
µW max
µW max
µW max
µW max
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Test Conditions/Comments
When in track
When in hold
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA;
ISINK = 200 µA
CODING bit = 0
CODING bit =1
1
Full-scale step input
Temperature ranges as follows: B Versions: −40°C to +85°C.
See the Terminology section.
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave >3.5 MHz) within the acquisition time may cause an incorrect conversion result to be
returned by the converter.
4
For full common-mode range see Figure 28 and Figure 29.
5
Sample tested during initial release to ensure compliance.
6
This device is operational with an external reference in the range 0.1 V to 3.5 V in differential mode and 0.1 V to VDD in pseudo-differential and single-ended modes.
See the Reference Section for more details.
7
Measured with a midscale dc input.
2
3
Rev. PrN | Page 6 of 32
Preliminary Technical Data
AD7938/AD7939
TIMING SPECIFICATIONS1
VDD = VDRIVE =2.7 V to 5.25V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 3.
Parameter
fCLKIN2
Limit at TMIN, TMAX
AD7938 AD7939
10
10
24
24
tQUIET
10
10
Unit
kHz
min
MHz
max
ns min
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t133
t144
10
20
TBD
0
0
25
10
5
0.5 tCLKIN
0
0
55
50
5
40
15
5
10
0
5
TBD
10
20
TBD
0
0
25
10
5
0.5 tCLKIN
0
0
55
50
5
40
15
5
10
0
5
TBD
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
t15
t16
t17
t18
t19
t20
Description
Minimum time between end of Read and start of next conversion (i.e., time from when the
data bus goes into three-state until the next falling edge of CONVST)
CONVST Pulse Width.
CONVST Falling Edge to CLKIN Falling Edge Setup Time.
CLKIN Falling Edge to BUSY Rising Edge.
CS to WR Setup Time.
CS to WR Hold Time.
WR Pulse Width.
Data Setup Time before WR.
Data Hold after WR.
New Data Valid before Falling Edge of BUSY.
CS to RD Setup Time.
CS to RD Hold Time.
RD Pulse Width.
Data Access Time after RD.
Bus Relinquish Time after RD.
Bus Relinquish Time after RD.
HBEN to RD Setup Time.
HBEN to RD Hold Time.
Minimum Time between Reads/Writes.
HBEN to WR Setup Time.
HBEN to WR Hold Time.
CLKIN Falling Edge to BUSY Falling Edge.
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance (see Figure 38, Figure 39, Figure 40and Figure 41.
Mark/space ratio for CLKIN is 40/60 to 60/40.
3
The time required for the output to cross TBD.
4
t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
2
Rev. PrN | Page 7 of 32
AD7938/AD7939
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to AGND/DGND
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to DGND
VREFIN to AGND
AGND to DGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec)
ESD
1
Rating
−0.3 V to +7 V
−0.3 V to VDD +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to 7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−65°C to +150°C
150°C
108.2°C/W (LFCSP)
121°C/W (TQFP)
32.71°C/W (LFCSP)
45°C/W (TQFP)
255°C
2 kV
Transient currents of up to 100 mA will not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrN | Page 8 of 32
Preliminary Technical Data
AD7938/AD7939
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
32
VDD
W/B
PIN FUNCTION DESCRIPTION
31
30
29
28
27
26
25
PIN 1
IDENTIFIER
24
VIN1
D1 2
23
VIN0
D2 3
22
VREFIN/VREFOUT
21
AGND
20
CS
D5 6
19
RD
D6 7
18
WR
D7 8
17
CONVST
AD7938/AD7939
D3 4
13
14
15
16
BUSY
CLKIN
DGND
12
D11
VDRIVE
11
D10
10
D9
9
D8/HBEN
TOP VIEW
(Not to Scale)
D4 5
03715-0-006
D0 1
Figure 2. Pin Configuration
Table 5. Pin Function Description
Pin
No
1 to
8
Mnemonic
DB0 to DB7
9
VDRIVE
10
DGND
11
DB8/HBEN
12
to
14
15
DB9 to
DB11
BUSY
16
CLKIN
17
CONVST
18
19
WR
RD
20
CS
Function
Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and
shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels
for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and DB1) are
always 0 and the LSB of the conversion result is available on DB2.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at
VDD but should never exceed VDD by more than 0.3 V.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and
must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS
, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data
being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of
the high byte will contain the ID of the channel for which the conversion result corresponds (see the channel address
bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from
the AD7939, the two LSBs of the low byte are 0s, and the remaining 6 bits, conversion data.
Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control and
shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the VDRIVE input.
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling
edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is
available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the
falling edge of BUSY on the 13th rising edge of SCLK, see Figure 38.
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13.5 clock cycles. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track to
hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down,
when operating in auto-shutdown or auto-standby modes, a rising edge on CONVST is used to power-up the device.
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result
is placed on the data bus following the falling edge of RD read while CS is low.
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
Rev. PrN | Page 9 of 32
AD7938/AD7939
Pin
No
Mnemonic
21
AGND
22
VREFIN/VREFOUT
23
to
30
VIN0 to VIN7
31
VDD
32
W/B
Preliminary Technical Data
Function
the internal registers.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The
nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an external
reference. The input voltage range for the external reference is 0.1 V to 3.5 V for the differential mode and is 0.1 V to
VDD for the single-ended and pseudo-differential modes, depending on VDD.
Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and-hold.
The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four pseudodifferential pairs, or seven pseudo-differential inputs by setting the MODE bits in the control register appropriately
(see Table 9). The analog input channel to be converted can either be selected by writing to the address bits (ADD2
to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used. The SEQ and SHDW
bits in conjunction with the address bits in the control register allow the shadow register to be programmed. The
input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can be binary or twos
complement, depending on the states of the RANGE and CODING bits in the control register. Any unused input
channels should be connected to AGND to avoid noise pickup.
Power Supply Input. The VDD range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to
AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit
words on Pins DB0/DB2 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID
are transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality.
Rev. PrN | Page 10 of 32
AD7938/AD7939
Preliminary Technical Data
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
mid scale transition (all 0s to all 1s) from the ideal VIN voltage,
i.e., VREF.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,
+VREF − 1 LSB) after the zero-code error has been adjusted out.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal that appears in the FFT of this channel.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the input varies from 1 kHz to 1 MHz.
PSRR (dB) = 10log(Pf/PfS)
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the end of
conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit
converter, this is 62 dB.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e.,
−VREFIN + 1 LSB) after the zero-code error has been adjusted
out.
Rev. PrN | Page 11 of 32
AD7938/AD7939
Preliminary Technical Data
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938/ AD7939, it is defined as
THD (dB ) = −20log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa
− 2fb).
The AD7938/AD7939 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Rev. PrN | Page 12 of 32
AD7938/AD7939
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Figure 3. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Figure 6. AD7938 FFT @ VDD = 5 V
Figure 4. AD7938 Channel-to-Channel Isolation
Figure 7. AD7938 Typical DNL @ VDD = 5 V
Figure 5. AD7938 SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 8. AD7938 Typical INL @ VDD = 5 V
Rev. PrN | Page 13 of 32
AD7938/AD7939
Preliminary Technical Data
Figure 9. AD7938 Change in INL vs. VREF for VDD = 5 V
Figure 12. AD7938 Offset vs. VREF
Figure 10.AD7938 Change in DNL vs. VREF for VDD = 5 V
Figure 13. AD7938 Histogram of Codes @ VDD = 5 V with the Internal Reference
Figure 11. AD7938 Change in ENOB vs. VREF for VDD = 5 V
Figure 14. AD7938 Histogram of Codes @ VDD = 5 V with an External Reference
Rev. PrN | Page 14 of 32
Preliminary Technical Data
AD7938/AD7939
Figure 15. AD7939 FFT @ VDD = 5 V
Figure 17. AD7939 Typical INL @ VDD = 5 V
Figure 16. AD7939 Typical DNL @ VDD = 5 V
Rev. PrN | Page 15 of 32
AD7938/AD7939
Preliminary Technical Data
ON-CHIP REGISTERS
The AD7938/AD7939 have two on-chip registers that are necessary for the operation of the device. These are the control register, which is
used to set up different operating conditions, and the shadow register, which is used to program the analog input channels to be
converted.
CONTROL REGISTER
The control register on the AD7938/AD7939 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The
control register is shown below and the functions of the bits are described in Table 7. At power up, the default bit settings in the control
register are all 0s.
Table 6. Control Register Bits
MSB
D11
PM1
D10
PM0
D9
CODING
D8
REF
D7
ADD2
D6
ADD1
D5
ADD0
D4
MODE1
D3
MODE0
D2
SHDW
D1
SEQ
LSB
D0
RANGE
Table 7. Control Register Bit Function Description
Bit No.
Mnemonic
11, 10
PM1, PM0
9
CODING
8
REF
7 to 5
ADD2 to
ADD0
4, 3
MODE1,
MODE0
2
SHDW
1
SEQ
0
RANGE
Description
Power Management Bits. These two bits are used to select the power mode of operation. The user can choose
between either normal mode or various power-down modes of operation as shown in Table 8.
This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight
(natural) binary. If this bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an
external reference should be applied to the VREF pin, and if this bit is Logic 1, the internal reference is selected (see
the Reference Section).
These three address bits are used to either select which analog input channel is converted in the next conversion
if the sequencer is not used or to select the final channel in a consecutive sequence when the sequencer is used as
described in Table 10. The selected input channel is decoded as shown in Table 9.
The two mode pins select the type of analog input on the eight VIN pins. The AD7938/AD7939 can have either
eight single-ended inputs, four fully differential inputs, four pseudo-differential inputs, or seven pseudodifferential inputs (see Table 9).
The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and
access the SHDW register (see Table 10).
The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and
access the SHDW register (see Table 10).
This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, then the analog input range extends
from 0 V to VREF. If it is set to 1, then the analog input range extends from 0 V to 2 × VREF. When this range is
selected, AVDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that
the analog input remains within the supply rails. See Analog Inputs section for more information.
Table 8. Power Mode Selection using the Power Management Bits in the Control Register
PM1
0
PM0
0
0
1
1
0
1
1
Mode
Normal
Mode
Auto
Shutdown
Auto
Standby
Full
Shutdown
Description
When operating in normal mode, all circuitry is fully powered up at all times.
When operating in auto-shutdown mode, the AD7938/AD7939 will enter full shutdown mode at the end of
each conversion. In this mode, all circuitry is powered down.
When the AD7938/AD7939 enter this mode, all circuitry is partially powered down. This mode is similar to
auto-shutdown mode, but it allows the part to power-up in 1 µsec.
When the AD7938/AD7939 enter this mode, all circuitry is powered down. The information in the control
register is retained.
Rev. PrN | Page 16 of 32
Preliminary Technical Data
AD7938/AD7939
Table 9. Analog Input Type Selection
Channel Address
ADD2
0
0
0
0
1
1
1
1
ADD1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
MODE0 = 0, MODE1 = 0
Eight Single-Ended
I/P Channels
VIN+
VINVIN0
AGND
VIN1
AGND
VIN2
AGND
VIN3
AGND
VIN4
AGND
VIN5
AGND
VIN6
AGND
VIN7
AGND
MODE0 = 0, MODE1 = 1
Four Fully Differential
I/P Channels
VIN+
VINVIN0
VIN1
VIN1
VIN0
VIN2
VIN3
VIN3
VIN2
VIN4
VIN5
VIN5
VIN4
VIN6
VIN7
VIN7
VIN6
MODE0 = 1, MODE1 = 0
Four Pseudo-Differential I/P
Channels (Pseudo Mode 1)
VIN+
VINVIN0
VIN1
VIN1
VIN0
VIN2
VIN3
VIN3
VIN2
VIN4
VIN5
VIN5
VIN4
VIN6
VIN7
VIN7
VIN6
MODE0 = 1, MODE1 = 1
Seven Pseudo-Differential I/P
Channels (Pseudo Mode 2)
VIN+
VINVIN0
VIN7
VIN1
VIN7
VIN2
VIN7
VIN3
VIN7
VIN4
VIN7
VIN5
VIN7
VIN6
VIN7
Not Allowed
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 10 outlines the four modes of operation of the sequencer.
Table 10. Sequence Selection
SEQ
SHDW
0
0
0
1
1
0
1
1
Sequence Type
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer
function being used, where each write to the AD7938/AD7939 selects the next channel for conversion.
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This will program the sequence of channels to be converted continuously after each CONVST
falling edge (see the shadow register description and Table 11).
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the WRITE
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
SHADOW REGISTER
The shadow register on the AD7938/AD7939 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of WR.
The eight LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits
in the control register were set to 0 and 1, respectively in the previous write to the control register. Each bit represents an analog input
from Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938/AD7939 cycles with each
consecutive conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in singleended mode or Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When
operating in differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required
in the sequence. With each consecutive CONVST pulse after the sequencer has been set up, the AD7938/AD7939 progress through the
selected channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and
SHDW bits configured in any way except 1, 0 (see Table 10). When a sequence is set up in differential or Pseudo Mode 1, the ADC does
not convert on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in Table 11. See the Analog Input
Selection section for further information on using the sequencer.
Table 11. Shadow Register Bit Functions
VIN0
VIN1
VIN2
VIN3
VIN4
Rev. PrN | Page 17 of 32
VIN5
VIN6
VIN7
AD7938/AD7939
Preliminary Technical Data
CIRCUIT INFORMATION
The AD7938/AD7939 provide the user with an on-chip trackand-hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP or
TQFP package.
The AD7938/AD7939 have eight analog input channels that can
be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo-differential pairs, or seven
pseudo-differential inputs with respect to one common input.
There is an on-chip user-programmable channel sequencer that
allows the user to select a sequence of channels through which
the ADC can progress and cycle with each consecutive falling
edge of CONVST.
When the ADC starts a conversion (Figure 19), SW3 opens and
SW1 and SW2 moves to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and the VIN− pins
must be matched; otherwise, the two inputs will have different
settling times, which results in errors.
CAPACITIVE
DAC
VIN+
CONVERTER OPERATION
The AD7938/AD7939 is a successive approximation ADC based
around two capacitive DACs. Figure 18 and Figure 19 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises of control logic, a SAR,
and two capacitive DACs. Both figures show the operation of
the ADC in differential/pseudo-differential mode. Single-ended
mode operation is similar but VIN− is internally tied to AGND.
In acquisition phase, SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
A
B
SW2
VREF
COMPARATOR
The output coding for the AD7938/AD7939 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code
transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs,
and so on) and the LSB size is VREF/4096 for the AD7938 and
VREF/1024 for the AD7939. The ideal transfer characteristics of
the AD7938/AD7939 for both straight binary and twos
complement output coding are shown in Figure 20 and Figure
21, respectively.
111...111
111...110
111...000
011...111
1 LSB = VREF/4096 (AD7938)
1 LSB = VREF/1024 (AD7939)
000...010
000...001
000...000
0V
1 LSB
+VREF–1 LSB
ANALOG INPUT
CONTROL
LOGIC
SW3
VIN–
CS
NOTE: VREF IS EITHER VREF OR 2 × VREF
CS
COMPARATOR
CAPACITIVE
DAC
Figure 18. ADC Acquisition Phase
Rev. PrN | Page 18 of 32
Figure 20. AD7938/AD7939 Ideal Transfer Characteristic
with Straight Binary Output Coding
03715-0-025
SW1
CONTROL
LOGIC
ADC TRANSFER FUNCTION
CS
A
SW2
Figure 19. ADC Conversion Phase
03715-0-023
VIN+
A
B
CAPACITIVE
DAC
CAPACITIVE
DAC
B
SW1
VREF
ADC CODE
The AD7938/AD7939 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0, in
the control register.
A
SW3
VIN–
The analog input range for the AD7938/AD7939 is 0 to VREF or
0 to 2 × VREF depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
CS
B
03715-0-024
The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit,
single-supply, successive approximation analog-to-digital
converters. The parts can operate from a 2.7 V to 5.25 V power
supply and feature throughput rates up to 1.5 MSPS.
Preliminary Technical Data
AD7938/AD7939
ANALOG INPUT STRUCTURE
1 LSB = 2 × VREF/4096 (AD7938)
1 LSB = 2 × VREF/1024 (AD7939)
Figure 23 shows the equivalent circuit of the analog input
structure of the AD7938/AD7939 in differential/pseudo
differential mode. In single-ended mode, VIN− is internally tied
to AGND. The four diodes provide ESD protection for the
analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than
300 mV. This causes these diodes to become forward-biased and
starts conducting into the substrate. These diodes can conduct
up to 10 mA without causing irreversible damage to the part.
ADC CODE
011...110
000...001
000...000
111...111
1 LSB = VREF/4096 (AD7938)
1 LSB = VREF/1024 (AD7939)
100...010
100...000
–VREF + 1 LSB
VREF
+VREF – 1 LSB
03715-0-026
100...001
Figure 21. AD7938/AD7939 Ideal Transfer Characteristic
with Twos Complement Output Coding
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the
AD7938/AD7939. The AGND and DGND pins are connected
together at the device for good noise suppression. The
VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 µF
capacitor to avoid noise pickup if the internal reference is used.
Alternatively, VREFIN/VREFOUT can be connected to an external
reference source, and in this case, the reference pin should be
decoupled with a 0.1 µF capacitor. In both cases, the analog
input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to
2 × VREF (RANGE bit = 1). The analog input configuration can
be either eight single-ended inputs, four differential pairs, four
pseudo-differential pairs, or seven pseudo-differential inputs
(see Table 9). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface and here, it is connected to the
same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section).
0.1µF
10µF
The C1 capacitors, in Figure 23, are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors and have a
capacitance of 16 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp will be a function of the
particular application.
VDD
D
VIN+
C1
D
C1
W/B
CLKIN
RD
µC/µP
WR
DB0
AGND
DGND
DB11/DB9
2.5V
VREF
VDRIVE
0.1µF
10µF
3V
SUPPLY
0.1µF EXTERNAL VREF
0.47µF INTERNAL VREF
03715-0-027
VREFIN/VREFOUT
D
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of THD that can
be tolerated. The THD increases as the source impedance
increases and performance degrades. Figure 24 shows a graph of
the THD versus the analog input signal frequency for different
source impedances for both VDD = 5 V and 3 V.
BUSY
CONVST
VIN7
C2
Figure 23. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
CS
0 TO VREF/
0 TO 2 × VREF
R1
VDD
3V/5V
SUPPLY
AD7938/AD7939
VIN0
C2
D
VIN–
VDD
R1
03715-0-028
011...111
Figure 22. Typical Connection Diagram
Rev. PrN | Page 19 of 32
AD7938/AD7939
Preliminary Technical Data
R
+1.25V
0V
–1.25V
0V
R
VIN
+2.5V
3R
VIN0
AD7938/
AD7939*
VIN7
VREFOUT
03715-0-031
0.47µF
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. Single-Ended Mode Connection Diagram
Figure 24. THD vs. Analog Input Frequency for Various Source Impedances
Figure 25 shows a graph of the THD versus the analog input
frequency for various supplies while sampling at 1.5 MHz with
an SCLK of 20 MHz. In this case, the source impedance is 10 Ω.
Differential Mode
The AD7938/AD7939 can have four differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 27 defines the fully differential analog
input of the AD7938/AD7939.
VIN+
VREF
p-p
VIN–
AD7938/
AD7939*
*ADDITIONAL PINS OMITTED FOR CLARITY
03715-0-032
COMMON-MODE
VOLTAGE
VREF
p-p
Figure 25. THD vs. Analog Input Frequency for Various Supply Voltages
Figure 27. Differential Input Definition
ANALOG INPUTS
The AD7938/AD7939 have software selectable analog input
configurations. The user can choose either eight single-ended
inputs, four fully differential pairs, four pseudo-differential
pairs, or seven pseudo-differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 9).
Single-Ended Mode
The AD7938/AD7939 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be
programmed to be either 0 to VREF or 0 to 2 × VREF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it of the correct format for the ADC.
Figure 26 shows a typical connection diagram when operating
the ADC in single-ended mode.
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (i.e., VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals each of amplitude VREF
that are 180° out of phase (assuming the 0 to VREF range is
selected). The amplitude of the differential signal is therefore
−VREF to +VREF peak-to-peak (i.e., 2 × VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals, i.e. (VIN+ + VIN−)/2 and is therefore the voltage
that the two inputs are centered on. This results in the span of
each input being CM ± VREF/2. This voltage has to be set up
externally and its range varies with VREF. As the value of VREF
increases, the common-mode range decreases. When driving
the inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output voltage swing.
Figure 28 and Figure 29 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 to
VREF range or 2 × VREF range, respectively. The common mode
must be in this range to guarantee the functionality of the
AD7938/AD7939.
Rev. PrN | Page 20 of 32
Preliminary Technical Data
AD7938/AD7939
When a conversion takes place, the common mode is rejected
resulting in a virtually noise free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096 for the
AD7938 and 0 to 1024 for the AD7939. If the 2 × VREF range was
used then the input signal amplitude would extend from −2VREF
to +2VREF after conversion.
3.5
2.0
1.5
1.0
03715-0-033
0
0.5
1.0
1.5
VREF (V)
2.0
2.5
3.0
Figure 28. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 30 and Figure 31 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 30 converts a
unipolar, single-ended signal into a differential signal.
The differential op amp driver circuit in Figure 31 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
4.5
4.0
3.5
220Ω
3.0
2 × VREF p-p
2.5
390Ω
GND
V+
27Ω
2.0
V–
1.5
220Ω
VIN+
220Ω
AD7938/
AD7939
220Ω
1.0
03715-0-034
V+
0.6
1.1
1.6
2.1
A
27Ω
V–
3.75V
2.5V
1.25V
VIN–
VREF
2.6
VREF (V)
20kΩ
0.47µF
10kΩ
03715-0-035
0.5
0
0.1
3.75V
2.5V
1.25V
Figure 29. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Figure 30. Dual Op Amp Circuit to Convert a Single-Ended
Unipolar Signal into a Differential Signal
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Since not
all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-todifferential conversion.
220Ω
2 × VREF p-p
VREF
GND
390Ω
V+
27Ω
V–
3.75V
2.5V
1.25V
VIN+
220Ω
AD7938/
AD7939
220Ω
V+
A
20kΩ
27Ω
V–
3.75V
2.5V
1.25V
VIN–
VREF
10kΩ
Figure 31. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
Rev. PrN | Page 21 of 32
0.47µF
03715-0-036
COMMON-MODE RANGE (V)
2.5
0.5
COMMON-MODE RANGE (V)
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7938/AD7939.
The circuit configurations shown in Figure 30 and Figure 31
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
that could be used in this configuration to provide differential
drive to the AD7938/AD7939 is the AD8022.
3.0
0
Using an Op Amp Pair
AD7938/AD7939
Preliminary Technical Data
Pseudo-Differential Mode
POWER ON
VREF p-p
VIN+
AD7938/
AD7939*
VIN–
VREF
*ADDITIONAL PINS OMITTED FOR CLARITY
0.47µF
03715-0-037
DC INPUT
VOLTAGE
Figure 32. Pseudo-Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 9, the user can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
Traditional Multichannel Operation (SEQ = SHDW = 0)
Any one of eight analog input channels or four pairs of channels
may be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 33 shows a flow chart of this
mode of operation. The channel configurations are shown in
Table 9.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
03715-0-038
The AD7938/AD7939 can have four pseudo-differential pairs
(Pseudo Mode 1) or seven pseudo differential inputs (Pseudo
Mode 2) by setting the MODE0 and MODE1 bits in the control
register to 1, 0 and 1, 1, respectively. In the case of the four
pseudo-differential pairs, VIN+ is connected to the signal source
which must have an amplitude of VREF to make use of the full
dynamic range of the part. A dc input is applied to the VIN− pin.
The voltage applied to this input provides an offset from ground
or a pseudo ground for the VIN+ input. In the case of the seven
pseudo-differential inputs, the seven analog input signals inputs
are referred to a dc voltage applied to VIN7. The benefit of
pseudo-differential inputs is that they separate the analog input
signal ground from the ADC’s ground allowing dc commonmode voltages to be cancelled. Figure 32 shows a connection
diagram for pseudo-differential mode.
Figure 33. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Programmable Sequence (SEQ = 0,
SHDW = 1 )
The AD7938/AD7939 may be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register to
1, see Table 11.
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed will be on the next highest channel in the
sequence and so on. When the last channel in the sequence is
converted, the internal multiplexer returns to the first channel
selected in the shadow register and commences the sequence
again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the
sequence, then ensure that the SEQ and SHDW bits are set to 1,
0 to avoid interrupting the conversion sequence. The sequence
program remains in force until such time as the
AD7938/AD7939 is written to and the SEQ and SHDW bits are
configured with any bit combination except 1, 0. Figure 34
shows a flow chart of the programmable sequence operation.
Rev. PrN | Page 22 of 32
Preliminary Technical Data
AD7938/AD7939
REFERENCE SECTION
POWER ON
The AD7938/AD7939 can operate with either the on-chip or
external reference. The internal reference is selected by setting
the REF bit in the internal control register to 1. A block diagram
of the internal reference circuitry is shown in Figure 36. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal
reference, the VREFIN/VREFOUT pin should be decoupled to AGND
with a 0.47 µF capacitor. This internal reference not only
provides the reference for the analog-to-digital conversion, but
it can also be used externally in the system. It is recommended
that the reference output is buffered using an external precision
op amp before applying it anywhere in the system.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = 0 SHDW = 1.
INITIATE A WRITE CYCLE.
THIS WRITE CYCLE IS TO THE SHADOW REGISTER.
SET RELEVANT BITS TO SELECT
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
IN THE SHADOW REGISTER
WITH EACH CONVST PULSE.
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
WITH EACH CONVST PULSE
BUT ALLOWS THE RANGE,
CODING, ANALOG INPUT TYPE,
ETC BITS IN THE CONTROL
REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
BUFFER
03715-0-039
SEQ BIT = 1
SHDW BIT = 0
REFERENCE
VREFIN/
VREFOUT
ADC
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register. This
is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. Once the control register
is written to, to set this mode up, the next conversion is on
Channel 0, then Channel 1, and so on until the channel selected
by the address bits (ADD2 to ADD0) is reached. The cycle
begins again provided the WR input is tied high. If low, the SEQ
and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 35
shows the flow chart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ = 1 SHDW = 1.
SEQ BIT = 1
SHDW BIT = 0
Figure 35. Consecutive Sequence Mode Flow Chart
Figure 36. Internal Reference Circuit Block Diagram
Alternatively, an external reference can be applied to the
VREFIN/VREFOUT pin of the AD7938/AD7939. An external
reference input is selected by setting the REF bit in the internal
control register to 0. When using an external reference, the
VREFIN/VREFOUT pin should be decoupled to AGND with a 0.1 µF
capacitor. When operating in differential mode, the external
reference input range is 0.1 V to 3.5 V, and in all other analog
input modes, the external reference input range is 0.1 V to VDD.
In all cases, the specified reference is 2.5 V.
It is important to ensure that, when choosing the reference
value, the maximum analog input range (VIN MAX) is never
greater than VDD + 0.3 V to comply with the maximum ratings
of the device. In the pseudo-differential modes, the user must
ensure that VREF + VIN− ≤ VDD when using the 0 to VREF range, or
when using the 2 × VREF range that 2 × VREF + VIN− ≤ VDD.
The following two examples calculate the maximum VREF input
that can be used when operating the AD7938/AD7939 in
differential mode, using the 0 to VREF range with a VDD of 5 V
and 3 V, respectively.
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
Example 1
VIN MAX = VDD + 0.3
VIN MAX = VREF + VREF/2
03715-0-040
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC BITS IN THE
CONTROL REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
AD7938/
AD7939
03715-0-041
Figure 34. Programmable Sequence Flow Chart
Consecutive Sequence (SEQ = 1, SHDW = 1)
If VDD = 5 V, then VIN MAX = 5.3 V.
Therefore, 3 × VREF/2 = 5.3 V.
VREF MAX = 3.5 V
Rev. PrN | Page 23 of 32
AD7938/AD7939
Preliminary Technical Data
Therefore, when operating at VDD = 5 V, the value of VREF can
range from 100 mV to a maximum value of 3.5 V. When VDD =
4.75 V, VREF MAX = 3.17 V.
AD7938/
AD7939*
AD780
VIN MAX = VDD + 0.3
NC
VDD
VIN MAX = VREF + VREF/2
0.1µF
If VDD = 3.6 V, then VIN MAX = 3.9 V.
10nF
0.1µF
1
O/PSELECT 8
2
+VIN
3
TEMP VOUT 6
4
GND
7
TRIM 5
NC
VREF
NC
2.5V
NC
0.1µF
NC = NO CONNECT
Therefore, 3 × VREF/2 = 3.6 V.
*ADDITIONAL PINS OMITTED FOR CLARITY
VREF MAX = 2.6 V
03715-0-042
Example 2
Figure 37. Typical VREF Connection Diagram
Therefore, when operating with at VDD = 3 V, the value of VREF
can range from 100 mV to a maximum value of 2.4 V. When
VDD = 2.7 V, VREF MAX = 2 V.
Digital Inputs
These examples show that the maximum reference applied to the
AD7938/AD7939 is directly dependant on the value applied to VDD.
The digital inputs applied to the AD7938/AD7939 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the AVDD + 0.3 V limit as on the analog inputs.
The performance of the part at different reference values is
shown in Figures TBD to TBD. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7938/AD7939 transfer function and add to specified fullscale errors on the part.
Another advantage of the digital inputs not being restricted by
the AVDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before
AVDD, then there is no risk of latch-up as there would be on the
analog inputs if a signal greater than 0.3 V was applied prior to
AVDD.
Table 12 lists examples of suitable voltage references that could
be used that are available from Analog Devices and Figure 37
shows a typical connection diagram for an external reference.
Table 12. Examples of Suitable Voltage References
Reference
AD780
ADR421
ADR420
Output
Voltage
2.5/3
2.5
2.048
Initial Accuracy
(% Max)
0.04
0.04
0.05
Operating
Current (µA)
1000
500
500
VDRIVE Input
The AD7938/AD7939 has a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V and 5 V processors.
For example, if the AD7938/AD7939 operate with an AVDD of
5 V and the VDRIVE pin is powered from a 3 V supply, the
AD7938/AD7939 has better dynamic performance with an
AVDD of 5V while still being able to interface directly to 3 V
processors. Care should be taken to ensure VDRIVE does not
exceed AVDD by more than 0.3 V (see the Absolute Maximum
Ratings section).
Rev. PrN | Page 24 of 32
Preliminary Technical Data
AD7938/AD7939
conversion is aborted and the track-and-hold goes back into
track. At the end of the conversion, BUSY goes low and can be
used to activate an interrupt service routine. The CS and RD
lines are then activated in parallel to read the 12- or 10- bits of
conversion data. When power supplies are first applied to the
device, a rising edge on CONVST puts the track-and-hold into
track. The acquisition time of 135 ns minimum must be allowed
before CONVST is brought low to initiate a conversion. The
ADC then goes into hold on the falling edge of CONVST and
back into track on the 13th rising edge of CLKIN after this (see
Figure 38). When operating the device in auto-shutdown or
auto-standby mode, where the ADC powers down at the end of
each conversion, a rising edge on the CONVST signal is used to
power up the device.
PARALLEL INTERFACE
The AD7938/AD7939 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7938) or 10-bits
(AD7939) wide and is capable of operating in either word (W/B
tied high) or byte (W/B tied low) mode. The CONVST signal is
used to initiate conversions on the ADC, and when operating in
auto-shutdown or auto-standby mode, it is used to power up the
device.
A falling edge on the CONVST signal is used to initiate
conversions and it also puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th rising edge of CLKIN; otherwise, the
B
t1
A
CONVST
1
CLKIN
BUSY
2
3
4
tCONVERT
5
12
13
14
t2
t20
t3
t9
INTERNAL
TRACK/HOLD
tAQUISITION
CS
t12
t13
DB0 TO DB11
THREE-STATE
t11
t14
DATA
THREE-STATE
tQUIET
WITH CS AND RD TIED LOW
DB0 TO DB11
OLD DATA
DATA
Figure 38. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle in Word Mode (W/B = 1)
Rev. PrN | Page 25 of 32
03715-0-004
t10
RD
AD7938/AD7939
Preliminary Technical Data
Reading Data from the AD7938/AD7939
is required to access data from the device. When operated in
byte mode, the two read cycles shown in Figure 39 are required
to access the full data-word from the device.
With the W/B pin tied logic high, the AD7938/AD7939
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word on
Pins DB0 to DB11. The DB8/HBEN pin assumes its DB8
function. With the W/B pin tied to logic low, the
AD7938/AD7939 interface operates in byte mode. In this case,
the DB8/HBEN pin assumes its HBEN function. Conversion
data from the AD7938/ AD7939 must be accessed in two read
operations with 8 bits of data provided on DB0 to DB7 for each
of the read operations. The HBEN pin determines whether the
read operation accesses the high byte or the low byte of the12or 10-bit word. For a low byte read, DB0 to DB7 provide the
eight LSBs of the 12-bit word. For 10-bit operation, the two
LSBs of the low byte are 0s and are followed by 6 bits of
conversion data. For a high byte read, DB0 to DB4 provide the
four MSBs of the 12-/10-bit word. DB5 to DB7 of the high byte
provide the Channel ID. Figure 38 shows the read cycle timing
diagram for a 12-/10-bit transfer. When operated in word mode,
the HBEN input does not exist, and only the first read operation
The CS and RD signals are gated internally and level triggered
active low. In either word mode or byte mode, CS and RD may
be tied together as the timing specifications for t10 and t11 are
0 ns minimum. This would mean the bus would be constantly
driven by the AD7938/AD7939.
The data is placed onto the data-bus a time t13 after both CS and
RD go low. The RD rising edge can be used to latch data out of
the device. After a time, t14, the data lines will become threestated.
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data-bus a time, t9,
before the falling edge of BUSY.
HBEN/DB8
t15
t16
t15
t16
CS
t11
RD
t13
DB0 TO DB7
t17
t12
t14
LOW BYTE
HIGH BYTE
03715-0-005
t10
Figure 39. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
Rev. PrN | Page 26 of 32
Preliminary Technical Data
AD7938/AD7939
Writing Data to the AD7938/AD7939
AD7938/AD7939. When operated in word mode, the HBEN
input does not exist and only the one write operation is required
to write the word of data to the device. Data should be provided
on DB0 to DB11. When operated in byte mode, the two write
cycles shown in Figure 41 are required to write the full dataword to the AD7938/AD7939. In Figure 41, the first write
transfers the lower 8 bits of the data-word from DB0 to DB7,
and the second write transfers the upper 4 bits of the data-word.
When writing to the AD7938/AD7939, the top 4 bits in the high
byte must be 0s.
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938/AD7939. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7938/AD7939 should be
provided on the DB0 to DB11 inputs with DB0 being the LSB of
the data-word. With W/B tied logic low, the AD7938/AD7939
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7938/AD7939 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word should be
written first with DB0 being the LSB of the full data-word. For
the high byte write, HBEN should be high and the data on the
DB0 input should be data bit 8 of the 12-bit word. In both word
and byte mode, a single write operation to the shadow register is
always sufficient since it is only 8-bits wide.
The data is latched into the device on the rising edge of WR.
The data needs to be setup a time, t7, before the WR rising edge
and held for a time, t8, after the WR rising edge. The CS and WR
signals are gated internally. CS and WR may be tied together as
the timing specifications for t4 and t5 are 0 ns minimum
(assuming CS and RD have not already been tied together).
Figure 40 shows the write cycle timing diagram of the
CS
t5
t6
t8
t7
DB0 TO DB11
03715-0-002
t4
WR
DATA
Figure 40. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
HBEN/DB8
t18
t19
t18
t19
CS
WR
t5
t7
DB0 TO DB11
t17
t6
t8
LOW BYTE
HIGH BYTE
03715-0-003
t4
Figure 41. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
Rev. PrN | Page 27 of 32
AD7938/AD7939
Preliminary Technical Data
POWER MODES OF OPERATION
The AD7938/AD7939 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 8. When power is first applied to the
AD7938/AD7939 an on-chip, power-on reset circuit ensures
that the default power-up condition is normal mode.
Note that, after power-on, the track-and-hold is in hold mode
and the first rising edge of CONVST places the track-and-hold
into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance because the user does not have to worry about any
power-up times associated with the AD7938/AD7939 because it
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Auto-Shutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7938/AD7939 automatically
enters full shutdown at the end of each conversion, which is
shown at Point A in Figure 38. In shutdown mode, all internal
circuitry on the device is powered down. The part retains
information in the control register during shutdown. The trackand-hold also goes into hold at this point and remains in hold
as long as the device is in shutdown. The AD7938/AD7939
remains in shutdown mode until the next rising edge of
CONVST (see Point B in Figure 38). In order to keep the device
in shutdown for as long as possible, CONVST should idle low
between conversions as shown in Error! Reference source not
found.. On this rising edge, the part begins to power-up and
track-and-hold returns to track mode. The power-up time
required depends on whether the user is operating with the
internal or external reference. With the internal reference, the
power-up time is typically TBD, and with an external reference,
the power-up time is typically TBD. The user should ensure that
the power-up time has elapsed before initiating a conversion.
Auto-Standby (PM1 = 1; PM0 = 0)
In this mode of operation, the AD7938/AD7939 automatically
enters standby mode at the end of each conversion, which is
shown as Point A in Figure 38. When this mode is entered, all
circuitry on the AD7938/AD7939 is powered down except for
the reference and reference buffer. The track-and-hold goes into
hold at this point also and remains in hold as long as the device
is in standby. The part remains in standby until the next rising
edge of CONVST powers up the device, which takes at least
TBD. The user should ensure this power-up time has elapsed
before initiating another conversion as shown in Error!
Reference source not found.. This rising edge of CONVST also
places track-and-hold back into track mode.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the
AD7938/AD7939 is powered down upon completion of the
write operation, i.e., on rising edge of WR. The part retains the
information in the control register while the part is in
shutdown. Also, track-and-hold goes into hold mode at this
point. The AD7938/AD7939 remains in full shutdown mode
and track-and-hold in hold mode, until the power management
bits (PM1 and PM0) in the control register are changed. If a
write to the control register occurs while the part is in full
shutdown mode, and the power management bits are changed
to PM0 = PM1 = 0, i.e., normal mode, the part begins to powerup on the WR rising edge and the track-and-hold returns to
track. To ensure the part is fully powered up before a conversion
is initiated, the power-up time, TBD, should be allowed before
the next CONVST falling edge; otherwise, invalid data will be
read.
tPOWER-UP
B
A
CONVST
1
14
1
14
03715-0-049
CLKIN
BUSY
Figure 42 Auto-Shutdown/Auto-Standby Mode
Rev. PrN | Page 28 of 32
Preliminary Technical Data
AD7938/AD7939
OPTIONAL
POWER VS. THROUGHPUT RATE
A0 TO A15
CONVST
ADDRESS BUS
AD7938/
AD7939*
ADSP-21xx*
DMS
ADDRESS
DECODER
IRQ2
CS
BUSY
WR
WR
RD
RD
DB0 TO DB11
D0 TO D23
03715-0-045
A big advantage of powering the ADC down after a conversion
is that the power consumption of the part is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7938/AD7939 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 43 and
Figure 44 show plots of power versus throughput when
operating in auto-shutdown and auto-standby modes.
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. Interfacing to the ADSP-21xx
AD7938/AD7939 to ADSP-21065L Interface
Figure 46 shows a typical interface between the
AD7938/AD7939 and the ADSP-21065L SHARC processor.
This interface is an example of one of three DMA handshake
modes. The MSx control line is actually three memory select
lines. Internal ADDR25-24 are decoded into MS3-0, these lines are
then asserted as chip selects. The DMAR1 (DMA request 1) is
used in this setup as the interrupt to signal the end of
conversion. The rest of the interface is standard handshaking
operation.
Figure 43. Power vs. Throughput in Auto-Shutdown Mode
OPTIONAL
ADDR0 TO ADDR23
MSX
ADDRESS BUS
CONVST
ADDRESS
LATCH
AD7938/
AD7939*
ADDRESS BUS
ADSP-21065L*
ADDRESS
DECODER
DMAR1
CS
BUSY
RD
RD
WR
WR
D0 TO D31
MICROPROCESSOR INTERFACING
DATA BUS
*ADDITIONAL PINS REMOVED FOR CLARITY
03715-0-046
DB0 TO DB11
Figure 44. Power vs. Throughput in Auto-Standby Mode
AD7938/AD7939 to ADSP-21xx Interface
Figure 45 shows the AD7938/AD7939 interfaced to the ADSP21xx series of DSPs as a memory mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (please see the ADSP-21xx
family User’s Manual for details). The following instruction
reads from the AD7938/AD7939
MR = DM(ADC)
where ADC is the address of the AD7938/AD7939.
Figure 46. Interfacing to the ADSP-21065L
AD7938/AD7939 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7938/AD7939 and the
TMS32020, TMS320C25, and TMS320C5x family of DSPs are
shown in Figure 47. The memory mapped address chosen for
the AD7938/AD7939 should be chosen to fall in the I/O
memory space of the DSPs. The parallel interface on the
AD7938/AD7939 is fast enough to interface to the TMS32020
with no extra wait states. If high speed glue logic, such as 74AS
devices, are used to drive the RD and the WR lines when
interfacing to the TMS320C25, then again, no wait states are
necessary. However, if slower logic is used, data accesses may be
Rev. PrN | Page 29 of 32
AD7938/AD7939
Preliminary Technical Data
slowed sufficiently when reading from and writing to the part to
require the insertion of one wait state. Extra wait states will be
necessary when using the TMS320C5x at their fastest clock
speeds (see the TMS320C5x User’s Guide for details).
Data is read from the ADC using the following instruction
IN D, ADC
where D is the data memory address and the ADC is the
AD7938/AD7939 address.
OPTIONAL
A0 TO A15
TMS32020/
TMS320C25/
TMS320C50*
CONVST
ADDRESS BUS
AD7938/AD7939 to 80C186 Interface
Figure 48 shows the AD7938/AD7939 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938/AD7939 finish a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
AD7938/
AD7939*
IS
ADDRESS
EN DECODER
OPTIONAL
CS
AD0 TO AD15
A16 TO A19
READY
TMS320C25
ONLY
MSC
STRB
ALE
CONVST
ADDRESS
LATCH
AD7938/
AD7939*
ADDRESS BUS
WR
R/W
ADDRESS/DATA BUS
80C186*
ADDRESS
DECODER
CS
RD
DATA BUS
DB11 TO DB0
*ADDITIONAL PINS OMITTED FOR CLARITY
Q
R
S
03715-0-047
DMD0 TO DMD15
BUSY
BUSY
RD
RD
WR
WR
DATA BUS DB0 TO DB11
Figure 47. Interfacing to the TMS32020/C25/C5x
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. Interfacing to the 80C186
Rev. PrN | Page 30 of 32
03715-0-048
DRQ1
INTX
Preliminary Technical Data
AD7938/AD7939
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7938/AD7939
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Digital and analog ground planes
should be joined in only one place, and the connection should
be a star ground point established as close to the ground pins on
the AD7938/AD7939 as possible. Avoid running digital lines
under the device as this will couple noise onto the die. The
analog ground plane should be allowed to run under the
AD7938/AD7939 to avoid noise coupling. The power supply
lines to the AD7938/AD7939 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This will reduce the effects of feedthrough through the
board. A microstrip technique is by far the best but is not always
possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized. The bottom
of the chip scale package has a thermal pad. The thermal pad on
the printed circuit board should be at least as large as this
exposed pad. On the printed circuit board, there should be a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern. This ensures that shorting is
avoided. Thermal vias may be used on the printed circuit board
thermal pad to improve thermal performance of the package. If
vias are used, they should be incorporated in the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via. The user should connect the printed
circuit board thermal pad to AGND.
EVALUATING THE AD7938/AD7939
PERFORMANCE
The recommended layout for the AD7938/AD7939 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the
AD7938/AD7939 evaluation board, as well as many other ADI
evaluation boards ending in the CB designator, to
demonstrate/evaluate the ac and dc performance of the
AD7938/AD7939.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the
AD7938/AD7939. The software and documentation are on the
CD that ships with the evaluation board.
Rev. PrN | Page 31 of 32
AD7938/AD7939
Preliminary Technical Data
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
25
24
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
TOP
VIEW
17
16
3.25
3.10 SQ
2.95
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1
BOTTOM
VIEW
0.50
0.40
0.30
1.00
0.85
0.80
32
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP], (CP-32)—Dimensions shown in millimeters
1.20
MAX
0.75
0.60
0.45
9.00 SQ
25
32
24
1
PIN 1
7.00
SQ
TOP VIEW
(PINS DOWN)
1.05
1.00
0.95
0.15
0.05
0° MIN
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
17
8
9
16
0.80
BSC
0.45
0.37
0.30
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 50. 32-Lead Thin Plastic Quad Flat Package [TQFP], (SU-32)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7938BCP
AD7939BCP
AD7938BSU
AD7939BSU
EVAL-ADxxxxCB2
EVAL-CONTROL BRD23
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Controller Board
Linearity Error (LSB)1
±1
±1
±1
±1
1
Package Option
CP-32
CP-32
SU-32
SU-32
Package Descriptions
LFCSP
LFCSP
TQFP
TQFP
Linearity error here refers to integral linearity error.
This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
3
Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB
designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVALADxxxxCB), the EVAL-CONTROL BRD2 and a 12 V
ac transformer. See the ADxxxx evaluation board technical note for more details.
2
©2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR03715-0-8/04(PrN)
Rev. PrN | Page 32 of 32