ASAHI KASEI [AK5355] AK5355 Low Power 16bit ∆Σ ADC FEATURES The AK5355 is a low voltage 16bit A/D converter for digital audio systems. The AK5355 also includes an Input Gain Amplifier, making it suitable for microphone applications or low-input signal levels. The analog signal input of the AK5355 is single-ended, eliminating the need for external filters. The AK5355 is housed in a space-saving 16pin TSSOP or 20pin QFN package. FEATURES 1. Resolution: 16bits 2. Recording Functions • Gain Amplifier (0dB / +15dB) • Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz) 3. ADC Characteristics • Single-ended Input • Input Level: 1.8Vpp@VA=3.0V (= 0.6 x VA) • S/(N+D): 85dB • DR, S/N: 91dB 4. Master Clock: 256fs/384fs/512fs 5. Audio Data Format: MSB First, 2’s compliment • 16bit MSB justified or I2S 8. Power Supply • VA, VD: 2.1 ∼ 3.6V (typ. 3.0V) 9. Power Supply Current: 5mA 10. Ta = -40 ∼ 85°C 11. Package: 16pin TSSOP 20pin QFN (4.2mm x 4.2mm, 0.5mm pitch) SEL DIF LIN ADC HPF Audio I/F Controller RIN LRCK BCLK SDTO VD VCOM PDN VA VSS Clock Divider MCLK MS0113-E-01 2005/01 -1- ASAHI KASEI [AK5355] Ordering Guide AK5355VT AK5355VN AKD5355 -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) -40 ∼ +85°C 20pin QFN (0.5mm pitch) Evaluation Board for AK5355VT Pin Layout (AK5355VT) VCOM 1 16 TST1 RIN 2 15 NC LIN 3 14 DIF VSS 4 13 PDN VA 5 12 BCLK VD 6 11 MCLK SEL 7 10 LRCK NC 8 9 SDTO Top View DIF PDN BCLK MCLK LRCK 14 13 12 11 5 20 VD VCOM 4 19 VA NC Top View 3 18 VSS NC AK5355 2 17 LIN TST1 1 16 RIN NC 15 Pin Layout (AK5355VN) MS0113-E-01 10 SDTO 9 NC 8 NC 7 NC 6 SEL 2005/01 -2- ASAHI KASEI [AK5355] PIN/FUNCTION (AK5355VT) No. 1 2 3 4 5 6 Pin Name VCOM RIN LIN VSS VA VD I/O O I I - Function ADC Common Voltage Output Pin Rch Input Pin Lch Input Pin Ground Pin Analog Power Supply Pin, +3.0V Digital Power Supply Pin, +3.0V Input Gain Select Pin 7 SEL I “L”: 0dB, “H”: +15dB 8 NC NC Pin (No internal bonding) 9 SDTO O Audio Serial Data Output Pin 10 LRCK I Input/Output Channel Clock Pin 11 MCLK I Master Clock Input Pin 12 BCLK I Audio Serial Data Clock Pin Reset & Power Down Pin 13 PDN I “L” : Reset & Power down, “H” : Normal operation Audio Data Format Select Pin 14 DIF I “L”: MSB justified, “H”: I2S 15 NC NC Pin (No internal bonding) TEST pin (Pull-down Pin) 16 TST1 I This pin should be left floating or connected to VSS Note: All digital input pins should not be left floating. MS0113-E-01 2005/01 -3- ASAHI KASEI [AK5355] PIN/FUNCTION (AK5355VN) No. 1 2 3 4 5 Pin Name RIN LIN VSS VA VD I/O I I - Function Rch Input Pin Lch Input Pin Ground Pin Analog Power Supply Pin, +3.0V Digital Power Supply Pin, +3.0V Input Gain Select Pin 6 SEL I “L”: 0dB, “H”: +15dB NC Pin (No internal bonding) 7 NC This pin should be left floating. NC Pin (No internal bonding) 8 NC This pin should be left floating. NC Pin (No internal bonding) 9 NC This pin should be left floating. 10 SDTO O Audio Serial Data Output Pin 11 LRCK I Input/Output Channel Clock Pin 12 MCLK I Master Clock Input Pin 13 BCLK I Audio Serial Data Clock Pin Reset & Power Down Pin 14 PDN I “L”: Reset & Power down, “H”: Normal operation Audio Data Format Select Pin 15 DIF I “L”: MSB justified, “H”: I2S NC Pin (No internal bonding) 16 NC This pin should be left floating. TEST pin (Pull-down Pin) 17 TST1 I This pin should be left floating or connected to VSS NC Pin (No internal bonding) 18 NC This pin should be left floating. NC Pin (No internal bonding) 19 NC This pin should be left floating. 20 VCOM O ADC Common Voltage Output Pin Note: All digital input pins should not be left floating. MS0113-E-01 2005/01 -4- ASAHI KASEI [AK5355] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Symbol Min Power Supply Analog VA -0.3 Digital VD -0.3 Input Current (Any Pin Except Supplies) IIN Analog Input Voltage (LIN, RIN pins) VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65 Note 1. All voltages with respect to ground. max 4.6 4.6 ±10 VA+0.3 VD+0.3 85 150 Units V V mA V V °C °C WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ Power Supply Analog (VA pin) VA 2.1 3.0 Digital (VD pin) VD 2.1 3.0 Note 1. All voltages with respect to ground. max 3.6 VA Units V V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS0113-E-01 2005/01 -5- ASAHI KASEI [AK5355] ANALOG CHARACTERISTICS (Ta=25°C; VA, VD=3.0V; fs=44.1kHz; Signal Frequency=1kHz; Measurement frequency=10Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Units Resolution 16 bits Input PGA Characteristics (IPGA): Gain = 0dB 1.65 1.8 1.95 Vpp Input Voltage (Note 2) Gain = +15dB 0.29 0.32 0.35 Vpp Gain = 0dB 27 40 kΩ Input Impedance Gain = +15dB 20 30 kΩ ADC Analog Input Characteristics: (Note 3) Gain = 0dB 75 85 dB S/(N+D) (-0.5dBFS Output) Gain = +15dB 70 80 dB Gain = 0dB 84 91 dB D-Range (-60dBFS Output, A-weight) Gain = +15dB 76 84 dB Gain = 0dB 84 91 dB S/N (A-weight) Gain = +15dB 76 84 dB Gain = 0dB 90 100 dB Interchannel Isolation Gain = +15dB 80 90 dB Gain = 0dB 0.2 0.5 dB Interchannel Gain Mismatch Gain = +15dB 0.2 1.0 dB Power Supplies Power Supply Current: VA+VD Normal Operation (PDN=“H”) 5 7.5 mA AK5355VT 10 100 µA Power Down (PDN=“L”) (Note 4) AK5355VN 10 20 µA Note 2. Analog input voltage (full-scale voltage) scales with VA. Gain = 0dB; 0.6 x VA Gain = +15dB; 0.107 x VA Note 3. ADC measurements are input from LIN/RIN and routed through input gain amplifier. The internal HPF cancels the offset of input gain amplifier and ADC. Note 4. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held at VD or VSS. PDN pin is held at VSS. MS0113-E-01 2005/01 -6- ASAHI KASEI [AK5355] FILTER CHARACTERISTICS (Ta=25°C; VA, VD=2.1 ∼ 3.6V; fs=44.1kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): PB 0 17.4 kHz Passband (Note 5) ±0.1dB 20.0 kHz -1.0dB 21.1 kHz -3.0dB Stopband (Note 5) SB 27.0 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 65 dB Group Delay (Note 6) GD 17.0 1/fs Group Delay Distortion 0 ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 5) -3dB FR 3.4 Hz -0.5dB 10 Hz -0.1dB 22 Hz Note 5. The passband and stopband frequencies scale with fs (sampling frequency). For examples, PB=0.454 x fs(@ADC: -1.0dB). Note 6. The calculated delay time caused by digital filtering. This time is from the input of an analog signal to setting the 16bit data of both channels to the output register of the ADC and includes the group delay of the HPF. DC CHARACTERISTICS (Ta=25°C; VA, VD=2.1 ∼ 3.6V) Parameter Symbol min High-Level Input Voltage (Except for TST1 VIH 75%VD pin) VIL Low-Level Input Voltage (Except for TST1 pin) VOH VD-0.4 High-Level Output Voltage (Iout=-80µA) VOL Low-Level Output Voltage (Iout=80µA) Input Leakage Current (Note 7) Iin Note 7. TST1 pin is pulled-down internally (typ. 100kΩ) MS0113-E-01 typ - max 25%VD Units V V - 0.4 ± 10 V V µA - 2005/01 -7- ASAHI KASEI [AK5355] SWITCHING CHARACTERISTICS (Ta=25°C; VA, VD=2.1 ∼ 3.6V; CL=20pF) Parameter Symbol min typ Control Clock Frequency Master Clock (MCLK) 11.2896 2.048 fCLK 256fs: Frequency 28 tCLKL Pulse Width Low 28 tCLKH Pulse Width High 16.9344 3.072 fCLK 384fs: Frequency 23 tCLKL Pulse Width Low 23 tCLKH Pulse Width High 22.5792 4.096 fCLK 512fs: Frequency 16 tCLKL Pulse Width Low 16 tCLKH Pulse Width High 44.1 8 fs Channel Clock (LRCK) Frequency 45 duty Duty Cycle Audio Interface Timing 312.5 tBLK BCLK Period 130 tBLKL BCLK Pulse Width Low 130 tBLKH Pulse Width High -tBLKH+50 tBLR BCLK “↓” to LRCK tDLR LRCK Edge to SDTO (MSB) tDSS BCLK “↓” to SDTO Reset / Initializing Timing 150 tPW PDN Pulse Width tPWV 4128 PDN “↑” to SDTO (Note 8) Note 8. This is the number of LRCK rising after the PDN pin is pulled high. MS0113-E-01 max Units 12.8 50 55 MHz ns ns MHz ns ns MHz ns ns kHz % tBLKL-50 80 80 ns ns ns ns ns ns 19.2 25.6 ns 1/fs 2005/01 -8- ASAHI KASEI [AK5355] Timing Diagram 1/fCLK VIH VIL MCLK tCLKH tCLKL 1/fs VIH VIL LRCK tBLK VIH VIL BCLK tBLKH tBLKL Figure 1. Clock Timing VIH VIL LRCK tBLR VIH VIL BCLK tDLR tDSS SDTO D15 (MSB) 50%VD Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0) tPW PDN VIL tPWV SDTO 50%VD Figure 3. Reset Timing MS0113-E-01 2005/01 -9- ASAHI KASEI [AK5355] OPERATION OVERVIEW System Clock The clocks required to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BCLK (32fs∼). The master clock (MCLK) should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2 automatically. *fs is sampling frequency. All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK5355 should be placed in power-down mode. Audio Data I/F Format The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes, MSB-first and 2’s compliment. The data format is set using the DIF pin. No. 0 1 DIF pin L H SDTO (ADC) LRCK 16bit MSB justified Lch: “H”, Rch: “L” I2S Compatible Lch: “L”, Rch: “H” Table 1. Audio Data Format BCLK ≥ 32fs ≥ 32fs Figure Figure 4 Figure 5 LRCK 0 1 2 8 3 9 10 11 12 13 14 15 0 1 2 8 3 9 10 11 12 13 14 15 0 1 BCLK(32fs) SDTO(o) 15 14 13 0 1 2 8 7 3 6 14 5 15 4 16 3 17 2 1 18 0 31 15 14 13 0 1 2 8 7 3 6 14 5 15 4 16 3 17 2 1 18 0 15 31 0 1 BCLK(64fs) SDTO(o) 15 14 13 13 2 1 0 15 14 13 1 2 1 0 15 15:MSB, 0:LSB Lch Data Rch Data Figure 4. Audio Data Timing (No.0) LRCK 0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1 BCLK(32fs) SDTO(o) 0 0 15 1 14 13 2 3 4 7 7 14 6 15 5 16 4 17 3 2 18 1 31 0 0 15 14 13 1 2 3 7 4 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 1 BCLK(64fs) SDTO(o) 15 14 13 2 1 0 15 14 13 2 2 1 0 15:MSB, 0:LSB Rch Data Lch Data Figure 5. Audio Data Timing (No. 1) MS0113-E-01 2005/01 - 10 - ASAHI KASEI [AK5355] Digital High Pass Filter The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs). Input Gain Amplifier The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input impedance is 40kΩ typically. SEL pin Gain L 0dB H +15dB Table 2. Input Gain Amplifier Power down The AK5355 is placed in the power-down mode by bringing PDN “L”. The digital filter is also reset at the same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. The output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the input signals at the end of initialization (Settling time equals the group delay time approximately). 4128/fs(93.6ms@fs=44.1kHz) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (1) GD A/D In (Analog) A/D Out (Digital) Clock In MCLK,LRCK,BCLK (2) “0”data Idle Noise “0”data Idle Noise (3) Notes: (1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD). (2) A/D output is “0” data in the power-down state. (3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the power-down state. Figure 6. Power-down/up sequence example System Reset The AK5355 should be reset once by bringing PDN ”L” upon power-up. The AK5355 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK5355 is in the power-down mode until MCLK and LRCK are input. MS0113-E-01 2005/01 - 11 - ASAHI KASEI [AK5355] SYSTEM DESIGN (AK5355VT) Figure 7 shows the system connection diagram. An evaluation board [AKD5355] is available which demonstrates the application circuit, optimum layout, power supply arrangements and measurement results. + 2.2µ Analog Supply 2.1 ∼ 3.6V Digital Supply 2.1 ∼ 3.6V 0.1µ Rch In + 1 VCOM Lch In + 2 RIN NC 15 3 LIN DIF 14 4 VSS 5 VA BCLK 12 6 VD MCLK 11 7 SEL LRCK 10 8 NC SDTO 10µ 10µ + + 0.1µ TST1 16 PDN 13 Top View 0.1µ Mode Setting Reset Controller 9 Analog Ground System Ground Figure 7. System Connection Diagram Example (AK5355VT) MS0113-E-01 2005/01 - 12 - ASAHI KASEI [AK5355] SYSTEM DESIGN (AK5355VN) Figure 8 shows the system connection diagram. An evaluation board [AKD5355] is available which demonstrates the application circuit, optimum layout, power supply arrangements and measurement results. Rch In + Lch In + Analog Supply 2.1 ∼ 3.6V 10µ + 16 Mode Setting NC 17 0.1µ TST1 18 + NC 19 NC VCOM 20 2.2µ 1 RIN DIF 15 2 LIN PDN 14 3 VSS BCLK 13 4 VA MCLK 12 5 VD LRCK 11 Top View Reset 0.1µ NC NC NC SDTO 7 8 9 10 + SEL 10µ 6 Controller Digital Supply 2.1 ∼ 3.6V 0.1µ Analog Ground System Groun Figure 8. System Connection Diagram Example (AK5355VN) MS0113-E-01 2005/01 - 13 - ASAHI KASEI [AK5355] MIC Device Connection Example Figure 9 and Figure 10 show the connection example of MIC Device. In this case, a mono microphone is connected to LIN pin the AK5355. Unused RIN pin can be open. The power supply for the microphone is provided via 4.4kΩ (2.2kΩ + 2.2kΩ) from analog power supply. The power supply noise provided to the microphone should be care because the microphone gain is usually high, around 40dB. In Figure 9, 1st order LPF by 2.2kΩ and 10µF is inserted between the power supply and the microphone. The AK5355 has a gain of +15dB in analog stage. However, as the usual application needs a gain of around 40dB or 50dB, the shortage of gain, 25dB or 35dB, should be covered by digital processing like DSP. The total S/N in each gain level is shown in Table 3 Analog Gain +15dB +15dB +15dB Digital Gain 0dB +25dB +35dB Table 3. S/N of each gain level + 2.2µ 0.1µ MIC S/N 83dB 58dB 48dB 0.1µ 2.2k 2.2k Analog Supply 2.1 ∼ 3.6V Digital Supply 2.1 ∼ 3.6V + 10µ 10µ 10µ + + TST1 16 1 VCOM 2 RIN NC 15 3 LIN DIF 14 4 VSS 5 VA BCLK 12 6 VD MCLK 11 7 SEL LRCK 10 8 NC SDTO 0.1µ PDN 13 Top View 0.1µ Mode Setting Reset Controller 9 Analog Ground System Ground Figure 9. MIC Device Connection Example (AK5355VT) MS0113-E-01 2005/01 - 14 - ASAHI KASEI [AK5355] 2.2k + 10µ Analog Supply 2.1 ∼ 3.6V 10µ + 16 Mode Setting NC 17 0.1µ TST1 18 + NC 2.2k NC VCOM 20 0.1µ MIC 19 2.2µ 1 RIN DIF 15 2 LIN PDN 14 3 VSS BCLK 13 4 VA MCLK 12 5 VD LRCK 11 Top View Reset 0.1µ NC NC NC SDTO 7 8 9 10 + SEL 10µ 6 Controller Digital Supply 2.1 ∼ 3.6V 0.1µ Analog Ground System Groun Figure 10. MIC Device Connection Example (AK5355VN) MS0113-E-01 2005/01 - 15 - ASAHI KASEI [AK5355] 1. Grounding and Power Supply Decoupling The AK5355 requires careful attention to power supply and grounding arrangements. VA is usually supplied from the analog supply in the system. VD is a power supply pin to interface with the external ICs and is supplied from the digital supply in the system. VSS of the AK5355 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5355 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The input to VA Voltage sets the analog input range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor are normally connected to VA and VSS pins. VCOM is a signal ground of this chip. An electrolytic 2.2µF in parallel with a 0.1µF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clock, should be kept away from the VA, VD and VCOM pins in order to avoid unwanted coupling into the AK5355. 3. Analog Inputs The analog inputs are single-ended and the input resistance is 40kΩ (typ). The input signal range scales with nominally (0.6 x VA) Vpp (typ) @ GAIN = 0dB centered around the internal common voltage (typ. 0.45 x VA). Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2πRC). The ADC output data format is 2’s complement. The DC offset including the ADC’s own DC offset is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz). MS0113-E-01 2005/01 - 16 - ASAHI KASEI [AK5355] PACKAGE (AK5355VT) 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.65 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0113-E-01 2005/01 - 17 - ASAHI KASEI [AK5355] PACKAGE (AK5355VN) 0. 11 20pin QFN (Unit: mm) ± 4.20 ± 0.10 -0 22 0. .6 9 4.00 ± 0.05 ± 3 A 05 0. 4.00 ± 0.05 B 35 0. 0.50 0.05 M S AB 0.22 +- 0.03 0.05 S 0.60 ± 0.10 11 0. 0.22 ± 0.05 ± 1.00 0.90 ± 0.05 C0.7 45.0° 0.50 1.00 45.0° 0.02TYP 0.005MIN 0.04MAX 4.20 ± 0.10 3 - C0.2 0.05 S Note: The black parts of back package should be open. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0113-E-01 2005/01 - 18 - ASAHI KASEI [AK5355] MARKING (AK5355VT) AKM 5355VT XXYYY 1) Pin #1 indication 2) Date Code : XXYYY (5 digits) XX : Lot# YYY : Date Code 3) Marketing Code : 5355VT 4) Asahi Kasei Logo MS0113-E-01 2005/01 - 19 - ASAHI KASEI [AK5355] MARKING (AK5355VT) 5355 XXXX 1 XXXX : Date code identifier (4 digits) Revision History Date (YY/MM/DD) 01/08/27 05/01/20 Revision 00 01 Reason First Edition Spec addition Page Contents 2 6 20pin QFN package is added. Power supply current (Power-down mode, 20QFN): 20µA(max) IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0113-E-01 2005/01 - 20 -