CAT9554, CAT9554A 8-bit I2C and SMBus I/O Port with Interrupt FEATURES DESCRIPTION ■ 400kHz I2C bus compatible* The CAT9554 and CAT9554A are CMOS devices that provide 8-bit parallel input/output port expansion for I2C and SMBus compatible applications. These I/O expanders provide a simple solution in applications where additional I/Os are needed: sensors, power switches, LEDs, pushbuttons, and fans. ■ 2.3V to 5.5V operation ■ Low stand-by current ■ 5V tolerant I/Os ■ 8 I/O pins that default to inputs at power-up The CAT9554/9554A consist of an input port register, an output port register, a configuration register, a polarity inversion register and an I2C/SMBus-compatible serial interface. ■ High drive capability ■ Individual I/O configuration ■ Polarity inversion register ■ Active low interrupt output Any of the eight I/Os can be configured as an input or output by writing to the configuration register. The system master can invert the CAT9554/9554A input data by writing to the active-high polarity inversion register. ■ Internal power-on reset ■ No glitch on power-up ■ Noise filter on SDA/SCL inputs The CAT9554/9554A features an active low interrupt output which indicates to the system master that an input state has changed. ■ Cascadable up to 8 devices ■ Industrial temperature range ■ RoHS-compliant 16-lead SOIC and TSSOP, and The device’s extended addressing capability allows up to 8 devices to share the same bus. The CAT9554A is identical to the CAT9554 except the fixed part of the I2C slave address is different. This allows up to 16 of devices (eight CAT9554 and eight CAT9554A) to be connected on the same bus. 16-pad TQFN (4 x 4 mm) packages APPLICATIONS ■ White goods (dishwashers, washing machines) ■ Handheld devices (cell phones, PDAs, digital cameras) ■ Data Communications (routers, hubs and For Ordering Information details, see page 15. servers) BLOCK DIAGRAM A0 I/O0 A1 I/O1 A2 I/O2 8-BIT SCL SDA I2C/SMBUS CONTROL INPUT FILTER WRITE pulse I/O3 INPUT/ OUTPUT PORTS I/O4 I/O5 READ pulse I/O6 I/O7 VCC POWER-ON RESET VSS LP FILTER VCC INT NOTE: ALL I/Os ARE SET TO INPUTS AT RESET * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25088, Rev. B CAT9554, CAT9554A PIN CONFIGURATION SOIC (W) TSSOP (Y) SDA 14 SCL I/O0 4 13 INT I/O1 5 12 I/O7 I/O2 6 11 I/O6 I/O3 7 10 I/O5 VSS 8 9 I/O4 13 15 3 12 SCL A2 1 I/O0 2 11 INT I/O1 3 10 I/O7 I/O2 4 9 I/O6 8 2 A2 VCC SDA 14 A1 A0 7 VCC 15 16 6 1 5 A0 16 TQFN (HV4) A1 I/O3 VSS I/O4 I/O5 4 x 4 mm Top View PIN DESCRIPTION SOIC / TSSOP TQFN PIN NAME FUNCTION 1 15 A0 Address Input 0 2 16 A1 Address Input 1 3 1 A2 Address Input 2 4-7 2-5 I/O0-3 8 6 VSS 9-12 7-10 I/O4-7 13 11 INT Interrupt Output (open drain) 14 12 SCL Serial Clock 15 13 SDA Serial Data 16 14 VCC Power Supply Input/Output Port 0 to Input/Output Port 3 Ground Input/Output Port 4 to Input/Output Port 7 ABSOLUTE MAXIMUM RATINGS(1) VCC with Respect to Ground ............... –0.5V to +6.5V VSS Supply Current .......................................... 100mA Voltage on Any Pin with Respect to Ground ........................ –0.5V to +5.5V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W DC Current on I/O0 to I/O7 ........................................... +50 mA Junction Temperature ..................................... +150°C DC Input Current ............................................. +20 mA Storage Temperature ........................ -65°C to +150°C VCC Supply Current ............................................ 85mA RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units VZAP(2) ESD Susceptibility JEDEC Standard JESD 22 2000 Volts ILTH(2)(3) Latch-up JEDEC Standard 17 100 mA Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. Doc. No. 25088, Rev. B 2 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A D.C. OPERATING CHARACTERISTICS VCC = 2.3 to 5.5 V; TA = -40°C to +85°C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit 2.3 — 5.5 V — 104 175 µA — 550 700 µA — 0.25 1 µA — 1.5 1.65 V -0.5 0.7 VCC 3 – 1 — — — — — — — — 0.3 VCC 5.5 — +1 6 8 V V mA µA pF pF Low level input voltage High level input voltage Input leakage current -0.5 2.0 -1 — — — 0.8 5.5 1 V V µA Low level input voltage High level input voltage -0.5 2.0 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 — — — — — — 10 13 17 24 14 19 — — — — — — — — — — 0.8 5.5 — — — — — — — — — — — — 1 -100 5 8 V V mA mA mA mA mA mA V V V V V V µA µA pF pF Supplies VCC Supply voltage ICC Supply current Istbl Standby current Istbh Standby current VPOR Power-on reset voltage Operating mode; VCC = 5.5 V; no load; fSCL = 100 kHz Standby mode; VCC = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VCC = 5.5 V; no load; VI = VCC; fSCL = 0 kHz; I/O = inputs No load; VI = VCC or VSS SCL, SDA, INT VIL (1) VIH (1) IOL IL CI (2) CO (2) Low level input voltage High level input voltage Low level output current Leakage current Input capacitance Output capacitance VOL = 0.4V VI = VCC or VSS VI = VSS VO = VSS A0, A1, A2 VIL (1) VIH (1) ILI I/Os VIL VIH IOL Low level output current VOH High level output voltage IIH IIL CI (2) CO (2) Input leakage current Input leakage current Input capacitance Output capacitance VOL = 0.5 V; VCC = 2.3 V; (3) VOL = 0.7 V; VCC = 2.3 V; (3) VOL = 0.5 V; VCC = 4.5 V; (3) VOL = 0.7 V; VCC = 4.5 V; (3) VOL = 0.5 V; VCC = 3.0 V; ((3) VOL = 0.7 V; VCC = 3.0 V; (3) IOH = – 8 mA; VCC = 2.3 V; (4) IOH = – 10 mA; VCC = 2.3 V; (4) IOH = – 8 mA; VCC = 3.0 V; (4) IOH = – 10 mA; VCC = 3.0 V; (4) IOH = – 8 mA; VCC = 4.75 V; (4) IOH = – 10 mA; VCC = 4.75 V; (4) VCC = 3.6 V; VI = VCC VCC = 5.5 V; VI = VSS Notes: 1. VIL min and VIH max are reference values only and are not tested. 2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 3. The total current sunk by all I/Os must be limited to 100 mA and each I/O limited to 25 mA maximum. 4. The total current sourced by all I/Os must be limited to 85 mA. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 25088, Rev. B CAT9554, CAT9554A A.C. CHARACTERISTICS VCC = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise specified(1). Symbol Parameter Min Max Units fSCL Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 50 ns tLOW Clock Low Period 1.3 µs tHIGH µs Clock High Period 0.6 (2) SDA and SCL Rise Time 20 300 ns (2) SDA and SCL Fall Time 20 300 ns tHD:STA Start Condition Hold Time 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD:DAT Data Input Hold Time 0 ns tSU:DAT Data In Setup Time 100 ns tSU:STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid tDH Data Out Hold Time 50 ns Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tR tF (2) tBUF 900 ns Port Timing tPV Output Data Valid 200 ns tPS Input Data Setup Time 100 ns tPH Input Data Hold Time 1 µs Interrupt Timing tIV Interrupt Valid 4 µs tIR Interrupt Reset 4 µs Notes: 1. Test conditions according to "AC Test Conditions" table. 2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. 25088, Rev. B 4 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A AC TEST CONDITIONS Input Rise and Fall time < = 10ns CMOS Input Voltages 0.2VCC to 0.8VCC CMOS Input Reference Voltages 0.3VCC to 0.7VCC TTL Input Voltages 0.4V to 2.4V TTL Input Reference Voltages 0.8V, 2.0V Output Reference Voltages 0.5VCC Output Load: SDA, INT Current Souce IOL = 3mA; CL = 100pF Output Load: I/Os Current Source: IOL/IOH = 10mA; CL = 50pF tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 1. 2-Wire Serial Interface Timing © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 25088, Rev. B CAT9554, CAT9554A PIN DESCRIPTION A0, A1, A2: Device Address Inputs SCL: Serial Clock These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VCC or VSS. When hardwired, up to eight CAT9554/9554As may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. SDA: Serial Data/Address I/O0 to I/O7: Input / Output Ports The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pull-up resistor must be connected from SDA line to Vcc. The value of the pull-up resistor, RP, can be calculated based on minimum and maximum values from Figure 2 and Figure 3 (see Note). Any of these pins may be configured as input or output. The simplified schematic of I/O0 to I/O7 is shown in Figure 4. When an I/O is configured as an input, the Q1 and Q2 output transistors are off creating a high impedance input with a weak pull-up resistor (typical 100 kΩ). If the I/O pin is configured as an output, the pushpull output stage is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VCC or VSS. (Fast Mode I2C Bus / tr max = 300ns) (IOL = 3mA @ VOLmax) 8.00 RP max (Kohm) RP min (Kohm) 2.5 2 1.5 1 0.5 0 2 2.4 2.8 3.2 3.6 4 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 4.4 4.8 5.2 5.6 50 VCC (V) 100 150 200 250 300 350 400 CBUS (pF) Figure 2. Minimum RP Value versus Supply Voltage Figure 3. Maximum RP Value versus Bus Capacitance Note: According to the Fast Mode I2C bus specification, for bus capacitance up to 200pF, the pull up device can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA) or a switched resistor circuit. Doc. No. 25088, Rev. B 6 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A INT: Interrupt Output The open-drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns Data from Shift Register Data from Shift Register to its previous state or the input port register is read. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. Output Port Register Data Configuration Register D Q VCC FF Write Configuration Pulse CK Q1 Q D Q FF Write Pulse I/O0 to I/O7 CK Q Output Port Register Q2 Input Port Register D Q LATCH Read Pulse Data from Shift Register VSS Input Port Register Data CK Q To INT D Q Polarity Register Data FF Write Polarity Register CK Q Polarity Inversion Register Figure 4. Simplified Schematic of I/O0 to I/O7 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 25088, Rev. B CAT9554, CAT9554A FUNCTIONAL DESCRIPTION START and STOP Conditions The CAT9554 and CAT9554A general purpose input/ output (GPIO) peripherals provide up to eight I/O ports, controlled through an I2C compatible serial interface The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT9554/9554A monitors the SDA and SCL lines and will not respond until this condition is met. The CAT9554/54A support the I2C Bus data transmission protocol. This I2C Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9554/9554A operate as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing After the bus Master sends a START condition, a slave address byte is required to enable the CAT9554/9554A for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 for the CAT9554 (Figure 6) and as 0111 for the CAT9554A (Figure 7). The CAT9554/9554A uses the next three bits as address bits. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7-bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 5). Following the START condition and the slave address byte, the CAT9554/9554A monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9554/9554A then performs a read or a write operation depending on the state of the R/W bit. SCL SDA START CONDITION STOP CONDITION Figure 5. START/STOP Conditions SLAVE ADDRESS SLAVE ADDRESS 0 1 0 FIXED 0 A2 A1 A0 0 R/W 1 FIXED PROGRAMMABLE HARDWARE SELECTABLE Figure 6. CAT9554 Slave Address Doc. No. 25088, Rev. B 1 1 A2 A1 A0 R/W PROGRAMMABLE HARDWARE SELECTABLE Figure 7. CAT9554A Slave Address 8 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 5). The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. The CAT9554/9554A respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. Table 2. Register 0 – Input Port Register When the CAT9554/9554A begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9554/9554A will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a STOP condition to return the CAT9554/9554A to the standby power mode and place the device in a known state. bit I7 I6 I5 I4 I3 I2 I1 I0 default 1 1 1 1 1 1 1 1 Table 3. Register 1 – Output Port Register bit O7 O6 O5 O4 O3 O2 O1 O0 default 1 1 1 1 1 1 1 1 Table 4. Register 2 – Polarity Inversion Register Registers and Bus Transactions The CAT9554/9554A consist of an input port register, an output port register, a polarity inversion register and a configuration register. Table 1 shows the register address table. Tables 2 to 5 list Register 0 through Register 3 information. bit N7 N6 N5 N4 N3 N2 N1 N0 default 0 0 0 0 0 0 0 0 Table 5. Register 3 – Configuration Register Table 1. Register Command Byte Command (hex) Protocol Function 0x00 Read byte Input port register 0x01 Read/write byte Output port register 0x02 Read/write byte Polarity inversion register 0x03 Read/write byte Configuration register bit C7 C6 C5 C4 C3 C2 C1 C0 default 1 1 1 1 1 1 1 1 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 BUS RELEASE DELAY (RECEIVER) 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP ACK DELAY Figure 8. Acknowledge Timing © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 25088, Rev. B CAT9554, CAT9554A The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value. the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At power-up, the I/Os are configured as inputs with a weak pull-up resistor to VCC. Data is transmitted to the CAT9554/9554A registers using the write mode shown in Figure 9 and Figure 10. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set (“1”) the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared (“0”), the original input port polarity is retained. The CAT9554/9554A registers are read according to the timing diagrams shown in Figure 11 and Figure 12. Once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte will be sent. The configuration register sets the directions of the ports. Set the bit in the configuration register to enable 1 SCL 2 3 4 5 6 7 slave address SDA S 0 1 0 0 8 9 command byte R/W A2 A1 A0 0 A 0 0 0 0 0 0 1 A acknowledge from slave acknowledge from slave start condition 0 data to port DATA 1 A acknowledge from slave P stop condition WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID tpv Figure 9. Write to Output Port Register 1 SCL 2 3 4 5 6 7 slave address SDA S 0 1 start condition 0 0 A2 A1 A0 8 9 command byte R/W 0 acknowledge from slave A 0 0 0 0 0 0 data to register 1 1/0 acknowledge from slave A DATA 1 acknowledge from slave A P stop condition WRITE TO REGISTER Figure 10. Write to Configuration or Polarity Inversion Register Doc. No. 25088, Rev. B 10 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A Power-On Reset Operation reset condition is released and the internal state machine and the CAT9554/9554A registers are initialized to their default state. When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9554/9554A in a reset state until VCC reaches VPOR level. At this point, the slave address S 0 1 0 0 slave address R/W A2 A1 A0 0 A A COMMAND BYTE acknowledge from slave S 0 1 0 0 acknowledge from master data from register R/W DATA A2 A1 A0 1 A acknowledge from slave acknowledge from slave A first byte At this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter no acknowledge from master data from register DATA NA P last byte Figure 11. Read from Register 1 SCL 2 3 4 5 6 7 8 slave address SDA S 0 1 0 0 data from port R/W A2 A1 A0 1 acknowledge from slave start condition 9 A DATA 1 A data from port acknowledge from master DATA 4 NA no acknowledge from master P stop condition READ FROM PORT DATA INTO PORT DATA 3 DATA 2 DATA 1 tPH DATA 4 tPS INT tIV tIR Figure 12. Read Input Port Register © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 25088, Rev. B CAT9554, CAT9554A PACKAGE DRAWINGS 16-LEAD 150 MIL WIDE SOIC (W) E1 E h x 45 D C A θ1 e A1 L b SYMBOL MIN A1 A b C D E E1 e h L θ1 0.10 1.35 0.33 0.17 9.80 5.80 3.80 0.25 0.40 0° NOM 9.90 6.00 3.90 1.27 BSC MAX 0.25 1.75 0.51 0.25 10.00 6.20 4.00 0.50 1.27 8° 16-Lead_SOIC.eps Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-013. Doc. No. 25088, Rev. B 12 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A PACKAGE DRAWINGS 16-LEAD TSSOP (Y) SEE DETAIL A E E1 C D A2 A GAGE PLANE e b A1 θ1 L 0.25 L1 DETAIL "A" SYMBOL A A1 A2 b c D E E1 e L L1 θ1 MIN 0.05 0.80 0.19 0.09 4.90 4.30 0.45 0.00 NOM 0.90 5.00 6.40 BSC 4.40 0.65 BSC 0.60 1.00 REF MAX 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.75 8.00 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 25088, Rev. B CAT9554, CAT9554A PACKAGE DRAWINGS 16-PAD TQFN (4 x 4 mm) (HV4) D2 C PIN 1 ID D E2 b L A1 E 3xe A SYMBOL MIN MIN MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 C e 0.20 REF D 3.95 4.00 4.05 D2 2.15 2.20 2.25 e 0.65 BSC E 3.95 4.00 4.05 E2 2.15 2.20 2.25 L 0.50 0.55 0.60 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MO-229. Doc. No. 25088, Rev. B 14 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT9554, CAT9554A ORDERING INFORMATION Prefix Device # CAT Optional Company ID Suffix 9554 W Product Number 9554 9554A I –G Temperature Range I = Industrial (-40°C to +85°C) T2 Tape & Reel T: Tape & Reel 2: 2000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu Package W: SOIC Y: TSSOP HV4: TQFN Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu pre-plated on SOIC and TSSOP packages and Matte-Tin on TQFN packages. (3) The device used in the above example is a CAT9554WI-GT2 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Ordering Part Number Package Lead Finish CAT9554WI-G SOIC NiPdAu CAT9554WI-GT2 SOIC CAT9554YI-G CAT9554YI-GT2 Package Lead Finish CAT9554AWI-G SOIC NiPdAu NiPdAu CAT9554AWI-GT2 SOIC NiPdAu TSSOP NiPdAu CAT9554AYI-G TSSOP NiPdAu TSSOP NiPdAu CAT9554AYI-GT2 TSSOP NiPdAu CAT9554HV4I TQFN Matte-Tin CAT9554AHV4I TQFN Matte-Tin CAT9554HV4I-T2 TQFN Matte-Tin CAT9554AHV4I-T2 TQFN Matte-Tin © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Ordering Part Number 15 Doc. No. 25088, Rev. B REVISION HISTORY Date 07/08/2005 06/28/2006 Rev. A B Comments Initial Issue Update Features Add Applications Update Descriptions Update Pin Description Table Update Absolute Maximum Ratings Update D.C Operating Characteristics Update A.C Characteristics Update AC Test Conditions Update Pin Description Update Figure 2, Figure 4, Figure 5, Figure 8 and Figure 12 Update Functional Description Update Package Drawings Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 25088 B 06/28/06