Fairchild F3S49092 20a/10a, 12v, 0.060/0.140 ohm, logic level, complementary power mosfet Datasheet

RF3S49092SM
Data Sheet
20A/10A, 12V, 0.060/0.140 Ohm, Logic
Level, Complementary Power MOSFET
These complementary power MOSFETs are manufactured
using an advanced MegaFET process. This process, which
uses feature sizes approaching those of LSI integrated
circuits, gives optimum utilization of silicon, resulting in
outstanding performance. It is designed for use in
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This product achieves full rated conduction at a
gate bias in the 3V to 5V range, thereby facilitating true
on-off power control directly from logic level (5V) integrated
circuits.
September 2004
Features
• 20A, 12V (N-Channel)
10A, 12V (P-Channel)
• rDS(ON) = 0.060Ω (N-Channel)
rDS(ON) = 0.140Ω (P-Channel)
• Temperature Compensating PSPICE® Model
• On-Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
Formerly developmental type TA49092.
S2
Ordering Information
PART NUMBER
RF3S49092SM
PACKAGE
MO-169AB
G2
BRAND
F3S49092
NOTE: When ordering, use the entire part number. For ordering the
MO-169AB in tape and reel, add the suffix 9A to the part number, i.e.,
RF3S49092SM9A.
D1
G1
S1
Packaging
JEDEC MO-169AB
G2
S2
D G1
S1
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified
N-CHANNEL
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . VDSS
P-CHANNEL
UNITS
-12
V
12
Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . .VDGR
12
-12
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±10
±10
V
Drain Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed (Figures 5, 26) . . . . . . . . . . . . . . . . . . . . . . . . . IDM
20
Refer to Peak Current Curve
10
Refer to Peak Current Curve
A
Pulsed Avalanche Rating (Figures 6, 27). . . . . . . . . . . . . EAS
Refer to UIS Curve
Refer to UIS Curve
Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
0.33
50
0.33
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG
-55 to 175
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . .Tpkg
300
260
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications (N-Channel)
PARAMETER
TC = 25oC, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, (Figure 13)
12
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, (Figure 12)
1
-
-
V
TC = 25o C
-
-
1
µA
TC = 150o C
-
-
50
µA
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
IDSS
VDS = 12V,
VGS = 0V
VGS = ±10V
-
-
±100
nA
rDS(ON)
ID = 20A, VGS = 5V, (Figure 9, 11)
-
-
0.060
Ω
tON
VDD = 6V, ID ≈ 20A, RL = 0.24Ω,
VGS = 5V, RGS = 25Ω
(Figure 10)
-
-
100
ns
-
18
-
ns
IGSS
td(ON)
tr
-
60
-
ns
td(OFF)
-
50
-
ns
tf
-
60
-
ns
tOFF
-
-
140
ns
-
20
25
nC
-
12
15
nC
-
0.9
1.2
nC
-
750
-
pF
-
700
-
pF
-
275
-
pF
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 9.6V,
ID = 20A,
RL = 0.42Ω
(Figure 15)
VDS = 10V, VGS = 0V, f = 1MHz
(Figure 14)
Thermal Resistance Junction to Case
Rθ JC
-
-
3.00
oC/W
Thermal Resistance Junction to Ambient
Rθ JA
-
-
62
oC/W
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.5
V
ISD = 20A, dISD/dt = 100A/µs
-
-
100
ns
N-Channel Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Voltage
VSD
Reverse Recovery Time
trr
©2004 Fairchild Semiconductor Corporation
TEST CONDITIONS
RF3S49092SM Rev. C
RF3S49092SM
Electrical Specifications (P-Channel)
PARAMETER
TC = 25o C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, (Figure 34)
-12
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, (Figure 33)
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
-1
-
-
V
TC = 25o C
-
-
-1
µA
TC = 150o C
-
-
-50
µA
VGS = ±10V
-
-
±100
nA
ID = 10A, VGS = -5V, (Figures 30, 32)
-
-
0.140
Ω
VDD = -6V, ID ≈ 10A, RL = 0.62Ω,
VGS = -5V, RGS = 25Ω
(Figure 31)
-
-
115
ns
-
25
-
ns
tr
-
65
-
ns
td(OFF)
-
40
-
ns
tf
-
45
-
ns
tOFF
-
-
110
ns
-
19
24
nC
-
10
14
nC
-
0.8
1.1
nC
-
775
-
pF
-
550
-
pF
-
150
-
pF
IDSS
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = -12V,
VGS = 0V
Total Gate Charge
Qg(TOT)
VGS = 0V to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0V to -5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -1V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = -9.6V,
ID = 10A,
RL = 1.0Ω
(Figure 36)
VDS = -10V, VGS = 0V, f = 1MHz
(Figure 35)
Thermal Resistance Junction to Case
RθJC
-
-
3.00
oC/W
Thermal Resistance Junction to Ambient
Rθ JA
-
-
62
oC/W
MIN
TYP
MAX
UNITS
ISD = -10A
-
-
-1.5
V
ISD = -10A, dISD/dt = -100A/µs
-
-
100
ns
P-Channel Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Voltage
VSD
Reverse Recovery Time
trr
TEST CONDITIONS
Typical Performance Curves (N-Channel)
25
1.0
ID , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
20
15
10
5
0.2
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
©2004 Fairchild Semiconductor Corporation
175
0
25
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
Zθ JC, NORMALIZED
THERMAL IMPEDANCE
1
(Continued)
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x Rθ JC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TJ = MAX RATED, TC = 25oC
5ms
10ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
100ms
1s
DC
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
1000
IDM, PEAK CURRENT CAPABILITY (A)
ID, DRAIN CURRENT (A)
100
I
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
ID , DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
10-4
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
10-3
10-2
10-1
t, PULSE WIDTH (s)
10 0
101
FIGURE 5. PEAK CURRENT CAPABILITY
100
1
0.01
175 - TC
150
VGS = 5V
10 -5
10
50
= I25
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
NOTE:
TC = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
VGS = 5V
VGS = 4.5V
40
VGS = 4V
30
20
VGS = 3V
10
PULSE DURATION = 80µs, TC = 25oC
DUTY CYCLE = 0.5% MAX
0
100
Refer to Fairchild Application Notes AN9321 and AN9322.
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
6
7
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
50
25oC
(Continued)
200
VDD = 6V
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
175oC
40
-55oC
30
20
10
I D = 5A
I D = 10A
100
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
6
0
0
7
FIGURE 8. TRANSFER CHARACTERISTICS
tr
100
tD(OFF)
80
tf
60
40
20
t D(ON)
20
30
40
10
RGS, GATE TO SOURCE RESISTANCE (Ω)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
SWITCHING TIME (ns)
120
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
PULSE DURATION = 80µs, VGS = 5V, ID = 20A
0.6
-80
50
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
0.6
-80
10
1.6
VDD = 6V, ID = 20A, RL = 0.24Ω
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
140
0
I D = 20A
150
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (N-Channel)
(Continued)
10
VGS = 0V, f = 1MHz
900 CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1200
CISS
COSS
600
CRSS
300
8
6
4
0
2
4
6
8
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
ID = 5A
2
0
0
VDD = 9.6V
5
0
10
15
Qg, GATE CHARGE (nC)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
25
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms (N-Channel)
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
VDS
tf
tr
VDS
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
90%
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
10%
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
RF3S49092SM Rev. C
RF3S49092SM
Test Circuits and Waveforms (N-Channel)
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
Typical Performance Curves (P-Channel)
-15
1.0
ID , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
-10
-5
0.2
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
0
25
175
Zθ JC, NORMALIZED
THERMAL IMPEDANCE
FIGURE 22. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
100
125
75
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 23. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x Rθ JC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
ID, DRAIN CURRENT (A)
-100
(Continued)
TJ = MAX RATED, TC = 25oC
-10
5ms
10ms
100ms
1s
DC
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-1
-1
-10
-200
IDM, PEAK CURRENT CAPABILITY (A)
Typical Performance Curves (P-Channel)
TC = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
-100
I
VGS = -5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-1
10-5
-50
FIGURE 25. FORWARD BIAS SAFE OPERATING AREA
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
101
-40
PULSE DURATION = 80µs,
TC = 25oC
DUTY CYCLE = 0.5% MAX
I D, DRAIN CURRENT (A)
VGS = -10V
IAS, AVALANCHE CURRENT (A)
100
FIGURE 26. PEAK CURRENT CAPABILITY
-100
STARTING TJ = 25oC
-10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
-1
0.01
NOTE:
-30
VGS = -5V
-20
VGS = -4.5V
VGS = -4V
-10
VGS = -3V
0
10
0.1
1
tAV, TIME IN AVALANCHE (ms)
100
0
-1
-2
-3
-4
-5
-6
-7
VDS, DRAIN TO SOURCE VOLTAGE (V)
Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 28. SATURATION CHARACTERISTICS
FIGURE 27. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
500
-40
VDD = -6V
25oC
-30
ID = -3A
175oC
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
175 - TC
150
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
- 55oC
-20
-10
0
-2
-4
-6
-8
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 29. TRANSFER CHARACTERISTICS
©2004 Fairchild Semiconductor Corporation
ID = -10A
400
I D = -6A
300
200
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
= I25
VGS = -10V
-10
0
0
-2
-4
-6
-8
VGS, GATE TO SOURCE VOLTAGE (V)
-10
FIGURE 30. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
RF3S49092SM Rev. C
RF3S49092SM
Typical Performance Curves (P-Channel)
(Continued)
1.6
120
tr
SWITCHING TIME (ns)
100
tf
80
60
tD(OFF)
40
tD(ON)
20
00
20
10
30
40
PULSE DURATION = 80µs, VGS = -5V, ID = -10A
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VDD = -6V, ID = -10A, RL = 0.62Ω
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
-80
50
-40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 31. SWITCHING TIME AS A FUNCTION OF GATE
RESISTANCE
1.2
1.0
0.8
-40
0
40
80
120
160
ID = -250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = -250µA
1.1
1.0
0.9
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
C, CAPACITANCE (pF)
CISS
900
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
COSS
600
CRSS
300
0
-2
-4
-6
-8
VDS, DRAIN TO SOURCE VOLTAGE (V)
40
80
120
160
200
-10
FIGURE 34. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
-10
VGS , GATE TO SOURCE VOLTAGE (V)
1200
0
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 33. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
0
200
FIGURE 32. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
0.6
-80
160
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
VDD = -9.6V
-8
-6
-4
WAVEFORMS IN
DESCENDING ORDER:
ID = -10A
ID = -6A
ID = -3A
-2
0
0
3
9
6
Qg, GATE CHARGE (nC)
12
15
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 35. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2004 Fairchild Semiconductor Corporation
FIGURE 36. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
RF3S49092SM Rev. C
RF3S49092SM
Test Circuits and Waveforms (P-Channel)
VDS
tAV
L
0
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 37. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 38. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
tr
VDS
0
RL
tf
10%
10%
VGS
VDS
VDD
+
VGS
90%
90%
VGS
0
10%
DUT
RGS
50%
50%
PULSE WIDTH
90%
FIGURE 39. SWITCHING TIME TEST CIRCUIT
FIGURE 40. RESISTIVE SWITCHING WAVEFORMS
VDS
RL
VDS
Qg(TH)
0
VGS= -1V
VGS
-
Qg(-5)
+
DUT
VGS= -5V
-VGS
VDD
VGS= -10V
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 41. GATE CHARGE TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
FIGURE 42. GATE CHARGE WAVEFORMS
RF3S49092SM Rev. C
RF3S49092SM
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering
should always be less than 100oC. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
3. The maximum temperature gradient should be less than
5oC per second when changing from preheating to
soldering.
4. The peak temperature in the soldering process should be
at least 30oC higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
PSPICE Electrical Model
SUBCKT RF3S49092 2 1 3;
N-Channel Model rev 9/6/94
CA 12 8 9.77e-10
CB 15 14 9.19e-10
CIN 6 8 7.81e-10
DPLCAP
5
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
DBREAK
RDRAIN
EBREAK 11 7 17 18 14.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
ESG
+
GATE
1
16
EBREAK
VTO +
21
DBODY
MOS2
MOS1
CIN
8
S1A
12
+
17
18
6
RIN
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S1B
S2A
S2B
11
6
8
EVTO
9
20 +
18
8
LGATE RGATE
LDRAIN 2 5 1e-9
LGATE 1 9 1.233e-9
LSOURCE 3 7 0.452e-9
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 4.91e-3
RGATE 9 20 2.74
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 5e-3
RVTO 18 19 RVTOMOD 1
DRAIN
2
LDRAIN
RSOURCE
7
LSOURCE
3
SOURCE
S2A
13
8
S1B
RBREAK
15
14
13
17
18
S2B
RVTO
13
CA
CB
+
EGS
6
8
EDS
+ 14
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.3215
.MODEL DBDMOD D (IS = 7.00e-13 RS = 2.15e-2 TRS1 = 0.5e-3 TRS2 = 3.68e-6 CJO = 1.28e-9 TT = 1.8e-8)
.MODEL DBKMOD D (RS = 1.28e-1 TRS1 = 1.69e-3 TRS2 = -2.0e-6)
.MODEL DPLCAPMOD D (CJO = 0.84e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.63 KP = 11.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.15e-4 TC2 = 3.13e-7)
.MODEL RDSMOD RES (TC1 = 7.00e-4 TC2 = 5.00e-6)
.MODEL RVTOMOD RES (TC1 = -2.155e-3 TC2 = -2.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -4.05)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF= -6.05)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.72 VOFF= 4.28)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.28 VOFF= -0.72)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Options; IEEE Power Electronics Specialist Conference Records, 1991.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
RF3S49092SM
PSPICE Electrical Model
SUBCKT RF3S49092 2 1 3 ;
P-Channel Model rev 11/8/94
CA 12 8 8.75e-10
CB 15 14 8.65e-10
CIN 6 8 7.65e-10
ESG
5
+
8
6
10
DRAIN
2
LDRAIN
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD
RDRAIN
DPLCAP
EBREAK 5 11 17 18 -23.75
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1
IT 8 17 1
VTO
GATE
1
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 7.36e-3
RGATE 9 20 6.1
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 4.56e-2
RVTO 18 19 RVTOMOD 1
+
21
EVTO
9
20 +
8
18
LGATE RGATE
MOS1
11
DBREAK
CIN
8
RSOURCE
7
LSOURCE
3
SOURCE
S2A
S1A
12
MOS2
6
RIN
LDRAIN 2 5 1e-9
LGATE 1 9 1.233e-9
LSOURCE 3 7 0.452e-9
S1A
S1B
S2A
S2B
DBODY
+
EBREAK 17
18
16
13
8
S1B
RBREAK
15
14
13
17
18
S2B
RVTO
13
CA
CB
+
EGS
14
+
6
8
EDS
5
8
IT
19
VBAT
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.558
.MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8)
.MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5)
.MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.61e-4 TC2 = -1.09e-6)
.MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6)
.MODEL RVTOMOD RES (TC1 = -1.82e-3 TC2 = 1.47e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Options; IEEE Power Electronics Specialist Conference Records, 1991.
©2004 Fairchild Semiconductor Corporation
RF3S49092SM Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
FAST
ActiveArray™
FASTr™
Bottomless™ FPS™
CoolFET™
FRFET™
CROSSVOLT™ GlobalOptoisolator™
DOME™
GTO™
EcoSPARK™ HiSeC™
E2CMOS™
I2C™
EnSigna™
i-Lo™
FACT™
ImpliedDisconnect™
FACT Quiet Series™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC
Across the board. Around the world.™ OPTOPLANAR™
PACMAN™
The Power Franchise
POP™
Programmable Active Droop™
Power247™
PowerEdge™
PowerSaver™
PowerTrench
QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
µSerDes™
SILENT SWITCHER
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
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TruTranslation™
UHC™
UltraFET
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I13
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