ams AS1130B-BSST 132-led cross-plexing dr iver wi th scrol l ing funct ion Datasheet

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D atas he et
A S11 30
1 32 - L E D C r o s s -P le x in g Dr iv e r w i th sc r o l lin g F u n c tio n
2 Key Features
1 General Description
1MHz I²C-Compatible Interface
Open and Shorted LED Error Detection
The AS1130 offers a 12x11 LED-Matrix with 1/12 cycle rate. The
required lines to drive all 132 LEDs are reduced to 12 by using the
cross-plexing feature optimizing space on the PCB. The whole LEDMatrix driving 132 LEDs can be analog dimmed from 0 to 30mA in
256 steps (8 bit).
132 LEDs in Dot Matrix
Low-Power Shutdown Current
Individual 8-bit LED PWM Control
8-bit Analog Brightness Control
Additionally each of the 132 LEDs can be dimmed individually with 8bit allowing 256 steps of linear dimming. To reduce CPU usage up to
6 frames can be stored with individual time delays between frames to
play small animations automatically.
8-bit Dot Correction for optimize RGB LED Operation
Programmable IRQ pin
Scroll Function
up to 36 Frames Memory for Animations
up to 6 Frames Memory for PWM sets
Supply Voltage Range: 2.7V to 5.5V
Minimum PCB space required
Available packages:
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The AS1130 is a compact LED driver for 132 single LEDs. The
devices can be programmed via an I²C compatible interface.
The AS1130 operates from 2.7V to 5.5V and features a very low
shutdown and operational current.
The device offers a programmable IRQ pin. Via a register it can be
set on what event (CP request, Interface time out, Error-detection,
POR, End of Frame or End of Movie) the IRO is triggered.
Also hardware scroll Function is implemented in the AS1130.
The device is available in a ultrasmall 20-pin WL-CSP and an easy
to solder 28-pin SSOP package.
- 20-pin WL-CSP
- 28-pin SSOP (planned)
3 Applications
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Figure 1. AS1130 - Typical Application
The AS1130 is ideal for dot matrix displays in mobile phones, personal electronic and toys.
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Revision 1.07
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AS1130
Datasheet - P i n o u t
4 Pinout
Pin Assignments
28-pin SSOP
Pin Descriptions
Table 1. Pin Descriptions
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20-pin WL-CSP
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Figure 2. Pin Assignments (Top View)
Pin Number
20-pin WL-CSP 28-pin SSOP
A3
1, 7, 14, 22, 28
Pin Name
Description
GND
Ground
Reset Input. Pull this pin to logic low to reset all control registers (set to default
values). For normal operation pull this pin to VDD.
I²C Address. Connect to external resistor for I²C address selection. Up to 8
devices can be connected on one bus. (see Table 6 on page 12)
Serial-Data I/O. Open drain digital I/O I²C data pin.
Serial-Clock Input
Positive Supply Voltage. Connect to a +2.7V to +5.5V supply. Bypass this pin
with 10µF capacitance to GND.
Synchronization Clock Input or Output. The SYNC frequency for Input and
Output is 1MHz. For SYNC_OUT the frequency can be reduced to 32kHz.
Interrupt Request. Programmable Open drain digital Output. It can be set via
an register after which event (Interface Timeout, POK, CP_Request, Error
Detection, End of Frame or End of Movie) the pin triggers an Interrupt Request.
C3
13
D1
17
D2
D3
16
15
SDA
SCL
B3
3, 10, 18, 19, 26
VDD
12
SYNC
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D4
RSTN
11
A1, A2, A4, A5,
B1, B2, B4, B5,
C1, C2, C4, C5
25, 27, 2, 4,
23, 24, 5, 6,
21, 20, 9, 8
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D5
IRQ
CS0, CS1, CS6, CS7,
CS2, CS3, CS8, CS9, Sinks and Sources for 132 LEDs.
CS4, CS5, CS10, CS11
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AS1130
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Min
Max
Units
-0.3
7
V
-0.3
7 or
VDD + 0.3
V
Sink Current
500
mA
Segment Current
100
mA
100
mA
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Parameter
VDD to GND
All other pins to GND
Input Current (latch-up immunity)
-100
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Electrical Parameters
Norm: JEDEC 78
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Electrostatic Discharge
Electrostatic Discharge HBM
2
kV
Norm: MIL 883 E method 3015
Temperature Ranges and Storage Conditions
Junction Temperature
Storage Temperature Range
+150
ºC
-55
+125
ºC
for 20-pin WL-CSP
-55
+150
ºC
for 28-pin SSOP
+260
ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/JEDEC
J-STD-020“Moisture/Reflow Sensitivity Classification for
Non-Hermetic Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
85
%
Package Body Temperature
Humidity non-condensing
5
20-pin
WL-CSP Represents a max. floor life time of unlimited
1
Moisture Sensitive Level
28-pin
SSOP
Represents a max. floor life time of 168h
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Revision 1.07
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AS1130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7V to 5.5V, typ. values are at TAMB = +25ºC (unless otherwise specified). All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Parameter
TAMB
Operating Temperature Range
-40
TJ
Operating Junction Temperature Range
-40
VDD
Operating Supply Voltage
2.7
Operating Supply Current
Software Shutdown Supply Current
IDDFSD
Full Shutdown Supply Current
IDIGIT
All current sources turned ON
@ VDD = 5.5V
340
All current sources turned OFF
@ VDD = 5.5V
0.5
All digital inputs at VDD or GND
@ VDD = 5.5V
Unit
85
°C
125
°C
5.5
V
7
15
µA
Pin RSTN = 0V, TAMB = +25ºC
0.1
1
µA
360
mA
32
mA
Digit Drive Sink Current
1
2
Segment Drive Source Current LED
VOUT = 1.8V to VDD-400mV
28
Segment Drive Current Matching LED
30
1
%
%
Device to Device Current Matching LED
VOUT = 1.8V, VDD = 3.3V
1
ILEAK
Leakage Output Current
All current sources OFF, VOUT = 0V,
VDD = 5.5V, TAMB = +25ºC
0.005
∆ILNR
Line Regulation
VOUT = 1.8V
0.25
%/V
Load Regulation
VOUT = 1.8V to VDD-400mV
0.25
%/V
Saturation Voltage
Current = 30mA, VDD = 3.3V
200
mV
∆ILDR
VDSSAT
RDSON(N)
0.3
Resistance for NMOS
VDD0.4
Open Detection Level Threshold
Oscillator Frequency
fREFRESH
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fOSC
Display Scan Rate
tRSTN
12x11 matrix
VDD0.1
Ω
V
mV
0.9
1
1.1
MHz
0.29
0.33
0.36
kHz
ns
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1. guaranteed by design
1
µA
900
500
Reset Pulse Width Low
0.5
770
Short Detection Level Threshold
I max – Imin
I SEG = --------------------------- × 100
I max + I min
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2.
Max
mA
(Drive capability of all sources of one digit )
ISEG
∆ISEG
Typ
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IDDSSD
Min
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IDD
Conditions
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Symbol
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AS1130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Logic Inputs/Outputs Characteristics
Symbol
Parameter
Conditions
IIH, IIL
Logic Input Current
VIN = 0V or VDD
VIH
CMOS Logic High Input Voltage
VIL
CMOS Logic Low Input Voltage
∆VI
CMOS Hysteresis Voltage
Unit
1
µA
V
Mobile Logic Low Input Voltage
∆VI
Hysteresis Voltage
VOL(SDA)
SDA Output Low Voltage
ISINK = 3mA
VOL(IRQ)
IRQ Output Low Voltage
ISINK = 3mA
Sync Clock Output Low Voltage
ISINK = 1mA
Sync Clock Output High Voltage
ISOURCE = 1mA
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1.6
V
1
0.6
1
0.1
V
V
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0.4
0.4
V
0.4
V
VDD-0.4
V
400
pF
Max
Unit
1000
kHz
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_OUT)
V
V
0.3
1
VIL
VOH(SYNC
-1
Max
0.3 x VDD
Mobile Logic High Input Voltage
OUT)
Typ
0.7 x VDD
VIH
VOL(SYNC_
Min
Capacitive Load for Each Bus Line
1. available on request, See Ordering Information on page 37
Table 5. I²C Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
fSCL
SCL Frequency
100
tBUF
Bus Free Time Between STOP and START Conditions
1.3
µs
Hold Time for Repeated
START Condition
260
ns
tLOW
SCL Low Period
500
ns
tHIGH
260
ns
260
ns
tSETUPDATA
SCL High Period
Setup Time for Repeated
START Condition
Data Setup Time
tHOLDDATA
Data Hold Time
70
ns
tRISE(SCL)
SCL Rise Time
SCL Rise Time after Repeated START Condition and After
an ACK Bit
SCL Fall Time
120
ns
120
ns
120
ns
SDA Rise Time
120
ns
SDA Fall Time
120
ns
tRISE(SCL1)
tFALL(SCL)
tRISE(SDA)
tFALL(SDA)
100
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tHOLDSTART
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tSETUPSTOP STOP Condition Setup Time
tSPIKESUP
260
Pulse Width of Spike Suppressed
ns
ns
6
ns
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Note: The Min / Max values of the Timing Characteristics are guaranteed by design.
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AS1130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Figure 3. Timing Diagram
SDI
tBUF
tHOLDSTART
tHIGH
tSETUPSTOP
tSETUPSTART
SCL
STOP START
Repeated
START
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tHOLDDATA
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tR
tLOW
tSPIKESUP
tSETUPDATA
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tHOLDSTART
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AS1130
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
Figure 5. Segment Drive Current vs. Temperature
32
31
30.5
30
29.5
29
-45°C
28.5
+25°C
+85°C
28
2.7
3.1
3.5
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31.5
31
30.5
30
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Segment Drive Source Current (mA)
32
29.5
Vdd = 2.7V
29
Vdd = 3.3V
Vdd = 4.5V
28.5
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Segment Drive Source Current (mA)
Figure 4. Segment Drive Current vs. Supply Voltage
3.9
4.3
4.7
5.1
Vdd = 5.5V
28
5.5
-45
-25
-5
75
0.5
31.5
-45°C
Vdd = 3.3V
+25°C
0.4
Vdd = 4.5V
31
+85°C
Vdd = 5.5V
RNMOS (Ω)
30.5
30
29.5
29
0.3
0.2
0.1
28.5
28
0
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
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Segment Drive Source Current (mA)
55
Vdd = 2.7V
1.6
2.7
3.1
Output Voltage (V)
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3.9
4.3
4.7
5.1
5.5
Figure 9. Short Detection Level vs. Supply Voltage
0.9
-45°C
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+25°C
250
0.85
+85°C
Short Detection Level (V)
300
3.5
Supply Voltage (V)
Figure 8. Open Detection Level vs. Supply Voltage
Open Detection Level (mV)
35
Figure 7. RONNMOS vs. Supply Voltage
Figure 6. Segment Drive Current vs. Output Voltage
32
15
Temperature (ΣC)
Supply Voltage (V)
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200
150
100
50
0.8
0.75
0.7
-45°C
0.65
+25°C
+85°C
0
0.6
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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AS1130
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 11. CMOS Logic Input Levels vs. Temperature
4
4
3.5
3.5
3
2.5
2
1.5
1
Logic High
0.5
3
2.5
2
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Logic Input Voltage Level (V)
Logic Input Voltage Level (V)
Figure 10. CMOS Logic Input Levels vs. Supply Voltage
1.5
1
Logic High
0.5
Logic Low
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-45
-25
-5
Supply Voltage (V)
35
75
Figure 13. MOBILE Logic Input Levels vs. Temperature
1.5
1
0.5
Logic Input Voltage Level (V)
2
Logic High
1.5
1
0.5
Logic High
Logic Low
Logic Low
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-45
-25
Supply Voltage (V)
35
55
75
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1.1
1.05
fOSC (kHz)
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1.05
15
Figure 15. Oscillator Frequency vs. Temperature
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1.1
-5
Temperature (ΣC)
Figure 14. Oscillator Frequency vs. Supply Voltage
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fOSC (kHz)
55
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2
15
Temperature (ΣC)
Figure 12. MOBILE Logic Input Levels vs. Supply Voltage
Logic Input Voltage Level (V)
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Logic Low
0.95
1
0.95
Vdd = 2.7V
- 45°C
Vdd = 3.3V
+ 25°C
Vdd = 4.5V
+ 85°C
Vdd = 5.5V
0.9
0.9
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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-45
-25
-5
15
35
55
75
Temperature (ΣC)
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AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
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Figure 16. AS1130 - Block Diagram
Cross-Plexing Theorem
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The cross-plexing theorem is using the fact that a LED has a forward and backward direction. A LED will only glow if there is a current flowing in
forward direction. A parallel LED in backward direction will block the current flow. This effect is used in a cross-plexed matrix of LED’s.
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Each CSx pin (CS0 to CS11) can be switched to VDD via the internal current source (“high”), to GND (“low”) or not connected (“highZ”).
The mode of operation which is controlled by an internal state machine looks like following. CS0 is switched to GND and all other CSx pins (CS1
to CS11) are controlled according to the settings in the On/Off Frame and Blink & PWM registers (see Table 7 on page 14).
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Than CS1 is switched to GND and all other CSx pins (CS0 and CS2 to CS11) are controlled according to the settings in the On/Off Frame and
Blink & PWM registers.
In this manner all LEDs in the matrix are scanned and turned on/off depending on the register settings.
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AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
I²C Interface
The AS1130 supports the I²C serial bus and data transmission protocol in fast mode at 1MHz. The AS1130 operates as a slave on the I²C bus.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and
STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.
Figure 17. I²C Interface Initialization
8
9
1
8
9
0
SDA
1
1
0
AD2 AD1 AD0 R/W
D15 D14 D13 D12 D11 D10
D9
D8
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AD2, AD1 and AD0 are defined by the pin ADDR (see I²C Device Address Byte on page 12)
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SCL
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Figure 18. Bus Protocol
MSB
SDI
ACK from
Receiver
Slave Address
R/W
Direction Bit
ACK from
Receiver
1
SCL
2
6
7
8
9
ACK
START
1
2
3-7
8
9
ACK
Repeat if More Bytes Transferred
STOP or
Repeated
START
The bus protocol (as shown in Figure 18) is defined as:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is
HIGH will be interpreted as control signals.
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The bus conditions are defined as:
- Bus Not Busy. Data and clock lines remain HIGH.
- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
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- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
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- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the
HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.
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- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
- Figure 18 on page 10 details how data transfer is accomplished on the I²C bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
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AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes.
The slave returns an acknowledge bit after the slave address and each received byte.
- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the
serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
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The AS1130 can operate in the following slave modes:
- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit.
Command Byte
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- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode
the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1130 while the serial clock
is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
The AS1130 operation, (see Table 13 on page 20) is determined by a command byte (see Table 19).
Figure 19. Command Byte
MSB
6
5
4
3
2
1
LSB
A7
A6
A5
A4
A3
A2
A1
A0
Figure 20. Command and Single Data Byte received by AS1130
From Master to Slave
AS1130 Registers
From Slave to Master
S
0
Slave Address
A7
A6
R/W A
A5
A4
A3
A2
A1
A0
D7
D6
A
Command Byte
D5
D4
D3
D2
D1
D0
Data Byte
A
P
1 Byte
Acknowledge
from AS1130
0
Acknowledge
from AS1130
0
0
Autoincrement
Memory Word
Address
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Acknowledge
from AS1130
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Figure 21. Setting the Pointer to a Address Register to select a Data Register for a Read Operation
From Master to Slave
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From Slave to Master
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AS1130 Registers
0
Slave Address
A7
R/W A
Acknowledge
from AS1130
0
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A6
A5
A4
A3
A2
A1
A0
Command Byte
Acknowledge
from AS1130
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AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 22. Reading n Bytes from AS1130
Autoincrement
Memory Word
Address
From Master to Slave
From Slave to Master
Acknowledge
from AS1130
Acknowledge
from Master
0
Stop reading
Not Acknowledge
from Master
0
1
n Bytes
R/W A
Slave Address
D7
1
A
First Data Byte
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
Autoincrement
to next address
D2
P
D1
D0
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AS1130 Registers
/A
Second Data Byte
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I²C Device Address Byte
The address byte (see Figure 23) is the first byte received following the START condition from the master device.
Figure 23. I²C Device Address Byte
address:
*) can be factory set to 1
MSB
6
5
4
3
2
1
LSB
0
1
1
0*
AD2
AD1
AD0
R/W
- The bit 1, 2 and 3 of the address byte are defined through the resistor @ the device select pin ADDR (see Table 6 on page 12). A
maximum of 8 devices with the same pre-set code can be connected on the same bus at one time.
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is selected; when set to a 0
a write operation is selected.
- I²C Common address. All devices are responding on the address “0111111” if the function is enabled in the register AS1130 Config
Register (0x06) on page 25.
Bit
Bit Name
Default
I2C Address
Access
Description
R
Defines the I²C address of one device via an external resistor on pin ADDR
000: 1MΩ or floating
001: 470kΩ
010: 220kΩ
011: 100kΩ
100: 47kΩ
101: 22kΩ
110: 10kΩ
111: 4.7kΩ or GND
i2c_addr
000
Te
ch
3:1
ni
Table 6. Device Address
ca
Following the START condition, the AS1130 monitors the I²C bus, checking the device type identifier being transmitted. Upon receiving the
address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
The pin ADDR is scanned after start up (POR) and defines the address for the device. The device reacts to this address until a hardware reset
(low on pin RSTN) is performed or the power-on-reset (POR) triggers again.
Note: The internal address decoder needs 5ms to identify the address and to set up the device for this address.
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
12 - 38
AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
Initial Power-Up
On initial power-up, the AS1130 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. At
this time, all registers should be programmed for normal operation. To bring the device into normal operation the following sequence needs to be
performed.
Shutdown Mode
am
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st
il
lv
- Power-up the AS1130 (connect VDD to a source), the devices is in shutdown;
- After 5ms the address of the AS1130 is valid and the first I²C command can be send.
- Define RAM Configuration; bit mem_conf in the AS1130 Config Register (see Table 20 on page 25)
- On/Off Frames
- Blink & PWM Sets
- Dot Correction, if specified
- Define Control Register (see Table 13 on page 20)
- Current Source
- Display options
- Display picture / play movie
- To light up the LEDs set the shdn bit to ‘1’ for normal operation mode (see Table 23 on page 26).
al
id
Start-up sequence:
The AS1130 device features two different shutdown modes. A software shutdown via shutdown register (see Shutdown & Open/Short
Register Format on page 26) and a hardware shutdown via the RSTN pin.
Te
ch
ni
ca
The software shutdown disables all LED’s and stops the internal operation of the logic. A shutdown mode via the RSTN pin additionally powers
down the power-on-reset (POR) of the device. In this shutdown mode the AS1130 consumes only 100nA (typ.).
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
13 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
9 Register Description
Register Selection
Within this register the access to one of the RAM sections, the Dot Correction or to the Control register is selected. After one section is selected
this section is valid as long as an other section is selected.
Register Section
Address
Data
HEX A7 A6 A5 A4 A3 A2 A1 A0 HEX D7 D6 D5 D4 D3 D2 D1 D0
0x00
0
0
0
0
0
0
0
0
0x01
0
0
0
0
0
0
0
1
On/Off Frame 1
0x02
0
0
0
0
0
0
1
0
On/Off Frame 2
0x03
0
0
0
0
0
0
1
1
0x23
0
0
1
0
0
1
1
....
.....
On/Off Frame 35
Blink & PWM Set 0
Blink & PWM Set 1
0xFD
Blink & PWM Set 2
Blink & PWM Set 3
Blink & PWM Set 4
Blink & PWM Set 5
Dot Correction
Control Register
0
No operation
On/Off Information for
each Frame (up to 36
Frames)
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On/Off Frame 34
Description
lv
NOP
On/Off Frame 0
al
id
Table 7. Register Selection Address Map
1
1
1
1
1
1
0
1
0x24
0
0
1
0
0
1
0
0
0x40
0
1
0
0
0
0
0
0
0x41
0
1
0
0
0
0
0
1
0x42
0
1
0
0
0
0
1
0
0x43
0
1
0
0
0
0
1
1
0x44
0
1
0
0
0
1
0
0
0x45
0
1
0
0
0
1
0
1
0x80
1
0
0
0
0
0
0
0
Selection of Dot
Correction Register
0xC0
1
1
0
0
0
0
0
0
Selection of
Control Register
Blink & PWM
Information Sets (up to
6 sets)
Data Definition of the single frames
One frame consists of 2 datasets, the On/Off dataset and the Blink & PWM dataset. Where more On/Off frames can be linked to one PWM set.
Depending on the used PWM sets more or less On/Off frames can be stored inside the AS1130 (see Table 8).
Each On/Off Frame needs to define the used Blink & PWM dataset.
ca
Table 8. RAM Configuration
On/Off Frames
On/Off Frames
with Dot Correction
1
36
35
2
30
29
3
1
2
24
23
4
4
18
17
5
5
12
11
6
6
6
5
Te
ch
3
ni
RAM Configuration Blink & PWM Sets
It’s necessary to define the RAM configuration before data can be written to the frame datasets. The RAM configuration is defined in the AS1130
config register (see Table 20 on page 25) via bit 2:0 and bit 4 for Dot Correction.
Note: After a first write of data to the frames, the configuration is locked in the AS1130 config register and can be changed only after a reset
of the device. A change of the RAM configuration requires to re-write the frame datasets.
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
14 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
12x11 LED Matrix
The AS1130 is configured to control one big LED matrix.
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Figure 24. AS1130 - Dot Matrix Structure
In Table 9 it’s described which databit represents which LED in the matrix. Per default all databits are ‘0’, meaning no LED is on. A ‘1’ puts the
LED on.
ca
Each Current Segment of the LED Matrix consists of 11 LEDs, therefore 2 bytes of data are required for one Current Segment. CS0 is defined by
the two bytes with address 0x00 and 0x01 and also includes the address of the used Blink & PWM dataset for this frame.
Table 9. LEDs On/Off Frame Register Format
ni
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x00
0
0
0
0
0
0
0
0
ch
Segment
D3
LED
03
0x01
0
0
0
0
0
0
0
1
0x02
0
0
0
0
0
0
1
0
Te
0
D7 D6 D5 D4
LED LED LED LED
07
06
05
04
PWM PWM PWM
X
[2]
[1]
[0]
LED LED LED LED
17
16
15
14
0x03
0
0
0
0
0
0
1
1
X
X
X
X
X
0x04
0
0
0
0
0
1
0
0
LED
27
LED
26
LED
25
LED
24
LED
23
0x05
0
0
0
0
0
1
0
1
X
X
X
X
X
1
2
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
X
LED
13
D2
LED
02
LED
0A
LED
12
LED
1A
LED
22
LED
2A
D1
LED
01
LED
09
LED
11
LED
19
LED
21
LED
29
D0
LED
00
LED
08
LED
10
LED
18
LED
20
LED
28
15 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 9. LEDs On/Off Frame Register Format
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x06
0
0
0
0
0
1
1
0x07
0
0
0
0
0
1
0x08
0
0
0
0
1
0x09
0
0
0
0
0x0A
0
0
0
0x0B
0
0
0x0C
0
0
0x0D
0
0x0E
0
0x0F
0
0x10
0
0x11
0
0x12
0
0x13
0
0x14
0
0x15
0
0x16
0
0x17
0
D6
LED
36
D5
LED
35
D4
LED
34
D3
LED
33
D2
LED
32
D1
LED
31
D0
LED
30
1
1
X
X
X
X
X
0
0
0
LED
47
LED
46
LED
45
LED
44
LED
43
LED
3A
LED
42
LED
39
LED
41
LED
38
LED
40
1
0
0
1
X
X
X
X
X
0
1
0
1
0
LED
57
LED
56
LED
55
LED
54
LED
53
LED
4A
LED
52
LED
49
LED
51
LED
48
LED
50
0
0
1
0
1
1
X
X
X
X
0
0
1
1
0
0
LED
67
LED
66
LED
65
LED
64
LED
5A
LED
62
LED
59
LED
61
LED
58
LED
60
LED
6A
LED
72
LED
69
LED
71
LED
68
LED
70
LED
7A
LED
82
LED
79
LED
81
LED
78
LED
80
3
4
5
X
LED
63
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6
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0
D7
LED
37
lv
Segment
7
8
9
A
0
0
1
1
0
1
X
X
X
X
X
0
0
0
1
1
1
0
LED
77
LED
76
LED
75
LED
74
LED
73
0
0
0
1
1
1
1
X
X
X
X
X
0
0
1
0
0
0
0
LED
87
LED
86
LED
85
LED
84
LED
83
0
0
1
0
0
0
1
X
X
X
X
X
LED
8A
LED
89
LED
88
0
0
1
0
0
1
0
LED
97
LED
96
LED
95
LED
94
LED
93
0
0
1
0
0
1
1
X
X
X
X
X
LED
92
LED
9A
LED
91
LED
99
LED
90
LED
98
0
0
1
0
1
0
0
LED
A7
LED
A6
LED
A5
LED
A4
LED
A3
0
0
1
0
1
0
1
X
X
X
X
X
LED
A2
LED
AA
LED
A1
LED
A9
LED
A0
LED
A8
0
0
1
0
1
1
0
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
0
0
1
0
1
1
1
X
X
X
X
X
LED
B2
LED
BA
LED
B1
LED
B9
LED
B0
LED
B8
ca
B
0
ni
The Blink & PWM sets contain blink on/off and the digital PWM information for each LED in the matrix. The number of PWM datasets is flexible
according to the defined RAM configuration (see Figure 8 on page 14).
ch
In the blink register (see Table 10) every single LED can be set to blink. The blink period is set in the display option register (see Display
Option Register Format on page 24).
Table 10. LEDs Blink Frame Register Format
HEX
Address
Data
A7
A6
A5
A4
A3
A2
A1
A0
0x00
0
0
0
0
0
0
0
0x01
0
0
0
0
0
0
0x02
0
0
0
0
0
0x03
0
0
0
0
0
Te
Segment
0
D7
LED
07
D6
LED
06
D5
LED
05
D4
LED
04
D3
LED
03
0
1
X
X
X
X
X
0
1
0
LED
17
LED
16
LED
15
LED
14
LED
13
0
1
1
X
X
X
X
X
0
1
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
D2
LED
02
LED
0A
LED
12
LED
1A
D1
LED
01
LED
09
LED
11
LED
19
D0
LED
00
LED
08
LED
10
LED
18
16 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 10. LEDs Blink Frame Register Format
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x04
0
0
0
0
0
1
0
0x05
0
0
0
0
0
1
0x06
0
0
0
0
0
0x07
0
0
0
0
0x08
0
0
0
0x09
0
0
0x0A
0
0
0x0B
0
0x0C
0
0x0D
0
0x0E
0
0x0F
0
0x10
0
0x11
0
0x12
0
0x13
0
0x14
0
0x15
0
0x16
0
0
D7
LED
27
D6
LED
26
D5
LED
25
D4
LED
24
D3
LED
23
0
1
X
X
X
X
X
1
1
0
LED
37
LED
36
LED
35
LED
34
LED
33
0
1
1
1
X
X
X
X
X
0
1
0
0
0
LED
47
LED
46
LED
45
LED
44
LED
43
0
0
1
0
0
1
X
X
X
X
0
0
1
0
1
0
LED
57
LED
56
LED
55
LED
54
2
3
4
7
8
9
A
0
D0
LED
20
LED
28
LED
30
LED
39
LED
41
LED
38
LED
40
LED
4A
LED
52
LED
49
LED
51
LED
48
LED
50
0
1
0
1
1
X
X
X
X
X
LED
5A
LED
62
LED
59
LED
61
LED
58
LED
60
0
0
0
1
1
0
0
LED
67
LED
66
LED
65
LED
64
LED
63
0
0
0
1
1
0
1
X
X
X
X
X
LED
6A
LED
72
LED
69
LED
71
LED
68
LED
70
0
0
0
1
1
1
0
LED
77
LED
76
LED
75
LED
74
LED
73
0
0
0
1
1
1
1
X
X
X
X
X
LED
7A
LED
82
LED
79
LED
81
LED
78
LED
80
0
0
1
0
0
0
0
LED
87
LED
86
LED
85
LED
84
LED
83
0
0
1
0
0
0
1
X
X
X
X
X
LED
8A
LED
92
LED
89
LED
91
LED
88
LED
90
0
0
1
0
0
1
0
LED
97
LED
96
LED
95
LED
94
LED
93
0
0
1
0
0
1
1
X
X
X
X
X
LED
9A
LED
A2
LED
99
LED
A1
LED
98
LED
A0
0
0
1
0
1
0
0
LED
A7
LED
A6
LED
A5
LED
A4
LED
A3
0
0
1
0
1
0
1
X
X
X
X
X
LED
AA
LED
B2
LED
A9
LED
B1
LED
A8
LED
B0
0
0
1
0
1
1
0
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
1
0
1
1
1
X
X
X
X
X
0
0
LED
BA
LED
B9
LED
B8
Te
ch
0x17
LED
53
0
ni
B
X
0
ca
6
D1
LED
21
LED
29
LED
31
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st
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5
D2
LED
22
LED
2A
LED
32
LED
3A
LED
42
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Address
lv
Segment
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Revision 1.07
17 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
In the PWM register (see Table 11) the brightness of every single LED can be set via a 8bit PWM (255 steps).
Table 11. LEDs PWM Register Format
Address
1
lv
al
id
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
1
255 steps for intensity each single LED
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
255 steps for intensity each single LED
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
255 steps for intensity each single LED
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
0
255 steps for intensity each single LED
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
1
ch
ni
2
HEX
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
am
lc s
on A
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nt
st
il
0
LED00
LED01
LED02
LED03
LED04
LED05
LED06
LED07
LED08
LED09
LED0A
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED17
LED18
LED19
LED1A
LED20
LED21
LED22
LED23
LED24
LED25
LED26
LED27
LED28
LED29
LED2A
LED30
LED31
LED32
LED33
LED34
LED35
LED36
LED37
LED38
LED39
LED3A
Data
ca
Segment
Te
3
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Revision 1.07
18 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 11. LEDs PWM Register Format
Address
ch
Te
B
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
1
1
0
0
0
1
255 steps for intensity each single LED
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
255 steps for intensity each single LED
0
1
1
0
1
1
0
0
0
1
al
id
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
ni
A
LEDA0
LEDA1
LEDA2
LEDA3
LEDA4
LEDA5
LEDA6
LEDA7
LEDA8
LEDA9
LEDA0
LEDB0
LEDB1
LEDB2
LEDB3
LEDB4
LEDB5
LEDB6
LEDB7
LEDB8
LEDB9
LEDBA
A7 A6 A5 A4 A3 A2
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
................
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
am
lc s
on A
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nt
st
il
5
HEX
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
ca
4
LED40
LED41
LED42
LED43
LED44
LED45
LED46
LED47
LED48
LED49
LED4A
LED50
LED51
LED52
LED53
LED54
LED55
LED56
LED57
LED58
LED59
LED5A
Data
lv
Segment
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Revision 1.07
255 steps for intensity each single LED
255 steps for intensity each single LED
19 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Dot Correction Register
The AS1130 offers a feature to define a correction factor for the analog current for every segment. This correction factor is called Dot Correction
and is defined in the Dot Correction register (see Table 12). The Dot Correction Register is selected via data 128 on addr 253.
Table 12. Dot Correction Register Format
A7
0
0
0
0
0
0
0
0
0
0
0
0
Control-Registers
A6
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
D7
D6
D5 D4 D3 D2
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
8 bit Dot Correction
D1
D0
al
id
HEX
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Data
lv
0
1
2
3
4
5
6
7
8
9
A
B
Address
am
lc s
on A
te G
nt
st
il
Segment
The AS1130 device contains 14 control-registers which are listed in Table 13. All registers are selected using a 8-bit address word, and communication is done via the serial interface. Select the Control Register via the Register Selection (see Table 7 on page 14).
The Control Register is selected via data 192 on addr 253.
Table 13. Control Register Address Map
Register Name
HEX
Picture
Register Address
A7
A6
A5
A4
A3
Register Data
A2
A1
A0
D7:D0
0x00
0
0
0
0
0
0
0
0
(see Table 14 on page 21)
0x01
0
0
0
0
0
0
0
1
(see Table 15 on page 21)
0x02
0
0
0
0
0
0
1
0
(see Table 16 on page 22)
0x03
0
0
0
0
0
0
1
1
(see Table 17 on page 23)
0x04
0
0
0
0
0
1
0
0
(see Table 18 on page 24)
0x05
0
0
0
0
0
1
0
1
(see Table 19 on page 24)
0x06
0
0
0
0
0
1
1
0
(see Table 20 on page 25)
0x07
0
0
0
0
0
1
1
1
(see Table 21 on page 25)
Interrupt Frame Definition
0x08
0
0
0
0
1
0
0
0
(see Table 22 on page 26)
Shutdown & Open/Short
0x09
0
0
0
0
1
0
0
1
(see Table 23 on page 26)
I²C Interface Monitoring
Movie
Movie Mode
Frame Time / Scroll
AS1130 Config
ni
Interrupt Mask
ca
Display Option
Current Source
0
0
0
0
1
0
1
0
(see Table 24 on page 27)
0x0B
0
0
0
0
1
0
1
1
(see Table 25 on page 27)
Interrupt Status
0x0E
0
0
0
0
1
1
0
0
(see Table 26 on page 28)
AS1130 Status
0x0F
0
0
0
0
1
1
0
1
(see Table 27 on page 29)
0x20
0
0
1
0
0
0
0
0
Te
ch
0x0A
CLK Synchronization
Open LED
........................
0x37
0
0
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
1
1
(see Table 28 on page 29)
0
Revision 1.07
1
1
1
20 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Picture Register (0x00)
In this register it must be set if a picture is to display on the LED matrix or not. Also the address of the picture which should be displayed must be
set withi n this register. The default setting of this register is 0x00.
Table 14. Picture Register Format
0x00 Picture Register
7
blink_pic
5:0
Access
0
R/W
All LEDs in blink mode during display picture
0: no blink
1: all LEDs blink
0
R/W
Display Picture
0: no picture
1: display picture
display_pic
pic_addr
Bit Description
Address of Picture
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
am
lc s
on A
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nt
st
il
6
Default
al
id
Bit Name
lv
Bit
000000
R/W
Note: The display_pic bit (bit 6 in Picture Register) has lower priority than the display_movie bit (bit 6 in Movie Register).
Movie Register (0x01)
In this register it must be set if a movie is to display on the LED matrix or not. Also the address of the first frame in the movie needs be set within
this register. The default setting of this register is 0x00.
Table 15. Movie Register Format
0x01 Movie Register
Bit Name
7
blink_movie
display_movie
Te
Bit Description
R/W
All LEDs in blink mode during play movie
0: no blink
1: all LEDs blink
0
R/W
0: no movie
1: start movie
R/W
Address of first Frame in Movie
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
movie_addr
ch
5:0
Access
0
ni
6
Default
ca
Bit
000000
Note: The display_movie bit (bit 6 in Movie Register) has higher priority than the display_pic bit (bit 6 in Picture Register).
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Revision 1.07
21 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Movie Mode Register (0x02)
Within this register two movie play options can be set. Per default this register is set to 0x00.
- In scroll mode a movie can stop with the last frame of the movie or scroll endless
- The number of frames to play in a movie
0x02 Movie Mode Register
Bit Name
7
blink_en
5:0
Access
Bit Description
1
0
R/W
LED blink option
0: enabled
1: disabled
0
R/W
defines at which frame a movie stops in scroll mode
0: movie ends with 1st frame
1: movie ends with last frame
end_last
movie_frames
Number of frames played in a movie, starting at movie_addr defined in
Movie Register
000000: Play 1 Frame
000001: Play 2 Frames
000010: Play 3 Frames
000011: Play 4 Frames
000100: Play 5 Frames
000101: Play 6 Frames
...............
100000: Play 33 Frames
100001: Play 34 Frames
100010: Play 35 Frames
100011: Play 36 Frames
am
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st
il
6
Default
lv
Bit
al
id
Table 16. Movie Mode Register Format
000000
R/W
Te
ch
ni
ca
1. Disable blink option overrides any blink definition in PWM data definition or global blink definition in picture register & movie register bit 7.
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Revision 1.07
22 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Frame Time/Scroll Register (0x03)
Every single frame in a movie is displayed for a certain time before the next frame is displayed. This time can be set within this register with 4
bits. The stated values in Table 17 are typical values.
Also the scroll options are set within this register. Per default this register is set to 0x00.
Table 17. Frame Time/Scroll Register Format
Bit Name
7
frame_fad
5
4
3:0
Access
0
R/W
Fade Frame Option (not available in 5 LED block configuration)
0: no fading
1: fading of a Frame
0
R/W
Scroll Direction
0: scroll to right
1: scroll to left
0
R/W
Define block size for scrolling
0: scroll in full matrix
1: scroll in 5 LED blocks (current sources split in 2 sections, See Scroll
Function on page 31)
0
R/W
Scroll digits at play movie
0: no scrolling
1: scrolling digits at play movie
R/W
Delay between frame change in a movie
0000: play frame only one time
0001: 32.5ms
0010: 65ms
0011: 97.5ms
0100: 130ms
0101: 162.5ms
0110: 195ms
0111: 227.5ms
1000: 260ms
1001: 292.5ms
1010: 325ms
1011: 357.5ms
1100: 390ms
1101: 422.5ms
1110: 455ms
1111: 487.5ms
scroll_dir
block_size
Enable Scrolling
frame_delay
Bit Description
am
lc s
on A
te G
nt
st
il
6
Default
lv
Bit
al
id
0x03 Frame Time/Scroll Register
Te
ch
ni
ca
0000
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Revision 1.07
23 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Display Option Register (0x04)
In this register the number of loops in a movie are defined. With the scan-limit it can be controlled how many digits are displayed in each matrix.
When all 12 digits in the matrix are displayed, the display scan rate is 430Hz (typ.). If the number of digits to display is reduced, the update frequency is increased. Per default this register is set to 0x20.
Table 18. Display Option Register Format
Bit Name
7:5
loops
Default
4
blink_freq
0
3:0
scan_limit
R/W
Bit Description
Number of loops played in one movie
000: not valid
001: 1 loop
010: 2 loops
011: 3 loops
100: 4 loops
101: 5 loops
110: 6 loops
111: play movie endless (needs to be reset to 0-6 to stop movie); for scroll
endless set bit end_last = ‘0’
am
lc s
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nt
st
il
001
Access
lv
Bit
al
id
0x04 Display Option Register
0000
R/W
Blink period
0: 1.5s
1: 3s
R/W
Number of displayed segments in one frame (scan-limit)
0000: CS0
0001: CS0 to CS1
0010: CS0 to CS2
0011: CS0 to CS3
0100: CS0 to CS4
0101: CS0 to CS5
0110: CS0 to CS6
0111: CS0 to CS7
1000: CS0 to CS8
1001: CS0 to CS9
1010: CS0 to CS10
1011: CS0 to CS11
ca
Note: To stop a movie in play endless mode, bits D7:D5 have to be set to a value between 000 to 110.
Current Source Register (0x05)
ni
Within this registers the current for every single LED can be set from 0mA to 30mA in 255 steps (8 bits). Per default this register is set to 0x00.
ch
Table 19. Current Source Register Format
Bit Name
7:0
current
Te
Bit
0x05 Current Source Register
Default
Access
00000000
R/W
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Bit Description
00000000: 0mA
..........
11111111: 30mA
Revision 1.07
24 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
AS1130 Config Register (0x06)
Per default this register is set to 0x00.
Table 20. AS1130 Config Register Format
0x06 AS1130 Config Register
Bit Name
7
low_vdd_rst
6
Default
Access
Bit Description
0
R/W
0: at the end of a movie or a display picture the “low_VDD” flag is not
changed
1: at the end of a movie or a display picture, the “low_VDD” flag is set to “0”
R/W
This bit indicates the supply status
0: if low_VDD is detected, the Interrupt Status Register will be updated
accordingly and pin IRQ is triggered.
1: the low_VDD bit is directly mapped to the pin IRQ. This can be used to
control an external DC/DC Converter or Charge Pump. In this case pin IRQ
can’t be used for interrupt functionality, the Interrupt Status REgister will be
updated accordingly.
low_vdd_stat
led_error_correction
R/W
This bit defines the LED open handling
0: open LEDs which are detected at LED open test, are NOT disabled
1: open LEDs which are detected at LED open test, are disabled
0
R/W
Analog current DotCorrection
0: disabled
1: enabled
0
R/W
I²C Common Address
0: disabled
1: enabled (all AS1130 are reacting on the same address “0111111”)
R/W
Define Memory Configuration (see Table 8 on page 14)
000: Invalid Configuration (default value)
001: RAM Configuration 1
010: RAM Configuration 2
011: RAM Configuration 3
100: RAM Configuration 4
101: RAM Configuration 5
110: RAM Configuration 6
am
lc s
on A
te G
nt
st
il
5
lv
0
0
4
3
2:0
dot_corr
1
common_addr
mem_conf
al
id
Bit
1
000
ca
1. This configuration is locked after the first write access to ON/OFF, PWM od DotCorrection data section. Unlock can be performed only by
a reset of the device.
Interrupt Mask Register (0x07)
ni
Per default this register is set to 0x20.
ch
Table 21. Interrupt Mask Register Format
Bit Name
7
selected_pic
Te
Bit
6
5
Default
0x07 Interrupt Mask Register
Access
Bit Description
0
R/W
IRQ pin triggers if defined Frame is displayed (see Interrupt Frame
Definition Register (0x08) on page 26)
0: disabled
1: enabled
0
R/W
IRQ pin triggers if the I²C watchdog triggers
0: disabled
1: enabled
1
R/W
IRQ pin triggers if POR is active
0: disabled
1: enabled
watchdog
por
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Revision 1.07
25 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 21. Interrupt Mask Register Format
0x07 Interrupt Mask Register
4
overtemp
2
1
0
Access
0
R/W
IRQ pin triggers if the over temperature limit is reached
0: disabled
1: enabled
0
R/W
IRQ pin triggers if VDD is to low for used LEDs (low_VDD flag)
0: disabled
1: enabled
0
R/W
IRQ pin triggers if an error on the open test occurs
0: disabled
1: enabled
0
R/W
IRQ pin triggers if an error on the short test occurs
0: disabled
1: enabled
low_vdd
open_err
short_err
movie_fin
Bit Description
IRQ pin triggers if a movie is finished
0: disabled
1: enabled
am
lc s
on A
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nt
st
il
3
Default
al
id
Bit Name
lv
Bit
0
R/W
Interrupt Frame Definition Register (0x08)
Per default this register is set to 0x3F.
Table 22. Interrupt Frame Definition Register Format
0x08 Interrupt Frame Definition Register
Bit
Bit Name
7:6
-
5:0
last_frame
Default
Access
00
n/a
R/W
ni
ca
111111
Bit Description
After this frame is displayed the last time (depending on the number of loops
played in a movie) an interrupt will be triggered.
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
..................
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
ch
Shutdown & Open/Short Register (0x09)
Per default this register is set to 0x02.
Te
Table 23. Shutdown & Open/Short Register Format
Bit
0x09 Shutdown & Open/Short Register
Bit Name
Default
Access
7:5
-
000
n/a
4
test_all
0
R/W
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
Bit Description
The LED open/short test is performed on all LED locations
0: disabled
1: enabled
Revision 1.07
26 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 23. Shutdown & Open/Short Register Format
0x09 Shutdown & Open/Short Register
3
auto_test
2
Default
Access
0
R/W
The LED open/short test is automatically started at display picture/frame
0: disabled
1: enabled
0
R/W
The LED open/short test is started manually
0: disabled
1: enabled
1
R/W
0: initialise control logic (internal State machine is reset again)
1: normal operation
0
R/W
0: device is in shutdown mode (Outputs are turned off, internal State
machine stops)
1: normal operation
manual_test
1
init
0
shdn
Bit Description
al
id
Bit Name
lv
Bit
am
lc s
on A
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nt
st
il
I²C Interface Monitoring Register (0x0A)
This register is used to monitor the activity on the I²C bus. If a deadlock situation occurs (e.g. the bus SDA pin is pulled to low and no communication is possible) the chip will reset the I²C interface and the master is able to start the communication again.
The time window for the reset of the interface of the AS1130 can bes set via 7 bits from 256µs to 33ms. The default setting of this register is
0xFF.
Table 24. I²C Interface Monitoring Register Format
0x0A I²C Interface Monitoring Register
Bit
Bit Name
7
-
6:1
Time out window
0
i2c_monitor
Default
Access
1
n/a
Bit Description
11111
R/W
Definition of the Time out window (0 to 127 => 1 to 128x256µs)
0000000: 256µs
........
1111111: 32.7ms
1
R/W
0: I²C monitoring off
1: I²C monitoring on
CLK Synchronization Register (0x0B)
ca
The default setting of this register is 0x00.
Table 25. CLK Synchronization Register Format
Bit
7:4
Bit Name
Default
Access
-
0000
n/a
clk_out
00
Te
ch
3:2
ni
0x0B CLK Synchronization Register
www.austriamicrosystems.com/LED-Driver-ICs/AS1130
R/W
Bit Description
Adjustable clock out frequency
00: 1MHz
01: 500kHz
10: 125kHz
11: 32kHz
Revision 1.07
27 - 38
AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 25. CLK Synchronization Register Format
0x0B CLK Synchronization Register
Bit
Bit Name
1
sync_out
Default
Access
Bit Description
The internal oscillator is used as system-clk. The selected clk frequency is
0
R/W
sync_in
available on pin D4 for synchronization. (Output)
0: disabled
1: enabled
al
id
1
0
1
0
R/W
The internal oscillator is disabled. Pin D4 is used as clk input for system-clk.
0: disabled
1: enabled
lv
1. CLK synchronization is done via the SYNC pin. Only one option can be activated (Input or Output).
Interrupt Status Register (0x0E)
am
lc s
on A
te G
nt
st
il
This is a read only register. Within this register the cause of an interrupt can be read out. After power up or a reset the default setting of this register is 0x20. A read out command will set this register to default and the IRQ pin will be released again.
Table 26. Interrupt Status Register Format
0x0E Interrupt Status Register
Bit
Bit Name
7
frame_int
i2c_int
5
por_int
4
overtemp_int
3
low_vdd_int
2
open_int
1
short_int
0
movie_int
Access
0
R
0: no interrupt
1: defined Frame is displayed (see Interrupt Frame Definition
Register (0x08) on page 26)
0
R
0: no interrupt
1: I²C watchdog reports a deadlock on the interface
1
R
0: no interrupt
1: POR was triggered
0
R
0: no interrupt
1: over temperature limit is reached
0
R
0: no interrupt
1: VDD is too low to drive requested current through the LEDs
0
R
0: no interrupt
1: error on open test
0
R
0: no interrupt
1: error on short test
0
R
0: no interrupt
1: play movie is finished
Bit Description
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Default
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Revision 1.07
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AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
AS1130 Status Register (0x0F)
This is a read only register. From this register the actual status of the AS1130 can be read out. The default setting of this register is 0x00.
Table 27. AS1130 Status Register Format
0x0F AS1130 Status Register
7:2
frame_on
Default
Access
1
movie_on
0
test_on
Actual displayed frame
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
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000000
Bit Description
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Bit
0
R
0: no movie
1: movie playing
0
R
0: no test is running
1: open/short test ongoing
AS1130 Open LED Register (0x20 to 0x37)
This is a read only register. From this register the LED’s which failed with an open error can be read out. A ‘1’ indicates LED okay, a ‘0’ stands for
LED open. If a LED, which is physically not connected to the device is tested, the Open LED test will return a ‘0’.
Table 28. Open LED Register Format
Address
HEX
A7
0x20
0
0x21
0
0x22
0
0x23
0
0x24
0
0
A4
A3
A2
A1
A0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
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2
A5
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Data
A6
0
D7
LED
07
D6
LED
06
D5
LED
05
D4
LED
04
D3
LED
03
0
1
0
0
0
0
0
0
1
0
LED
17
LED
16
LED
15
LED
14
LED
13
0
0
1
1
0
0
0
0
0
0
0
1
0
0
LED
27
LED
26
LED
25
LED
24
LED
23
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Segment
0x25
0
0
1
0
0
1
0
1
0
0
0
0
0
0x26
0
0
1
0
0
1
1
0
LED
37
LED
36
LED
35
LED
34
LED
33
0x27
0
0
1
0
0
1
1
1
0
0
0
0
0
0x28
0
0
1
0
1
0
0
0
LED
47
LED
46
LED
45
LED
44
LED
43
0x29
0
0
1
0
1
0
0
1
0
0
0
0
0
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Revision 1.07
D2
LED
02
LED
0A
LED
12
LED
1A
LED
22
LED
2A
LED
32
D1
LED
01
LED
09
LED
11
LED
19
LED
21
LED
29
LED
31
D0
LED
00
LED
08
LED
10
LED
18
LED
20
LED
28
LED
30
LED
3A
LED
42
LED
39
LED
41
LED
38
LED
40
LED
4A
LED
49
LED
48
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AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 28. Open LED Register Format
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x2A
0
0
1
0
1
0
1
0x2B
0
0
1
0
1
0
0x2C
0
0
1
0
1
0x2D
0
0
1
0
0x2E
0
0
1
0x2F
0
0
0x30
0
0
0x31
0
0x32
0
0x33
0
0x34
0
0x35
0
0x36
0
0x37
0
D6
LED
56
D5
LED
55
D4
LED
54
D3
LED
53
D2
LED
52
D1
LED
51
D0
LED
50
1
1
0
0
0
0
0
1
0
0
LED
67
LED
66
LED
65
LED
64
LED
63
LED
5A
LED
62
LED
59
LED
61
LED
58
LED
60
1
1
0
1
0
0
0
0
0
0
1
1
1
0
LED
77
LED
76
LED
75
LED
74
LED
73
LED
6A
LED
72
LED
69
LED
71
LED
68
LED
70
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
LED
87
LED
86
LED
85
LED
84
LED
7A
LED
82
LED
79
LED
81
LED
78
LED
80
LED
8A
LED
92
LED
89
LED
91
LED
88
LED
90
LED
9A
LED
A2
LED
99
LED
A1
LED
98
LED
A0
5
6
8
9
A
LED
83
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
LED
97
LED
96
LED
95
LED
94
LED
93
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
LED
A7
LED
A6
LED
A5
LED
A4
LED
A3
0
1
1
0
1
0
1
0
0
0
0
0
LED
AA
LED
A9
LED
A8
0
1
1
0
1
1
0
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
0
1
1
0
1
1
1
0
0
0
0
0
LED
B2
LED
BA
LED
B1
LED
B9
LED
B0
LED
B8
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LED
57
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Segment
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Revision 1.07
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AS1130
Datasheet - Ty p i c a l A p p l i c a t i o n
10 Typical Application
Scroll Function
The AS1130 offers a feature for scrolling a picture through the matrix without the need of communication via a µP. The scrolling can be done in
the whole matrix (11x12) or optimized for a ticker in a 5x24 Matrix (see Figure 25).
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Figure 25. LED configuration for 5LED block scroll function
In the movie display mode the frame is shown in the matrix at once. On the contrary in the scroll function the frame is shifted through the matrix
segment after segment (CS0 to CS1 to CS2 to CS3 ......).
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Figure 26. Scrolling
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AS1130
Datasheet - Ty p i c a l A p p l i c a t i o n
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Figure 27. Ticker Application with 5x96 LED Matrix
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Revision 1.07
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AS1130
Datasheet - Ty p i c a l A p p l i c a t i o n
LED Current Calculation
The current through a LED in the matrix is set via three registers (Current Source Register, Dot Correction and PWM). The resulting current
through the single LED can be calculated as shown in the following.
First it’s necessary to calculate the time how long one LED will be ON.
PWM
t LEDon = -------------f OSC
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(EQ 1)
Where:
tLEDon . . . . time where the LED is ON
PWM . . . value set in the register (0 - 256), (see Table 11 on page 18)
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fOSC . . . frequency set in the CLK Synchronization Register, (see Table 25 on page 27)
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The refresh rate is defined by the scan-limit and fOSC.
( scanlimit + 1 ) × 256
t REFRESH = -----------------------------------------------------f OSC
Where:
(EQ 2)
tREFRESH . . . time needed to refresh the matrix
scan-limit . . . is set via the Display Option Register (0 - 11), (see Table 18 on page 24)
fOSC . . . frequency set in the CLK Synchronization Register, (see Table 25 on page 27)
With the LED on-time and the refresh rate an average LED ON factor can be calculated.
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t LEDon
PWM
LEDon avg = ------------------------ = -----------------------------------------------------t REFRESH
( scanlimit + 1 ) × 256
(EQ 3)
The resulting current is then the Segment Current (set in the Current Source Register) times the average LED ON factor.
Where:
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PWM
I LEDavg = I SEG × LEDon avg = I SEG × -----------------------------------------------------( scanlimit + 1 ) × 256
(EQ 4)
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ISEG . . . Segment Current set via register (see Table 19 on page 24)
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Example:
Assume that following conditions are set in the registers: PWM = 256, scan-limit = 5 (half filled matrix, 66 LEDs), ISEG = 30mA
256
I LEDavg = 30mA × -------------------------------- = 5mA
( 5 + 1 ) × 256
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Revision 1.07
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AS1130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
11 Package Drawings and Markings
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Figure 28. 20-pin WL-CSP Marking
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Figure 29. 28-pin SSOP Marking
Table 29. Packaging Code YYWWRZZ
YY
WW
manufacturing week
R
ZZ
plant identifier
free choice / traceability code
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last two digits of the current year
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AS1130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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Figure 30. 20-pin WL-CSP Package
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AS1130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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Figure 31. 28-pin SSOP Package
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Revision 1.07
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AS1130
Datasheet - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 30.
Table 30. Ordering Information
Logic Levels
AS1130-BSST
AS1130
CMOS
Address
0x30 - 0x37
AS1130B-BSST*
AS1130B
Mobile
AS1130C-BSST*
AS1130C
CMOS
0x38 - 0x3E
AS1130D-BSST*
AS1130D
Mobile
AS1130-BWLT
AS1130
CMOS
0x30 - 0x37
AS1130B
AS1130C-BWLT*
tbd
Mobile
CMOS
0x38 - 0x3E
AS1130D-BWLT*
*) on request
tbd
Delivery Form
Package
Tape and Reel
Tape and Reel
28-pin SSOP
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
20-pin WL-CSP
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AS1130B-BWLT*
Description
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
132-LED Cross-Plexing Driver with
scrolling Function
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Marking
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Ordering Code
Mobile
Tape and Reel
Tape and Reel
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
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For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.07
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AS1130
Datasheet
Copyrights
Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the
freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the
manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
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Headquarters
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austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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