16-Bit, 100 kSPS PulSAR Differential ADC in MSOP AD7684 FEATURES Serial interface SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible Power Dissipation : 4 mW @ 5 V, 1.5 mW @ 2.7 V, 150 µW @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead MSOP package APPLICATION DIAGRAM 0.5V TO VDD 2.7V TO 5.5V VREF 0 REF +IN –IN VREF VDD DCLOCK AD7684 GND DOUT 3-WIRE SPI INTERFACE CS 04302-001 16-bit resolution with no missing codes Throughput: 100 kSPS INL: ±1 LSB typ, ±3 LSB max True differential analog input range: ±VREF 0 V to VREF with VREF up to VDD on both inputs Single-supply operation: 2.7 V to 5.5 V 0 Figure 1. APPLICATIONS Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADCs Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control Type True Differential Pseudo Differential/Unipolar Unipolar 100 kSPS AD7684 AD7683 250 kSPS AD7687 AD7685 AD7694 500 kSPS AD7688 AD7686 AD7680 GENERAL DESCRIPTION The AD7684 is a 16-bit, charge redistribution, successive approximation, PulSAR™ analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CS falling edge, it samples the voltage difference between +IN and –IN pins. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7684 is housed in an 8-lead MSOP package, with an operating temperature specified from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7684 TABLE OF CONTENTS Specifications..................................................................................... 3 Typical Connection Diagram ................................................... 13 Timing Specifications....................................................................... 5 Analog Input ............................................................................... 13 Absolute Maximum Ratings............................................................ 6 Driver Amplifier Choice............................................................ 13 ESD Caution.................................................................................. 6 Voltage Reference Input ............................................................ 14 Pin Configuration and Function Descriptions............................. 7 Power Supply............................................................................... 14 Terminology ...................................................................................... 8 Digital Interface.......................................................................... 14 Typical Performance Characteristics ............................................. 9 Layout .......................................................................................... 14 Application Information................................................................ 12 Evaluating the AD7684’s Performance .................................... 14 Circuit Information.................................................................... 12 Outline Dimensions ....................................................................... 15 Converter Operation.................................................................. 12 Ordering Guide .......................................................................... 15 Transfer Functions...................................................................... 12 REVISION HISTORY 10/04—Initial Version: Revision 0 Rev. 0 | Page 2 of 16 AD7684 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DCLOCK Frequency REFERENCE Voltage Range Load Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance DIGITAL OUTPUTS Data Format VOH VOL POWER SUPPLIES VDD VDD Range1 Operating Current Standby Current2, 3 Power Dissipation TEMPERATURE RANGE Specified Performance 1 2 3 Conditions Min 16 +IN − (–IN) +IN, –IN fIN = 100 kHz Acquisition phase −VREF −0.1 Typ Max Unit Bits +VREF VDD + 0.1 V V dB nA 65 1 See the Analog Input section. 0 0 0.5 100 kSPS, V+IN = V−IN = VREF/2 = 2.5 V 10 100 2.9 µS kSPS MHz VDD + 0.3 V µA 0.3 × VDD VDD + 0.3 +1 +1 V V µA µA pF 50 −0.3 0.7 × VDD −1 −1 5 ISOURCE = −500 µA ISINK = +500 µA Specified performance 100 kSPS throughput VDD = 5 V VDD = 2.7 V VDD = 5 V, 25°C VDD = 5 V VDD = 2.7 V VDD = 2.7 V, 10 kSPS throughput Serial 16 Bits Twos Complement. VDD − 0.3 0.4 V V 2.7 2.0 5.5 5.5 V V 50 6 µA µA nA mW mW µW +85 °C 800 560 1 4 1.5 150 2 TMIN to TMAX −40 See the Typical Performance Characteristics section for more information. With all digital inputs forced to VDD or GND, as required. During acquisition phase. Rev. 0 | Page 3 of 16 AD7684 VDD = 5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error1, TMIN to TMAX Gain Error Temperature Drift Zero Error , TMIN to TMAX Zero Temperature Drift Power Supply Sensitivity Conditions VDD = 5 V ±5% AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz Min 16 −3 1 1 2 88 88 Typ Max ±1 0.5 ±2 ±0.3 ±0.4 ±0.3 ±0.05 +3 ±15 ±1.6 Unit Bits LSB LSB LSB ppm/°C mV ppm/°C LSB dB2 dB dB dB Bits 91 −108 −106 91 14.8 See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. VDD = 2.7 V; VREF = 2.5 V; TA = –40°C to +85°C, unless otherwise noted. Table 4. Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error1, TMIN to TMAX Gain Error Temperature Drift Zero Error , TMIN to TMAX Zero Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits Conditions Min Typ Max +3 VDD = 2.7 V ±5% ±1 0.85 ±2 ±0.3 ±0.7 ±0.3 ±0.05 fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz 86 −100 −98 86 14 16 −3 1 1 2 ±15 ±3.5 Unit Bits LSB LSB LSB ppm/°C mV ppm/°C LSB dB2 dB dB dB Bits See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. 0 | Page 4 of 16 AD7684 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter Throughput Rate CS Falling to DCLOCK Low CS Falling to DCLOCK Rising DCLOCK Falling to Data Remains Valid CS Rising Edge to DOUT High Impedance DCLOCK Falling to Data Valid Acquisition Time DOUT Fall Time DOUT Rise Time Symbol tCYC tCSD tSUCS tHDO tDIS tEN tACQ tF tR tCYC Min Typ 20 5 Max 100 0 16 14 16 100 50 11 11 25 25 400 COMPLETE CYCLE CS tSUCS tACQ POWER DOWN 1 4 5 tCSD DOUT tEN Hi-Z 0 tDIS tHDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) NOTE: A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING. Figure 2. Serial Interface Timing Rev. 0 | Page 5 of 16 0 Hi-Z 04302-002 DCLOCK Unit kHz µs ns ns ns ns ns ns ns AD7684 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Inputs +IN1, –IN1 REF Supply Voltages VDD to GND Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) 1 Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −65°C to +150°C 150°C 200°C/W 44°C/W 215°C 220°C See the Analog Input section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500µA IOL TO DOUT 1.4V 500µA 04302-003 CL 100pF IOH Figure 3. Load Circuit for Digital Interface Timing 2V 0.8V tDELAY 2V 0.8V 04302-004 tDELAY 2V 0.8V Figure 4. Voltage Reference Levels for Timing 90% 10% tR tF Figure 5. DOUT Rise and Fall Timing Rev. 0 | Page 6 of 16 04302-005 DOUT AD7684 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7684 +IN 2 8 VDD 7 DCLOCK TOP VIEW 6 DOUT (Not to Scale) GND 4 5 CS –IN 3 04302-006 REF 1 Figure 6. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 4 5 +IN –IN GND CS AI AI P DI 6 7 8 DOUT DCLOCK VDD DO DI P 1 Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a ceramic capacitor of a few µF. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Chip Select Input. On its falling edge, it initiates the conversions. The part returns in shutdown mode as soon as the conversion is done. It also enables DOUT. When high, DOUT is high impedance. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. Power Supply. AI = Analog Input; DI = Digital Input; DO = Digital Output; and P = Power. Rev. 0 | Page 7 of 16 AD7684 TERMINOLOGY Integral Nonlinearity Error (INL) Effective Number of Bits (ENOB) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 21). ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula Differential Nonlinearity Error (DNL) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, i.e., 0 V, and the actual voltage producing the midscale output code, i.e., 0 LSB. The first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ½ LSB above the nominal negative full scale (−4.999924 V for the ±5 V range). The last transition (from 011…10 to 011…11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999771 V for the ±5 V range.) The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the idea levels. SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. and is expressed in bits. Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Gain Error Spurious-Free Dynamic Range (SFDR) ENOB = (S /[N + D]dB − 1.76) / 6.02 S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function was applied. Rev. 0 | Page 8 of 16 AD7684 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 POSITIVE DNL = +0.9LSB NEGATIVE DNL = –0.45LSB 2 1 1 DNL (LSB) 2 0 –1 –1 –2 –2 –3 0 16384 32768 49152 04302-010 0 04302-017 INL (LSB) POSITIVE INL = +0.83LSB NEGATIVE INL = –1.07LSB –3 0 65536 16384 32768 49152 CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 120000 150000 VDD = REF = 5V VDD = REF = 2.5V 123872 94794 100000 80000 100000 COUNTS COUNTS 65536 CODE 60000 40000 50000 18557 17388 151 0 182 0 0 0003 0004 0005 0 FFFD FFFE FFFF 0000 0001 0002 4150 3050 0 0 0 FFFB FFFC FFFD FFFE FFFF CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Center 0 0 16384 POINT FFT VDD = REF = 5V fS = 100kSPS fIN = 20.43kHz –60 –80 –100 –120 04302-009 –140 –160 –180 0 10 20 30 40 50 –40 –60 –80 –100 –120 –140 04302-012 –40 16384 POINT FFT VDD = REF = 2.5V fS = 100kSPS fIN = 20.43kHz –20 AMPLITUDE (dB of Full Scale) –20 AMPLITUDE (dB of Full Scale) 04302-011 0 04302-008 20000 –160 –180 0 10 20 30 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. FFT Plot Rev. 0 | Page 9 of 16 40 50 AD7684 1200 17 100 fS = 100kSPS SNR SNR, S/[N+D] (dB) S/[N+D] 15 90 ENOB ENOB (Bits) 16 95 14 85 OPERATING CURRENT (µA) 1000 800 600 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 13 5.5 04302-016 80 04302-013 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) SUPPLY (V) Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage Figure 16. Operating Current vs. Supply 100 5.5 1000 VREF = 5V, –10dB VDD = 5V 95 OPERATING CURRENT (µA) 800 S/[N+D](dB) VREF = 2.5V, –1dB 85 80 600 400 200 04302-014 75 70 0 50 100 150 VDD = 2.7V 04302-017 VREF = 5V, –1dB 90 0 200 –55 –35 –15 5 25 45 65 85 105 FREQUENCY (kHz) TEMPERATURE (°C) Figure 14. S/[N + D] vs. Frequency Figure 17. Operating Current vs. Temperature –80 125 1000 VREF = 2.5V, –1dB –95 –100 VREF = 5V, –1dB –105 –110 04302-015 THD (dB) –90 –115 0 40 80 120 160 200 750 500 250 04302-018 POWER-DOWN CURRENT (µA) –85 0 –55 –35 –15 5 25 45 65 85 105 FREQUENCY (kHz) TEMPERATURE (°C) Figure 15. THD, ENOB vs. Frequency Figure 18. Power-Down Current vs. Temperature Rev. 0 | Page 10 of 16 125 AD7684 5 4 3 2 ZERO ERROR 1 0 –1 –2 GAIN ERROR –3 –4 04302-019 ZERO ERROR, FULL-SCALE ERROR (LSB) 6 –5 –6 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 19. Offset and Gain Error vs. Temperature Rev. 0 | Page 11 of 16 AD7684 APPLICATION INFORMATION +IN SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 04302-020 CNV –IN Figure 20. ADC Simplified Schematic CIRCUIT INFORMATION The AD7684 is a low power, single-supply, 16-bit ADC using a successive approximation architecture. It is capable of converting 100,000 samples per second (100 kSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes typically 150 µW with a 2.7 V supply, ideal for battery-powered applications. into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code. TRANSFER FUNCTIONS The ideal transfer function for the AD7684 is shown in Figure 21 and Table 8. ADC CODE (TWOS COMPLEMENT) The AD7684 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. The AD7684 is specified from 2.7 V to 5.5 V. It is housed in a 8-lead MSOP package. CONVERTER OPERATION The AD7684 is a successive approximation ADC based on a charge redistribution DAC. Figure 20 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. 011...111 011...110 011...101 100...010 100...000 –FS –FS + 1 LSB +FS – 1 LSB +FS – 1.5 LSB –FS + 0.5 LSB During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the +IN and −IN inputs. When the acquisition phase is complete and the CS input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs, +IN and −IN, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4...VREF/65536). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back ANALOG INPUT 04302-021 100...001 Figure 21. ADC Ideal Transfer Function Table 8. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 Analog Input VREF = 5 V 4.999847 V 152.6 µV 0V –152.6 µV –4.999847 V –5 V Digital Output Code Hexa 7FFF1 0001 0000 FFFF 8001 80002 This is also the code for an overranged analog input (V+IN – V–IN above VREF – VGND). 2 This is also the code for an underranged analog input (V+IN – V–IN below −VREF + VGND). Rev. 0 | Page 12 of 16 AD7684 (NOTE 1) 2.7V TO 5.25V REF 100nF 2.2µF TO 10µF (NOTE 2) 33Ω REF 0 TO VREF VDD +IN 2.7nF (NOTE 3) DCLOCK AD7684 (NOTE 4) DOUT –IN 33Ω 3-WIRE INTERFACE CS GND VREF TO 0 2.7nF (NOTE 3) 04302-022 (NOTE 4) NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION. NOTE 2: CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION. NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 22. Typical Application Diagram TYPICAL CONNECTION DIAGRAM Figure 22 shows an example of the recommended application diagram for the AD7684. ANALOG INPUT Figure 23 shows an equivalent circuit of the input structure of the AD7684. The two diodes, D1 and D2, provide ESD protection for the analog inputs, +IN and −IN. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this will cause these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7684 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. DRIVER AMPLIFIER CHOICE Although the AD7684 is easy to drive, the driver amplifier needs to meet the following requirements: • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7684. Note that the AD7684 has a noise much lower than most other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7684 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. • For ac applications, the driver needs to have a THD performance suitable to that of the AD7684. Figure 15 shows the THD vs. frequency that the driver should exceed. • For multichannel multiplexed applications, the driver amplifier and the AD7684 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. VDD D1 +IN OR –IN CIN D2 04302-023 CPIN RIN GND Figure 23. Equivalent Analog Input Circuit This analog input structure allows the sampling of the differential signal between +IN and −IN. By using this differential input, small signals common to both inputs are rejected. For instance, by using −IN to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input +IN can be modeled as a parallel combination of the capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 Ω and is a lumped component made up of some serial resistors and the on-resistance of the Rev. 0 | Page 13 of 16 AD7684 A falling edge on CS initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked MSB first by subsequent DCLOCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. Table 9. Recommended Driver Amplifiers Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031 Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low power Small, low power, and low frequency High frequency and low power CONVERT DIGITAL HOST CS AD7684 The AD7684 voltage reference input, REF, has a dynamic input impedance. It should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (e.g., an unbuffered reference voltage like the low temperature drift ADR43x reference or a reference buffer using the AD8031 or the AD8605), a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially DNL. POWER SUPPLY The AD7684 powers down automatically at the end of each conversion phase and therefore the power scales linearly with the sampling rate, as shown in Figure 24. This makes the part ideal for low sampling rates (even of a few Hz) and low batterypowered applications. DCLOCK DOUT DATA IN CLK 04302-025 VOLTAGE REFERENCE INPUT Figure 25. Connection Diagram LAYOUT The printed circuit board housing the AD7684 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7684 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7684 is used as a shield. Fast switching signals, such as CS or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog section. In such a case, it should be joined underneath the AD7684. 1000 The AD7684 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low impedance traces. VDD = 5V 10 VDD = 2.7V 1 0.1 04302-024 OPERATING CURRENT (µA) 100 0.01 10 100 1k 10k 100k Finally, the power supply, VDD, of the AD7684 should be decoupled with a ceramic capacitor, typically 100 nF, and placed close to the AD7684. It should be connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. EVALUATING THE AD7684’S PERFORMANCE SAMPLING RATE (SPS) Figure 24. Operating Current vs. Sampling Rate DIGITAL INTERFACE The AD7684 is compatible with SPI, QSPI, digital hosts, and DSPs (e.g., Blackfin® ADSP-BF53x or ADSP-219x). The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2. Other recommended layouts for the AD7684 are outlined in the evaluation board for the AD7684 (EVAL-AD7684). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2. Rev. 0 | Page 14 of 16 AD7684 OUTLINE DIMENSIONS 3.00 BSC 8 5 4.90 BSC 3.00 BSC 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 8° 0° 0.23 0.08 0.80 0.60 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 26. 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions Shown in Millimeters ORDERING GUIDE Models AD7684BRM AD7684BRMRL7 EVAL-AD7684CB1 EVAL-CONTROL BRD22 EVAL-CONTROL BRD32 1 2 Integral Nonlinearity ±3 LSB max ±3 LSB max Temperature Range –40°C to +85°C –40°C to +85°C Package (Option) MSOP (RM-8) MSOP (RM-8) Evaluation Board Controller Board Controller Board Transport Media, Quantity Tube, 50 Reel, 1,000 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators. Rev. 0 | Page 15 of 16 Branding C1D C1D AD7684 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04302-0-10/04(0) Rev. 0 | Page 16 of 16