AD ADA4941-1YRZ Single-supply, differential, 18-bit adc driver Datasheet

Single-Supply, Differential,
18-Bit ADC Driver
ADA4941-1
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Single-ended-to-differential converter
Excellent linearity
Distortion −110 dBc at 100 kHz for VO, dm = 2 V p-p
Low noise: 10.2 nV/√Hz, output-referred, G = 2
Extremely low power: 2.2 mA (3 V supply)
High input impedance: 24 MΩ
User-adjustable gain
High speed: 31 MHz, −3 dB bandwidth (G = +2)
Fast settling time: 300 ns to 0.005% for a 2 V step
Low offset: 0.8 mV maximum, output-referred, G = 2
Rail-to-rail output
Disable feature
Wide supply voltage range: 2.7 V to 12 V
Available in space-saving, 3 mm × 3 mm LFCSP
FB
1
8
IN
REF
2
7
DIS
V+
3
6
V–
OUT+
4
5
OUT–
05704-001
FEATURES
Figure 1.
APPLICATIONS
Single-supply data acquisition systems
Instrumentation
Process control
Battery-power systems
Medical instrumentation
GENERAL DESCRIPTION
The ADA4941-1 is ideal for driving the 16-bit and 18-bit
PulSAR® ADCs, such as the AD7687, AD7690, and AD7691.
The ADA4941-1 is manufactured on Analog Devices, Inc.,
proprietary, second-generation, eXtra fast complementary
Rev. D
The ADA4941-1 is available in a small 8-lead LFCSP as well as a
standard 8-lead SOIC and is rated to work over the extended
industrial temperature range, −40°C to +125°C.
–60
–65
–70
–75
VO = 6V p-p
–80
–85
–90
–95
–100
–105
–110
VO = 2V p-p
–115
–120
HD2
HD3
–125
–130
–135
–140
0.1
HD3
HD2
1
10
100
1000
FREQUENCY (kHz)
05704-045
With a wide input voltage range (0 V to 3.9 V on a single 5 V
supply), rail-to-rail output, high input impedance, and a useradjustable gain, the ADA4941-1 is designed to drive single-supply
ADCs with differential inputs found in a variety of low power
applications, including battery-operated devices and singlesupply data acquisition systems.
bipolar (XFCB) process, which enables the amplifier to achieve
18-bit performance on low supply currents.
DISTORTION (dBc)
The ADA4941-1 is a low power, low noise differential driver for
analog-to-digital converters (ADCs) up to 18 bits in systems
that are sensitive to power. The ADA4941-1 is configured in an
easy-to-use, single-ended-to-differential configuration and
requires no external components for a gain of 2 configuration.
A resistive feedback network can be added to achieve gains greater
than 2. The ADA4941-1 provides essential benefits, such as low
distortion and high SNR that are required for driving high
resolution ADCs.
Figure 2. Distortion vs. Frequency at Various Output Amplitudes
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ADA4941-1
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
DC Error Calculations ............................................................ 16
Applications ................................................................................... 1
Output Voltage Noise .............................................................. 17
Functional Block Diagram............................................................ 1
Frequency Response vs. Closed-Loop Gain .......................... 19
General Description ...................................................................... 1
Applications Information............................................................ 20
Revision History ............................................................................ 2
Overview .................................................................................. 20
Specifications ................................................................................. 3
Using the REF Pin.................................................................... 20
Absolute Maximum Ratings ......................................................... 6
Internal Feedback Network Power Dissipation..................... 20
Thermal Resistance ................................................................... 6
Disable Feature......................................................................... 20
Maximum Power Dissipation ................................................... 6
Adding a 3-Pole, Sallen-Key Filter.......................................... 21
ESD Caution............................................................................... 6
Driving the AD7687 ADC ...................................................... 22
Pin Configuration and Function Descriptions............................ 7
Gain of −2 Configuration........................................................ 22
Typical Performance Characteristics............................................ 8
Outline Dimensions .................................................................... 23
Theory of Operation.................................................................... 15
Ordering Guide........................................................................ 23
Basic Operation ....................................................................... 15
REVISION HISTORY
5/16—Rev. C to Rev. D
Change CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 4........................................................................7
Added Figure 5; Renumbered Sequentially ..................................7
Updated Outline Dimensions......................................................23
Changes to Ordering Guide .........................................................23
8/11—Rev. B to Rev. C
Change to Gain Error Drift Unit, Table 1 .....................................3
Change to Gain Error Drift Unit, Table 2 .....................................4
Change to Gain Error Drift Unit, Table 3 .....................................5
8/10—Rev. A to Rev. B
Added Caption to Figure 1.............................................................1
Added Exposed Pad Notation to Figure 4 and Table 6 ................7
Added Exposed Pad Notation to Outline Dimensions..............23
Changes to Ordering Guide .........................................................23
3/09—Rev. 0 to Rev. A
Change to Gain Error Drift Parameter, Table 1............................3
Change to Gain Error Drift Parameter, Table 2............................4
Change to Gain Error Drift Parameter, Table 3............................5
Updated Outline Dimensions......................................................23
4/06—Revision 0: Initial Version
Rev. D | Page 2 of 23
Data Sheet
ADA4941-1
SPECIFICATIONS
TA = 25°C, VS = 3 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 1.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time 0.005%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
RTO Voltage Noise
Input Current Noise
DC PERFORMANCE
Differential Output Offset Voltage
Differential Input Offset Voltage Drift
Single-Ended Input Offset Voltage
Single-Ended Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disable
Power Supply Rejection Ratio (PSRR)
+PSRR
−PSRR
DISABLE
DIS Input Voltage
DIS Input Current
Test Conditions/Comments
Min
Typ
VO = 0.1 V p-p
VO = 2.0 V p-p
+Recover/−recovery
VO = 2 V step
VO = 2 V p-p step
21
4.6
30
6.5
320/650
22
300
MHz
MHz
ns
V/µs
ns
−116/−112
−101/−98
−75/−71
10.2
1.6
dBc
dBc
dBc
nV/√Hz
pA/√Hz
f C = 40 kHz, VO = 2 V p-p, HD2/HD3
f C = 100 kHz, VO = 2 V p-p, HD2/HD3
f C = 1 MHz, VO = 2 V p-p, HD2/HD3
f = 100 kHz
f = 100 kHz
Amp A1 or Amp A2
IN and REF
IN and REF
(+OUT − −OUT)/(IN − REF)
1.98
−1
0.2
1.0
0.1
0.3
3
0.1
2.00
1
IN and REF
IN and REF
Max
0.8
0.4
4.5
2.01
+1
5
24
1.4
CMRR = VOS, dm/VCM , VREF = VIN, VCM = 0.2 V to 1.9 V, G = 4
0.2
81
Each single-ended output, G = 4
±2.90
20% overshoot, VO, dm = 200 mV p-p
105
±2.95
25
20
V
mA
pF
1.9
2.2
10
Disabled, DIS = high
Enabled, DIS = low
Disabled, DIS = high
Enabled, DIS = low
Turn-On Time
Turn-Off Time
Rev. D | Page 3 of 23
86
86
mV
µV/°C
mV
µV/°C
µA
µA
V/V
%
ppm/°C
MΩ
pF
V
dB
2.7
PSRR = VOS, dm/ΔVS, G = 4
Unit
12
2.4
16
V
mA
µA
100
110
dB
dB
≥1.5
≤1.0
5.5
4
0.7
30
V
V
µA
µA
µs
µs
8
6
ADA4941-1
Data Sheet
TA = 25°C, VS = 5 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 2.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time 0.005%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
RTO Voltage Noise
Input Current Noise
DC PERFORMANCE
Differential Output Offset Voltage
Differential Input Offset Voltage Drift
Single-Ended Input Offset Voltage
Single-Ended Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disable
Power Supply Rejection Ratio (PSRR)
+PSRR
−PSRR
DISABLE
DIS Input Voltage
DIS Input Current
Test Conditions/Comments
Min
Typ
VO = 0.1 V p-p
VO = 2.0 V p-p
+Recover/−recovery
VO = 2 V step
VO = 6 V p-p step
22
4.9
31
7
200/600
24.5
610
MHz
MHz
ns
V/µs
ns
−118/−119
−110/−112
−83/−73
10.2
1.6
dBc
dBc
dBc
nV/√Hz
pA/√Hz
f C = 40 kHz, VO = 2 V p-p, HD2/HD3
f C = 100 kHz, VO = 2 V p-p, HD2/HD3
f C = 1 MHz, VO = 2 V p-p, HD2/HD3
f = 100 kHz
f = 100 kHz
Amp A1 or Amp A2
IN and REF
IN and REF
(+OUT − −OUT)/(IN − REF)
1.98
−1
0.2
1.0
0.1
0.3
3
0.1
2
1
IN and REF
IN and REF
Max
0.8
0.4
4.5
2.01
+1
5
24
1.4
CMRR = VOS, dm/VCM , VREF = VIN, VCM = 0.2 V to 3.9 V, G = 4
0.2
84
Each single-ended output, G = 4
±4.85
20% overshoot, VO, dm = 200 mV p-p
106
±4.93
25
20
V
mA
pF
3.9
2.3
12
Disabled, DIS = high
Enabled, DIS = low
Disabled, DIS = high
Enabled, DIS = low
Turn-On Time
Turn-Off Time
Rev. D | Page 4 of 23
87
87
mV
µV/°C
mV
µV/°C
µA
µA
V/V
%
ppm/°C
MΩ
pF
V
dB
2.7
PSRR = VOS, dm/ΔVS, G = 4
Unit
12
2.6
20
V
mA
µA
100
110
dB
dB
≥1.5
≤1.0
5.5
4
0.7
30
V
V
µA
µA
µs
µs
8
6
Data Sheet
ADA4941-1
TA = 25°C, VS = ±5 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 0 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time 0.005%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion
RTO Voltage Noise
Input Current Noise
DC PERFORMANCE
Differential Output Offset Voltage
Differential Input Offset Voltage Drift
Single-Ended Input Offset Voltage
Single-Ended Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disable
Power Supply Rejection Ratio (PSRR)
+PSRR
−PSRR
DISABLE
DIS Input Voltage
DIS Input Current
Test Conditions/Comments
Min
Typ
VO = 0.1 V p-p
VO = 2.0 V p-p
+Recover/−recovery
VO = 2 V step
VO = 12 V p-p step
23
5.2
32
7.5
200/650
26
980
MHz
MHz
ns
V/µs
ns
−118/−119
−109/−112
−84/−75
10.2
1.6
dBc
dBc
dBc
nV/√Hz
pA/√Hz
f C = 40 kHz, VO = 2 V p-p, HD2/HD3
f C = 100 kHz, VO = 2 V p-p, HD2/HD3
f C = 1 MHz, VO = 2 V p-p, HD2/HD3
f = 100 kHz
f = 100 kHz
Amp A1 or Amp A2
IN and REF
IN and REF
(+OUT − −OUT)/(IN − REF)
1.98
−1
0.2
1.0
0.1
0.3
3
0.1
2
1
IN and REF
IN and REF
Max
0.8
0.4
4.5
2.01
+1
5
24
1.4
CMRR = VOS, dm/VCM , VREF = VIN,
VCM = −4.8 V to +3.9 V, G = 4
Each single-ended output, G = 4
−4.8
85
VS − 0.25
20% overshoot, VO, dm = 200 mV p-p
105
VS ± 0.14
25
20
V
mA
pF
+3.9
2.5
15
Disabled, DIS = high
Enabled, DIS = low
Disabled, DIS = high
Enabled, DIS = low
Turn-On Time
Turn-Off Time
Rev. D | Page 5 of 23
87
87
mV
µV/°C
mV
µV/°C
µA
µA
V/V
%
ppm/°C
MΩ
pF
V
dB
2.7
PSRR = VOS, dm/ΔVS, G = 4
Unit
12
2.7
26
V
mA
µA
100
110
dB
dB
≥ −3
≤ −4
7
4
0.7
30
V
V
µA
µA
µs
µs
10
6
ADA4941-1
Data Sheet
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12 V
See Figure 3
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad (if applicable) on the PCB
surface that is thermally connected to a copper plane, with zero
airflow.
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(126°C/W) and for the 8-lead LFCSP (83°C/W) on a JEDEC
standard 4-layer board. The LFCSP must have its underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
2.5
Table 5. Thermal Resistance
Package Type
8-Lead SOIC on 4-Layer Board
8-Lead LFCSP with EP on 4-Layer Board
θJA
126
83
θJC
28
19
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4941-1
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4941-1. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
2.0
LFCSP
1.5
1.0
SOIC
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
05704-002
Table 4.
MAXIMUM POWER DISSIPATION (W)
ABSOLUTE MAXIMUM RATINGS
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
Rev. D | Page 6 of 23
Data Sheet
ADA4941-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADA4941-1
FB 1
8 IN
REF 2
7 DIS
TOP VIEW
(Not to Scale)
V+ 3
6 V–
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE.
IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB
THAT IS THERMALLY CONDUCTIVE.
05704-102
5 OUT–
OUT+ 4
Figure 4. 8-Lead LFCSP Pin Configuration
ADA4941-1
FB 1
8
IN
7 DIS
TOP VIEW
V+ 3 (Not to Scale) 6 V–
OUT+ 4
5
OUT–
05704-101
REF 2
Figure 5. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
FB
REF
V+
OUT+
OUT−
V−
DIS
IN
EPAD (LFCSP Only)
Description
Feedback Input.
Reference Input.
Positive Power Supply.
Noninverting Output.
Inverting Output.
Negative Power Supply.
Disable.
Input.
Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to
ground or a power plane on the PCB that is thermally conductive.
Rev. D | Page 7 of 23
ADA4941-1
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = +5V
VS = ±5V
10
100
1000
FREQUENCY (MHz)
VO, dm = 0.1V p-p
+85°C
+25°C
–40°C
1
10
100
1000
FREQUENCY (MHz)
VO, dm = 0.1V p-p
RL, dm = 1kΩ
RL, dm = 5kΩ
RL, dm = 500Ω
1
10
100
FREQUENCY (MHz)
1000
100
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
0.1
VO, dm = 6V p-p
+85°C
–40°C
+25°C
1
10
100
Figure 10. Large Signal Frequency Response at Various Temperatures
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
10
FREQUENCY (MHz)
05704-006
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 7. Small Signal Frequency Response at Various Temperatures
1
Figure 9. Large Signal Frequency Response for Various Power Supplies
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
VS = +5V
VO, dm = 6V p-p
FREQUENCY (MHz)
05704-005
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 6. Small Signal Frequency Response for Various Power Supplies
VS = ±5V
VO, dm = 12V p-p
05704-008
1
VS = +3V
VO, dm = 2V p-p
Figure 8. Small Signal Frequency Response for Various Resistive Loads
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
0.1
VO, dm = 6V p-p
RL, dm = 1kΩ
RL, dm = 500Ω
RL, dm = 5kΩ
1
FREQUENCY (MHz)
10
05704-009
VS = +3V
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
0.1
05704-007
VO, dm = 0.1V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
05704-004
NORMALIZED CLOSED-LOOP GAIN (dB)
Unless otherwise noted, VS = 5 V, RL, dm = 1 kΩ, REF = 2.5 V, DIS = low, OUT+ directly connected to FB (G = 2), TA = 25°C.
Figure 11. Large Signal Frequency Response for Various Resistive Loads
Rev. D | Page 8 of 23
G = +10
G = +4
G = –2
10
1
100
G = +2
G = –2
G = +10
1
100
10
1000
Figure 12. Small Signal Frequency Response for Various Gains
Figure 15. Large Signal Frequency Response for Various Gains
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
0.1
VO, dm = 0.1V p-p
CL = 20pF
CL = 0pF
1
10
100
1000
FREQUENCY (MHz)
VO, dm = 0.1V p-p
VO, dm = 6V p-p
1
10
1000
100
Figure 16. Frequency Response for Various Output Amplitudes
–70
VO, dm = 2V p-p
VREF = MIDSUPPLY
VREF = 0.05V p-p
–80
–90
DISTORTION (dBc)
VS = ±5V
–100
HD3
–110
–120
VS = +3V
RL = 2kΩ
–130
1
10
FREQUENCY (MHz)
RL = 1kΩ
HD2
1000
Figure 14. REF Input Small Signal Frequency Response for Various Supplies
Rev. D | Page 9 of 23
–140
0.1
RL = 500Ω
HD2
1
10
100
FREQUENCY (kHz)
Figure 17. Distortion vs. Frequency for Various Loads
1000
05704-015
VS = +5V
05704-012
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
VO, dm = 2V p-p
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Capacitive Loads
NORMALIZED CLOSED-LOOP GAIN (dB)
VO, dm = 2V p-p
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
G = +4
05704-013
G = +2
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
05704-014
NORMALIZED CLOSED-LOOP GAIN (dB)
VO, dm = 0.1V p-p
05704-010
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
ADA4941-1
05704-011
NORMALIZED CLOSED-LOOP GAIN (dB)
Data Sheet
ADA4941-1
Data Sheet
–65
f = 10kHz
VS = +3V
VS = ±5V
–85
DISTORTION (dBc)
VS = +5V
–95
–105
HD3
–115
2
0
4
6
8
10
12
14
16
18
20
–145
0
4
6
8
10
12
14
16
20
18
Figure 21. Distortion vs. Output Amplitude for Various Supplies (G = −2)
–70
VO, dm = 2V p-p
VREF = MIDSUPPLY
VO, dm = 2V p-p
VREF = MIDSUPPLY
–80
–75
–80
–85
–90
–95
–100
HD2
–100
–110
HD2
–120
HD3
HD2
HD3
VS = +3V
HD3
1
VS = ±5V
10
1000
100
FREQUENCY (kHz)
G = +2
–140
0.1
HD3
G = +4
HD3
1
10
1000
100
FREQUENCY (kHz)
Figure 19. Distortion vs. Frequency for Various Supplies
Figure 22. Distortion vs. Frequency for Various Gains
0.12
–60
CL = 0pF
VOUT = 200mV p-p
0.08
OUTPUT VOLTAGE (V)
VO = 6V p-p
CL = 20pF
0.04
0
–0.04
VO = 2V p-p
HD2
HD3
HD3
HD2
1
10
100
1000
FREQUENCY (kHz)
Figure 20. Distortion vs. Frequency at Various Output Amplitudes
–0.12
50ns/DIV
05704-022
–0.08
05704-045
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
0.1
G = –2
–130
VS = +5V
05704-020
DISTORTION (dBc)
–90
–125 HD2
–130
–135
–140
0.1
DISTORTION (dBc)
2
OUTPUT AMPLITUDE (V p-p)
05704-017
DISTORTION (dBc)
HD2
–135
Figure 18. Distortion vs. Output Amplitude for Various Supplies (G = +2)
–60
HD3
–125
OUTPUT AMPLITUDE (V p-p)
–65
–70
VS = ±5V
HD3
HD2
HD3
VS = +5V
HD3
–115
HD2
–125
–120
VS = +3V
–105
HD3
HD2
–105
–110
–115
–95
05704-016
DISTORTION (dBc)
–85
–135
DIFFERENTIAL G = –2
f = 10kHz
–75
–75
05704-019
–65
Figure 23. Small Signal Transient Response for Various Capacitive Loads
Rev. D | Page 10 of 23
Data Sheet
ADA4941-1
0.12
VS = +3V
8
VOUT = 200mV p-p
0.08
VS = +5V OR VS = ±5V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VS = ±5V
VO, dm = 12V p-p
6
0.04
0
–0.04
VS = ±2.5V
VO, dm = 6V p-p
4
2
VS = ±1.5V
VO, dm = 2V p-p
0
–2
–4
–0.08
VS = ±5V
VO, dm = 12V p-p
ERROR = 2 × VIN – VO, dm
1.8
8
1.2
0.6
0
0
–2
–0.6
2 × VIN
–4
–1.2
–6
ERROR = 2 × VIN – VO, dm
6
5
0
VO, dm
4
3
05704-023
–0.9
–1.2
1
Figure 28. Settling Time (0.005%), VS = +5 V
8
INPUT × 2
6
OUTPUT VOLTAGE (V)
OUTPUT
4
2
0
–2
–4
–6
INPUT × 2
4
2
OUTPUT
0
–2
–4
–8
–6
1µs/DIV
–12
1µs/DIV
05704-024
–10
–0.6
1µs/DIV
8
6
–0.3
2 × VIN
Figure 25. Settling Time (0.005%), VS = ±5 V
10
0.6
0.3
2
–2.4
12
05704-021
0.9
VS = +5V
VO, dm = 6V p-p
7
–1.8
1µs/DIV
–8
1.2
–8
Figure 26. Input Overdrive Recovery, VS = ±5 V
Figure 29. Input Overdrive Recovery, VS = +5 V
Rev. D | Page 11 of 23
05704-027
2
OUTPUT VOLTAGE (V)
AMPLITUDE (V)
4
9
AMPLITUDE (V)
6
2.4
ERROR (mV) 1 DIV = 0.005%
VO, dm
Figure 27. Large Signal Transient Response for Various Supplies
ERROR (mV) 1 DIV = 0.005%
Figure 24. Small Signal Transient Response for Various Supplies
8
200ns/DIV
–8
05704-026
–0.12
05704-018
–6
50ns/DIV
ADA4941-1
Data Sheet
0
0.18
±5V SUPPLIES, POSITIVE RAIL
–10
OUTPUT SATURATION VOLTAGE
WITH RESPECT TO RAIL (V)
–20
–30
PSRR (dB)
–40
+PSRR
–50
–60
–PSRR
–70
–80
–90
0.16
0.14
±5V SUPPLIES, NEGATIVE RAIL
0.12
+5V SUPPLIES, POSITIVE RAIL
0.10
+5V SUPPLIES, NEGATIVE RAIL
0.08
+3V SUPPLIES, POSITIVE RAIL
0.06
–100
0.1
1
10
100
1000
FREQUENCY (MHz)
0.04
–40
+3V SUPPLIES, NEGATIVE RAIL
–20
0
20
40
Figure 30. Power Supply Rejection Ratio vs. Frequency
100
120
2.5
ICC @ VS = ±5V
VPD = VS–
2.0
SUPPLY CURRENT (mA)
3.0
VS = +5V
2.5
VS = ±5V
2.0
VS = +3V
1.5
ICC @ VS = +3V
ICC @ VS = +5V
1.5
1.0
0.5
1.0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
–0.5
0.6
1.0
1.2
1.4
1.6
1.8
2.0
Figure 34. Power Supply Current vs. Disable Voltage
Figure 31. Power Supply Current vs. Temperature
140
150
120
125
VOS_A2 = 10V
100
0.8
DISABLE INPUT VOLTAGE WITH RESPECT TO VS– (V)
05704-032
0
05704-029
100
FREQUENCY
VOS_A2 = 5V
75
VOS_A2 = 3V
80
VOS1
MEAN = –8µV
STD. DEV = 47µV
VOS2
MEAN = 11µV
STD. DEV = 20µV
NO. OF UNITS = 611
60
50
40
VOS_A1 10V
VOS_A1 = 5V
40
60
80
100
120
TEMPERATURE (°C)
0
OFFSET VOLTAGE (µV)
Figure 35. Differential Output Offset Distribution
Figure 32. Differential Output Offset Voltage vs. Temperature
Rev. D | Page 12 of 23
05704-033
20
80
100
120
140
160
180
200
0
60
–20
20
40
0
–40
20
–200
–180
–160
–140
–120
–100
–80
–60
–40
VOS_A1 = 3V
05704-030
25
–20
0
POWER SUPPLY CURRENT (mA)
80
Figure 33. Output Saturation Voltage vs. Temperature
3.5
DIFFERENTIAL OUTPUT OFFSET (µV)
60
TEMPERATURE (°C)
05704-031
0.01
05704-028
–110
0.001
ADA4941-1
100
28
26
INPUT CURRENT NOISE (pA/√Hz)
24
10
22
20
18
16
14
12
10
8
6
4
1
10
100
1k
10k
100k
1M
10M
100M
0
FREQUENCY (Hz)
10
1
10k
100k
1M
Figure 39. Input Current Noise vs. Frequency
3.5
2.65
VS = ±5V
INPUT BIAS CURRENT (µA)
INPUT BIAS CURRENT (µA)
1k
FREQUENCY (Hz)
Figure 36. Differential Output Voltage Noise vs. Frequency
2.60
100
05704-037
2
1
05704-034
DIFFERENTIAL OUTPUT VOLTAGE NOISE (nV/√Hz)
Data Sheet
VS = +5V
2.55
VS = +3V
2.50
2.45
3.0
2.5
VS = +3V
VS = ±5V
VS = +5V
2.0
–25
–10
5
20
35
50
65
80
95
125
110
1.5
–0.5
05704-035
2.35
–40
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
INPUT VOLTAGE WITH RESPECT TO VS– (V)
05704-038
2.40
Figure 40. Input Bias Current vs. Input Voltage
Figure 37. Input Bias Current vs. Temperature for Various Supplies
4.0
3.3
REFERENCE I BIAS = 10V
3.1
3.0
REFERENCE I BIAS = 5V
2.9
REFERENCE I BIAS = 3V
2.8
2.7
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
3.5
3.0
VS = +3V
VS = ±5V
VS = +5V
2.5
2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
10.0
9.5
REFERENCE INPUT VOLTAGE WITH RESPECT TO VS– (V)
Figure 41. REF Input Bias Current vs. REF Input Voltage
Figure 38. REF Input Bias Current vs. Temperature
Rev. D | Page 13 of 23
05704-039
REFERENCE INPUT BIAS CURRENT (µA)
3.2
05704-036
REFERENCE BIAS CURRENT (µA)
VREF = VIN
ADA4941-1
Data Sheet
14
VS = ±5V
G=4
RF = 1kΩ
RL = ∞
DIS = HIGH
8
12
DISABLE INPUT CURRENT (µA)
DISABLED SUPPLY CURRENT (µA)
10
VS = ±5V
6
VS = +5V
4
VS = +3V
2
10
8
6
4
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
05704-040
0
–40
0
1
2
3
4
5
6
7
8
9
10
DISABLE INPUT VOLTAGE WITH RESPECT TO VS– (V)
05704-043
2
Figure 45. Disable Input Current vs. Disable Input Voltage
Figure 42. Disable Supply Current vs. Temperature for Various Supplies
VO, dm
500mV/DIV
500mV/DIV
VO, dm
VPD
40µs/DIV
40µs/DIV
Figure 43. Disable Assert Time
Figure 46. Disable Deassert Time
–40
100
VIN = 50mV p-p
–50
10
VON
IMPEDANCE (Ω)
–70
–80
1
0.1
0.01
VOP
–90
1
10
100
1000
FREQUENCY (MHz)
Figure 44. Disabled Input-to-Output Isolation vs. Frequency
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 47. Single-Ended Output Impedance vs. Frequency
Rev. D | Page 14 of 23
100
05704-025
0.001
–100
05704-042
ISOLATION (dB)
–60
–110
0.1
05704-044
05704-041
VPD
Data Sheet
ADA4941-1
THEORY OF OPERATION
The ADA4941-1 is a low power, single-ended input, differential
output amplifier optimized for driving high resolution ADCs.
Figure 48 illustrates how the ADA4941-1 is typically connected.
The amplifier is composed of an uncommitted amplifier, A1,
driving a precision inverter, A2. The negative input of A1 is
brought out to Pin 1 (FB), allowing for user-programmable
gain. The inverting op amp, A2, provides accurate inversion of
the output of A1, VOP, producing the output signal VON.
OUT+
IN
VG
VIN
A2
REF
2
RF || RG
VO, dm = 2(VIN) − 2(VREF)
OUT–
500Ω
4.99kΩ
VS+
4
+
VOP
–
1kΩ
A1
A2
REF
500Ω
OUT–
5
+
VON
–
6
–5V
Figure 49. Dual Supply, G = 2.4, Single-Ended-to-Differential Amplifier
Figure 49 shows an example of a dual-supply connection. In this
example, VG and VREF are set to 0 V, and the external RF and
RG network provides a noninverting gain of 1.2 in A1. This
example takes full advantage of the rail-to-rail output stage.
The gain equation is
VOP − VON = 2.4(VIN)
(6)
The in-series, 825 Ω resistor combined with Pin 8 compensates
for the voltage error generated by the input offset current of A1.
The linear output range of both A1 and A2 extends to within
200 mV of each supply rail, which allows a peak-to-peak
differential output voltage of 19.2 V on ±5 V supplies.
In Figure 48, RG and RF form the external gain-setting network.
VG and VREF are externally applied voltages. VO, cm is defined
as the output common-mode voltage and VO, dm is defined as
the differential-mode output voltage. The following equations
can be derived from Figure 48:
OUT+
3
(1)
VIN

  2(VREF )


IN
VIN
BASIC OPERATION

R
R 
VON   VIN 1  F   VG F
R
G 

 RG
FB
8
825Ω
The voltage applied to the REF pin appears as the output
common-mode voltage. Note that the voltage applied to the
REF pin does not affect the voltage at the OUT+ pin. Because of
this, a differential offset can exist between the outputs, while the
desired output common-mode voltage is present. For example,
when VOP = 3.5 V and VON = 1.5 V, the output commonmode voltage is equal to 2.5 V, just as it is when both outputs
are at 2.5 V. In the first case, the differential voltage (or offset) is
2.0 V, and in the latter case, the differential voltage is 0 V. When
calculating output voltages, both differential and common-mode
voltages must be considered at the same time to avoid undesired
differential offsets.




1
1kΩ
+5V
VS–
2
Figure 48. Basic Connections (Power Supplies Not Shown)

R
R 
VOP  VIN 1  F   VG  F
R
G 

 RG
OUT+
3
5
+
VON
–
VREF
(5)
1kΩ
1kΩ
A1
(4)
05704-053
8
(3)

  2(VREF )


When RF = 0 and RG is removed, Equation 3 simplifies to the
following:
05704-052
RG
FB
R

  2VG F
R

 G

 VOP  VON 
VO , cm  
  VREF
2


+
VOP
–
1kΩ
1
4
 R
VOP  VON  2(VIN )1  F
 RG
1
FB
8
IN
1kΩ
+5V
VS+
1kΩ
A1
6
VS–
2
4
+
VOP
–
A2
REF
500Ω
+2.5V
(2)
OUT–
5
+
VON
–
05704-054
RF
VO , dm 
Figure 50. Single +5V Supply, G=2 Single-Ended-to-Differential Amplifier
Figure 50 shows a single 5 V supply connection with A1 used as
a unity gain follower. The 2.5 V at the REF pin sets the output
common-mode voltage to 2.5 V. The transfer function is then
VOP − VON = 2(VIN) − 5 V
Rev. D | Page 15 of 23
(7)
ADA4941-1
Data Sheet
In this case, the linear output voltage is limited by A1. On the
low end, the output of A1 starts to saturate and show degraded
linearity when VOP approaches 200 mV. On the high end, the
input of A1 becomes saturated and exhibits degraded linearity
when VIN moves beyond 4 V (within 1 V of VCC). This limits
the linear differential output voltage in the circuit shown in
Figure 50 to about 7.6 V p-p.
1.02kΩ
3
665Ω
8
FB
VS+
VS–
2
6
VIN
 R
VOP_error  1  F
 RG
1kΩ
A1
IN
402Ω
1kΩ
+5V
4
+
VOP
–
A2
REF
OUT–
5
+
VON
–
500Ω
+2.5V
Figure 51 shows a single 5 V supply connection for G = 5. The
RF and RG network sets the gain of A1 to 2.5, and the 2.5 V at
the REF input provides a centered 2.5 V output common-mode
voltage. The transfer function is then
VOP − VON = 5(VIN) − 5 V
1
RG
8
VOS–A1
IBP– A1
A2
REF
2
RS–REF
VOS  VOS _nom 
500Ω
OUT–
VOS–A2
5
+
VON
–
IBP– A2
05704-056
RS–IN
4
1kΩ
A1
Figure 52. DC Error Sources
Figure 52 shows the major contributions to the dc output
voltage error. For each output, the total error voltage can be
calculated using familiar op amp concepts. Equation 9 expresses
the dc voltage error present at the VOP output.

VOS _A1  (I BP _A1)(RS _IN )  (I BP _A1)RF


ΔVCM
ΔVS ΔVOUT


CMRR PSRR
AVOL
(12)
where:
VOS_nom is the nominal output offset voltage without including
the effects of CMRR, PSRR, and AVOL.
Δ indicates the change in conditions from nominal.
VCM is the input common-mode voltage (for A1, the voltage at
IN, and for A2, the voltage at REF).
VS is the power supply voltage.
VOUT is either op amp output.
VOP_error 
 RF
1 
 R
G

(11)
The output offset voltage of each amplifier in the ADA4941-1
also includes the effects of finite common-mode rejection ratio
(CMRR), power supply rejection ratio (PSRR), and dc openloop gain (AVOL).
IBN– A2
FB
(RS_REF = 0 Ω)
VO_error, dm = VOP_error − VON_error
+
VOP
–
1kΩ
IN
VON_error =
−(VOP_error) + 2[VOS_A2] + (IOS)1000
The differential output voltage error VO_error, dm, is the
difference between VOP_error and VON_error:
DC ERROR CALCULATIONS
OUT+
(10)
The internal 500 Ω resistor is provided on-chip to minimize dc
errors due to the input offset current in A2. The minimum
error is achieved when RS_REF = 0 Ω. In this case, Equation 10
is reduced to
(8)
The output range limits of A1 and A2 limit the differential
output voltage of the circuit shown in Figure 51 to approximately
8.4 V p-p.
IBN– A1
(RS  RF || RG )
VON_error = −(VOP_error) + 2[VOS_A2 −
(IBP_A2)(RS_REF + 500)] + 1000(IBN_A2)
Figure 51. 5 V Supply, G = 5, Single-Ended-to-Differential Amplifier
RF

VOS _A1  (I OS )RF


Equation 10 expresses the dc voltage error present at the VON
output.
05704-055
1
OUT+
When using data from the Specifications tables, it is often more
expedient to use input offset current in place of the individual
input bias currents when calculating errors. Input offset current
is defined as the magnitude of the difference between the two
input bias currents. Using this definition, each input bias
current can be expressed in terms of the average of the two
input bias currents, IB, and the input offset current, IOS, as
IBP, N = IB ± IOS/2. DC errors are minimized when RS = RF || RG. In
this case, Equation 9 is reduced to
(9)
Rev. D | Page 16 of 23
Data Sheet
ADA4941-1
Table 7, Table 8, and Table 9 show typical error budgets for the
circuits shown in Figure 49, Figure 50, and Figure 51.
Figure 53 shows the major contributors to the ADA4941-1
differential output voltage noise. The differential output noise
mean-square voltage equals the sum of twice the noise meansquare voltage contributions from the noninverting channel
(A1), plus the noise mean-square voltage terms associated with
the inverting channel (A2).
RF = 1.0 kΩ, RG = 4.99 kΩ, RS_IN = 825 Ω, RS_REF = 0 Ω
Table 7. Output Voltage Error Budget for G = 2.4 Amplifier
Shown in Figure 49
Error
Source
VOS_A1
IBP_A1
IBN_A1
VOS_A2
Typical
Value
0.1 mV
3 μA
3 μA
0.1 mV
VOP_error
+0.12 mV
+2.48 mV
−2.48 mV
0 mV
2
VO , dm _ n 
VO_dm_error
+0.24 mV
−4.96 mV
+4.96 mV
+0.2 mV
VON_error
−0.12 mV
−2.48 mV
+2.48 mV
+0.2 mV
2


R 
2 1  F   (vn _ A1)  2 
RG 


2


2
R 
1  F   (ip _ A1  RS )  2 in _ A1  RF 
R
G 


Total VO_error, dm = 0.44 mV
2
RF = 0 Ω, RG = ∞, RS_IN = 0 Ω, RS_REF = 0 Ω
VOP_error
+0.1 mV
+2.48 mV
−2.48 mV
0 mV
VO_dm_error
+0.2 mV
−4.96 mV
+4.96 mV
+0.2 mV
VON_error
−0.1 mV
−2.48 mV
+2.48 mV
+0.2 mV
2

VOP_error
+0.25 mV
+1.21 mV
−1.21 mV
0 mV
OUT+
√4kT (1kΩ)
in–A2
in–A1
IN
RS
√4kTRG
√4kT (1kΩ)
A1
√4kTRS
ip–A1
2
RS–REF
√4kT (500Ω)
4
+
VOP
–
1kΩ
1kΩ
A2
REF
vn–A1
500Ω
vn–A2
OUT–
5
+
VON
–
ip–A2
√4kT (RS–REF)

2
(14)
Table 10, Table 11, and Table 12 show the noise contributions
and output voltage noise for the circuits in Figure 49, Figure 50,
and Figure 51.
05704-057
8
FB
2
When A1 is used as a unity gain follower, the output voltage
noise spectral density is at its minimum, 10 nV/√Hz. Higher
voltage gains have higher output voltage noise.
OUTPUT VOLTAGE NOISE
RF
 
where:
vn_A1 and vn_A2 are the input voltage noises of A1 and A2,
each equal to 2.1 nV/√Hz.
in_A1, in_A2, ip_A1, and ip_A2 are amplifier input current
noise terms, each equal to 1 pA/√Hz.
RS, RF, and RG are the external source, feedback, and gain
resistors, respectively.
kT is Boltzmann’s constant times absolute temperature, equal to
4.2 x 10-21 W-s at room temperature.
RS_REF is any source resistance at the REF pin.
Total VO_error, dm = 0.7 mV
√4kTRF

8 kT (1000)  16 kT (500)  16 kT (RS _REF )
VO_dm_error
+0.5 mV
−2.4 mV
+2.4 mV
+0.2 mV
VON_error
−0.25 mV
−1.21 mV
+1.21 mV
+0.2 mV
2
4 (ip _ A2)(500  RS _ REF )  1000(in _ A2) 
Table 9. Output Voltage Error Budget for G = 5 Amplifier
Shown in Figure 51
Typical
Value
0.1 mV
3 μA
3 μA
0.1 mV

VON_n  4 vn_A2
RF = 1.02 kΩ, RG = 665 Ω, RS_IN = 402 Ω, RS_REF = 0 Ω
RG
2

R 
 2  4 kTRG  F   2 
RG 

where VON_n2 is calculated as
Typical
Value
0.1 mV
3 μA
3 μA
0.1 mV
1

(13)
2
Total VO_error, dm = 0.4 mV
Error
Source
VOS_A1
IBP_A1
IBN_A1
VOS_A2
4 kTRF



2
R 
1  F   4 kTRS   VON _ n
R
G 


Table 8. Output Voltage Error Budget for Amplifier Shown
in Figure 50
Error
Source
VOS_A1
IBP_A1
IBN_A1
VOS_A2

2

Figure 53. Noise Sources
Rev. D | Page 17 of 23
ADA4941-1
Data Sheet
Table 10. Output Voltage Noise, G = 2.4 Differential Amplifier Shown in Figure 49
Noise Source
vn_A1
ip_A1
in_A1
√4 kTRF
√4 kTRG
√4 kTRS
vn_inverter
√RS_REF
ip_A2 × RS_REF
Typical Value
2.1 nV/√Hz
1 pA/√Hz
1 pA/√Hz
4 nV/√Hz
9 nV/√Hz
3.6 nV/√Hz
9.2 nV/√Hz
0
0
VOP Contribution (nV√Hz)
2.5
1
1
4
1.8
4.4
0
0
0
VON Contribution (nV√Hz)
2.5
1
1
4
1.8
4.4
9.2
0
0
VO, dm Contribution (nV√Hz)
5
2
2
8
3.6
8.8
9.2
0
0
Totals
6.8
11.4
16.5
RF = 1.0 kΩ, RG = 4.99 kΩ, RS = 825 Ω, RS_REF = 0 Ω.
vn_inverter = noise contributions from A2 and its associated internal 1 kΩ feedback resistors and 500 Ω offset current balancing resistor.
Table 11. Output Voltage Noise, G = 2 Differential Amplifier Shown in Figure 50
Noise Source
vn_A1
ip_A1
in_A1
√4 kTRF
√4 kTRG
√4 kTRS
vn_inverter
√RS_REF
ip_A2 × RS_REF
Typical Value
2.1 nV/√Hz
0
0
0
0
0
9.2 nV/√Hz
0
0
VOP Contribution (nV√Hz)
2.1
0
0
0
0
0
0
0
0
VON Contribution (nV√Hz)
2.1
0
0
0
0
0
9.2
0
0
VO, dm Contribution (nV√Hz)
4.2
0
0
0
0
0
9.2
0
0
Totals
2.1
9.4
10
RF = 0 Ω, RG = ∞, RS = 0 Ω, RS_REF = 0 Ω.
Table 12. Output Voltage Noise, G = 5 Differential Amplifier Shown in Figure 51
Noise Source
vn_A1
ip_A1
in_A1
√4 kTRF
√4 kTRG
√4 kTRS
vn_inverter
√RS_REF
ip_A2 × RS_REF
Typical Value
2.1 nV/√Hz
1 pA/√Hz
1 pA/√Hz
4 nV/√Hz
3.26 nV/√Hz
2.54 nV/√Hz
9.2 nV/√Hz
0
0
VOP Contribution (nV√Hz)
5.25
1
1
4
4.9
6.54
0
0
0
VON Contribution (nV√Hz)
5.25
1
1
4
4.9
6.54
9.2
0
0
VO, dm Contribution (nV√Hz)
10.5
2
2
8
9.8
13.1
9.2
0
0
Totals
10.7
14.1
23.1
RF = 1.02 kΩ, RG = 665 Ω, RS = 402 Ω, RS_REF = 0 Ω.
Rev. D | Page 18 of 23
Data Sheet
ADA4941-1
FREQUENCY RESPONSE VS. CLOSED-LOOP GAIN
The operational amplifiers used in the ADA4941-1 are voltage
feedback with an open-loop frequency response that can be
approximated with the integrator response, as shown in Figure 54.
100
40
fcr = 50MHz
20
0
0.001


1
VO, dm = VOP − VON = VOP + VOP × 

f
 1  25 MHz




1
RF  

VO , dm  VIN  1 

R


R
R

f
G  

G
1 F

  R
50
MHz
G

 
60
0.01
0.1
1
10
100
FREQUENCY (MHz)
05704-062
OPEN-LOOP GAIN (dB)
80
The frequency response of A1 depends on the external feedback
network as indicated by Equation 15. The overall differential
output voltage is therefore
For each amplifier, the frequency response can be approximated
by the following equations:
(15)
(Noninverting Response)





  RF  
1

VO _A2  VIN  


 RG   1   RF  RG   f 

  R

G
 fcr 
 
(16)
(Inverting Response)
fCR is the gain-bandwidth frequency of the amplifier (where the
open-loop gain shown in Figure 54 equals 1). fCR for both
amplifiers is about 50 MHz.




1


   VOP  
f

1

25
MHz


(19)






 R 
VO , dm  VIN 1  F  
 RG 






2






f
f
 1   RF  RG  



 1

  R

 
G
 50 MHz   25 MHz  
 
(20)
There are two poles in this transfer function, and the lower
frequency pole limits the bandwidth of the differential
amplifier. If VOP is shorted to IN− (A1 is a unity gain follower),
the 25 MHz closed-loop bandwidth of the inverting channel
limits the overall bandwidth. When A1 is operating with higher
noise gains, the bandwidth is limited by the closed-loop
bandwidth of A1, which is inversely proportional to the noise
gain (1 + RF/RG). For instance, if the external feedback network
provides a noise gain of 10, the bandwidth drops to 5 MHz.
The inverting amplifier A2 has a fixed feedback network. The
transfer function is approximately


1

VO _ A2   VIN  
2 f
1

50 MHz








(18)
Multiplying the terms and neglecting negligible terms leads to
the following approximation:
Figure 54. ADA4941-1 Op Amp Open-Loop Gain vs. Frequency






 RF 
1

VO _A1  VIN  1 


 RG   1   RF  RG   f 




  RG  fcr 


1
1 

f
 1  25 MHz









 (17)



Rev. D | Page 19 of 23
ADA4941-1
Data Sheet
APPLICATIONS INFORMATION
OVERVIEW
The ADA4941-1 is an adjustable-gain, single-ended-to-differential
voltage amplifier, optimized for driving high resolution ADCs.
Single-ended-to-differential gain is controlled by one feedback
network, comprised of two external resistors: RF and RG.
USING THE REF PIN
The REF pin sets the output base line in the inverting path and
is used as a reference for the input signal. In most applications,
the REF pin is set to the input signal midswing level, which in
many cases is also midsupply. For bipolar signals and dual power
supplies, REF is generally set to ground. In single-supply
applications, setting REF to the input signal midswing level
provides optimal output dynamic range performance with
minimum differential offset. Note that the REF input only
affects the inverting signal path or VON.
Most applications require a differential output signal with the
same dc common-mode level on each output. It is possible for
the signal measured across VOP and VON to have a commonmode voltage that is of the desired level but not common to
both outputs. This type of signal is generally avoided because
it does not allow for optimal use of the output dynamic range of
the amplifier.
Defining VIN as the voltage applied to the input pin, the
equations that govern the two signal paths are given in
Equation 21 and Equation 22.
VOP = VIN
(21)
VON = −VIN + 2 (REF)
(22)
When the REF voltage is set to the midswing level of the input
signal, the two output signals fall directly on top of each other
with minimal offset. Setting the REF voltage elsewhere results
in an offset between the two outputs.
The best use of the REF pin can be further illustrated by
considering a single-supply case with a 10 V power supply and
an input signal that varies between 2 V and 7 V. This is a case
where the midswing level of the input signal is not at midsupply
but is at 4.5 V. Setting the REF input at 4.5 V and neglecting
offsets, Equation 21 and Equation 22 are used to calculate the
results. When the input signal is at its midpoint of 4.5 V, OUT+
is at 4.5 V, as is VON. This can be considered as a base line state
where the differential output voltage is 0. When the input increases
to 7 V, VOP tracks the input to 7 V, and VON decreases to 2 V.
This can be viewed as a positive peak signal where the differential
output voltage equals 5 V. When the input signal decreases to
2 V, VOP again tracks to 2 V, and VON increases to 7 V. This
can be viewed as a negative peak signal where the differential
output voltage equals −5 V. The resulting differential output
voltage is 10 V p-p.
The previous discussion reveals how the single-ended-todifferential gain of 2 is achieved.
INTERNAL FEEDBACK NETWORK POWER
DISSIPATION
While traditional op amps do not have on-chip feedback
elements, the ADA4941-1 contains two on-chip, 1 kΩ resistors
that comprise an internal feedback loop. The power dissipated
in these resistors must be included in the overall power dissipation
calculations for the device. Under certain circumstances, the
power dissipated in these resistors could be comparable to the
quiescent dissipation of the device. For example, on ±5 V supplies
with the REF pin tied to ground and OUT− at +4 VDC, each
1 kΩ resistor carries 4 mA and dissipates 16 mW for a total of
32 mW. This is comparable to the quiescent power and must
therefore be included in the overall device power dissipation
calculations. For ac signals, rms analysis is required.
DISABLE FEATURE
The ADA4941-1 includes a disable feature that can be asserted
to minimize power consumption in a device that is not needed
at a particular time. When asserted, the disable feature does not
place the device output in a high impedance or tristate condition.
The disable feature is active high. See the Specifications tables
for the high and low level voltage specifications.
Rev. D | Page 20 of 23
Data Sheet
ADA4941-1
Figure 55 illustrates a 3-pole, Sallen-Key, low-pass filter with a
−3 dB cutoff frequency of 100 kHz. The 1.69 kΩ resistor is
included to minimize dc errors due to the input offset current
in A1. The passive RC filters on the outputs are generally
required by the ADC converter that is being driven. The
frequency response of the filter is shown in Figure 56.
ADDING A 3-POLE, SALLEN-KEY FILTER
The noninverting amplifier in the ADA4941-1 can be used as
the buffer amplifier of a Sallen-Key filter. A 3-pole, low-pass
filter can be designed to limit the signal bandwidth in front of
an ADC. The input signal first passes through the noninverting
stage where it is filtered. The filtered signal is then passed through
the inverting stage to obtain the complementary output.
OUT+
3
10nF
562Ω
562Ω
1.69kΩ 1
562Ω
8
FB
VS+
6
560pF
3.9nF
OUT–
A2
REF
+
VO, dm
–
0.1µF
1kΩ
VS–
2
2.7nF
1kΩ
+5V
A1
IN
33Ω
4
33Ω
5
2.7nF
500Ω
–5V
0.1µF
05704-058
VIN
Figure 55. Sallen-Key, Low-Pass Filter with 100 kHz Cutoff Frequency
0
VO, dm = 3V p-p
–10
–20
VO, dm/VIN (dB)
–30
–40
–50
–60
–70
–80
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 56. Frequency Response of the Circuit Shown in Figure 55
Rev. D | Page 21 of 23
05704-059
–90
–100
10
ADA4941-1
Data Sheet
DRIVING THE AD7687 ADC
GAIN OF −2 CONFIGURATION
The ADA4941-1 is an excellent driver for high resolution
ADCs, such as the AD7687, as shown in Figure 57. The SallenKey, low-pass filter shown in Figure 55 is included in this
example but is not required. The circuit shown in Figure 57
accepts single-ended input signals that swing between 0 V and 3 V.
The ADA4941-1 can be operated in a configuration referred to
as gain of −2. Clearly, a gain of −2 can be achieved by simply
swapping the outputs of a gain of +2 circuit, but the
configuration described here is different. The configuration is
referred to as having negative gain to emphasize that the input
amplifier, A1, is operated as an inverting amplifier instead of in
its usual noninverting mode. As implied in its name, the voltage
gain from VIN to VO, dm is −2 V/V. See Figure 58 for the gain
of −2 configuration on ±5 V supplies.
The ADR443 provides a stable, low noise, 3 V reference that is
buffered by one of the AD8032 amplifiers and applied to the
AD7687 REF input, providing a differential input full-scale level
of 6 V. The reference voltage is also divided by two and buffered
to supply the midsupply REF level of 1.5 V for the ADA4941-1.
The gain of −2 configuration is most useful in applications that
have wide input swings because the input common-mode
voltages are held at constant levels. The signal size is therefore
constrained by the output swing limits. The gain of −2 has a low
input resistance that is equal to RG.
+5V
0.1µF
OUT+
1kΩ
3
10nF
562Ω
VS+
IN
8
VS– ADA4941-1
2 REF 500Ω
6
VIN
0V TO 3V
560pF
3.9nF
2
0.1µF
VIN
VOUT
GND
33Ω
4
IN– GND
REF
5
1
0.1µF
+5V
+5V
10µF
5
2.7nF
–5V
ADR443
OUT–
A2
IN+ VDD
AD7687
0.1µF
1kΩ
A1
2
3
10µF
0.1µF
6
3
0.1µF
2
4
8
1
1/2
4 AD8032
10µF
1kΩ
1kΩ
5
6
7
1/2
AD8032
Figure 57. ADA4941-1 Driving the AD7687 ADC
RF
1kΩ
OUT+
3
RG
1kΩ
1
8
VIN
FB
1kΩ
+5V
VS+
VS–
2
500Ω
6
+
VO, dm
–
1kΩ
A1
IN
4
A2
REF
500Ω
–5V
Figure 58. Gain of −2 Configuration
Rev. D | Page 22 of 23
OUT–
5
05704-060
562Ω
FB
33Ω
2.7nF
05704-061
562Ω
1.69kΩ 1
4
Data Sheet
ADA4941-1
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
1.84
1.74
1.64
3.10
3.00 SQ
2.90
1.55
1.45
1.35
EXPOSED
PAD
0.50
0.40
0.30
0.80
0.75
0.70
0.30
0.25
0.20
1
4
BOTTOM VIEW
TOP VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1 INDEX
AREA
SEATING
PLANE
0.50 BSC
8
5
Figure 60. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4941-1YRZ
ADA4941-1YRZ-RL
ADA4941-1YRZ-R7
ADA4941-1YCPZ-R2
ADA4941-1YCPZ-RL
ADA4941-1YCPZ-R7
ADA4941-1YCP-EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05704-0-5/16(D)
Rev. D | Page 23 of 23
Package
Option
R-8
R-8
R-8
CP-8-13
CP-8-13
CP-8-13
Ordering
Quantity
98
2,500
1,000
250
5,000
1,500
Branding
H0C
H0C
H0C