TI1 CDCFR83A Direct rambus clock generator Datasheet

CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
DIRECT RAMBUS™ CLOCK GENERATOR
FEATURES
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533-MHz Differential Clock Source for Direct
Rambus™ Memory Systems for an 1066-MHz
Data Transfer Rate
Fail-Safe Power Up Initialization
Synchronizes the Clock Domains of the
Rambus Channel With an External System or
Processor Clock
Three Power Operating Modes to Minimize
Power for Mobile and Other Power-Sensitive
Applications
Operates From a Single 3.3-V Supply and
120 mW at 300 MHz (Typ)
Packaged in a Shrink Small-Outline Package
(DBQ)
Supports Frequency Multipliers: 4, 6, 8, 16/3
No External Components Required for PLL
Supports Independent Channel Clocking
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
Designed for Use With TI's 133-MHz Clock
Synthesizers CDC924 and CDC921
Cycle-Cycle Jitter Is Less Than 40 ps at
533 MHz
Certified by Gigatest Labs to Exceed the
Rambus DRCG Validation Requirement
Supports Industrial Temperature Range of
–40°C to 85°C
DBQ PACKAGE
(TOP VIEW)
VDDIR
REFCLK
VDDP
GNDP
GNDI
PCLKM
SYNCLKN
GNDC
VDDC
VDDIPD
STOPB
PWRDNB
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
S0
S1
VDDO
GNDO
CLK
NC
CLKB
GNDO
VDDO
MULT0
MULT1
S2
NC − No internal connection
DESCRIPTION
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or
processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory
applications.
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable
synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus
memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and
memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs
and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies
by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase
difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between
PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary
without incurring additional latency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIRECT RAMBUS, Rambus are trademarks of Rambus Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one
of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with
clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass
mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where
synchronization between the Rambus clock and a system clock is not required. Test modes are provided to
bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state
for board testing.
The CDCFR83A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.
The CDCFR83A is characterized for operation over free-air temperatures of –40°C to 85°C.
FUNCTIONAL BLOCK DIAGRAM
PWRDWNB
S0
S1
S2
STOPB
Test MUX
Bypass MUX
ByPCLK
PLLCLK
CLK
PLL
Phase
Aligner
B
REFCLK
A
CLKB
PACLK
φD
2
PCLKM
MULT0
MULT1
SYNCLKN
FUNCTION TABLE (1)
S0
S1
S2
CLK
CLKB
Normal
MODE
0
0
0
Phase aligned clock
Phase aligned clock B
Bypass
1
0
0
PLLCLK
PLLCLKB
Test
1
1
0
REFCLK
REFCLKB
Output test (OE)
0
1
x
Hi-Z
Hi-Z
Reserved
0
0
1
–
–
Reserved
1
0
1
–
–
Reserved
1
1
1
Hi-Z
Hi-Z
(1)
2
X = don't care, Hi-Z = high impedance
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CLK
20
O
Output clock
CLKB
18
O
Output clock (complement)
GNDC
8
GND for phase aligner
GNDI
5
GND for control inputs
GNDO
17, 21
GND for clock outputs
GNDP
4
MULT0
15
I
PLL multiplier select
MULT1
14
I
PLL multiplier select
NC
19
GND for PLL
Not used
PCLKM
6
I
Phase detector input
PWRDNB
12
I
Active low power down
REFCLK
2
I
Reference clock
S0
24
I
Mode control
S1
23
I
Mode control
S2
13
I
Mode control
STOPB
11
I
Active low output disable
SYNCLKN
7
I
Phase detector input
VDDC
9
VDD for phase aligner
VDDIPD
10
Reference voltage for phase detector inputs and STOPB
VDDIR
1
Reference voltage for REFCLK
VDDO
16, 22
VDDP
3
VDD for clock outputs
VDD for PLL
3
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
PLL DIVIDER SELECTION
Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,
provided that (267 MHz < BUSCLK < 533 MHz) and (33 MHz < REFCLK < 100 MHz).
Table 1. REFCLK and BUSCLK Frequencies
MULT0
MULT1
REFCLK
(MHz)
MULTIPLY
RATIO
BUSCLK (1)
(MHz)
0
0
67
4
267
0
1
50
6
300
0
1
67
6
400
1
1
33
8
267
1
1
50
8
400
1
1
67
8
533
1
0
67
16/3
356
(1)
BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying
REFCLK, the PLL requires stabilization time to achieve phase lock.
Table 2. Clock Output Driver States
STATE
PWRDNB
STOPB
CLK
CLKB
Powerdown
0
X
GND
GND
CLK stop
1
0
Normal
1
1
(1)
VX,
VX,
STOP
PACLK/PLLCLK/REFCLK (1)
STOP
PACLKB/PLLCLKB/REFCLKB
Depending on the state of S0, S1, and S2
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage range (2)
VO
Output voltage range at any output terminal
VI
Input voltage rangeat any input terminal
–0.5 V to 4 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
DISSIPATION RATINGS
(1)
4
PACKAGE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C (1)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBQ
1400 mW
11 mW/°C
905 mW
740 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
VIH
High-level input voltage (CMOS)
VIL
Low-level input voltage (CMOS)
Initial phase error at phase detector inputs
(required range for phase aligner)
VIL
REFCLK low-level input voltage
VIH
REFCLK high-level input voltage
VIL
Input signal low voltage (STOPB)
VIH
Input signal high voltage (STOPB)
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
0.7 × VDD
V
–0.5 × tc(PD)
0.3 × VDD
V
0.5 × tc(PD)
V
0.3 × VDDIR
V
0.7 × VDDIR
V
0.3 × VDDIPD
0.7 × VDDIPD
V
Input reference voltage for (REFCLK) (VDDIR)
1.235
3.465
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)
1.235
3.465
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
V
–40
V
V
–16
mA
16
mA
85
°C
TIMING REQUIREMENTS
tc(in)
Input cycle time
MIN
MAX
10
40
ns
250
ps
Input cycle-to-cycle jitter
Input duty cycle over 10,000 cycles
fmod
Input frequency modulation
40%
30
Modulation index, nonlinear maximum 0.5%
Phase detector input cycle time (PCLKM and SYNCLKN)
SR
Input slew rate
Input duty cycle (PCLKM and SYNCLKN)
UNIT
60%
33
kHz
0.6%
30
100
1
4
25%
75%
ns
V/ns
5
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN TYP (2)
MAX
UNIT
VO(STOP)
Output voltage during CLK Stop (STOPB = 0)
See Figure 1
1.1
2
VO(X)
Output crossing-point voltage
See Figure 1 and Figure 6
1.3
1.8
V
VO
Output voltage swing
See Figure 1
0.4
0.6
V
VIK
Input clamp voltage
VDD = 3.135 V,
–1.2
V
II = –18 mA
See Figure 1
VOH
High-level output voltage
2
VDD = min to max,
IOH = –1 mA
VDD = 3.135 V,
IOH = –16 mA
See Figure 1
VOL
Low-level output voltage
IOH
High-level output current
VDD = min to max,
IOH = 1 mA
0.1
VDD = 3.135 V,
IOH = 16 mA
0.5
VDD = 3.135 V,
VO = 1 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.465 V,
VO = 3.135 V
VDD = 3.135 V,
VO = 1.95 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.465 V,
VO = 0.4 V
Low-level output current
IOZ
High-impedance-state output current
S0 = 0, S1 = 1
IOZ(STOP)
High-impedance-state output current
during CLK stop
Stop = 0, VO = GND or VDD
IOZ(PD)
High-impedance-state output current in
power-down state
PWRDNB = 0, VO = GND or VDD
IIH
High-level input
current
Low-level input
current
IIL
ZO
Output impedance
Reference current
PWRDNB, S0, S1,
S2, MULT0, MULT1
REFCLK, PCLKM,
SYNCLKN, STOPB
PWRDNB, S0, S1,
S2, MULT0, MULT1
V
2.4
1
IOL
REFCLK, PCLKM,
SYNCLKN, STOPB
VDD– 0.1
–32
–52
–51
–14.5
43
V
mA
–21
61.5
65
25.5
–10
mA
36
±10
µA
±100
µA
100
µA
10
VDD = 3.465 V,
µA
VI = VDD
10
–10
VDD = 3.465 V,
µA
VI = 0
–10
High state
RI at IO– 14.5 mA to –16.5 mA
15
35
50
Low state
RI at IO 14.5 mA to 16.5 mA
11
17
35
VDDIR, VDDIPD
VDD = 3.465 V
Ω
PWRDNB = 0
50
µA
PWRDNB = 1
0.5
mA
CI
Input capacitance
VI = VDD or GND
2
pF
CO
Output capacitance
VO = VDD or GND
3
pF
Supply current in pwoer-down state
REFCLK = 0 MHz to 100 MHz,
PWDNB = 0, STOPB = 1
IDD(PD)
IDD(CLKSTOP) Supply current in CLK stop state
BUSCLK configured for 533 MHz
IDD(NORMAL)
BUSCLK = 533 MHz
(1)
(2)
6
Supply current in normal state
VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP
All typical values are at VDD = 3.3 V, TA = 25°C.
100
µA
45
mA
100
mA
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
tc(out)
TEST CONDITIONS
Clock output cycle time
MIN
TYP (1) MAX
1.87
3.75
267 MHz
t(jitter)
Total cycle jitter over 1, 2,
3, 4, 5, or 6 clock cycles
Infinite and
stopped phase
alignment
300 MHz
356 MHz
70
See Figure 3
60
400 MHz
Phase detector phase error for distributed loop
t(phase, SSC) PLL output phase error when tracking SSC
I(DC)
Output duty cycle over 10,000 cycles
err)
Output cycle-to-cycle duty
cycle error
Infinite and
stopped phase
alignment
40
Static phase error (3)
–100
100
ps
Dynamic phase error (3)
–100
100
ps
See Figure 4
45%
55%
80
300 MHz
356 MHz
ps
50
267 MHz
t(DC,
ns
80
533 MHz (2)
t(phase)
UNIT
70
See Figure 5
60
400 MHz
ps
50
533 MHz
50
tr, tf
Output rise and fall times (measured at 20%–80% of output
voltage)
See Figure 7
∆t
Difference between rise and fall times on a single device
(20%–80%) |tf– tr|
See Figure 7
(1)
(2)
(3)
All typical values are at VDD = 3.3 V, TA = 25°C.
Jitter measurement according to Rambus validation specification
Assured by design
160
400
ps
100
ps
MAX
UNIT
STATE TRANSITION LATENCY SPECIFICATIONS
PARAMETER
t(powerup)
Delay time, PWRDNB↑ to CLK/CLKB output
settled (excluding t(DISTLOCK))
Delay time, PWRDNB↑ to internal PLL and
clock are on and settled
t(VDDpowerup) Delay time, power up to CLK/CLKB output
settled
Delay time, power up to internal PLL and
clock are on and settled
t(MULT)
MULT0 and MULT1 change to CLK/CLKB
output resettled (excluding t(DISTLOCK))
t(CLKON)
t(CLKSETL)
FROM
TO
Powerdown
Normal
TEST
CONDITIONS
See Figure 8
3
ms
3
See Figure 8
VDD
3
Normal
ms
3
Normal
Normal
STOPB↑ to CLK/CLKB glitch-free clock
edges
CLK Stop
Normal
STOPB↑ to CLK/CLKB output settled to
within 50 ps of the phase before
STOPB was disabled
CLK Stop
Normal
t(CLKOFF)
STOPB↓ to CLK/CLKB output disabled
Normal
CLK Stop
t(powerdown)
Delay time, PWRDNB↓ to the device in the
power-down mode
Normal
t(STOP)
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode (STOPB = 1)
STOPB
Normal
See Figure 10
t(ON)
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
Normal
CLK Stop
See Figure 10
t(DISTLOCK)
Time from when CLK/CLKB output is settled
to when the phase error between SYNCLKN
and PCLKM falls within t(phase)
Unlocked
Locked
(1)
MIN TYP (1)
See Figure 9
1
ms
10
ns
See Figure 10
20
cycles
See Figure 10
5
ns
1
ms
100
µs
See Figure 10
Powerdown See Figure 8
100
ms
5
ms
All typical values are at VDD = 3.3 V, TA = 25°C.
7
CDCFR83A
www.ti.com
SCAS812 – AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
68 Ω, ±5%
39 Ω, ±5%
10 pF
39 Ω, ±5%
68 Ω, ±5%
RT = 28 Ω
RT = 28 Ω
100 pF
10 pF
Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL)
CLK
CLKB
tc(1)
tc(2)
Cycle-to-cycle jitter = | tc(1) − tc(2)| over 10000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
CLK
CLKB
tc(3)
tc(4)
Cycle-to-cycle jitter = | tc(3) − tc(4)| over 10000 consecutive cycles
Figure 3. Short Term Cycle-to-Cycle Jitter Over Four Cycles
CLK
CLKB
tpd(1)
tc(5)
Duty cycle = (tpd(1)/tc(5))
Figure 4. Output Duty Cycle
8
CDCFR83A
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SCAS812 – AUGUST 2005
PARAMETER MEASUREMENT INFORMATION (continued)
CLK
CLKB
tpd(2)
tpd(3)
tc(6)
tc(7)
Duty cycle error = tpd(2) − tpd(3)
Figure 5. Duty Cycle Error (Cycle-to-Cycle)
CLK
VO(X)+
VO(X), nom
VO(X)−
CLKB
Figure 6. Crossing-Point Voltage
VOH
80%
20%
VOL
tr
tf
Figure 7. Voltage Waveforms
PWRDNB
CLK/CLKB
t(power up)
t(power down)
Figure 8. PWRDNB Transition Timings
MULT0 and/or
MULT1
CLK/CLKB
t(MULT)
Figure 9. MULT Transition Timings
9
CDCFR83A
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SCAS812 – AUGUST 2005
PARAMETER MEASUREMENT INFORMATION (continued)
t(ON)
t(STOP)
STOPB
t(CLKSETL)
t(CLKON)
(see Note A)
CLK/CLKB
Output clock
not specified
glitches ok
A.
Clock enabled
and glitch free
Clock output settled
within 50 ps of the
phase before disabled
Vref = VO± 200 mV
Figure 10. STOPB Transition Timings
10
t(CLKOFF)
(see Note A)
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCFR83ADBQR
Package Package Pins
Type Drawing
SSOP
DBQ
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCFR83ADBQR
SSOP
DBQ
24
2500
367.0
367.0
38.0
Pack Materials-Page 2
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