Cypress CY7C1257V18-375BZXI 36-mbit ddr-ii sram 2-word burst architecture (2.0 cycle read latency) Datasheet

CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.0 Cycle Read Latency)
Features
Functional Description
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36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
300 MHz to 375 MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) @ 375 MHz
• Read latency of 2.0 clock cycles
• Two input clocks (K and K) for precise DDR timing
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•
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The CY7C1246V18, CY7C1257V18, CY7C1248V18, and
CY7C1250V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of
an SRAM core with advanced synchronous peripheral
circuitry. Addresses for read and write are latched on alternate
rising edges of the input (K) clock. Write data is registered on
the rising edges of both K and K. Read data is driven on the
rising edges of both K and K. Each address location is
associated with two 8-bit words (CY7C1246V18), 9-bit words
(CY7C1257V18), 18-bit words (CY7C1248V18), or 36-bit
words (CY7C1250V18) that burst sequentially into or out of the
device.
— SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both in Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, which share the
same physical pins with the data inputs, D) are tightly matched
to the two output echo clocks CQ/CQ, eliminating the need to
capture data separately from individual DDR SRAMs in the
system design.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1246V18 – 4M x 8
CY7C1257V18 – 4M x 9
CY7C1248V18 – 2M x 18
CY7C1250V18 – 1M x 36
Selection Guide
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
1210
1080
1000
mA
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation
Document Number: 001-06348 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 15, 2007
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
K
K
DOFF
VREF
R/W
NWS[1:0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
2M x 8 Array
21
2M x 8 Array
A(20:0)
Read Add. Decode
Logic Block Diagram (CY7C1246V18)
8
Output
Logic
Control
R/W
Read Data Reg.
16
Control
Logic
8
Reg.
Reg.
CQ
8
CQ
8
8
DQ[7:0]
8
Reg.
QVLD
K
K
DOFF
VREF
R/W
BWS[0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
2M x 9 Array
21
2M x 9 Array
A(20:0)
Read Add. Decode
Logic Block Diagram (CY7C1257V18)
9
Output
Logic
Control
R/W
Read Data Reg.
18
Control
Logic
9
9
Reg.
Reg.
CQ
9
CQ
9
Reg.
9
DQ[8:0]
QVLD
Document Number: 001-06348 Rev. *C
Page 2 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
K
K
DOFF
VREF
R/W
BWS[1:0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
1M x 18 Array
20
1M x 18 Array
A(19:0)
Read Add. Decode
Logic Block Diagram (CY7C1248V18)
18
Output
Logic
Control
R/W
Read Data Reg.
36
18
Control
Logic
Reg.
18
Reg.
18
Reg.
CQ
18
CQ
DQ[17:0]
18
QVLD
K
K
DOFF
VREF
R/W
BWS[3:0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
512K x 36 Array
19
512K x 36 Array
A(18:0)
Read Add. Decode
Logic Block Diagram (CY7C1250V18)
36
Output
Logic
Control
R/W
Read Data Reg.
72
Control
Logic
36
36
Reg.
Reg.
Reg.
CQ
36
36
CQ
36
DQ[35:0]
QVLD
Document Number: 001-06348 Rev. *C
Page 3 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Pin Configurations
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1246V18 (4M x 8)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC
NC/72M
A
R/W
NWS1
K
NC/144M
LD
A
A
CQ
NC
NC
A
NC/288M
K
NC
NC
DQ3
NC
NC
NC
NC
VSS
VSS
A
VSS
VSS
NC
VSS
A
VSS
NWS0
A
VSS
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
NC
VDDQ
VDD
VSS
VDDQ
DOFF
NC
DQ5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
NC
VREF
NC
VDD
VDD
VDD
VDD
NC
VREF
DQ1
NC
NC
ZQ
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ7
A
A
QVLD
A
A
NC
NC
NC
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
6
7
8
9
10
11
K
K
NC/144M
LD
A
A
A
CQ
NC
NC
DQ3
CY7C1257V18 (4M x 9)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
NC/72M
A
NC
NC
NC
NC
NC
NC
NC
NC
4
5
R/W
A
NC
NC/288M
VSS
VSS
VSS
A
VSS
A
BWS0
A
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DOFF
NC
NC
VREF
NC
DQ5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
DQ1
NC
ZQ
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
DQ7
A
A
QVLD
A
A
NC
NC
DQ8
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-06348 Rev. *C
Page 4 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1248V18 (2M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
NC/72M
A
DQ9
NC
NC
NC
NC
NC
DQ10
NC
4
5
6
7
NC/144M
R/W
A
BWS1
NC/288M
K
K
VSS
VSS
A
VSS
NC
VSS
8
9
10
11
LD
A
A
A
CQ
NC
NC
DQ8
NC
NC
BWS0
A
VSS
VSS
VSS
NC
NC
DQ7
NC
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
NC
DOFF
NC
NC
VREF
NC
DQ13
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
DQ4
NC
ZQ
NC
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
NC
NC
DQ16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
DQ1
NC
NC
NC
NC
NC
DQ17
A
A
QVLD
A
A
NC
NC
DQ0
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
7
8
9
10
11
A
NC/72M
CQ
CY7C1250V18 (1M x 36)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
NC/144M
A
4
DQ27
DQ18
R/W
A
NC
NC
NC
DQ29
DQ28
DQ19
VSS
VSS
NC
NC
DQ20
NC
NC
DQ30
DQ21
DOFF
NC
DQ31
VREF
NC
DQ22
VDDQ
DQ32
NC
NC
5
BWS2
6
BWS1
BWS0
A
VSS
LD
A
NC
NC
DQ8
VSS
VSS
NC
NC
DQ17
NC
DQ7
DQ16
VSS
VSS
VDDQ
NC
DQ15
DQ6
VSS
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
NC
VREF
DQ13
DQ5
DQ14
ZQ
DQ4
VSS
VDD
VDDQ
NC
DQ12
DQ3
K
K
BWS3
A
VSS
NC
VSS
VDDQ
VSS
VDDQ
VDD
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
DQ23
VDDQ
VDD
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
NC
NC
NC
DQ35
DQ34
DQ25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
DQ11
NC
DQ1
DQ10
NC
NC
DQ26
A
A
QVLD
A
A
NC
DQ9
DQ0
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-06348 Rev. *C
Page 5 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Pin Definitions
Pin Name
IO
Pin Description
DQ[x:0]
Input/Output- Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during
Synchronous valid write operations. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K clocks during read operations. When
read access is deselected, Q[x:0] are automatically tri-stated.
CY7C1246V18 − DQ[7:0]
CY7C1257V18 − DQ[8:0]
CY7C1248V18 − DQ[17:0]
CY7C1250V18 − DQ[35:0]
LD
InputSynchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and read/write direction. All transactions operate on a burst of
2 data. LD must meet the setup and hold times around edge of K.
NWS0, NWS1 InputSynchronous
Nibble Write Select 0, 1, Active LOW (CY7C1246V18 only). Sampled on the rising edge of
the K and K clocks during write operations. Used to select which nibble is written into the device
during the current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select causes the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
BWS2, BWS3
InputByte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1257V18 − BWS0 controls D[8:0]
CY7C1248V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1250V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select causes the corresponding byte of data to be ignored and not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operaSynchronous tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1246V18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1257V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1248V18, and
1M x 36 (2 arrays each of 512K x 36) for CY7C1250V18.
R/W
InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (read
Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and
hold times around edge of K.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ.
K
InputClock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
InputClock
Negative Input Clock Input. K is used to capture synchronous data being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22.
Document Number: 001-06348 Rev. *C
Page 6 of 27
[+] Feedback
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Pin Definitions (continued)
Pin Name
IO
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with DDR-I timing.
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs,
and AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Document Number: 001-06348 Rev. *C
Page 7 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Functional Overview
The CY7C1246V18, CY7C1257V18, CY7C1248V18, and
CY7C1250V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input and output timing refer to the
rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the input
clocks (K and K).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K\K).
CY7C1248V18 is described in the following sections. The
same basic descriptions apply to CY7C1246V18,
CY7C1257V18, and CY7C1250V18.
Read Operations
The CY7C1248V18 is organized internally as a single array of
2M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). Following the next two K clock rising edges, the
corresponding 18-bit word of data from this address location
is driven onto the Q[17:0] using K as the output timing
reference. On the subsequent rising edge of K the next 18-bit
data word is driven onto the Q[17:0]. The requested data is valid
0.45 ns from the rising edge of the input clock (K and K). To
maintain the internal logic, each read access must be allowed
to complete. Read accesses can be initiated on every rising
edge of the positive input clock (K).
When read access is deselected, the CY7C1248V18
completes the pending read transactions. Synchronous
internal circuitry automatically tri-states the outputs following
the next rising edge of the positive input clock (K). This
enables a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
Address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit Write
Data register, provided BWS[1:0] are both asserted active. On
the subsequent rising edge of the Negative Input Clock (K), the
information presented to D[17:0] is also stored into the Write
Data register, provided BWS[1:0] are both asserted active. The
36 bits of data are then written into the memory array at the
specified location. Write accesses can be initiated on every
rising edge of the positive input clock (K). Doing so pipelines
the data flow such that 18 bits of data can be transferred into
the device on every rising edge of the input clocks (K and K).
When write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Document Number: 001-06348 Rev. *C
Byte Write Operations
Byte write operations are supported by the CY7C1248V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0
and BWS1, which are sampled with each set of 18-bit data
words. Asserting the appropriate Byte Write Select input
during the data portion of a write enables the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write enables the data stored in the device for that byte to
remain unaltered. This feature can be used to simplify
read/modify/write operations to a byte write operation.
Double Data Rate Operation
The CY7C1248V18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and DDR mode of operation. The CY7C1248V18 requires two
No Operation (NOP) cycles when transitioning from a read to
a write cycle. At higher frequencies, some applications may
require a third NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the
write are stored in registers. The write information must be
stored because the SRAM cannot perform the last word write
to the array without conflicting with the read. The data stays in
this register until the next write cycle occurs. On the first write
cycle after the read(s), the stored data from the earlier write is
written into the SRAM array. This is called a Posted Write.
If a read is performed on the same address on which a write
is performed in the previous cycle, the SRAM reads out the
most current data. The SRAM does this by bypassing the
memory array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to enable the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15%, is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data
capture on high speed systems. Two echo clocks are
generated by the DDR-II+. CQ is referenced with respect to K
and CQ is referenced with respect to K. These are
free-running clocks and are synchronized to the input clock of
the DDR-II+. The timing for the echo clocks is shown in
“Switching Characteristics” on page 22.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on
high speed systems. The QVLD is generated by the DDR-II+
Page 8 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
device along with data output. This signal is also edge aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. The
DLL may be disabled by applying ground to the DOFF pin.
When the DLL is turned off, the device behaves in DDR-I mode
(with 1.0 cycle latency and a longer access time). For more
information, refer to the application note, DLL Considerations
in QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of
30 ns. However, it is not necessary for the DLL to be reset to
lock to the desired frequency. During power up, when the
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
Application Example
Figure 1 shows the use of two DDR-II+ in an application.
Figure 1. Application Example
DQ
A
SRAM#1
LD
R/W
ZQ
CQ/CQ
K K
DQ
A
R = 250ohms
SRAM#2
LD
R/W
ZQ
CQ/CQ
K K
R = 250ohms
DQ
Addresses
BUS
Cycle
Start
MASTER
R/W
(CPU or ASIC)
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Truth Table
The truth table for the CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 follows.[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
L-H
L
L
D(A) at K(t + 1) ↑
D(A + 1) at K(t + 1) ↑
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle; read data on consecutive K and
K rising edges.
L-H
L
H
Q(A) at K(t + 2) ↑
Q(A + 1) at K(t + 2) ↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
DQ
DQ
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document Number: 001-06348 Rev. *C
Page 9 of 27
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CY7C1257V18
CY7C1248V18
CY7C1250V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1246V18 and CY7C1248V18 follows.[2, 8]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence :
CY7C1246V18 − both nibbles (D[7:0]) are written into the device,
CY7C1248V18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence :
CY7C1246V18 − both nibbles (D[7:0]) are written into the device,
CY7C1248V18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence :
CY7C1246V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1248V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence :
CY7C1246V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1248V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence :
CY7C1246V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1248V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence :
CY7C1246V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1248V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle descriptions table for CY7C1257V18 follows.[2, 8]
BWS0
K
K
Comments
L
L-H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L-H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L-H
–
No data is written into the device during this portion of a write operation.
H
–
L-H
No data is written into the device during this portion of a write operation.
Note
8. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are met.
Document Number: 001-06348 Rev. *C
Page 10 of 27
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CY7C1257V18
CY7C1248V18
CY7C1250V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1250V18 follows.[2, 8]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L-H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
–
L
H
H
H
L-H
L
H
H
H
–
H
L
H
H
L-H
H
L
H
H
–
H
H
L
H
L-H
H
H
L
H
–
H
H
H
L
L-H
H
H
H
L
–
H
H
H
H
L-H
H
H
H
H
–
Document Number: 001-06348 Rev. *C
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L-H No data is written into the device during this portion of a write operation.
Page 11 of 27
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CY7C1257V18
CY7C1248V18
CY7C1250V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-2001. The TAP operates using
JEDEC standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternately be connected
to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state
which does not interfere with the operation of the device.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in “TAP Controller Block Diagram”
on page 15. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
enable fault isolation of the board level serial test path.
Bypass Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Mode Select
Boundary Scan Register
Test Access Port – Test Clock
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. You can leave this
pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information about loading the instruction register, see “TAP
Controller State Diagram” on page 14. TDI is internally pulled
up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on
any register.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and
output ring.
“Boundary Scan Order” on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine (see “Instruction Codes” on
page 17). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in “Identification Register Definitions” on page 17.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Document Number: 001-06348 Rev. *C
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction
Codes” on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction after it is shifted in, the TAP
controller must be moved into the Update-IR state.
Page 12 of 27
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CY7C1257V18
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CY7C1250V18
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state. The IDCODE
instruction is loaded into the instruction register upon power
up or whenever the TAP controller is in a Test-Logic-Reset
state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
issued during the Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Document Number: 001-06348 Rev. *C
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
before the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required — that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state,” is latched into the preload register during the
Update-DR state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered
as the current instruction. When HIGH, it enables the output
buffers to drive the output bus. When LOW, this bit places the
output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit
directly controls the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 27
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CY7C1257V18
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CY7C1250V18
TAP Controller State Diagram
The state diagram for the TAP controller follows.[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
SHIFT-IR
1
0
1
0
UPDATE-IR
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06348 Rev. *C
Page 14 of 27
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CY7C1257V18
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CY7C1250V18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30 29
.
.
2
Identification Register
108 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range[10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 µA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
−5
5
µA
Notes
10. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.
11. Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2).
12. All voltage refers to ground.
Document Number: 001-06348 Rev. *C
Page 15 of 27
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CY7C1257V18
CY7C1248V18
CY7C1250V18
TAP AC Switching Characteristics
Over the Operating Range[13, 14]
Parameter
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
20
MHz
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions.[14]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
50Ω
1.8V
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-06348 Rev. *C
Page 16 of 27
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CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Identification Register Definitions
Value
Instruction
Field
Description
CY7C1246V18
CY7C1257V18
CY7C1248V18
CY7C1250V18
Revision
Number (31:29)
000
000
000
000
Cypress Device
ID (28:12)
11010111100000111
11010111100001111
11010111100010111
Cypress JEDEC
ID (11:1)
00000110100
00000110100
00000110100
00000110100
Enables unique
identification of
SRAM vendor.
1
1
1
1
Indicates the
presence of an
ID register.
ID Register
Presence (0)
Version number.
11010111100100111 Defines the type
of SRAM.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input/output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input/output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input/output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document Number: 001-06348 Rev. *C
Page 17 of 27
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CY7C1257V18
CY7C1248V18
CY7C1250V18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-06348 Rev. *C
Page 18 of 27
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Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
Power Up Sequence
• Apply power with DOFF tied HIGH (all other inputs can be
HIGH or LOW)
DLL Constraints
• DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
• The DLL functions at frequencies down to 120 MHz.
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. To avoid this, provide 2048 cycles
stable clock to relock to the desired clock frequency.
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• Provide stable power and clock (K, K) for 2048 cycles to
lock the DLL
Power Up Waveforms
~
~
Figure 3. Power Up Waveforms
K
~
~
K
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)
VDD/VDDQ
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
DOFF
Document Number: 001-06348 Rev. *C
Fix HIGH (tie to VDDQ)
Page 19 of 27
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Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch up Current..................................................... >200 mA
Operating Range
Ambient Temperature with Power Applied . –55°C to + 125°C
Supply Voltage on VDD Relative to GND....... –0.5V to + 2.9V
Range
Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD
Com’l
DC Applied to Outputs in High-Z..........–0.5V to VDDQ + 0.3V
Ind’l
Ambient
Temperature
VDD[15]
VDDQ[15]
0°C to +70°C
1.8 ± 0.1V
1.4V to VDD
–40°C to +85°C
DC Input Voltage[11] ...............................–0.5V to VDD + 0.3V
Electrical Characteristics
Over the Operating Range [12]
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 16
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 17
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = –0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
–2
2
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
–2
2
µA
0.95
V
VDD = Max., IOUT = 0 mA, 300 MHz
f = fMAX = 1/tCYC
333 MHz
1000
mA
1080
mA
375 MHz
1210
mA
300 MHz
290
mA
333 MHz
300
mA
375 MHz
320
mA
Voltage[18]
VREF
Input Reference
IDD
VDD Operating Supply
ISB1
Automatic Power Down
Current
Typical Value = 0.75V
Max. VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
0.68
0.75
AC Input Requirements
Over the Operating Range [11]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
–
VREF – 0.2
V
\
Notes
15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
18. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 001-06348 Rev. *C
Page 20 of 27
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Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Max.
Unit
5
pF
4
pF
5
pF
Test Conditions
165 FBGA
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.25
°C/W
2.91
°C/W
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
RL = 50Ω
VREF = 0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[19]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Note
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-06348 Rev. *C
Page 21 of 27
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Switching Characteristics
Over the Operating Range [19, 20]
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the first Access[21]
tPOWER
375 MHz
333 MHz
300 MHz
Min Max Min Max Min Max
1
–
1
–
1
–
Unit
ms
tCYC
tKHKH
K Clock Cycle Time
2.66
8.4
3.0
8.4
3.3
8.4
ns
tKH
tKHKL
Input Clock (K/K) HIGH
0.4
–
0.4
–
0.4
–
tCYC
tKL
tKLKH
Input Clock (K/K) LOW
0.4
–
0.4
–
0.4
–
tCYC
tKHKH
tKHKH
K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13
–
1.28
–
1.40
–
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.4
–
ns
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K, K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.28
–
0.28
–
0.28
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
ns
Address Hold after K Clock Rise
Control Hold after K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
ns
Hold Times
tHA
tKHAX
tHC
tKHIX
0.4
–
0.4
–
0.4
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.28
–
0.28
–
0.28
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
ns
–
0.45
–
0.45
–
0.45
ns
–
–0.45
–
–0.45
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
tDOH
tCHQX
Data Output Hold after K/K Clock Rise (Active to Active) –0.45
tCCQO
tCHCQV
tCQOH
tCHCQX
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH[22]
tCQHCQH
tCQHCQH
tCHZ
tCHQZ
CQ Clock Rise to CQ Clock Rise[22]
(rising edge to rising edge)
Clock (K/K) Rise to High-Z (Active to High-Z)[23, 24]
tCLZ
tQVLD
tCHQX1
tCQHQVLD
[23, 24]
Clock (K/K) Rise to Low-Z
Echo Clock High to QVLD Valid
[25]
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
ns
–
0.2
–
0.2
–
0.2
ns
–0.2
–
–0.2
–
–0.2
–
ns
0.88
–
1.03
–
1.15
–
ns
0.88
–
1.03
–
1.15
–
ns
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
ns
–0.20 0.20 –0.20 0.20 –0.20 0.20
ns
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL Lock Time (K)
2048
–
2048
–
2048
–
Cycles
tKC Reset
tKC Reset
K Static to DLL Reset[26]
30
–
30
–
30
–
ns
Notes
20. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is
being operated and will output data with the output timing of that frequency range.
21. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
22. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.
23. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±100 mV from steady-state
voltage.
24. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
25. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
26. Hold to >VIH or <VIL.
Document Number: 001-06348 Rev. *C
Page 22 of 27
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Switching Waveforms
Read/Write/Deselect Sequence[27, 28, 29]
Figure 5. Waveform for 2.0 Cycle Read Latency
NOP
1
READ
2
NOP
4
READ
3
NOP
5
NOP
6
WRITE
7
WRITE
8
READ
9
NOP
10
NOP
11
12
K
t KH
tCYC
t KL
t KHKH
K
LD
tSC tHC
R/W
A
A0
t SA t HA
A3
A2
A1
A4
t QVLD
tQVLD
t QVLD
QVLD
tHD
t HD
tSD
Q00
DQ
t
Q01 Q10
tCO
t CQOH
CQ
t CQOH
D20 D21
D30
D31
Q40 Q41
t CHZ
t DOH
CLZ
(Read Latency = 2.0 Cycles)
Q11
tSD
t CQD
t CCQO
t CCQO
t CQDOH
t CQH
t CQHCQH
CQ
DON’T CARE
UNDEFINED
Notes
27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
28. Outputs are disabled (High-Z) one clock cycle after a NOP.
29. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency
operation, it may be required to avoid bus contention.
Document Number: 001-06348 Rev. *C
Page 23 of 27
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
375
Ordering Code
CY7C1246V18-375BZC
Package
Diagram
Operating
Range
Package Type
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1257V18-375BZC
CY7C1248V18-375BZC
CY7C1250V18-375BZC
CY7C1246V18-375BZXC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-375BZXC
CY7C1248V18-375BZXC
CY7C1250V18-375BZXC
CY7C1246V18-375BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1257V18-375BZI
CY7C1248V18-375BZI
CY7C1250V18-375BZI
CY7C1246V18-375BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-375BZXI
CY7C1248V18-375BZXI
CY7C1250V18-375BZXI
333
CY7C1246V18-333BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1257V18-333BZC
CY7C1248V18-333BZC
CY7C1250V18-333BZC
CY7C1246V18-333BZXC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-333BZXC
CY7C1248V18-333BZXC
CY7C1250V18-333BZXC
CY7C1246V18-333BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1257V18-333BZI
CY7C1248V18-333BZI
CY7C1250V18-333BZI
CY7C1246V18-333BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-333BZXI
CY7C1248V18-333BZXI
CY7C1250V18-333BZXI
Document Number: 001-06348 Rev. *C
Page 24 of 27
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Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
300
Ordering Code
CY7C1246V18-300BZC
Package
Diagram
Operating
Range
Package Type
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1257V18-300BZC
CY7C1248V18-300BZC
CY7C1250V18-300BZC
CY7C1246V18-300BZXC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-300BZXC
CY7C1248V18-300BZXC
CY7C1250V18-300BZXC
CY7C1246V18-300BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1257V18-300BZI
CY7C1248V18-300BZI
CY7C1250V18-300BZI
CY7C1246V18-300BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1257V18-300BZXI
CY7C1248V18-300BZXI
CY7C1250V18-300BZXI
Document Number: 001-06348 Rev. *C
Page 25 of 27
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Package Diagram
Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
"/44/- 6)%7
4/0 6)%7
Π- # ! "
0). #/2.%2
Œ
0). #/2.%2
Π- #
8
!
"
"
#
#
!
$
$
&
&
'
'
(
*
%
¼
%
(
*
+
,
,
+
-
-
.
.
0
0
2
2
!
"
¼
#
¼
¼
#
8
./4%3 3/,$%2 0!$ 490% ./. 3/,$%2 -!3+ $%&).%$ .3-$
0!#+!'% 7%)'(4 G
*%$%# 2%&%2%.#% -/ $%3)'. #
0!#+!'% #/$% ""!$
-!8
3%!4).' 0,!.%
#
51-85195-*A
Document Number: 001-06348 Rev. *C
Page 26 of 27
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only
in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except
as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document History Page
Document Title: CY7C1246V18/CY7C1257V18/CY7C1248V18/CY7C1250V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Document Number: 001-06348
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
425689
See ECN
NXR
New Data Sheet
*A
461639
See ECN
NXR
Revised the MPNs from
CY7C1257AV18 to CY7C1257V18
CY7C1248AV18 to CY7C1248V18
CY7C1250AV18 to CY7C1250V18
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,
tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP
AC Switching Characteristics table
Modified Power-Up waveform
*B
497628
See ECN
NXR
Changed the VDDQ operating voltage to 1.4V to VDD in the Features section,
in Operating Range table and in the DC Electrical Characteristics table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Changed VREF (Max.) spec from 0.85V to 0.95V in the DC Electrical
Characteristics table and in the note below the table
Updated foot note #17 to specify Overshoot and Undershoot Spec
Updated ΘJA and ΘJC values
Removed x9 part and its related information
Updated footnote #24
*C
1093183
See ECN
VKN
Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed IDD values from 925 mA to 1210 mA for 375 MHz, 800 mA to 1080
mA for 333 MHz, 725 mA to 1000 mA for 300 MHz
Changed ISB values from 290 mA to 320 mA for 375 MHz, 270 mA to 300
mA for 333 MHz, 250 mA to 290 mA for 300 MHz
Changed ΘJA value from 12.43 °C/W to 16.25 °C/W
Changed tCYC max spec to 8.4 ns for all speed bins
Updated Ordering Information table
Document Number: 001-06348 Rev. *C
Page 27 of 27
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