TI1 ALS174 Hex/quadruple d-type flip-flop Datasheet

SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
D
D
D
’ALS174 and ’AS174 Contain Six Flip-Flops
With Single-Rail Outputs
’ALS175 and ’AS175B Contain Four
Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
SN54ALS174 . . . J OR W PACKAGE
SN54AS174 . . . J PACKAGE
SN74ALS174, SN74AS174 . . . D , N, OR NS PACKAGE
(TOP VIEW)
CLR
1Q
1D
2D
2Q
3D
3Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
D
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(’AS Only)
SN54ALS175 . . . J OR W PACKAGE
SN54AS175B . . . J PACKAGE
SN74ALS175, SN74AS175B . . . D, N, OR NS PACKAGE
(TOP VIEW)
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
VCC
6Q
6D
5D
5Q
4D
4Q
CLK
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4Q
4Q
4D
3D
3Q
3Q
CLK
1Q
CLR
NC
VCC
4Q
6D
5D
NC
5Q
4D
1Q
1D
NC
2D
2Q
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4Q
4D
NC
3D
3Q
2Q
GND
NC
CLK
3Q
3Q
GND
NC
CLK
4Q
1D
2D
NC
2Q
3D
16
SN54ALS175 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
VCC
6Q
SN54ALS174, SN54AS174 . . . FK PACKAGE
(TOP VIEW)
1
NC – No internal connection
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
ORDERING INFORMATION
PDIP – N
0°C to 70°C
Tube
SOIC – D
SOP – NS
CFP – W
SN74AS174N
SN74AS174N
SN74ALS175N
SN74ALS175N
SN74AS175BN
SN74AS175BN
SN74ALS174D
SN74ALS174DR
Tube
SN74AS174D
Tape and reel
SN74AS174DR
Tube
SN74ALS175D
Tape and reel
SN74ALS175DR
Tube
SN74AS175BD
Tape and reel
SN74AS175BDR
Tube
LCCC – FK
SN74ALS174N
Tape and reel
Tube
Tube
TOP-SIDE
MARKING
SN74ALS174N
Tube
Tape and reel
CDIP – J
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
ALS174
AS174
ALS175
AS175B
SN74ALS174NSR
ALS174
SN74AS174NSR
74AS174
SN74ALS175NSR
ALS175
SN74AS175BNSR
74AS175B
SNJ54ALS174J
SNJ54ALS174J
SNJ54AS174J
SNJ54AS174J
SNJ54ALS175J
SNJ54ALS175J
SNJ54AS175BJ
SNJ54AS175BJ
SNJ54ALS174W
SNJ54ALS174W
SNJ54ALS175W
SNJ54ALS175W
SNJ54ALS174FK
SNJ54AS174FK‡
SNJ54ALS174FK
SNJ54ALS175FK
SNJ54AS174FK
SNJ54ALS175FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡ This orderable is not recommended for new designs.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
OUTPUTS
D
Q
Q§
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
§ ’ALS175 and ’AS175B only
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
logic diagrams (positive logic)
’ALS174, ’AS174
CLR
CLK
1D
’ALS175, ’AS175B
1
CLK
9
CLR
3
1D
1D
C1
2
9
1
4
2
1D
1Q
1Q
C1
R
3
R
To Five Other Channels
1Q
To Three Other Channels
Pin numbers shown are for the D, J, N, NS, and W packages.
absolute maximum ratings over operating free-air temperature range, SN54/74ALS174,
SN54/74ALS175 (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54ALS174
SN54ALS175
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
TA
Low-level output current
High-level input voltage
SN74ALS174
SN74ALS175
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
2
High-level output current
2
–55
V
V
0.8
0.8
V
–0.4
–0.4
mA
8
mA
70
°C
4
Operating free-air temperature
UNIT
MIN
125
0
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
SN54ALS174
SN54ALS175
TEST CONDITIONS
MIN
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = –18 mA
IOH = –0.4 mA
VOL
VCC = 4
4.5
5V
IOL = 4 mA
IOL = 8 mA
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
All others
CLK
IO‡
ICC
’ALS174
’ALS175
5V
VCC = 5
5.5
V,
4V
VI = 0
0.4
VCC = 5.5 V,
VO = 2.25 V
VCC = 5
5.5
5V
V,
See Note 3
TYP†
SN74ALS174
SN74ALS175
MAX
MIN
TYP†
–1.5
VCC– 2
UNIT
MAX
–1.5
VCC– 2
0.25
0.4
V
0.25
0.4
0.35
0.5
V
0.1
0.1
mA
20
20
µA
–0.1
–0.1
–0.15
–20
V
–112
–30
–112
11
19
11
19
8
14
9
14
mA
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 3: ICC is measured with D inputs and CLR grounded, and CLK at 4.5 V.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS174
SN54ALS175
MIN
fclock
Clock frequency
40
Pulse duration
CLK high
12.5
10
CLK low
12.5
10
Set p time before CLK↑
Setup
15
10
8
6
th
Hold time, data after CLK↑
0
0
CLR inactive
UNIT
MAX
50
10
Data
tsu
MIN
15
CLR low
tw
MAX
SN74ALS174
SN74ALS175
MHz
ns
ns
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX§
SN54ALS174
SN74ALS174
SN54ALS175
SN74ALS175
MIN
fmax
tPLH
MAX
40
MIN
MAX
50
MHz
3
20
5
18
5
30
8
23
3
20
3
Any
yQ
CLK
(or Q, ’ALS175)
tPHL
5
24
5
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
15
tPHL
tPLH
4
CLR
POST OFFICE BOX 655303
Anyy Q
(or Q, ’ALS175)
• DALLAS, TEXAS 75265
UNIT
17
ns
ns
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
absolute maximum ratings over operating free-air temperature range, SN54/74AS174,
SN54/74AS175B (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54AS174
SN54AS175B
SN74AS174
SN74AS175B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–2
–2
mA
IOL
TA
Low-level output current
20
20
mA
70
°C
High-level input voltage
2
Operating free-air temperature
2
–55
125
V
V
0
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS174
SN54AS175B
MIN
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = –18 mA
IOH = –2 mA
VOL
II
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 20 mA
VI = 7 V
IIH
IIL
IO§
VCC = 5.5 V,
VCC = 5.5 V,
VI = 2.7 V
VI = 0.4 V
VCC = 5.5 V,
VO = 2.25 V
5V
VCC = 5
5.5
V,
See Note 4
ICC
’AS174
’AS175B
TYP‡
SN74AS174
SN74AS175B
MAX
MIN
TYP‡
–1.2
VCC– 2
UNIT
MAX
–1.2
VCC– 2
0.35
0.5
V
0.5
V
0.1
0.35
0.1
mA
20
20
µA
–0.5
mA
–112
mA
–0.5
–30
V
–112
–30
30
45
30
45
22.5
34
22.5
34
mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 4: ICC is measured with D inputs, CLR, and CLK grounded.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54AS174
SN54AS175B
MIN
fclock*
Clock frequency
tsu*
MIN
100
CLR low
tw*
MAX
SN74AS174
SN74AS175B
CLK high
Pulse duration
5
4
4
CLK low
’AS174
6
6
CLK low
’AS175B
5
5
’AS174
4
4
’AS175B
3
3
6
6
Data
Setup time before CLK↑
↑
100
5.5
CLR inactive
UNIT
MAX
MHz
ns
ns
th*
Hold time, data after CLK↑
1
1
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
SN54AS174
SN74AS174
MIN
fmax*
tPHL
tPLH
MAX
100
CLR
Any Q
MIN
UNIT
MAX
100
MHz
5
15
5
14
3.5
9.5
3.5
8
Any Q
CLK
tPHL
4.5
11.5
4.5
10
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
ns
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
SN54AS175B
SN74AS175B
MIN
fmax*
tPLH
tPHL
tPLH
MAX
100
CLR
A Q or Q
Any
CLK
Any Q or Q
MIN
MAX
100
MHz
4
10
4
9
4.5
15
4.5
13
3
8.5
3
7.5
tPHL
3
11
3
10
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC
RL = R1 = R2
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
tPZH
1.3 V
1.3 V
0.3 V
tPHL
≈3.5 V
tPLH
VOL
0.3 V
VOH
1.3 V
3.5 V
Input
1.3 V
tPHZ
Waveform 2
S1 Open
(see Note B)
1.3 V
0.3 V
≈0 V
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9553701QEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9553701QE
A
SNJ54AS175BJ
83019012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83019012A
SNJ54ALS
174FK
8301901EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301901EA
SNJ54ALS174J
8301901FA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301901FA
SNJ54ALS174W
8301902EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301902EA
SNJ54ALS175J
JM38510/37201B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
37201B2A
JM38510/37201BEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
37201BEA
JM38510/37202B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
37202B2A
JM38510/37202BEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
37202BEA
M38510/37201B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
37201B2A
M38510/37201BEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
37201BEA
M38510/37202B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
37202B2A
M38510/37202BEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
37202BEA
SN54ALS174J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54ALS174J
SN54ALS175J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54ALS175J
SN74ALS174D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
Addendum-Page 1
ALS174
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74ALS174DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS174
SN74ALS174DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS174
SN74ALS174DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS174
SN74ALS174N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS174N
SN74ALS174N3
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
0 to 70
SN74ALS174NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS174
SN74ALS175D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS175
SN74ALS175DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS175
SN74ALS175DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS175
SN74ALS175N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS175N
SN74ALS175NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS175N
SN74ALS175NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS175
SN74AS174D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
AS174
SN74AS174N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74AS174N
SN74AS174NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74AS174
SN74AS175BD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AS175B
SN74AS175BN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74AS175BN
SN74AS175BNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74AS175B
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
17-Dec-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54ALS174FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83019012A
SNJ54ALS
174FK
SNJ54ALS174J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301901EA
SNJ54ALS174J
SNJ54ALS174W
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301901FA
SNJ54ALS174W
SNJ54ALS175J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8301902EA
SNJ54ALS175J
SNJ54AS174J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54AS174J
SNJ54AS175BJ
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9553701QE
A
SNJ54AS175BJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B, SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B :
• Catalog: SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
• Military: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74ALS174DR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74ALS174NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74ALS175DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74ALS175NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AS174NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AS175BNSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALS174DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74ALS174NSR
SO
NS
16
2000
367.0
367.0
38.0
SN74ALS175DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74ALS175NSR
SO
NS
16
2000
367.0
367.0
38.0
SN74AS174NSR
SO
NS
16
2000
367.0
367.0
38.0
SN74AS175BNSR
SO
NS
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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