TI1 CY74FCT138CTQCT 1-of-8 decoder Datasheet

CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
O0
O1
O2
O3
O4
O5
O6
CY54FCT138T . . . L PACKAGE
(TOP VIEW)
A1
A0
NC
VCC
O0
D
A0
A1
A2
E1
E2
E3
O7
GND
A2
E1
NC
E2
E3
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
O7
D
CY54FCT138T . . . D PACKAGE
CY74FCT138T . . . Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
Dual 1-of-8 Decoder With Enables
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CY54FCT138T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT138T
– 64-mA Output Sink Current
– 32-mA Output Source Current
O1
O2
NC
O3
O4
GND
NC
O6
O5
D
NC – No internal connection
description
The ’FCT138T devices are 1-of-8 decoders. These devices accept three binary weighted inputs (A0, A1, A2)
and, when enabled, provide eight mutually exclusive active-low outputs (O0–O7). The ’FCT138T devices
feature three enable inputs: two active low (E1, E2) and one active high (E3).
All outputs are high unless E1 and E2 are low and E3 is high. This multiple-enable function allows easy parallel
expansion of the device to a 1-of-32 (five lines to 32 lines) decoder with just four ’FCT138T devices and one
inverter.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
A
DESCRIPTION
Address inputs
E1, E2
Enable inputs (active low)
E3
O
Enable input (active high)
Outputs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
PACKAGE†
TA
QSOP – Q
Tape and reel
5
CY74FCT138CTQCT
Tube
5
CY74FCT138CTSOC
Tape and reel
5
CY74FCT138CTSOCT
Tape and reel
5.8
CY74FCT138ATQCT
Tube
5.8
CY74FCT138ATSOC
Tape and reel
5.8
CY74FCT138ATSOCT
QSOP – Q
Tape and reel
9
CY74FCT138TQCT
LCC – L
Tube
6
CY54FCT138CTLMB
LCC – L
Tube
12
CY54FCT138TLMB
SOIC – SO
–40°C to 85°C
QSOP – Q
SOIC – SO
–55°C to 125°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
FT138-3
FCT138C
FT138-1
FCT138A
FT138
CDIP – D
Tube
12
CY54FCT138TDMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
E1
H
E2
X
E3
X
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H = High logic level, L = Low logic level, X = Don’t care
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
logic diagram (positive logic)
15
A0
A1
A2
14
13
3
12
10
6
9
4
7
E1
E2
O1
2
11
E3
O0
1
O2
O3
O4
O5
O6
O7
5
Pin numbers shown are for the D, Q, and SO packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
recommended operating conditions (see Note 2)
CY54FCT138T
CY74FCT138T
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–32
mA
IOL
TA
Low-level output current
32
64
mA
85
°C
High-level input voltage
2
Operating free-air temperature
2
–55
125
V
V
–40
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT138T
TYP†
MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
ICCD¶
0.3
0.3
0.2
0.55
0.2
±1
±1
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
0.1
0.5
VCC = 5.5 V, Outputs open, One bit switching at 50% duty
cycle, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
VCC = 5.25 V, Outputs open, One bit switching at 50%
duty cycle, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
0.06
–225
±1
0.2
0.1
0.2
0.5
2
2
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
V
V
5
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V,
3.3
0.55
IOL = 64 mA
–60
V
V
2
IOH = –15 mA
IOL = 32 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT138T
TYP†
MAX
MIN
0.12
µA
µA
µA
mA
µA
mA
mA
mA/
MHz
0.06
0.12
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
CY54FCT138T
TYP†
MAX
TEST CONDITIONS
MIN
VCC = 5.5 V,
Outputs open,
Switch E1, E2, or
E3
One output
switching
at f1 = 10 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
VCC = 5.25 V,
Outputs open,
Switch E1, E2, or
E3
One output
switching
at f1 = 10 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
IC#
VIN = 3.4 V or GND
0.7
1.4
1
2.4
CY74FCT138T
TYP†
MAX
MIN
UNIT
mA
0.7
1.4||
1
2.4||
VIN = 3.4 V or GND
Ci
5
10
5
10
pF
Co
9
12
9
12
pF
† Typical values are at VCC = 5 V, TA = 25°C.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
O
tPLH
tPHL
E1 or E2
O
tPLH
tPHL
E3
O
CY54FCT138T
CY54FCT138CT
MIN
MAX
MIN
MAX
1.5
12
1.5
6
1.5
12
1.5
6
1.5
12.5
1.5
6.1
1.5
12.5
1.5
6.1
1.5
12.5
1.5
6.1
1.5
12.5
1.5
6.1
UNIT
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
O
tPLH
tPHL
E1 or E2
O
tPLH
tPHL
E3
O
POST OFFICE BOX 655303
CY74FCT138T
CY74FCT138AT
CY74FCT138CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
9
1.5
5.8
1.5
5
1.5
9
1.5
5.8
1.5
5
1.5
9
1.5
5.9
1.5
5
1.5
9
1.5
5.9
1.5
5
1.5
9
1.5
5.9
1.5
5
1.5
9
1.5
5.9
1.5
5
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
5
CY54FCT138T, CY74FCT138T
1-OF-8 DECODERS
SCCS013B – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9223302M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629223302M2A
CY54FCT
138TLMB
5962-9223302MEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9223302ME
A
CY54FCT138TDMB
5962-9223306M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629223306M2A
CY54FCT
138CTLMB
5962-9223306MEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9223306ME
A
CY54FCT138CTLMB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629223306M2A
CY54FCT
138CTLMB
CY54FCT138TDMB
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9223302ME
A
CY54FCT138TDMB
CY54FCT138TLMB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629223302M2A
CY54FCT
138TLMB
CY74FCT138ATQCT
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FT138-1
CY74FCT138ATSOC
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT138A
CY74FCT138ATSOCG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT138A
CY74FCT138ATSOCT
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT138A
CY74FCT138CTQCT
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FT138-3
CY74FCT138CTQCTE4
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FT138-3
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CY74FCT138CTSOC
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT138C
CY74FCT138TQCT
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FT138
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
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10-Jun-2014
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CY74FCT138ATSOCT
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CY74FCT138ATSOCT
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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