Cypress CY7C1351G-133AXI 4-mbit (128k x 36) flow-through sram with noblâ ¢ architecture Datasheet

CY7C1351G
4-Mbit (128K x 36) Flow-through SRAM
with NoBL™ Architecture
Functional Description[1]
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
The CY7C1351G is a 3.3V, 128K x 36 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• Byte Write capability
• 128K x 36 common I/O architecture
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• Burst Capability—linear or interleaved burst order
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Low standby power
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
BWC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BWD
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
E
READ LOGIC
SLEEP
Control
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05513 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 4, 2006
[+] Feedback
CY7C1351G
Selection Guide
133 MHz
100 MHz
Unit
6.5
225
40
8.0
205
40
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configurations
Document #: 38-05513 Rev. *D
OE
ADV/LD
87
86
85
A
CEN
88
44
45
46
47
48
49
50
A
A
A
A
A
A
A
43
42
39
NC/144M
NC/36M
38
NC/288M
NC/72M
37
A0
41
36
A1
VDD
35
A
40
34
A
VSS
33
81
WE
89
82
CLK
90
NC/9M
VSS
91
A
VDD
92
83
CE3
93
84
BWA
94
NC/18M
BWC
96
BWB
BWD
97
95
CE2
98
A
CE1
32
BYTE D
A
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
A
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1351G
31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
99
100
A
100-Pin TQFP Pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 2 of 14
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CY7C1351G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
3
4
5
6
7
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
C
NC/576M
NC/1G
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
DQC
DQPC
VSS
NC
VSS
DQPB
DQB
E
F
DQC
VDDQ
DQC
DQC
VSS
VSS
CE1
OE
VSS
VSS
DQB
DQB
DQB
VDDQ
G
H
J
DQC
DQC
VDDQ
DQC
DQC
VDD
BWC
VSS
VSS
NC/9M
WE
VDD
BWB
VSS
VSS
DQB
DQB
VDD
DQB
DQB
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
NC
BWA
DQA
DQA
M
N
VDDQ
DQD
DQD
DQD
VSS
VSS
CEN
A1
VSS
VSS
DQA
DQA
VDDQ
DQA
DQD
DQPD
DQPA
DQA
P
R
T
U
A
NC/144M
NC
NC/72M
VDDQ
NC
VSS
A0
VSS
MODE
A
VDD
A
NC
A
NC
NC
NC
A
NC/288M
ZZ
NC/36M
NC
VDDQ
Pin Definitions
I/O
Description
A0, A1, A
Name
InputSynchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D]
InputSynchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2, and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
OE is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Document #: 38-05513 Rev. *D
Page 3 of 14
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CY7C1351G
Pin Definitions (continued)
Name
I/O
Description
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.
DQs
I/OSynchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the read cycle. The direction of the pins is controlled
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQs and DQP[A:D] are placed in a tri-state condition. The outputs are automatically
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
DQP[A:D]
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE
VDD
VDDQ
Input
Strap Pin
Power Supply
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VSS
Ground
Ground for the device.
NC
–
No Connects. Not Internally connected to the die.
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
Functional Overview
The CY7C1351G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Document #: 38-05513 Rev. *D
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within
6.5 ns (133-MHz device) provided OE is active LOW. After the
first clock of the read access, the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW
in order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
Page 4 of 14
[+] Feedback
CY7C1351G
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQP[A:D].
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW[A:D] signals. The CY7C1351G provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write operations.
Because the CY7C1351G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP[A:D] inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP[A:D].are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:D] inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Document #: 38-05513 Rev. *D
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
40
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Page 5 of 14
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CY7C1351G
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Address
Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
None
H
X
X
L
L
X
X
X
L
L->H
None
X
X
H
L
L
X
X
X
L
L->H
DQ
Tri-State
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
WRITE Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
NOP/WRITE ABORT (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
WRITE ABORT (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Partial Truth Table for Read/Write [2, 3, 9]
Function
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Notes:
2. X = Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP[A:D] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tri-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05513 Rev. *D
Page 6 of 14
[+] Feedback
CY7C1351G
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Ambient
Temperature (TA)
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Range
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
Industrial
−40°C to +85°C
VDD
VDDQ
3.3V –5%/+10% 2.5V –5%
to VDD
Electrical Characteristics Over the Operating Range [10,11]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
for 3.3V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
V
for 3.3V I/O, IOH = -4.0 mA
2.4
V
for 2.5V I/O, IOH = -1.0 mA
2.0
V
for 3.3V I/O, IOL= 8.0 mA
0.4
V
for 2.5V I/O, IOL= 1.0 mA
0.4
V
Input HIGH Voltage
for 3.3V I/O
2.0
VDD + 0.3V
V
Input HIGH Voltage
for 2.5V I/O
1.7
VDD + 0.3V
V
Voltage[10]
for 3.3V I/O
–0.3
0.8
V
Input LOW Voltage[10]
for 2.5V I/O
–0.3
0.7
V
Input Leakage Current
except ZZ and MODE
GND < VI < VDDQ
−5
5
µA
Input = VSS
–30
Input LOW
Input Current of MODE
Input = VDD
Input Current of ZZ
µA
5
Input = VSS
µA
–5
Input = VDD
µA
30
µA
5
µA
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100 MHz
205
mA
Automatic CE Power-down VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
Current—TTL Inputs
VIN > VIH or VIN ≤ VIL, f = fMAX,
10-ns cycle, 100 MHz
inputs switching
90
mA
80
mA
IOZ
Output Leakage Current
GND < VI < VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
–5
ISB2
Automatic CE Power-down VDD = Max, Device Deselected, All speeds
Current—CMOS Inputs
VIN > VDD – 0.3V or VIN < 0.3V,
f = 0, inputs static
40
mA
ISB3
Automatic CE Power-down VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
Current—CMOS Inputs
VIN > VDDQ – 0.3V or VIN < 0.3V, 10-ns cycle, 100 MHz
f = fMAX, inputs switching
75
mA
65
mA
45
mA
ISB4
Automatic CE Power-down VDD = Max, Device Deselected, All speeds
Current—TTL Inputs
VIN > VIH or V IN < VIL, f = 0,
inputs static
Notes:
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05513 Rev. *D
Page 7 of 14
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CY7C1351G
Capacitance[12]
Parameter
Description
CIN
Input Capacitance
CCLOCK
Clock Input Capacitance
CI/O
I/O Capacitance
119 BGA
Max.
Test Conditions
100 TQFP
Max.
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ=3.3V
5
5
pF
5
5
pF
5
7
pF
100 TQFP
Package
119 BGA
Package
Unit
30.32
34.1
°C/W
6.85
14.0
°C/W
Unit
Thermal Resistance[12]
Parameters
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
R = 1538Ω
VT = 1.25V
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
(b)
≤ 1ns
≤ 1ns
(c)
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05513 Rev. *D
Page 8 of 14
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CY7C1351G
Switching Characteristics Over the Operating Range[17, 18]
–133
Parameter
tPOWER
Description
[13]
VDD(Typical) to the first Access
Min.
–100
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
4.0
ns
tCL
Clock LOW
2.5
4.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[14, 15, 16]
6.5
2.0
8.0
2.0
ns
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z14, 15, 16]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
tOEHZ
OE LOW to Output
Low-Z[14, 15, 16]
OE HIGH to Output
High-Z[14, 15, 16]
0
ns
0
0
ns
0
3.5
ns
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
2.0
ns
tALS
ADV/LD Set-up Before CLK Rise
1.5
2.0
ns
tWES
WE, BWX Set-Up Before CLK Rise
1.5
2.0
ns
tCENS
CEN Set-up Before CLK Rise
1.5
2.0
ns
tDS
Data Input Set-up Before CLK Rise
1.5
2.0
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.5
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Hold Times
Notes:
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
18. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05513 Rev. *D
Page 9 of 14
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CY7C1351G
Switching Waveforms
Read/Write Waveforms[19, 20, 21]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BW[A:D]
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05513 Rev. *D
Page 10 of 14
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CY7C1351G
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[19, 20, 22]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A5
tCHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tDOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing[23,24]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05513 Rev. *D
Page 11 of 14
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CY7C1351G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1351G-133AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1351G-133BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1351G-133BGXC
Commercial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1351G-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1351G-133BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1351G-133BGXI
100
Operating
Range
Part and Package Type
lndustrial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1351G-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1351G-100BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1351G-100BGXC
Commercial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1351G-100AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1351G-100BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1351G-100BGXI
lndustrial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05513 Rev. *D
A
Page 12 of 14
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CY7C1351G
Package Diagrams (continued)
119-ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05513 Rev. *D
Page 13 of 14
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1351G
Document History Page
Document Title: CY7C1351G 4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05513
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
224360
See ECN
RKF
New data sheet
*A
276690
See ECN
VBL
Deleted 66 MHz
Changed TQFP package in Ordering Information section to lead-free TQFP
Added comment of availability of BG lead-free package
*B
333626
See ECN
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Packages
as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal
Resistance table
Changed the package name for 100 TQFP from A100RA to A101
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
418633
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North
First Street” to “198 Champion Court”
Modified Typo in VOH test condition from “for 3.3V I/O” to “for 3.3V I/O, IOH = –4.0 mA”
and from “for 2.5V I/O” to “for 2.5V I/O, IOH = –1.0 mA” in the Electrical Characteristics
Table
Modified Typo in VOL test condition for 3.3V I/O from “IOH = –4.0 mA” to “IOH = 8.0 mA”
and for 2.5V I/O from “IOH = –1.0 mA” to “IOH = 1.0 mA” in the Electrical Characteristics
Table
Modified Typo in the test condition for VIH from “for 3.3V I/O, IOH = 8.0 mA” to “for 3.3V
I/O” and from “for 2.5V I/O, IOH =1.0 mA” to “for 2.5V I/O” in the Electrical Characteristics
Table
Modified Typo in IX Input Load Current test condition from “for 3.3V” to “GND ≤ VI ≤
VDDQ” and IX Input Current of Mode test condition from “for 2.5V I/O and “GND ≤ VI ≤
VDDQ” to Input = VSS and Input = VDD respectively in the Electrical Characteristics Table
Modified Typo in ISB4 from “VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V” to “VIN ≥ VIH or VIN ≤ VIL”
in the Electrical Characteristics Table
Added VDDQ for 3.3V I/O in the Electrical Characteristics Table
Modified test condition from VDDQ < VDD to VDDQ < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information
table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
480124
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
Document #: 38-05513 Rev. *D
Page 14 of 14
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