TI1 CDCVF2510PWR 3.3-v phase-lock loop clock driver Datasheet

CDCVF2510
www.ti.com
SCAS638C – JULY 2001 – REVISED APRIL 2006
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Designed to Meet and Exceed PC133 SDRAM
Registered DIMM Specification Rev. 1.1
Spread Spectrum Clock Compatible
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to
166 MHz Is ±125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz
Is |70| ps
Advanced Deep Submicron Process Results
in More Than 40% Lower Power Consumption
Versus Current Generation PC133 Devices
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
10 Outputs
External Feedback (FBIN) Terminal Is Used to
Synchronize the Outputs to the Clock Input
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
PW PACKAGE
(TOP VIEW)
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
NOT RECOMMENDED
FOR NEW DESIGNS
USE CDCVF2510A AS
A REPLACEMENT
DESCRIPTION
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock
(CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a
3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the
G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are
disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.
The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCVF2510 is characterized for operation from 0°C to 85°C.
For application information see the application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking
(SSC) (SCAA039).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2006, Texas Instruments Incorporated
CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
FUNCTION TABLE
INPUTS
OUTPUTS
G
CLK
1Y
(0:9)
X
L
L
L
L
H
L
H
H
H
H
H
FBOUT
FUNCTIONAL BLOCK DIAGRAM
G
11
3
4
5
8
9
15
CLK
24
16
17
PLL
FBIN
13
20
21
AVCC
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
23
12
AVAILABLE OPTIONS
PACKAGE
TA
0°C to 85°C
2
1Y0
SMALL OUTLINE
(PW)
CDCVF2510PWR
CDCVF2510PW
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FBOUT
CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDCVF2510 clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to
phase lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9,
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 14, 22
Power
GND
6, 7, 18, 19
Ground Ground
Power supply
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
AVCC (2)
Supply voltage range
AVCC < VCC +0.7 V
VCC
Supply voltage range
-0.5 V to 4.3 V
VI
(3)
Input voltage range
-0.5 V to 4.6 V
VO (4)
Voltage range applied to any output in the high or low state
-0.5 V to VCC + 0.5 V
IIK(VI < 0)
Input clamp current
-50 mA
IOK(VO < 0 or VO > VCC)
Output clamp current
±50 mA
IO(VO = 0 to VCC)
Continuous output current
±50 mA
VCC or GND
Continuous current through each
±100 mA
TA = 55°C (in still air) (5)
Maximum power dissipation
0.7 W
Tstg
Storage temperature range
-65°C to 150°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AVCC must not exceed VCC + 0.7 V.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For
more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book
(SCBD002).
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SCAS638C – JULY 2001 – REVISED APRIL 2006
DISSIPATION RATING TABLE
PACKAGE
PW
(1)
(2)
DERATING
FACTOR (2) ABOVE
TA = 25°C
TA = 70°C POWER
RATING
TA = 85°C POWER
RATING
920 mW
8.7 mW/°C
520 mW
390 mW
1690 mW
16.1 mW/°C
960 mW
720 mW
TA≤ 25°C POWER
RATING
BOARD
TYPE (1)
RΘJA
JEDEC low-K
114.5°C/W
JEDEC high-K
62.1°C/W
JEDEC high-K board has better thermal performance due to multiple internal copper planes.
This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA).
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
MAX
3.6
VCC, AVCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI
Input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
UNIT
V
V
0.8
0
0
V
VCC
V
-12
mA
12
mA
85
°C
Unused inputs must be held high or low to prevent them from floating.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
fclk
MIN
MAX
UNIT
50
175
MHz
40%
60%
Clock frequency (1)
Input clock duty cycle
Stabilization time (2)
(1)
(2)
1
ms
To avoid any self oscillation of the PLL, a continous clock signal has to be present at the clock input.
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the Switching Characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
VOL
IOH
High-level output voltage
Low-level output voltage
High-level output current
IOL
Low-level output current
II
Input current
(1)
4
Input clamp voltage
TEST CONDITIONS
II = -18 mA
VCC, AVCC
MIN
TYP (1)
3V
MAX
UNIT
-1.2
V
IOH = -100 µA
MIN to MAX
VCC-0.2
IOH = -12 mA
3V
2.1
IOH = -6 mA
3V
2.4
IOL = 100 µA
MIN to MAX
0.2
IOL = 12 mA
3V
0.8
IOL = 6 mA
3V
VO = 1 V
3V
V
0.55
-28
VO = 1.65 V
3.3 V
VO = 3.135 V
3.6 V
VO = 1.95 V
3V
VO = 1.65 V
3.3 V
VO = 0.4 V
3.6 V
10
VI = VCC or GND
3.6 V
±5
-36
mA
-8
30
40
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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V
mA
µA
CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC, AVCC
TYP (1)
MIN
MAX
UNIT
ICC (2)
Supply current
(static, output not switching)
VI = VCC or GND,
Outputs: low or high
∆ICC
Change in supply current
One input at VCC - 0.6 V,
Other inputs at VCC or GND
Ci
Input capacitance
VI = VCC or GND
3.3 V
2.5
pF
Co
Output capacitance
VO = VCC or GND
3.3 V
2.8
pF
(2)
IO = 0,
3.6 V, 0 V
40
µA
3.3 V to 3.6 V
500
µA
For dynamic ICC vs Frequency, see Figure 8 and Figure 9.
SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, See
Figure 2
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
Phase error time-static
(normalized),
CLK↑ = 66 MHz to166 MHz
See Figure 3 through Figure 6
tsk(o)
Output skew time
(2)
Phase error time-jitter
FBIN↑
Any Y
(3)
CLK = 66 MHz to 100 MHz
(1)
and Figure 1 and
VCC, AVCC = 3.3 V
± 0.3 V
MIN
TYP
-125
Any Y
Any Y or FBOUT
-50
|70|
|65|
CLK = 100 MHz to
166 MHz
Any Y or FBOUT
125
ps
100
ps
50
Any Y or FBOUT
Jitter(cycle-cycle), See Figure 7
UNIT
MAX
ps
ps
Duty cycle
f(CLK) > 60 MHz
Any Y or FBOUT
45%
55%
tr
Rise time
VO = 0.4 V to 2 V
Any Y or FBOUT
0.3
1.1
ns/V
tf
Fall time
VO = 2 V to 0.4 V
Any Y or FBOUT
0.3
1.1
ns/V
tPLH(bypass
mode)
Low-to-high propagation delay
CLK
time, bypass mode
Any Y or FBOUT
1.8
3.9
ns
tPHL(bypass
mode)
High-to-low propagation delay
time, bypass mode
Any Y or FBOUT
1.8
3.9
ns
(1)
(2)
(3)
CLK
These parameters are not production tested.
The tsk(o) specification is only valid for equal loading of all outputs.
Calculated per PC DRAM SPEC (tphase error, static - jitter(cycle-to-cycle)).
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CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 2V
0.4 V
Output
25 pF
50% VCC
tr
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
6
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CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
600
600
VCC = 3.3 V
fc = 100 MHz
C(LY1-n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
200
VCC = 3.3 V
fc = 133 MHz
C(LY1-n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
400
Static Phase Error - ps
400
CLK to Y1-n
0
-200
200
CLK to Y1-n
0
-200
CLK to FBOUT
CLK to FBOUT
-400
-400
-600
-600
3
8
13
18
23
28
33
38
3
8
C(LF) - Load Capacitance - pF
13
18
23
28
33
38
C(LF) - Load Capacitance - pF
Figure 3.
Figure 4.
STATIC PHASE ERROR
vs
SUPPLY VOLTAGE AT FBOUT
0
fc = 133 MHz
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
-50
Static Phase Error - ps
Static Phase Error - ps
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
-100
-150
CLK to FBOUT
-200
-250
-300
-350
-400
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC - Supply Voltage at FBOUT - V
Figure 5.
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CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
TYPICAL CHARACTERISTICS (continued)
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
0
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
Static Phase Error - ps
-50
-100
-150
CLK to FBOUT
-200
-250
-300
-350
-400
50
75
100
125
150
175
200
fc - Clock Frequency - MHz
Figure 6.
NOTE:
1. Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω
2. C(LY) = Lumped capacitive load Y1-n
3. C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
JITTER
vs
CLOCK FREQUENCY AT FBOUT
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
140
AI CC - Analog Supply Current - mA
120
25
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes C and D
Jitter - ps
100
80
60
Cycle to Cycle
40
20
0
50
8
75
100
125
150
175
200
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
20
15
10
5
0
0
25
50
75
100
125
150
fc - Clock Frequency at FBOUT - MHz
fc - Clock Frequency - MHz
Figure 7.
Figure 8.
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175
200
CDCVF2510
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SCAS638C – JULY 2001 – REVISED APRIL 2006
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
I CC - Supply Current - mA
200
150
100
50
0
0
25
50
75
100
125
150
175
200
fc - Clock Frequency - MHz
Figure 9.
NOTE:
1. Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω
2. Total current = ICC + AICC
3. C(LY) = Lumped capacitive load Y1-n
4. C (LFx) = Lumped feedback capacitance at FBOUT = FBIN
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCVF2510PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2510
CDCVF2510PWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2510
CDCVF2510PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2510
CDCVF2510PWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2510
HPA00015PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2510
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCVF2510PWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2510PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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