ATMEL ATA6833 Bldc motor driver and lin system basis chip Datasheet

Features
• ATA6833 Temperature Range TA = 125°C, TJ = 150°C
• ATA6834 Extended Temperature Range TA = 150°C, TJ = 200°C
• Direct Driving of 6 External NMOS Transistors with a Maximum Switching Frequency of
50 kHz
• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
Built-in 5V/3.3V Voltage Regulator with Current Limitation
Reset Signal for the Microcontroller
Sleep Mode with Supply Current of typically < 45 µA
Wake-up via LIN Bus or High Voltage Input
Programmable Window Watchdog
Battery Overvoltage Protection and Battery Undervoltage Management
Overtemperature Warning and Protection (Shutdown)
200 mA Peak Current for Each Output Driver
LIN Transceiver Conformal to LIN 2.1 and SAEJ2602-2 with Outstanding EMC and ESD
Performance
• QFN48 Package 7 mm × 7 mm
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1. Description
The ATA6833 and ATA6834 are system basis chips for three-phase brushless DC
motor controllers designed in Atmel ® ’s state-of-the-art 0.8 µm SOI technology
SMART-I.S.™1. In combination with a microcontroller and six discrete power MOSFETs, the system basis chip forms a BLDC motor control unit for automotive
applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window
watchdog.
BLDC Motor
Driver and LIN
System Basis
Chip
ATA6833
ATA6834
Preliminary
The circuit includes various control and protection functions like overvoltage and overtemperature protection, short circuit detection, and undervoltage management.
Thanks to these function blocks, the driver fulfils a maximum of safety requirements
and offers a high integration level to save cost and space in various applications. The
target applications are most suitable for the automotive market due to the robust technology and the high qualification level. ATA6834, in particular, is designed for
applications in a high-temperature environment.
9122B–AUTO–10/08
Figure 1-1.
Block Diagram
VBAT
VBAT
VBATSW VINT VG
CPHI1
CPHI2
CPOUT
CPLO1
CPLO2
PBAT
VMODE
DG1
DG2
Microcontroller
DG3
3.3/5V VCC
Regulator
13V
Regulator
Supervisor:
Short Circuit
Overtemperature
Undervoltage
VINT 5V
Regulator
CP
VBG
Oscillator
High-side
Driver 3
H3
High-side
Driver 2
H2
High-side
Driver 1
H1
S1
/RESET
S2
WD
S3
Logic Control
IH1-3
ATA6833/34
IL1-3
RX
LIN
TX
Hall A
Hall B
LIN
WD
Timer
EN1 EN2 GND RWD WDD
CC
Timer
CC
Low-side
Driver 1
L1
Low-side
Driver 2
L2
Low-side
Driver 3
L3
M
Hall A
Hall B
Hall C
VCC
PGND
Hall C
2
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
2. Pin Configuration
Pinning QFN48
VBATSW
EN2
VBAT
NC
VCC
PGND
L3
L2
L1
VG
PBAT
NC
Figure 2-1.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
Atmel YWW
31
6
ATA6833/ATA6834 30
7
ZZZZZ-AL
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VMODE
VINT
RWD
CC
/RESET
WD
WDD
EN1
LIN
NC
TXD
IL3
IH3
IL2
IH2
IL1
IH1
RXD
DG1
DG2
NC
NC
GND
NC
CPLO1
CPHI1
CPLO2
CPHI2
CPOUT
S1
H1
S2
H2
S3
H3
DG3
Note:
YWW
ATA683x
ZZZZZ
AL
Date code (Y = Year - above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin Description
Pin
Symbol
I/O
1
VMODE
I
2
VINT
I/O
3
RWD
I
4
CC
I/O
RC combination to adjust cross conduction time
5
/RESET
O
Reset signal for microcontroller
6
WD
I
Watchdog trigger signal
7
WDD
I
Enable and disable the watchdog
8
EN1
I
Microcontroller output to switch system in Sleep Mode
9
N.C.
Connect to GND
10
N.C.
Connect to GND
11
GND
I
Function
Selector for VCC and interface logic voltage level
Blocking capacitor
Resistor defining the watchdog interval
Ground
12
NC
13
LIN
Connect to GND
14
NC
15
TXD
I
Transmit signal to LIN bus from microcontroller
16
IL3
I
Control Input for output L3
17
IH3
I
Control Input for output H3
I/O
LIN-bus terminal
Connect to GND
3
9122B–AUTO–10/08
Table 2-1.
Pin Description
Pin
Symbol
I/O
18
IL2
I
19
IH2
I
Control Input for output H2
20
IL1
I
Control Input for output L1
21
IH1
I
Control Input for output H1
22
RXD
O
Receive signal from LIN bus for microcontroller
23
DG1
O
Diagnostic output 1
24
DG2
O
Diagnostic output 2
25
DG3
O
Diagnostic output 3
26
H3
O
Gate voltage high-side 3
27
S3
I/O
Voltage at half bridge 3
28
H2
O
Gate voltage high-side 2
29
S2
I/O
Voltage at half bridge 2
30
H1
O
Gate voltage high-side 1
4
Function
Control Input for output L2
31
S1
I/O
Voltage at half bridge 1
32
CPOUT
I/O
Charge pump output capacitor
33
CPHI2
I
Charge pump capacitor 2
34
CPLO2
O
Charge pump capacitor 2
35
CPHI1
I
Charge pump capacitor 1
36
CPLO1
O
Charge pump capacitor 1
37
NC
38
PBAT
I
39
VG
I/O
Blocking capacitor
40
L1
O
Gate voltage H-bridge, low-side 1
41
L2
O
Gate voltage H-bridge, low-side 2
42
L3
O
Gate voltage H-bridge, low-side 3
43
PGND
I
Power ground for H-bridge and charge pump
44
VCC
O
5V/100 mA supply for microcontroller
45
NC
46
VBAT
Connect to GND
Power supply (after reverse protection) for charge pump and gate drivers
Connect to GND
I
Supply voltage for IC core (after reverse protection)
47
EN2
I
High voltage enable input
48
VBATSW
O
100Ω PMOS switch from VBAT
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
3. Functional Description
3.1
3.1.1
Power Supply Unit with Supervisor Functions
Power Supply
The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC,
proper external protection circuitry has to be added. It is recommended to use at least one
capacitor combination of storage and RF capacitors behind the reverse protection circuitry,
which is connected close to the VBAT and GND pins of the IC.
A fully integrated low-power and low-drop regulator (VINT regulator), stabilized by an external
blocking capacitor, provides the necessary low-voltage supply needed for the wake-up process.
A trimmed low-power band gap is used as reference for the VINT regulator as well as for the
VCC regulator. All internal blocks are supplied by VINT regulator. VINT regulator must not be
used for any external supply purposes.
Nothing inside the IC except the logic interface to the external microcontroller is supplied by the
5V/3.3V VCC regulator.
Both voltage regulators are checked by a “power-good comparator”, which keeps the whole chip
in reset as long as the internal supply voltage (VINT regulator output) is too low and generates a
reset for the external microcontroller if the output voltage of the VCC regulator is not sufficient.
3.1.2
VBatt Switch
This high-voltage switch provides the battery voltage at pin VBATSW for various purposes. It is
switched ON after power on reset when the IC transits to Active Mode and it will only turn OFF
when the IC changes to Sleep Mode. Watchdog resets do not have an effect on the switch. The
switch can be used for measuring purposes as well as to switch on external voltage regulators.
3.1.3
Voltage Supervisor
This function is implemented to protect the IC and the external power MOS transistors from
damage due to overvoltage on PBAT input. In the event of overvoltage (VTHOV) or undervoltage
(VTHUV), the external NMOS motor driver transistors will be switched off. The failure state will be
flagged on DG2 pin. It is recommended to block PBAT with an external RF capacitor to suppress
high frequency disturbances.
3.1.4
Temperature Supervisor
An integrated temperature sensor prevents the IC from overheating. If the temperature is above
the overtemperature pre-warning threshold TJPW set, the diagnostic pin DG3 will be switched to
HIGH to signal this event to the external microcontroller. The microcontroller should take actions
to reduce the power dissipation in the IC. If the temperature rises above the overtemperature
shutdown threshold TJ switch off, the VCC regulator and all output drivers together with the LIN
transceiver will be switched OFF immediately and the /RESET signal will go LOW. Both thresholds have a built-in hysteresis to avoid oscillations. The IC will return to normal operation (Active
Mode) when it has cooled down below the shutdown threshold. When the junction temperature
drops below the pre-warning threshold, bit DG3 will be switched LOW.
5
9122B–AUTO–10/08
3.2
Active Mode and Sleep Mode
The IC has two modes: Sleep Mode and Active Mode. Switching between the modes is
described below. By default the IC starts in Active Mode (which means normal operation) after
power-on. A Go to Sleep procedure switches the IC from Active Mode to Sleep Mode (standby).
A Go to Active procedure brings the IC back from Sleep Mode to Active Mode. When in Sleep
Mode the internal 5V supply (VINT regulator), the EN2 pin input structure, and a certain part of
the LIN receiver remain active to ensure a proper startup of the system. The VCC regulator is
turned off.
The Go to Sleep and Go to Active procedures are implemented as follows:
Go to Sleep:
Pin EN1 is a low-voltage input supplied by the VCC regulator. It is ESD protected by diodes
against VCC and GND. Thus the input voltage at pin EN1 must not go below GND or exceed the
output voltage of the VCC regulator. A transition from HIGH to LOW followed by a permanent
LOW signal for a minimum time period tgotosleep (typical 10 µs) at pin EN1 switches the IC to
Sleep Mode as the EN1 is edge triggered. VCC is switched off in Sleep Mode. It is recommended
to keep EN1 LOW during normal operation.
Go to Active Using Pin EN2:
Pin EN2 is a high-voltage input for external wake-up signals. Its input structure consists of a
comparator with a built-in hysteresis. It is ESD-protected by diodes against GND and VBAT, B,
and for this reason the applied input voltage must not go below GND or exceed VBAT. Pulling
EN2 up to VBAT switches the IC to Active Mode. EN2 is debounced and edge triggered.
Go to Active Using the LIN Interface:
Using the LIN interface provides a second possibility to wake-up the IC (see Figure 3-1). A falling edge at pin LIN followed by a dominant bus level maintained for a minimum time period
(Tbus) and ending with a rising edge leads to a remote wake-up request. The device switches
from Sleep Mode to Active Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on.
Figure 3-1.
Wake-up Using the LIN Interface
Active Mode
Sleep Mode
Active Mode
EN1
Tdebounce
VCC
LIN
Tgotosleep = 10 µs
6
Tbus = 90 µs
Regulator Wake-up Time = 4 × TOSC
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
3.3
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated. It requires an external electrolytic capacitor in the range
of 2.2 µF up to 10 µF and with an ESR in the range from 2Ω to 15Ω for stability (see Figure 3-2).
The output voltage can be configured as either 5V or 3.3V by connecting pin VMODE to either
pin VINT or GND. Since the regulator is not designed to be switched between both output voltages during operation, it is advisable to hard-wire VMODE pin. The logic levels of the
microcontroller interface are adapted to the VCC regulator output voltage. The maximum output
current (IOS1) of the regulator is 100 mA. For TJ > 150°C the IOS1 of ATA6834 is reduced to
80 mA. The VCC regulator has a built-in short circuit protection. A comparator checks the output
voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is below the lower operation minimum (shown in Figure 3-33).
Figure 3-2.
ESR versus Load Current for External Capacitors with Different Values
ESR versus Load Current at Pin VCC
ESR versus Load Current at Pin VCC
25
40
35
20
ESRmax (CVCC = 10 µF)
ESRmax (CVCC = 2.2 µF)
25
ESR (Ω)
ESR (Ω)
30
20
15
10
10
5
ESRmin (CVCC = 2.2 µF)
5
15
ESRmin (CVCC = 10 µF)
0
0
0
25
50
75
10 0
12 5
150
Load Current (mA)
Figure 3-3.
0
25
50
75
10 0
12 5
150
Load Current (mA)
/RESET as Function of the VCC Output Voltage
VCC
100% VCC
88% VCC
80% VCC
0V
/RESET
7
9122B–AUTO–10/08
3.4
Reset and Watchdog Management
The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time TOSC
is determined by the external resistor RWD. A HIGH signal on WDD pin enables the watchdog
function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor
the watchdog is enabled by default. In order to keep the current consumption as low as possible
the watchdog is switched off during Sleep Mode.
The timing diagram in Figure 3-4 shows the watchdog and external reset timing.
Figure 3-4.
Timing Diagram of the Watchdog in Conjunction with the /RESET Signal
VCC
88% VCC
Watchdog
trigger edge
/RESET
Watchdog trigger
in t2 window
tresshort
WD
t1
tres
td
tres
t2
t1
t2
td
Reset and lead Reset and lead time, Watchdog cycle,
time, no trigger trigger during lead time
no trigger
t1
Watchdog cycle, trigger
during t2 window
After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET
output stays LOW for the timeout period tres (typical 10 ms). Subsequently /RESET output
switches to HIGH. During the following time td (typical 500 ms) a rising edge at the input WD is
expected otherwise another external reset will be triggered.
When the watchdog has been correctly triggered for the first time, normal watch-dog operation
begins. A normal watchdog cycle consists of two time sections t1 and t2 followed by a short pulse
for the time tresshort at /RESET if no valid trigger has been applied at pin WD during t2. Rising
edges on WD pin during t1 also cause a short pulse on /RESET. Start for such a cycle is always
the time of the last rising edge either on WD pin or on /RESET pin.
If the watchdog is disabled (WDD = LOW), only the initial reset for the time tres after power-up
will be generated.
Additional resets will be generated if the VCC output voltage drops below 80% of its nominal
value.
The following example demonstrates how to calculate the timing scheme for valid watchdog trigger pulses, which the external microcontroller has to provide in order to prevent undesired
resets.
8
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
Example:
Using an external resistor RWD = 33 kΩ ±1% results in typical parameters as follows:
TOSC = 12.32 µs
t1 = 980 × TOSC = 12.07 ms ±10%
t2 = 780 × TOSC = 9.609 ms ±10%
t1 + t2 = 21.68 ms ±10%
Hence, the minimum time the external microcontroller has to wait before pin WD can be triggered is in worst case tmin = 1.1 × t1 = 13.28 ms. The maximum time for the watchdog trigger on
WD pin is t max = 0.9 × (t1 + t2) = 19.51 ms. Thus watchdog trigger input must remain within
tmax – tmin = 6.23 ms.
Other values can be set up by picking a different resistor value for RWD. The dependency of TOSC
on the value of RWD is shown in Figure 3-5.
Figure 3-5.
TOSC versus RWD
45
40
TOSC (µs)
TOSC (µs)
35
30
TOSCmax (µs)
25
20
15
TOSCmin (µs)
10
5
0
10
20
30
40
50
60
70
80
90
10 0
RWD (kΩ)
3.5
Charge Pump
A charge pump has been implemented in order to provide sufficient voltage to operate the external high-side power-NMOS transistors and the VG regulator, which drives the low-side
Power-NMOS transistors. The charge pump output voltage at CPOUT pin is controlled to settle
typically about 15V above the voltage at pin PBAT. A built-in supervisor circuit checks if the output voltage is sufficient to operate the VG regulator and external Power-NMOS transistors. The
output voltage is accepted as good when it rises above VCPCPGOOD. A charge pump failure is
flagged at DG2 if this minimum can not be reached or if the output voltage drops below the lower
threshold of VCPCPGOOD due to overloading.
The two shuffle capacitors should have the same value. The value of the reservoir capacitor
should be at least twice the value of one shuffle capacitor. Two external shuffle capacitors and
an external reservoir capacitor have to be provided. The typical values for the two shuffle capacitor is 100F, and for the reservoir capacitor is 470 nF. All capacitors should be ceramic. It is
advisable to pick a reservoir capacitor with twice or three-times the size of the two equally-sized
shuffle capacitors. The greater the capacitors, the greater the output current capability.
9
9122B–AUTO–10/08
3.6
VG Regulator
The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver sufficient voltage for the external low-side Power-NMOS transistors. Typically the output voltage is
12V. In order to guarantee reliable operation even with a low battery voltage, the VG regulator is
supplied by the charge pump output. For stability, an external ceramic capacitor of typically
470 nF has to be provided. There is no internal supervision of the VG output voltage.
3.7
Output Drivers and Control Inputs IL1-IL3, IH1-IH3
This IC offers six push-pull output drivers for the external low-side and high-side power-NMOS
transistors. To guarantee reliable operation, the low-side drivers are supplied by the VG regulator while the high-side drivers are supplied directly by the charge pump. All drivers are designed
to operate at switching frequencies in the range of DC up to 50 kHz. The maximum gate charge
that can be delivered to each external Power-NMOS transistor at 50 kHz is 100 nC.
The output drivers are directly controlled by the digital input pins IL1 to IL3 and IH1 to IH3 (see
Table 3-1). All pins are equipped with an internal pull-down resistor. To operate the output drivers properly the following requirements have to be fulfilled:
1. Device is in Active Mode.
2. In case of watchdog is enabled, at least one valid watchdog trigger has been accepted.
3. The voltage at pin PBAT lies within its operation range. Neither undervoltage nor overvoltage is present.
4. The charge pump output voltage has been accepted as good, thus it exceeded
VCPCPGOOD.
5. No overtemperature shutdown has occurred.
If a short circuit is detected by one of the sense inputs S1 to S3, the output drivers will be
switched off after a debounce time of 6 µs and the output DG1 will be flagged (see also Section
3.8 “Short Circuit Detection” on page 11). The output drivers will be enabled again and DG1 will
be cleared with a rising edge at one of the control inputs (IL1 to IL3, IH1 to IH3).
Additional logic prevents short circuits due to switching on one power-NMOS transistor while the
opposite one in the same branch is switched on already.
Table 3-1.
10
Status of the Output Drivers Depending on the Control Inputs
Mode
Control
Inputs
IL[1..3]
Control
Inputs
IH[1..3]
Driver Stage for External
Power MOS
L[1..3], H[1..3]
Comments
Sleep
X
X
OFF
Sleep Mode
Active
0
0
OFF
Active
1
0
L[1..3] ON, H[1..3] OFF
Active
0
1
H[1..3] ON, L[1..3] OFF
Active
1
1
OFF
Shoot-through protection
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
3.8
Short Circuit Detection
Short circuits in the motor bridge circuitry are sensed by S1 to S3 inputs. Internal comparators
monitor the voltage differences between the drain and the source terminals of the external
power-NMOS transistors. If one transistor switches on and the voltage drop from its drain to
source stays higher than the threshold VSC (typical 4V) for a longer time than tSC (typically 6 µs),
a short circuit in this branch is detected. In this case, all output drivers are switched off immediately and DG1 pin will be set to HIGH. With a rising edge at any of the pins IL1 to IL3 or IH1 to
IH3, the diagnostic output DG1will be reset and the drivers can be switched on again.
3.9
Cross Conduction Timer
In order to prevent damage of the motor bridge due to peak currents a non-overlapping phase
for switching the power-NMOS transistors is mandatory. Therefore, a cross conduction timer has
been implemented to prevent switching on any output driver for a time tCC after any other driver
has been switched off. This also accounts for toggling any other driver after a short circuit was
detected. An external RC parallel combination defines the value for tCC and can be estimated as
follows:
tCC = KCC × RCC [kΩ] × CCC [nF], KCC is specified in Section 8. “Electrical Characteristics” on
page 15.
The RC combination is connected between CC and GND pins. When one of the drivers has
been switched off the RC combination is charged to 5V (VINT) and discharged with its time constant. Any low to high transition at the control inputs will be masked out at the driver outputs until
the voltage at CC pin drops below 67% of its initial value (VINT). The timer will be re-triggered at
any time by any falling edge at the control inputs. This is shown in the following figure.
Figure 3-6.
Timing Scheme of the Cross Conduction Timer
IL1
L1
IH1
H1
IL3
L3
VCC = VVINT
CC
VCC = 67% VVINT
tcc
tcc
tcc
At least 5 kΩ minimum and 5 nF at maximum should be used as values for the RC combination.
10 kΩ is recommended. If the non-overlapping phase is controlled by the external microcontroller, it is possible to do without the external capacitor. The minimum time tCC is defined by the
parasitic capacitance at CC pin.
11
9122B–AUTO–10/08
3.10
Diagnostic Outputs D1 - D3
As mentioned in the sections above, the diagnostic outputs DG1 to DG3 are used to signal failures. This is summarized in the following table.
Table 3-2.
Status of the Diagnostic Outputs (Normal Operation)
Device Status
Diagnostic Outputs
Comments
CPOK
OT1
OV
UV
SC
DG1
DG2
DG3
0
X
X
X
X
–
1
–
Charge pump failure
X
1
X
X
X
–
–
1
Overtemperature prewarning
X
X
1
X
X
–
1
–
Overvoltage
X
X
X
1
X
–
1
–
Undervoltage
X
X
X
X
1
1
–
–
Short circuit
Note:
X represents: no effect)
OT1: overtemperature warning
OV: overvoltage of PBAT
UV: undervoltage of PBAT
SC: short circuit
CPOK: charge pump OK
In order to differentiate between LIN and EN2 wake-up, DG1 output will be set to LOW or HIGH
respectively. LOW indicates wake-up by LIN, HIGH indicates wake-up by EN2. DG1 output will
be cleared by the first valid watchdog trigger after wake-up or by the first rising edge at one of
the control inputs (IL1 to IL3 and IH1 toIH3) if the watchdog is disabled.
Table 3-3.
Indicating Wake-up Source
Diagnostic Outputs
3.11
DG1
DG2
DG3
Wake-up Source
1
–
–
EN2
0
–
–
LIN
LIN Transceiver
ATA6833 and ATA6834 include a fully integrated LIN transceiver complying with LIN specification 2.1 and SAEJ2602 2. The transceiver consists of a low-side driver with slew rate control,
wave shaping, current limiting, and a high voltage comparator followed by a debouncing unit in
the receiver.
During transmission, the data applied at pin TXD will be transferred to the bus driver to generate
a bus signal on LIN pin. TXD input has an internal pull-up resistor.
To minimize the electromagnetic emission of the bus line, the bus driver has a built-in slew rate
control and wave-shaping unit. The transmission will be aborted by a thermal shutdown or by a
transition to Sleep Mode.
12
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
Figure 3-7.
Definition of Bus Timing Parameters
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an
active diode. This diode protects against reverse currents on the bus line in case of a voltage difference between the bus line and VSUP (VBUS > VSUP). No additional termination resistor is
necessary to use the IC as a LIN slave. If this IC is used as a LIN master, the LIN pin is terminated by an external 1 kΩ resistor in series with a diode to VBAT.
As PWM communication directly over the LIN transceiver in both directions is possible, there is
no TXD timeout feature implemented in the LIN transceiver.
13
9122B–AUTO–10/08
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to pin GND. [xxx] Values for the ATA6834.
Parameters
Pin
Symbol
Min.
Max.
Unit
Input voltage
PGND
VPGND
–0.3
+0.3
V
Negative input current
VBAT
IVBAT
TBD
TBD
mA
Negative input current
PBAT
IPBAT
TBD
TBD
mA
Supply voltage
VBAT
VVBAT
–0.3
+40 (500 ms)
V
Supply voltage
PBAT
VPBAT
–0.3
+40 (500 ms)
V
Logic output voltage
/RESET, DG1,
DG2, DG3, RXD
V/RESET, VDG1, VDG2,
VDG3, VRXD
–0.3
VVCC + 0.3
V
Logic input voltage
IL1-3, IH1-3, WD,
WDD, EN1, TXD
VIL1-3, VIH1-3, VWD,
VEN1, VTXD
–0.3
VVCC + 0.3
V
Output voltage
VINT, VCC
VINT, VVVCC
–0.3
+5.5
V
Analog input voltage
RWD, CC
VRWD
–0.3
VVCC + 0.3
V
Digital input voltage
EN2
VEN2
–0.3
VVBAT + 0.3
V
Digital input voltage
VMODE
VVMODE
–0.3
VVINT + 0.3
V
Output voltage
VG
VVG
–0.3
+16
V
Input voltage
LIN
VVLIN
–27
VVBAT + 2
V
Output voltage
S1, S2, S3
VS1, VS2, VS3
–6
+30
V
Output voltage
L1, L2, L3
VL1, VL2, VL3
VPGND – 0.3
VVG + 0.3
V
Output voltage
H1, H2, L3
VH1, VH2, VH3
VS1, 2, 3 – 1
VS1, 2, 3 + 16
V
Charge pump
CPLO1, 2
VCPLO1, VCPLO2
–0.3
VPBAT + 0.3
V
Charge pump
CPHI1, 2
VCPHO1, VCPHO2
–0.3
VCPOUT + 0.3
V
Output voltage
CPOUT
VCPOUT
–0.3
+40
V
Output voltage
VBATSW
VVBATSW
–0.3
VVBAT + 0.3
V
TStorage
–55
+150
°C
Storage temperature
5. Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance junction to heat slug
Rthjc
<5
K/W
Thermal resistance junction to ambient when heat slug
is soldered to PCB
Rthja
25
K/W
14
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
6. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied unless otherwise stated explicitly. [xxx] Values for the ATA6834
Parameters
Symbol
Min
Max
Unit
5.5
VTHOV(4)
V
VVBAT
4.3
5.5
V
VVBAT
VTHOV(4)
40
V
Ambient temperature range
TA
–40
+150
°C
Junction temperature range
TJ
–40
+150 (200)
°C
Operating supply voltage
(1)
Operating supply voltage
(2)
Operating supply voltage
(3)
Notes:
VVBAT
(t = 500 ms)
1. Full functionality
2. Output drivers are switched off, extended range for parameters for voltage regulators
3. Output drivers and charge pump are switched off
4. Voltages higher VTHOV for maximum 500 ms
7. Noise and Surge Immunity
Parameters
Standard and Test Conditions
Conducted interferences
ISO 7637-1
Conducted disturbances
CISP25
Level 5
ESD (Human Body Model)
ESD S 5.1
±2 kV
ESD (Human Body Model)
DIN EN61000-4-2, Pin LIN, VBAT, PBAT to GND
±6 kV
Latch-up immunity
JESD78, AEL-Q100 (004)
Note:
Value
Level 4(1)
Class II, level A
1. Test pulse 5: Vbat max = 40V
8. Electrical Characteristics
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
1
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit Type*
VBAT
IVBAT
7
mA
A
Power Supply and Supervisor Functions
1.1 Current consumption VVBAT VVBAT = 13.5V(1)
1.3
Current consumption VVBAT
VVBAT = 13.5V
in Standby Mode
VBAT
IVBAT
65
µA
A
1.4
Current consumption VVBAT
VPBAT = 13.5V
in Standby Mode
PBAT
IVPBAT
TBD
µA
A
VINT
VVINT
4.7
5.3
V
A
1.6 Overvoltage threshold
PBAT
VTHOV
19.8
22.3
V
A
Overvoltage threshold
hysteresis
PBAT
VTOVhys
1
1.5
V
A
1.8 Undervoltage threshold
PBAT
VTHUV
5.0
5.5
V
A
Undervoltage threshold
hysteresis
PBAT
VTUVhys
0.2
0.4
V
A
100
Ω
A
1.5 Internal power supply
1.7
1.9
1.10 RDSON VBAT-Switch switch
VVBAT > 7V
VVBAT = 13.5V,
IVBATSW = –15 mA
VBATSW RON_VBATSW
5.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
15
9122B–AUTO–10/08
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
TJPW set
120
(170)
145
(195)
170
(220)
°C
B
1.12 Thermal prewarning reset
TJPW reset
105
(155)
130
(180)
155
(205)
°C
B
Thermal prewarning
hysteresis
ΔTJPW
°C
B
1.11 Thermal prewarning set
1.13
15
Unit Type*
1.14 Thermal shutdown off
TJ switch off
150
(200)
175
(225)
200
(250)
°C
B
1.15 Thermal shutdown on
TJ switch on
135
(185)
160
(210)
185
(235)
°C
B
°C
B
1.16
Thermal shutdown
hysteresis
ΔTJ switch off
1.17
Ratio thermal shutdown
off/thermal prewarning set
TJ switch off/
TJPW set
1.05
1.15
B
TJ switch on/
TJPW reset
1.05
1.15
B
Ratio thermal shutdown
1.18 on/thermal prewarning
reset
2
15
5V/3.3V Regulator
2.1 Regulated output voltage
VMODE = VINT, 7V < VBAT < 40V
VMODE = GND, 5.5V < VBAT < 40V
ILoad = 0 to 100 mA
2.2 Regulated output voltage
VMODE = VINT, 7V < VBAT < 40V
VMODE = GND, 5.5V < VBAT < 40V
ILoad = 0 to 80 mA
150°C < TJ < 200°C
VCC
VVCC
2.3 Regulated output voltage
VMODE = VINT, 5.5V < VBAT < 7V
VMODE = GND, 5V < VBAT < 5.5V
ILoad = 0 to 60 mA
VCC
VVCC
2.4 Regulated output voltage
VMODE = VINT, 5.5V < VBAT < 7V
VMODE = GND, 5V < VBAT < 5.5V
ILoad = 0 to 50 mA
150°C < TJ < 200°C
VCC
2.5 Line regulation
VMODE = VINT, 7V < VBAT < 40V
VMODE = GND, 5.5V < VBAT < 40V
ILoad = 50 mA, –40°C < TJ < 150°C
VCC
2.6 Load regulation
VMODE = VINT, VBAT > 7V
VMODE = GND, VBAT > 5.5V
ILoad = 0 to 100 mA
ILoad = 0 to 80 mA,
150°C < TJ < 200°C
VCC
2.7 Output current limit
VMODE = VINT, VBAT > 7V
VMODE = GND, VBAT > 5.5V
ILoad @ RESET
VCC
VCC
VVCC
VVCC
4.85
3.20
5.15
3.40
4.85
3.20
5.15
3.40
4.50
2.97
5.15
3.40
4.50
2.97
5.15
3.40
50
50
V
A
V
A
V
A
V
A
mV
A
mV
A
mA
C
50
50
IOS1
100
100
320
320
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
16
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
Test Conditions
2.8 Output current limit
VMODE = VINT, VBAT > 7V
VMODE = GND, VBAT > 5.5V
ILoad @ RESET,
150°C < TJ < 200°C
Pin
VCC
Symbol
IOS1
Min.
70
70
2.12 HIGH threshold VMODE
VVMODE H
2.13 LOW threshold VMODE
VVMODE L
0.7
VtHRESH
4.1
(2.7)
3
3.1
Typ.
Max.
320
320
4.0
Unit Type*
mA
C
V
A
V
A
V
A
V
A
Reset and Watchdog
VCC threshold voltage level VMODE = VINT
for /RESET
(VMODE = GND)
4.7
(3.0)
3.2 Hysteresis of /RESET level
HYSRESth
3.3 Length of pulse at /RESET
tres
8
12
ms
A
tresshort
1.8
2.2
ms
A
td
400
600
ms
A
2
µs
C
13.55
µs
A
3.4
Length of short pulse at
/RESET
3.5 Wait for the first WD trigger
3.6
Time for VCC < VtHRESL
before activating /RESET
0.2
tdelayRESL
3.8 Watchdog oscillator period RRWD = 33 kΩ
TOSC
11.09
3.12 Close window
t1
980 ×
TOSC
3.13 Open window
t2
780 ×
TOSC
3.14
Output low-level at pin
/RESET
3.15
Internal pull-up resistor at
pin /RESET
4
IOLRES = 1 mA
VOLRES
RPURES
5
2
10
A
A
0.4
V
A
15
kΩ
D
mA
D
mA
D
V
A
LIN Transceiver
4.1 Low-level output current
Normal mode;
VLIN = 0V, VRXD = 0.4V
ILRXD
4.2 High-level output current
Normal mode; VLIN = VBAT
VRXD = VCC – 0.4V
IHRXD
–2
0.9 ×
VBAT
4.3
Driver recessive output
voltage
VTXD = VCC; ILIN = 0 mA
VBUSrec
4.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.3V
Rload = 500Ω
V_LoSUP
1.2
V
A
4.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 500Ω
V_HiSUP
2
V
A
4.6
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.3V
Rload = 1000Ω
V_LoSUP_1k
0.6
V
A
4.7
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 1000Ω
V_HiSUP_1k_
0.8
V
A
RLIN
20
47
kΩ
A
IBUS_LIM
50
200
mA
A
4.8 Pull up resistor to VS
serial diode required
4.9 Current limitation
VBUS = VBAT_max
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
17
9122B–AUTO–10/08
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
Test Conditions
Pin
Input leakage current
Input leakage current at the
driver off
4.10 receiver including pull-up
VBUS = 0V
resistor as specified
VBAT = 12V
Symbol
Min.
IBUS_PAS_dom
–1
Driver off
8V < VBAT < 18V
8V < VBUS < 18V
VBUS = VBAT
IBUS_PAS_rec
Leakage current at ground
loss
Control unit disconnected GNDDevice = VS
VBAT = 12V
4.12 from ground
Loss of local ground must 0V < VBUS < 18V
not affect communication in
the residual network
IBUS_NO_gnd
Leakage current LIN
4.11
recessive
Node has to sustain the
current that can flow under VBAT disconnected
4.13 this condition. Bus must
VSUP_Device = GND
remain operational under
0V < VBUS < 18V
this condition
Typ.
–1
IBUS
0.475 ×
VVBAT
0.5 ×
VVBAT
Max.
Unit Type*
mA
A
20
µA
A
+1
mA
A
100
µA
A
0.525 ×
VVBAT
V
A
0.4 ×
VVBAT
V
A
V
A
V
A
4.14 Center of receiver threshold
VBUS_CNT =
(Vth_dom + Vth_rec)/2
VBUS_CNT
4.15 Receiver dominant state
VEN = 5V
VBUSdom
4.16 Receiver recessive state
VEN = 5V
VBUSrec
4.17 Receiver input hysteresis
VHYS = Vth_rec – Vth_dom
VBUShys
4.18 Duty cycle 1
7V < VVBAT < 18V
THrec(max) = 0.744 × VVBAT
THDom(max) = 0.581 × VVBAT
tBit = 50 µs
D1 = tBus_rec(min)/(2 × tBit)
Load1: 1 nF + 1 kΩ
Load2: 10 nF + 500Ω
D1
4.19 Duty cycle 2
7V < VVBAT < 18V
THrec(min) = 0.422 × VVBAT
THDom(min) = 0.284 × VVBAT
tBit = 50 µs
D2 = tBus_rec(max)/(2×tBit)
Load1: 1 nF + 1 kΩ
Load2: 10 nF + 500Ω
D2
0.581
4.20 Receiver propagation delay
7V < VVBAT < 18V
trec_pd = max(trx_pdr, trx_pdf)
trx_pd
6
µs
Symmetry of receiver
4.21 propagation delay rising
edge minus falling edge
7V < VVBAT < 18V
trx_sym = trx_pdr – trx_pdf
trx_sym
+2
µs
0.6 ×
VVBAT
0.175 ×
VVBAT
0.396
–2
A
A
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
4.22
5
Test Conditions
Pin
Dominant time for wake-up
VLIN = 0V
via LIN-bus
Symbol
Min.
Typ.
Max.
Unit Type*
TBUS
30
90
150
µs
A
0.3 ×
VVCC
V
A
V
A
Control Inputs EN1, IL1-3, IH1-3, WD, TX, WDD
5.1 Input low-level threshold
VIL
5.2 Input high-level threshold
VIH
0.7 ×
VVCC
HYS
0.3
5.3 Hysteresis
C
5.4 Pull-down resistor
EN1, IL1-3, IH1-3, WD
RPD
25
50
100
kΩ
A
5.5 Pull-up resistor
TXD, WDD
RPU
25
50
100
kΩ
A
tgotosleep
9
10
11
µs
A
VVBAT
+ 18
V
A
V
A
µs
B
5.7 Debounce time EN1
6
Charge Pump
6.1 Charge pump voltage
VVBAT > 7V
ILoadCPOUT = 0A
ILoadVG = 0A
CCP1,2 = 47 nF
CCPOUT = 220 nF
CPOUT
VCPOUT
VVBAT
+ 11V
6.2 Charge pump voltage
VVBAT > 7V
ILoadCPOUT = 7.5 mA,
ILoadVG = 0A
CCP1,2 = 47 nF
CCPOUT = 220 nF
CPOUT
VCPOUT
VVBAT
+10V
6.3
Period charge pump
oscillator
6.4
Charge pump output
voltage for active drivers
7
2.5
TCP
CPOUT VCPCPGOOD
TBD
7.5
TBD
V
A
11
12.5
14
V
A
VG Regulator
7.1
VG Regulator Output
Voltage
VBAT = 13.5V
VCPOUT = 20V
ILoadVG = 7.5 mA
VG
VVG
7.2
VG Regulator Line
Regulation
VBAT = 13.5V
VCPOUT1 = 20V, VCPOUT2 = 35V
ILoadVG = 7.5 mA
VG
ΔVVG_Line
100
mV
A
7.3
VG Regulator Load
Regulation
VBAT = 13.5V
VCPOUT = 25V
ILoadVG1 = 1 mA, ILoadVG2 = 60 mA
VG
ΔVVG_Load
100
mV
A
VLxH
VVG
V
D
8
H-bridge Driver
8.1
Low-side driver HIGH
output voltage
8.2
ON-resistance of sink stage
ILX = 100 mA
of pins Lx
RDSON_LxL
20
Ω
A
8.3
ON-resistance of source
stage of pins Lx
RDSON_LxH
20
Ω
A
ILX = 100 mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
19
9122B–AUTO–10/08
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
Test Conditions
Pin
Symbol
Min.
–100
8.4
Output peak current at pins
VLx = 3V
Lx switched to LOW
ILxL
8.5
Output peak current at pins
VLx = 3V
Lx switched to HIGH
ILxH
8.6
Sink resistance between Lx
and GND
8.7
ON-resistance of sink stage
VSx = 0V
of pins Hx
8.8
ON-resistance of source
stage of pins Hx
Typ.
Max.
Unit Type*
mA
D
100
mA
D
115
kΩ
A
RDSON_HxL
20
Ω
A
RDSON_HxH
20
Ω
A
V – VSx = 0V;
Output peak current at pins Hx
VVBAT = 7V – 20V
8.9 Hx (switched from low to
C = 10 nF
high
R = 1Ω
IHxH,
–200
mA
C
V – VSx = 10V;
Output peak current at pins Hx
VVBAT = 7 – 20V
8.10 Hx (switched from high to
C = 10 nF
low)
R = 1Ω
IHxL
mA
C
V = 0V;
Output peak current at pins Lx
VVBAT = 7 – 20V
8.11 Hx (switched from low to
C = 10 nF
high
R = 1Ω
ILxH,
mA
C
V = 10V;
Output peak current at pins LX
VVBAT = 7 – 20V
8.12 Hx (switched from high to
C = 10 nF
low)
R = 1Ω
ILxL
mA
C
0.3
V
A
VVCPOUT
V
A
115
kΩ
A
MΩ
D
Lx to
GND
VSx = VVBAT
IHx = 100 mA
8.13
Output voltage low level
pins Hx
VSx = 0V
IHx = 1 mA
8.14
Output voltage high level
pins Hx
IHx = –100 µA
8.15
Sink resistance between Hx
and Sx
8.16
Sink resistance between Sx
and GND
RLxsink
45
75
200
–200
200
VHxL
Sx to
GND
VHxHstat
VVCPOUT
– 1V
RHxsink
45
RSxsink
75
1
Dynamic Parameters
Propagation delay time,
8.17 low-side driver from high to
low
tLxHL
0.9
µs
A
Propagation delay time,
8.18 low-side driver from low to
high
tLxLH
0.9
µs
A
8.19 Fall time low-side driver
VVBAT = 13.5V
CGx = 5 nF
tLxf
TBD
µs
A
8.20 Rise time low-side driver
VVBAT = 13.5V
CGx = 5 nF
tLxr
TBD
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN
GND. [xxx] Values for the ATA6834.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit Type*
Propagation delay time,
8.21 high-side driver from high
to low
tHxHL
0.9
µs
A
Propagation delay time,
8.22 high-side driver from low to
high
tHxLH
0.9
µs
A
8.23 Fall time high-side driver
VVBAT = 13.5V,
CGx = 5 nF
tHxf
TBD
µs
A
8.24 Rise time high-side driver
VVBAT = 13.5V,
CGx = 5 nF
tHxr
TBD
µs
A
Short circuit detection
voltage
VSC
3.5
4
4.5
V
A
8.26 Short circuit detection time
tSC
5.4
6
6.6
µs
A
KCC
TBD
0.41
TBD
9.1 Input low level threshold
VIL
2.3
3.6
V
A
9.2 Input high level threshold
VIH
2.8
4.0
V
A
V
C
8.25
Cross Conduction Timer
8.27
9
Cross conduction time
constant
B
Input EN2
9.3 Hysteresis
HYS
9.4 Pull-down resistor
RPD
50
100
200
kΩ
A
tdb
10
20
25
µs
A
2
mA
A
mA
A
9.5 Debounce time
0.47
10 Diagnostic Outputs DG1, DG2, DG3
10.1 Low level output current
VDG = 0.4V
IL
10.2 High level output current
VDG = VCC – 0.4V
IH
–2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
9122B–AUTO–10/08
9. Application
This section describes the principal application for which the ATA6833/ATA6834 was designed.
Figure 9-1.
Typical Application
Battery
+
CCPOUT
PBAT
CPOUT
CPHI2
CPLO2
CCP2
CPHI1
CPLO1
CCP1
VG
CVCC
CVG
VINT
VBAT
VBATSW
CVINT
VMODE
VCC
DG1
DG2
DG3
3.3/5V VCC
Regulator
13V
Regulator
Supervisor:
Short Circuit
Overtemperature
Undervoltage
CP
VINT 5V
Regulator
VBG
Oscillator
High-side
Driver 3
H3
High-side
Driver 2
H2
High-side
Driver 1
H1
S1
S3
WD
Logic Control
IH1-3
ATA6833/34
Low-side
Driver 1
L1
Low-side
Driver 2
L2
Low-side
Driver 3
L3
IL1-3
EN1
RX
WD
Timer
LIN
CC
Timer
CC
WDD
RWD
GND
LIN
EN2
TX
PGND
Microcontroller
S2
/RESET
ADC
Hall C
RWD
Hall B
RCC
CCC
Hall A
LIN
KL 15
22
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
Table 9-1.
Component
Typical External Components
Min.
Typical
Max.
CVINT
Function
Blocking capacitor at VINT
100 nF
220 nF/10V
470 nF
CVCC
Blocking capacitor at VCC
1.5 µF
10 µF
ESL (CVCC)
Serial inductance to CVCC including
PCB
1 nH
20 nH
ESR (CVCC)
Serial resistance to CVCC including
PCB
2Ω
15Ω
CVG
Blocking capacitor at VG
220 nF
470 nF, 25V
1 µF
CCP1
Charge pump shuffle capacitor
47 nF
220 nF/25V
470 nF
CCP2
Charge pump shuffle capacitor
47 nF
220 nF/25V
470 nF
Charge pump reservoir capacitor
220 nF
470 nF, 25V
1 µF
Resistor defining internal bias currents
for watchdog oscillator
10 kΩ
33 kΩ
91 kΩ
RCC
Cross conduction time definition
resistor
5 kΩ
10 kΩ
CCC
Cross conduction time definition
capacitor
CCPOUT
RRWD
330 pF
5 nF
23
9122B–AUTO–10/08
10. Ordering Information
Extended Type Number
Package
ATA6833-PLQW
QFN48
ATA6834-PLQW
QFN48
Remarks
11. Package Information
Package: VQFN_7 x 7_48L
Exposed pad 4.5 x 4.5
Dimensions in mm
Not indicated tolerances ±0.05
Bottom
4.5±0.15
Top
37
48
48
1
36
1
12
25
12
Pin 1 identification
24
7
Z
0.2
0.4±0.1
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5137.01-4
Issue: 1; 19.10.06
0.5 nom.
5.5
0.9±0.1
Z 10:1
13
0.23±0.07
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
24
Revision No.
History
9122B-AUTO-10/08
• Put datasheet in the latest template
• Section 8 “Electrical Characteristics” on pages 15 to 21 changed
ATA6833/ATA6834 [Preliminary]
9122B–AUTO–10/08
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9122B–AUTO–10/08