TI1 CD4053BPWG4 Cmos single 8-channel analog multiplexer/demultiplexer Datasheet

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CD4051B, CD4052B, CD4053B
SCHS047H – AUGUST 1998 – REVISED APRIL 2015
CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer
With Logic-Level Conversion
1 Features
3 Description
•
The CD405xB analog multiplexers and demuliplexers
are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current.
These multiplexer circuits dissipate extremely low
quiescent power over the full VDD – VSS and VDD –
VEE supply-voltage ranges, independent of the logic
state of the control signals.
1
•
•
•
•
•
•
•
•
Wide Range of Digital and Analog Signal Levels
– Digital: 3 V to 20 V
– Analog: ≤20 VP-P
Low ON Resistance,125 Ω (Typical) Over 15 VP-P
Signal Input Range for VDD – VEE = 18 V
High OFF Resistance, Channel Leakage of ±100
pA (Typical) at VDD – VEE = 18 V
Logic-Level Conversion for Digital Addressing
Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V)
to Switch Analog Signals to 20 VP-P (VDD – VEE =
20 V) Matched Switch Characteristics, rON = 5 Ω
(Typical) for VDD – VEE = 15 V Very Low Quiescent
Power Dissipation Under All Digital-Control Input
and Supply Conditions, 0.2 µW (Typical) at VDD –
VSS = VDD – VEE = 10 V
Binary Address Decoding on Chip
5 V, 10 V, and 15 V Parametric Ratings
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1 µA at 18 V Over Full
Package Temperature Range, 100 nA at 18 V and
25°C
Break-Before-Make Switching Eliminates Channel
Overlap
Device Information(1)
PART NUMBER
CD405xB
PACKAGE
BODY SIZE (NOM)
CDIP (16)
19.50 mm × 6.92 mm
PDIP (16)
19.30 mm × 6.35 mm
SOIC (16)
9.90 mm × 3.91 mm
SOP (16)
10.30 mm × 5.30 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagrams of CD405xB
INH
C
B
•
•
•
•
•
•
•
•
Analog and Digital Multiplexing and
Demultiplexing
A/D and D/A Conversion
Signal Gating
Factory Automation
Televisions
Appliances
Consumer Audio
Programmable Logic Circuits
Sensors
Ch 0
CBA
000
001
Ch 1
010
Ch 2
011
Ch 3
100
Ch 4
COM
101
110
111
2 Applications
•
A
CD4051B
INH
B
Ch X0
A
BA
00
Ch 6
Ch 7
INH
Ch Y0
Ch X1
X COM
01
Ch Y1
Y COM
10
Ch X2
11
Ch Y2
Ch X3
CD4052B
Ch 5
Ch Y3
ax OR ay
bx OR by
cx OR cy
A
ax
A
ay
B
bx
B
by
C
cx
C
cy
CD4053B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4051B, CD4052B, CD4053B
SCHS047H – AUGUST 1998 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
AC Performance Characteristics............................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 12
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagrams ..................................... 16
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision G (October 2003) to Revision H
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added Device Information table. ............................................................................................................................................ 1
2
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SCHS047H – AUGUST 1998 – REVISED APRIL 2015
5 Pin Configuration and Functions
CD4051B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP
(Top View)
4 1
16 VDD
6 2
15 2
COM OUT/IN 3
14 1
CHANNELS
IN/OUT
CD4052B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
CHANNELS IN/OUT
CHANNELS
IN/OUT
7 4
13 0
5 5
12 3
INH 6
0 1
16 VDD
2 2
15 2
COMMON “Y” OUT/IN 3
14 1
Y CHANNELS
IN/OUT
3 4
13 COMMON “X” OUT/IN
1 5
12 0
INH 6
11 3
VEE 7
10 A
VSS 8
9 B
Y CHANNELS
IN/OUT
11 A
VEE 7
10 B
VSS 8
9 C
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
CD4053B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
by 1
16 VDD
bx 2
15 OUT/IN bx OR by
cy 3
14 OUT/IN ax OR ay
OUT/IN CX OR CY 4
13 ay
IN/OUT CX 5
12 ax
INH 6
11 A
VEE 7
10 B
VSS 8
9 C
IN/OUT
Pin Functions CD4051B
PIN
I/O
DESCRIPTION
NO.
NAME
1
CH 4 IN/OUT
I/O
Channel 4 in/out
2
CH 6 IN/OUT
I/O
Channel 6 in/out
3
COM OUT/IN
I/O
Common out/in
4
CH 7 IN/OUT
I/O
Channel 7 in/out
5
CH 5 IN/OUT
I/O
Channel 5 in/out
6
INH
I
7
VEE
—
Negative power input
8
VSS
—
Ground
9
C
I
Channel select C. See Table 1.
10
B
I
Channel select B. See Table 1.
11
A
I
Channel select A. See Table 1.
12
CH 3 IN/OUT
I/O
Channel 3 in/out
13
CH 0 IN/OUT
I/O
Channel 0 in/out
14
CH 1 IN/OUT
I/O
Channel 1 in/out
15
CH 2 IN/OUT
I/O
Channel 2 in/out
16
VDD
—
Positive power input
Disables all channels. See Table 1.
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Pin Functions CD4052B
PIN
I/O
DESCRIPTION
NO.
NAME
1
Y CH 0 IN/OUT
I/O
Channel Y0 in/out
2
Y CH 2 IN/OUT
I/O
Channel Y2 in/out
3
Y COM OUT/IN
I/O
Y common out/in
4
Y CH 3 IN/OUT
I/O
Channel Y3 in/out
5
Y CH 1 IN/OUT
I/O
Channel Y1 in/out
6
INH
I
7
VEE
—
Negative power input
8
VSS
—
Ground
9
B
10
A
11
X CH 3 IN/OUT
I/O
Channel X3 in/out
12
X CH 0 IN/OUT
I/O
Channel X0 in/out
13
X COM IN/OUT
I/O
X common out/in
14
X CH 1 IN/OUT
I/O
Channel in/out
15
X CH 2 IN/OUT
I/O
Channel in/out
16
VDD
—
Positive power input
Disables all channels. See Table 1.
I
Channel select B. See Table 1.
I
Channel select A. See Table 1.
Pin Functions CD4053B
PIN
I/O
DESCRIPTION
NO.
NAME
1
BY IN/OUT
I/O
B channel Y in/out
2
BX IN/OUT
I/O
B channel X in/out
3
CY IN/OUT
I/O
C channel Y in/out
4
CX OR CY
OUT/IN
I/O
C common out/in
5
CX IN/OUT
I/O
C channel X in/out
6
INH
I
7
VEE
—
Negative power input
8
VSS
—
Ground
9
C
I
Channel select C. See Table 1.
10
B
I
Channel select B. See Table 1.
11
A
I
Channel select A. See Table 1.
12
AX IN/OUT
I/O
A channel X in/out
13
AY IN/OUT
I/O
A channel Y in/out
14
AX OR AY
OUT/IN
I/O
A common out/in
15
BX OR BY
OUT/IN
I/O
B common out/in
16
VDD
—
Positive power input
4
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Disables all channels. See Table 1.
Copyright © 1998–2015, Texas Instruments Incorporated
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SCHS047H – AUGUST 1998 – REVISED APRIL 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
V+ to V-, Voltages Referenced to VSS Terminal
DC Input Voltage
DC Input Current
MIN
MAX
UNIT
–0.5
20
V
–0.5
VDD + 0.5
V
–10
10
mA
Any One Input
TJMAX1
Maximum junction temperature, ceramic package
175
°C
TJMAX2
Maximum junction temperature, plastic package
150
°C
TLMAX
Maximum lead temperature, SOIC - Lead Tips Only, Soldering 10s
265
°C
Tstg
Storage temperature
150
°C
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
CD4051B in PDIP, CDIP, SOIC, SOP, TSSOP Packages
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
+3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
+2000
V
CD4053B in PDIP, CDIP, SOP and TSSOP Packages
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
+2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
+1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Temperature Range
MIN
MAX
UNIT
–55
125
°C
6.4 Thermal Information
CD405xB
THERMAL METRIC
RθJA
(1)
Junction-to-ambient thermal resistance
(1)
E (PDIP)
M (SOIC)
NS (SOP)
PW
(TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
67
73
64
108
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range, VSUPPLY = ±5 V, AV = +1, and RL = 100 Ω, (unless otherwise noted) (1)
TEST CONDITIONS
PARAMETER
VIS (V)
VEE (V)
VSS (V)
MIN
VDD (V)
TYP
MAX
UNIT
TEMP
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
5
–55°C
5
–40°C
5
25°C
0.04
150
125°C
150
–55°C
10
–40°C
10
Quiescent Device Current, IDD Max
15
25°C
10
0.04
0
0
5
85°C
300
300
–55°C
20
–40°C
20
25°C
0.04
600
125°C
600
–55°C
100
25°C
100
0.08
0
0
Change in ON Resistance
(Between Any Two Channels),
∆rON
(1)
6
0
0
10
15
0
0
5
0
0
10
0
0
15
100
85°C
3000
125°C
3000
–55°C
800
–40°C
850
25°C
470
1050
85°C
1200
125°C
1300
–55°C
310
25°C
300
180
400
85°C
520
125°C
550
–55°C
200
–40°C
210
25°C
µA
20
85°C
–40°C
Drain to Source ON Resistance rON Max
0 ≤ VIS ≤ VDD
10
125°C
–40°C
20
5
85°C
125
Ω
240
85°C
300
125°C
300
15
25°C
10
Ω
5
Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.
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Electrical Characteristics (continued)
over operating free-air temperature range, VSUPPLY = ±5 V, AV = +1, and RL = 100 Ω, (unless otherwise noted)(1)
TEST CONDITIONS
PARAMETER
VIS (V)
VEE (V)
VSS (V)
MIN
VDD (V)
TYP
MAX
UNIT
TEMP
–55°C
± 100
–40°C
OFF Channel Leakage Current: Any
Channel OFF (Max) or ALL Channels OFF
(Common OUT/IN) (Max)
25°C
0
0
± 0.01
18
±
100 (2)
nA
±
1000 (2
85°C
)
125°C
Input, CIS
–5
–5
–5
25°C
CD4051
Capacitance
Output, COS CD4052
25°C
CD4053
Feed through, CIOS
pF
18
9
0.2
VDD
Propagation Delay Time (Signal Input to
Output)
(2)
5
30
RL = 200 kΩ ,
5
CL = 50 pF,
10
tr , tf = 20 ns
15
25°C
30
60
15
30
10
20
ns
Determined by minimum feasible leakage measurement for automatic testing.
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Electrical Characteristics (continued)
over operating free-air temperature range, VSUPPLY = ±5 V, AV = +1, and RL = 100 Ω, (unless otherwise noted)(1)
TEST CONDITIONS
PARAMETER
VIS (V)
VEE (V)
VSS (V)
MIN
VDD (V)
TYP
MAX
UNIT
TEMP
CONTROL (ADDRESS OR INHIBIT), VC
5
Input Low Voltage, VIL , Max
10
15
VIL = VDD
through 1
kΩ ;
VIH = VDD
through 1
kΩ
VEE = VSS,
RL = 1 kΩ to VSS,
IIS < 2 µA on All
OFF Channels
–55°C
1.5
–40°C
1.5
25°C
1.5
85°C
1.5
125°C
1.5
–55°C
3
–40°C
3
25°C
3
85°C
3
125°C
3
–55°C
4
–40°C
4
25°C
4
85°C
4
125°C
4
–55°C
3.5
–40°C
5
25°C
3.5
3.5
85°C
3.5
125°C
3.5
–55°C
7
–40°C
Input High Voltage, VIH , Min
10
25°C
7
7
7
125°C
7
–55°C
11
25°C
85°C
Input Current, IIN (Max)
Propagation
Delay Time
Propagation
Delay Time
8
VIN = 0, 18
Address-to-Signal OUT
(Channels ON or OFF) (See
Figure 10, Figure 11, and
Figure 14)
tr , tf = 20
ns,
CL = 50
pF,
RL = 10
kΩ
Inhibit-to-Signal OUT
(Channel Turning ON) (See
Figure 11)
tr , tf = 20
ns,
CL = 50
pF,
RL = 1 kΩ
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18
V
85°C
–40°C
15
V
11
11
11
125°C
11
–55°C
± 0.1
–40°C
± 0.1
25°C
± 10–5
85°C
±1
125°C
±1
± 0.1
0
0
5
450
720
0
0
10
160
320
0
0
15
120
240
–5
0
5
225
450
0
0
5
400
720
0
0
10
160
320
0
0
15
120
240
–10
0
5
200
400
µA
ns
ns
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Electrical Characteristics (continued)
over operating free-air temperature range, VSUPPLY = ±5 V, AV = +1, and RL = 100 Ω, (unless otherwise noted)(1)
TEST CONDITIONS
PARAMETER
Propagation
Delay Time
Inhibit-to-Signal OUT
(Channel Turning OFF) (See
Figure 16)
MIN
TYP
MAX
VIS (V)
VEE (V)
VSS (V)
VDD (V)
tr , tf = 20
ns,
CL = 50
pF,
RL = 10
kΩ
0
0
5
200
450
0
0
10
90
210
0
0
15
70
160
–10
0
5
130
300
5
7.5
UNIT
TEMP
Input Capacitance, CIN (Any Address or
Inhibit Input)
ns
pF
6.6 AC Performance Characteristics
PARAMETER
TEST CONDITIONS
VIS (V)
5
VDD (V)
(1)
10
Cutoff (–3dB)
Frequency
Channel ON (Sine
Wave Input)
1
VOS at Common OUT/IN
CD4053
30
CD4052
25
CD4051
20
2 (1)
60
5
10
5 (1)
15
3
VOS at Any Channel
VOS
= – 3 dB
VIS
(1)
UNIT
MHz
VEE = VSS ,
20 Log
Total Harmonic
Distortion, THD
TYP
RL (kΩ)
0.3%
10
0.2%
0.12%
VEE = VSS, fIS = 1 kHz Sine Wave
5 (1)
10
–40dB
VEE = VSS ,
Feedthrough
Frequency
VOS
(All Channels OFF)
20 Log
= – 40dB
1
VOS at Common
OUT/IN
5
–40dB Signal
Crosstalk
Frequency
Address-or-Inhibitto-Signal
Crosstalk
(1)
(2)
10
1
10
CD4051
12
VOS
20 Log
= – 40dB
VIS
Between Any Two
Sections, CD4053
Only
10
MHz
8
Between Any two Channels
Between Sections,
CD4052 Only
VEE = VSS,
10
8
CD4052
VOS at Any Channel
VIS
(1)
CD4053
3
Measured on Common
6
Measured on Any
Channel
10
In Pin 2, Out Pin 14
2.5
In Pin 15, Out Pin 14
6
(2)
VEE = 0, VSS = 0, tr , tf = 20 ns,
VCC = VDD – VSS (Square Wave)
MHz
65
65
mVPEAK
Peak-to-Peak voltage symmetrical about (VDD - VEE) / 2.
Both ends of channel.
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6.7 Typical Characteristics
300
VDD - VEE = 5V
rON , CHANNEL ON RESISTANCE (Ω)
rON , CHANNEL ON RESISTANCE (Ω)
600
500
400
TA = 125oC
300
TA = 25oC
200
TA = -55oC
100
250
150
TA = 25oC
100
TA = -55oC
50
0
-10
0
-4
-3
-2
-1
0
1
2
3
4
5
-7.5
-5
-2.5
0
2.5
5
VIS , INPUT SIGNAL VOLTAGE (V)
rON , CHANNEL ON RESISTANCE (Ω)
TA = 25oC
VDD - VEE = 5V
500
400
300
200
10V
15V
100
0
-10
-7.5
-5
-2.5
0
2.5
5
7.5
VDD - VEE = 15V
200
TA = 125oC
150
TA = 25oC
100
TA = -55oC
50
0
-10
10
-7.5
-5
Figure 3. Channel ON Resistance vs Input Signal Voltage
(All Types)
0
2.5
7.5
105
VDD = 5V
VSS = 0V
VEE = -5V
TA = 25oC
RL = 100kΩ, RL = 10kΩ
1kΩ
500Ω
100Ω
2
-2
f
VDD = 15V
VDD = 10V
102
-4
-4
-2
0
2
4
VIS , INPUT SIGNAL VOLTAGE (V)
6
Figure 5. ON Characteristics for 1 of 8 Channels (CD4051B)
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TEST CIRCUIT
VDD
TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
104
103
0
-6
5
Figure 4. Channel ON Resistance vs Input Signal Voltage
(All Types)
PD , POWER DISSIPATION PACKAGE (µ W)
VOS , OUTPUT SIGNAL VOLTAGE (V)
6
10
-2.5
VIS , INPUT SIGNAL VOLTAGE (V)
VIS , INPUT SIGNAL VOLTAGE (V)
-6
10
250
600
4
7.5
Figure 2. Channel ON Resistance vs Input Signal Voltage
(All Types)
Figure 1. Channel ON Resistance vs Input Signal Voltage
(All Types)
rON , CHANNEL ON RESISTANCE (Ω)
TA = 125oC
200
VDD = 5V
B/D
CD4029
A B C
VDD
100Ω 11 10 9
13
14
15
12 CD4051
1
5
3
2
48 7 6 C
L
100Ω
Ι
CL = 15pF
10
1
10
102
103
104
SWITCHING FREQUENCY (kHz)
105
Figure 6. Dynamic Power Dissipation vs Switching
Frequency (CD4051B)
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TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
104
f
VDD = 15V
103
VDD = 10V
102
VDD = 5V
CL = 15pF
10
1
10
TEST CIRCUIT
VDD
CD4029
VDD B/D
A B
100Ω
10 9
1
3 CL
13
5
12
2
4 CD4052 14
15
6
11
7
8
Ι
102
103
104
SWITCHING FREQUENCY (kHz)
105
Figure 7. Dynamic Power Dissipation vs Switching
Frequency (CD4052B)
PD , POWER DISSIPATION PACKAGE (µW)
105
100Ω
PD , POWER DISSIPATION PACKAGE (µW)
Typical Characteristics (continued)
105
TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
104
VDD = 15V
VDD = 10V
103
VDD = 5V
102
CL = 15pF
TEST CIRCUIT
VDD f
9
4
CL
100Ω
3
12
5
13
100Ω
CD4053 2
10
1
11
15
6
14
7
8
Ι
10
1
10
102
103
104
SWITCHING FREQUENCY (kHz)
105
Figure 8. Dynamic Power Dissipation vs Switching
Frequency (CD4053B)
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7 Parameter Measurement Information
VDD = 15V
VDD = 7.5V
VDD = 5V
VDD = 5V
5V
7.5V
16
5V
16
16
16
VSS = 0V
VSS = 0V
VSS = 0V
VEE = 0V
7
8
VEE = -7.5V
7
8
VEE = -10V
7
8
VEE = -5V
7
8
VSS = 0V
(D)
(C)
(B)
(A)
Figure 9. Typical Bias Voltages
NOTE
The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.
tr = 20ns
tr = 20ns
tf = 20ns
90%
50%
90%
50%
90%
50%
10%
tf = 20ns
10%
90%
50%
10%
10%
TURN-ON TIME
90%
50%
90%
10%
10%
10%
TURN-OFF TIME
TURN-OFF TIME
Figure 10. Waveforms, Channel Being Turned ON
(RL = 1 kΩ)
16
15
14
13
12
11
10
9
IDD
Figure 11. Waveforms, Channel Being Turned OFF
(RL = 1 kΩ)
VDD
VDD
1
2
3
4
5
6
7
8
TURN-ON
TIME
tPHZ
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
1
2
3
4
5
6
7
8
IDD
16
15
14
13
12
11
10
9
IDD
CD4053
CD4052
Figure 12. OFF Channel Leakage Current - Any Channel OFF
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Figure 13. OFF Channel Leakage Current - All Channels OFF
VDD
1
2
3
4
5
6
7
8
VDD
VEE
16
15
14
13
12
11
10
9
VDD
OUTPUT
OUTPUT
OUTPUT
1
RL
CL
2
RL
CL
3
VDD
VEE
4
VDD
5
VEE
6
VEE
VSS CLOCK
7
IN
8
VSS
VSS
VSS
CD4051
VDD
16
15
14
13
12
11
10
9
VEE
VDD
VSS CLOCK
VSS
IN
VSS
CD4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RL
CL
VEE
VDD
VSS CLOCK
IN
VSS
CD4053
Figure 14. Propagation Delay - Address Input to Signal Output
VDD
OUTPUT
RL
1
2
3
4
5
6
7
8
50pF
VEE
VDD
VSS
VDD
CLOCK VEE
IN
VSS
16
15
14
13
12
11
10
9
VDD
OUTPUT
50pF
RL
VEE
VDD
VSS
VDD
CLOCK VEE
IN VSS
tPHL AND tPLH VSS
CD4051
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTPUT
RL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
50pF
VEE
VDD
VDD
VSS CLOCK VEE
IN VSS
VDD
V
tPHL AND tPLH SS
CD4053
V
tPHL AND tPLH SS
CD4052
Figure 15. Propagation Delay - Inhibit Input to Signal Output
VDD
VDD
VDD
µA
VIH
1K
VIH
VIL
1K
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051B
VIH
VIL
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
1K
1K
µA
VIH
1K
VIL
VIH
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
16
15
14
13
12
11
10
9
1K
µA
VIH
VIL
CD4053B
CD4052B
VIL
1
2
3
4
5
6
7
8
VIL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
Figure 16. Input Voltage Test Circuits (Noise Immunity)
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VDD
VDD
Ι
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
KEITHLEY
160 DIGITAL
MULTIMETER
TG
“ON”
10kΩ
X-Y
PLOTTER
H.P.
MOSELEY
7030A
CD4053
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
Ι
VSS
CD4051
CD4053
X
Figure 18. Channel ON Resistance Measurement
Circuit
VDD
1
2
3
4
5
6
7
8
Y
VSS
CD4052
Ι
Figure 17. Quiescent Device Current
VSS
1kΩ
RANGE
16
15
14
13
12
11
10
9
VDD
Ι
VSS
CD4052
VSS
NOTE: Measure inputs sequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS .
NOTE: Measure inputs sequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS .
Figure 19. Input Current
5VP-P
OFF
CHANNEL
1K
5VP-P
CHANNEL
ON
RF
VM
COMMON
CHANNEL
OFF
RF
VM
RL
VDD
RL
6
7
8
RL
Figure 20. Feedthrough (All Types)
5VP-P
CHANNEL
ON
RF
VM
CHANNEL
OFF
RL
Figure 21. Crosstalk Between Any Two Channels
(All Types)
CHANNEL IN Y
ON OR OFF
CHANNEL IN X
ON OR OFF
RL
RF
VM
RL
Figure 22. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
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DIFFERENTIAL
SIGNALS
CD4052
CD4052
LINK
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
RECEIVER
DIFF.
MULTIPLEXING
DEMULTIPLEXING
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs,
the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent
current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or
CD4053B.
Figure 23. Typical Time-Division Application of the CD4052B
A
B
CD4051B
C
INH
A
B
C
D
E
Q0
A
1/2
CD4556
B
E
Q1
Q2
A
B
CD4051B
C
INH
COMMON
A
B
CD4051B
C
INH
Figure 24. 24-to-1 MUX Addressing
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8 Detailed Description
8.1 Overview
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by
digital signal amplitudes of 4.5 V to 20 V (if VDD – VSS = 3 V, a VDD – VEE of up to 13 V can be controlled; for
VDD – VEE level differences above 13 V, a VDD – VSS of at least 4.5 V is required). For example, if VDD = +4.5 V,
VSS = 0 V, and VEE = –13.5 V, analog signals from –13.5 V to +4.5 V can be controlled by digital inputs of 0 V to
5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE
supply-voltage ranges, independent of the logic state of the control signals. When a logic 1 is present at the
inhibit input terminal, all channels are off.
The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an
inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to
the output.
The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C,
and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
CHANNEL IN/OUT
16 VDD
7
6
5
4
3
2
1
0
4
2
5
1
12
15
14
13
TG
TG
A 11
TG
B 10
LOGIC
LEVEL
CONVERSION
C
9
INH
6
TG
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
COMMON
OUT/IN
3
TG
TG
TG
TG
7 VEE
8 VSS
All inputs are protected by standard CMOS protection network.
Figure 25. Functional Block Diagram, CD4051B
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Functional Block Diagrams (continued)
X CHANNELS IN/OUT
3
2
1
0
11
15
14
12
TG
16 VDD
A
TG
TG
COMMON X
OUT/IN
TG
13
10
B
9
INH
6
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
3
TG
TG
COMMON Y
OUT/IN
TG
TG
8 VSS
7
VEE
1
5
2
4
0
1
2
3
Y CHANNELS IN/OUT
All inputs are protected by standard CMOS protection network.
Figure 26. Functional Block Diagram, CD4052B
LOGIC
LEVEL
CONVERSION
16 VDD
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
IN/OUT
cy
cx
by
bx
ay
ax
3
5
1
2
13
12
TG
COMMON
OUT/IN
ax OR ay
14
A 11
TG
TG
COMMON
OUT/IN
bx OR by
15
B 10
TG
COMMON
OUT/IN
C
TG
9
cx OR cy
4
TG
INH
6
VDD
8
VSS
7
VEE
All inputs are protected by standard CMOS protection network.
Figure 27. Functional Block Diagram, CD4053B
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8.3 Feature Description
The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels.
Digital signals range from 3 V to 20 V, and analog signals are accepted at levels ≤ 20 V. They have low ON
resistance, typically 125 Ω over 15 VP-P signal input range for VDD – VEE = 18 V. This allows for very little signal
loss through the switch. Matched switch characteristics are typically rON = 5 Ω for VDD – VEE = 15 V.
The CD405xB devices also have high OFF resistance, which keeps from wasting power when the switch is in the
OFF position, with typical channel leakage of ±100 pA at VDD – VEE = 18 V. Very low quiescent power dissipation
under all digital-control input and supply conditions, typically 0.2 µW at VDD – VSS = VDD – VEE = 10 V keeps
power consumption total very low. All devices have been 100% tested for quiescent current at 20 V with
maximum input current of 1 µA at 18 V over the full package temperature range, and only 100 nA at 18 V and
25°C.
Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to switch analog
signals to 20 VP-P (VDD – VEE = 20 V). Binary address decoding on chip makes channel selection easy. When
channels are changed, a break-before-make system eliminates channel overlap.
8.4 Device Functional Modes
Table 1. Truth Table (1)
INPUT STATES
INHIBIT
ON CHANNEL(S)
C
B
A
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
CD4051B
0
1
1
1
7
1
X
X
X
None
0
0
0
0x, 0y
0
0
1
1x, 1y
0
1
0
2x, 2y
0
1
1
3x, 3y
1
X
X
None
CD4052B
CD4053B
(1)
18
0
X
X
0
ax
0
X
X
1
ay
0
X
0
X
bx
0
X
1
X
by
0
0
X
X
cx
0
1
X
X
cy
1
X
X
X
None
X = Don't Care
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CD405xB multiplexers and demuliplexers can be used for a wide variety of applications.
9.2 Typical Application
One application of the CD4051B is to use it in conjunction with a microcontroller to poll a keypad. Figure 28
shows the basic schematic for such a polling system. The microcontroller uses the channel select pins to cycle
through the different channels while reading the input to see if a user is pressing any of the keys. This is a very
robust setup, allowing for multiple simultaneous key-presses with very little power consumption. It also utilizes
very few pins on the microcontroller. The down side of polling is that the microcontroller must continually scan
the keys for a press and can do little else during this process.
Microcontroller
Input
Channel Select
3.3 V
INH
C
B
A
Ch 0
CBA
000
001
010
COM
3.3 V
Ch 3
100
Ch 4
110
111
VEE
VSS
CD4051B
k1
Ch 2
011
101
VDD
Ch 1
k0
Ch 5
Ch 6
Ch 7
k2
k3
k4
k5
k6
k7
Pull-down resistors (10NŸ)
Figure 28. The CD4051B Being Used to Help Read Button Presses on a Keypad.
9.2.1 Design Requirements
These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions should be considered to prevent ringing.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For switch time specifications, see propagation delay times in Electrical Characteristics.
– Inputs should not be pushed more than 0.5 V above VDD or below VEE.
– For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics.
2. Recommended Output Conditions
– Outputs should not be pulled above VDD or below VEE.
3. Input/output current consideration: The CD405xB series of parts do not have internal current drive circuitry
and thus cannot sink or source current. Any current will be passed through the device.
9.2.3 Application Curve
VOS , OUTPUT SIGNAL VOLTAGE (V)
6
4
VDD = 5V
VSS = 0V
VEE = -5V
TA = 25oC
RL = 100kΩ, RL = 10kΩ
1kΩ
500Ω
100Ω
2
0
-2
-4
-6
-6
-4
-2
0
2
4
VIS , INPUT SIGNAL VOLTAGE (V)
6
Figure 29. ON Characteristics for 1 of 8 Channels
(CD4051B)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 30 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 30. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CD4051B
Click here
Click here
Click here
Click here
Click here
CD4052B
Click here
Click here
Click here
Click here
Click here
CD4053B
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
7901502EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
7901502EA
CD4052BF3A
8101801EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8101801EA
CD4053BF3A
CD4051BE
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU | CU SN
N / A for Pkg Type
-55 to 125
CD4051BE
CD4051BEE3
PREVIEW
PDIP
N
16
TBD
Call TI
Call TI
-55 to 125
CD4051BE
CD4051BEE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4051BE
CD4051BF
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4051BF
CD4051BF3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4051BF3A
CD4051BF3AS2283
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
CD4051BM
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BM96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BM96G3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BM96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BMG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BMT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051BM
CD4051BNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051B
CD4051BNSRE4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4051B
CD4051BPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM051B
CD4051BPWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM051B
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4051BPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM051B
CD4051BPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CM051B
CD4051BPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM051B
CD4052BE
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU | CU SN
N / A for Pkg Type
-55 to 125
CD4052BE
CD4052BEE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4052BE
CD4052BF
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4052BF
CD4052BF3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
7901502EA
CD4052BF3A
CD4052BM
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BM96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BM96E4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BM96G3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BM96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BMG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BMT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052BM
CD4052BNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052B
CD4052BNSRG4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4052B
CD4052BPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM052B
CD4052BPWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM052B
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4052BPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CM052B
CD4052BPWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
CM052B
CD4052BPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM052B
CD4053BE
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4053BE
CD4053BEE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4053BE
CD4053BF
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4053BF
CD4053BF3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8101801EA
CD4053BF3A
CD4053BF3AS2283
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
CD4053BM
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BM96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BM96E4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BM96G3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BM96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BMG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BMT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053M
CD4053BNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4053B
CD4053BPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM053B
CD4053BPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM053B
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
31-Jan-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4053BPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CM053B
CD4053BPWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
CM053B
CD4053BPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM053B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :
• Catalog: CD4051B, CD4052B, CD4053B
• Automotive: CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1
• Military: CD4051B-MIL, CD4052B-MIL, CD4053B-MIL
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD4051BM96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BM96
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BM96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BM96G3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BM96G4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BM96G4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4051BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4051BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4051BPWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4052BM96
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD4052BM96G3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD4052BM96G4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4052BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4052BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4052BPWRG3
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4052BPWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4053BM96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4053BM96
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Mar-2016
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD4053BM96G3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD4053BM96G4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD4053BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4053BPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4053BPWRG3
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4053BPWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD4051BM96
SOIC
D
16
2500
333.2
345.9
28.6
CD4051BM96
SOIC
D
16
2500
364.0
364.0
27.0
CD4051BM96
SOIC
D
16
2500
367.0
367.0
38.0
CD4051BM96G3
SOIC
D
16
2500
364.0
364.0
27.0
CD4051BM96G4
SOIC
D
16
2500
367.0
367.0
38.0
CD4051BM96G4
SOIC
D
16
2500
333.2
345.9
28.6
CD4051BPWR
TSSOP
PW
16
2000
364.0
364.0
27.0
CD4051BPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4051BPWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4052BM96
SOIC
D
16
2500
364.0
364.0
27.0
CD4052BM96G3
SOIC
D
16
2500
364.0
364.0
27.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Mar-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD4052BM96G4
SOIC
D
16
2500
333.2
345.9
28.6
CD4052BPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4052BPWR
TSSOP
PW
16
2000
364.0
364.0
27.0
CD4052BPWRG3
TSSOP
PW
16
2000
364.0
364.0
27.0
CD4052BPWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4053BM96
SOIC
D
16
2500
333.2
345.9
28.6
CD4053BM96
SOIC
D
16
2500
364.0
364.0
27.0
CD4053BM96G3
SOIC
D
16
2500
364.0
364.0
27.0
CD4053BM96G4
SOIC
D
16
2500
333.2
345.9
28.6
CD4053BPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4053BPWR
TSSOP
PW
16
2000
364.0
364.0
27.0
CD4053BPWRG3
TSSOP
PW
16
2000
364.0
364.0
27.0
CD4053BPWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
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www.ti.com/audio
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www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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