ALSC ASM5I9658-32-ER 3.3v 1:10 lvcmos pll clock generator Datasheet

ASM5I9658
July 2005
rev 0.2
3.3V 1:10 LVCMOS PLL Clock Generator
Features
and the reference clock frequency determines the VCO
ƒ
1:10 PLL based low-voltage clock generator
ƒ
Supports zero-delay operation
ƒ
3.3V power supply
ƒ
Generates clock signals up to 250MHz
ƒ
Maximum output skew of 120pS
ƒ
Differential LVPECL reference clock input
ƒ
External PLL feedback
ƒ
Drives up to 20 clock lines
ƒ
32 lead LQFP packaging
ƒ
Pin and function compatible to the MPC958 and
frequency. Both must be selected to match the VCO
frequency range. The internal VCO of the ASM5I9658 is
running at either 2x or 4x of the reference clock frequency.
The ASM5I9658 has a differential LVPECL reference input
along with an external feedback input. The ASM5I9658 is
ideal for use as a zero delay, low skew fanout buffer. The
device performance has been tuned and optimized for zero
delay performance.
MPC9658
The PLL_EN and BYPASS controls select the PLL bypass
configuration for test and diagnosis. In this configuration,
the selected input reference clock is bypassing the PLL and
routed either to the output dividers or directly to the
outputs. The PLL bypass configurations are fully static and
the minimum clock frequency specification and all other
Functional Description
The ASM5I9658 is a 3.3V compatible, 1:10 PLL based
clock generator and zero-delay buffer targeted for high
performance low-skew clock distribution in mid-range to
high-performance telecom, networking and computing
applications. With output frequencies up to 250MHz and
output skews less than 120pS the device meets the needs
of the most demanding clock applications. The ASM5I9658
is specified for the temperature range of 0°C to +70°C.
The ASM5I9658 utilizes PLL technology to frequency lock
its outputs onto an input reference clock. Normal operation
of the ASM5I9658 requires the connection of the QFB
output to the feedback input to close the PLL feedback path
(external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device
and VCO_SEL selects the operating frequency range of 50
to 125MHz or 100 to 250MHz. The two available post-PLL
PLL characteristics do not apply. The outputs can be
disabled (high-impedance) and the device reset by
asserting the MR/OE pin. Asserting MR/OE also causes the
PLL to loose lock due to missing feedback signal presence
at FB_IN. Deasserting MR/OE will enable the outputs and
close the phase locked loop, enabling the PLL to recover to
normal operation.
The ASM5I9658 is fully 3.3V compatible and requires no
external loop filter components. The inputs (except PCLK)
accept LVCMOS except signals while the outputs provide
LVCMOS compatible levels with the capability to drive
terminated 50Ω transmission lines. For series terminated
transmission lines, each of the ASM5I9658 outputs can
drive one or two traces giving the devices an effective
fanout of 1:16. The device is packaged in a 7x7 mm2
32-lead LQFP & TQFP Packages.
dividers selected by VCO_SEL (divide-by-2 or divide-by-4)
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5I9658
July 2005
rev 0.2
Block Diagram
Q0
VCC
2-25k
PCLK
PCLK
Q1
0
&
Ref
VCC
VCO
0
÷1
1
÷2
0
÷2
Q2
1
1
Q3
PLL
Q4
200-500 MHz
25k
FB_IN
Q5
FB
VCC
Q6
3-25k
Q7
PLL_EN
Q8
VCO_SEL
Q9
BYPASS
QFB
MR/OE
25k
GND
Q5
VCC
Q4
GND
Q3
Q2
Pin Configuration
VCC
Figure 1. ASM5I9658 Logic Diagram
24 23 22 21 20 19 18 17
GND
25
16
Q6
Q1
26
15
VCC
14
Q7
13
GND
Q8
VCC
27
Q0
28
ASM5I9658
GND
29
12
QFB
30
11
VCC
VCC
31
10
Q9
VCO_SEL
32
2
3
4
5
6
7
8
VCC_PLL
FB_IN
BYPASS
PLL_EN
MR/OE
PCLK
PCLK
GND
9
1
GND
Figure 2. ASM5I9658 32-Lead Package Pinout (Top View)
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9658
July 2005
rev 0.2
Table 1: Pin Configuration
Pin #
Pin Name
6
7
2
PCLK,
PCLK
FB_IN
32
VCO_SEL
I/O
Type
Input
LVPECL
Function
LVPECL reference clock signal
Input
LVCMOS
PLL feedback signal input, connect to QFB
Input
LVCMOS
Operating frequency range select
Input
LVCMOS
PLL and output divider bypass select
Input
LVCMOS
PLL enable/disable
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0-9
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
1
VCC_PLL
Supply
VCC
11,15,19,
23,27,31
VCC
Supply
VCC
3
4
5
28,26,24,
22,20,18,
16,14,12,
10
30
8,9,13,17
21,25,29
BYPASS
PLL_EN
MR/OE
Negative power supply (GND)
PLL positive power supply (analog power supply). It is recommended
to use an external RC filter for the analog power supply pin VCC_PLL.
Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected
to the positive power supply for correct operation
Table 2: FUNCTION TABLE
Control
Default
0
1
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. ASM59658 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
Selects the VCO output1
BYPASS
1
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
routed to the outputs. ASM59658 is fully static
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the output dividers.
VCO_SEL
1
VCO ÷ 1 (High frequency range).
fREF = fQ0-9 =2. fVCO
VCO ÷ 2 (Low frequency range).
fREF =fQ0-9 =4.fVCO
Outputs enabled (active)
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
PLL_EN
MR/OE
0
1
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9658
July 2005
rev 0.2
Table 3: ABSOLUTE MAXIMUM RATINGS1
Symbol
VCC
VIN
VOUT
IIN
IOUT
TS
Characteristics
Supply Voltage
Min
Max
Unit
-0.3
3.9
V
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
±20
mA
±50
mA
125
°C
DC Input Current
DC Output Current
Storage Temperature
-65
Condition
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4: GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
Latch-Up Immunity
200
mA
LU
VCC÷2
Unit
Condition
V
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
LQFP 32 Thermal resistance junction to ambient
JESD 51-3, single layer test board
4.0
pF
Inputs
Natural
convection
θJA
JESD 51-6, 2S2P multilayer test board
θJC
LQFP 32 Thermal resistance junction to case
83.1
86.0
°C/W
73.3
68.9
75.4
70.9
°C/W
63.8
57.4
65.3
59.6
°C/W
59.0
54.4
52.5
60.6
55.7
53.8
°C/W
°C/W
50.4
47.8
51.5
48.8
°C/W
23.0
26.3
°C/W
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
°C/W
°C/W
°C/W
°C/W
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural
convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
MIL-SPEC 883E
Method 1012.1
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ASM5I9658
July 2005
rev 0.2
Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)
Symbol
VIH
VIL
VPP
VCMR1
VOH
VOL
ZOUT
IIN
ICC_PLL
ICCQ
Characteristics
Min
Input high voltage
Input low voltage
2.0
Peak-to-peak input voltage
(PCLK)
Common Mode Range
(PCLK)
Output High Voltage
250
Typ
1.0
Unit
V
V
LVPECL
V
LVPECL
V
IOH=-24 mA2
0.55
0.30
V
V
IOL=24mA
IOL=12mA
2.4
14 -17
±200
Ω
µA
Maximum PLL Supply Current
12
15
mA
Maximum Quiescent Supply Current
13
15
mA
Input Current
4
Condition
LVCMOS
LVCMOS
mV
VCC-0.6
Output Low Voltage3
Output impedance
Max
VCC +0.3
0.8
VIN=VCC or GND
VCC_PLL Pin
All VCC Pins
Note: 1. VCMR (DC) is the cross point of the differential input signal. Functional operation is obtained ,when the crosspoint is within the VCMR
range and the input swing lies within the VPP (DC) specification.
2.The ASM3P9658 is capable of driving 50Ωtransmission lines on the incident edge. Each output drives one 50Ωparallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ωseries terminated transmission lines.
3.The ASM5I9658 output levels are compatible to the MPC958 output levels.
4.Inputs have pull-down or pull-up resistors affecting the input current.
3.3V 1:10 LVCMOS PLL Clock Generator
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ASM5I9658
July 2005
rev 0.2
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)1
Symbol
Characteristics
fREF
fVCO
fMAX
Input reference frequency
PLL mode, external feedback
÷2 feedback2
÷4 feedback3
Input reference frequency in PLL bypass mode4
VCO operating frequency range5
3
Output Frequency
÷2 feedback
÷4 feedback4
tsk(O)
Peak-to-peak input voltage
PCLK
Common Mode Range
PCLK
Input Reference Pulse Width7
Propagation Delay (static phase offset) 8 PCLK to
FB_IN
fREF=100MHz
any frequency
Propagation Delay PLL and divider bypass,
PCLK to Q0-9
Output-to-output Skew9
DC
Output duty cycle10
tR ,tF
tPLZ, HZ
tPZL, LZ
Output Rise/Fall Time
Output Disable Time
Output Enable Time
VPP
VCMR6
tPW,MIN
t(Ø)
tPD
Min
Max
Unit
100
50
Typ
250
125
MHz
MHz
0
200
100
50
250
MHz
500
250
125
MHz
MHz
MHz
PLL locked
PLL locked
500
1000
mV
LVPECL
1.2
VCC-0.9
V
LEPVCL
2
nS
-70
-125
+80
+125
pS
pS
1.0
4.0
120
(T÷2)+4
00
1.0
7.0
6.0
nS
pS
nS
nS
nS
(T÷2)400
0.1
T÷2
Cycle-to-cycle jitter
80
pS
tJIT(PER)
Period Jitter
I/O Phase Jitter
fVCO=500 MHz and ÷ 2 feedback, RMS (1σ)11
fVCO=500 MHz and ÷ 4 feedback, RMS (1σ)
12
÷2 feedback8
PLL closed loop bandwidth 
PLL mode, external feedback
÷4 feedback9
Maximum PLL Lock Time
80
pS
5.5
6.5
pS
pS
MHz
MHz
mS
BW
tLOCK
6-20
2-8
10
PLL locked
pS
tJIT(CC)
tJIT(Ø)
Condition
PLL locked
PLL locked
0.55 to 2.4V
Note:1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
4.In bypass mode, the ASM3P9658 divides the input reference clock.
5.The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
6.VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø).
7.Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF. 100% and DCREF,MAX = 100% - DCREF,MIN.
8.Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø) [pS] = 50 pS ± (1÷(120 . fREF)).
9.See application section for part-to-part skew calculation in PLL zero-delay mode.
10.Output duty cycle is DC = (0.5 ± 400 pS. fOUT) V 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.
11.See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies.
12.-3 dB point of PLL transfer characteristics.
3.3V 1:10 LVCMOS PLL Clock Generator
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ASM5I9658
July 2005
rev 0.2
Applications Information
Driving Transmission Lines
The ASM5I9658 supports output clock frequencies from
50 to 250MHz. Two different feedback divider
configurations can be used to achieve the desired
frequency operation range. The feedback divider
(VCO_SEL) should be used to situate the VCO in the
frequency lock range between 200 and 500MHz for
stable and optimal operation. Two operating frequency
ranges are supported: 50 to 125MHz and 100 to 250
MHz. Table 7 illustrates the configurations supported by
the ASM5I9658. PLL zero-delay is supported if
BYPASS=1, PLL_EN=1 and the input frequency is within
the specified PLL reference frequency range.
Table 7: ASM5I9658 Configurations (QFB connected to FB_IN)
BYPASS
PLL_
EN
VCO_
SEL
Operation
0
X
X
1
0
1
0
Ratio
Frequency
Output range (fQ0-7)
VCO
Test mode: PLL and divider bypass
fQ0-9 =fREF
0-250 MHz
n/a
0
Test mode: PLL bypass
fQ0-9 =fREF ÷ 2
0-125 MHz
n/a
1
Test mode: PLL bypass
fQ0-9 =fREF ÷ 4
0-62.5 MHz
n/a
1
1
0
PLL mode (high frequency range)
fQ0-9 =fREF
100 to 250 MHz
fVCO =fREF 2
1
1
1
PLL mode (low frequency range)
fQ0-9 =fREF
50 to 125 MHz
fVCO =fREF 4
Power Supply Filtering
The ASM5I9658 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA_PLL power supply impacts the
device characteristics, for instance I/O jitter. The
ASM5I9658 provides separate power supplies for the
output buffers (VCC) and the phase-locked loop (VCCA_PLL)
of the device. The purpose of this design technique is to
isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simple but effective form
of isolation is a power supply filter on the VCC_PLL pin for
the ASM5I9658. Figure 3. illustrates a typical power
supply filter scheme. The ASM5I9658 frequency and
phase stability is most susceptible to noise with spectral
content in the 100KHz to 20MHz range. Therefore the
filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is
the DC voltage drop across the series filter resistor RF.
From the data sheet the ICC_PLL current (the current
sourced through the VCC_PLL pin) is typically 12 mA (20
mA maximum), assuming that a minimum of 2.835V must
be maintained on the VCC_PLL pin.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide attenuation greater than 40 dB for
ASM5I9658
Figure 3. VCC_PLL Power Supply Filter
noise whose spectral content is above 100 KHz. In the
example RC filter shown in Figure 3.“VCC_PLL Power
Supply Filter”, the filter cut-off frequency is around 3-5
kHz and the noise attenuation at 100 kHz is better than
42dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to
look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL.
Although the ASM5I9658 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9658
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rev 0.2
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
Using the ASM5I9658 in zero-delay applications
Nested clock trees are typical applications for the
ASM5I9658. Designs using the ASM5I9658, as LVCMOS
PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions
developed from CMOS fanout buffers. The external
feedback option of the ASM59658 clock driver allows for
its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device (the
propagation delay through the device is virtually
eliminated). The maximum insertion delay of the device in
zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-tooutput skew error relative to the feedback output.
Calculation of part-to-part skew
The ASM5I9658 zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I9658 are connected together, the
maximum overall timing uncertainty from the common
PCLK input to any output is:
tSK(PP) = t(φ) + tSK(O) + tPD, LINE(FB) + tJIT(φ) _ CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Due to the statistical nature of I/O jitter a RMS value (1σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Table 8: Confidence Factor CF
Probability of clock edge within the
CF
distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (±3σ) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -214 pS to 224 pS relative to PCLK
(fREF = 100 MHz, FB=÷4, tjit(φ)=8 pS RMS at fVCO = 400
MHz):
tSK(PP) = [–70pS...80pS] + [–120pS...120pS] +
[(8pS _ –3)...(8pS _ 3)] + tPD, LINE(FB)
tSK(PP) = [–214pS...224pS] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
5. can be used for a more precise timing performance
analysis.
Figure 5. Maximum I/O Jitter versus frequency
Figure 4. ASM5I9658 max device-to-device skew
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9658
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Driving Transmission Lines
The ASM5I9658 clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20Ω the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50Ω
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM59658 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 6. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM5I9658 clock driver is
effectively doubled due to its capability to drive multiple
lines.
this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the
36Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
VL = VS ( Z0 ÷(RS+R0 +Z0))
Z0 = 50Ω|| 50 Ω
RS = 36 Ω|| 36 Ω
R0 = 14 Ω
VL = 3.0 ( 25 ÷(18+14+25))
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
ASM5I9658
OUTPUT BUFFER
IN
14Ω
Z0=50Ω
RS=36Ω
OUTA
Figure 7. Single versus Dual Waveforms
ASM5I9658
OUTPUT BUFFER
IN
Z0=50Ω
RS=36Ω
OUTB0
14Ω
RS=36Ω
Z0=50Ω
OUTB1
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the ASM5I9658 output buffer
is more than sufficient to drive 50Ω transmission lines on
the incident edge. Note from the delay measurements in
the simulations a delta of only 43pS exists between the
two differently loaded outputs. This suggests that the dual
line driving need not be used exclusively to maintain the
tight output-to-output skew of the ASM5I9658. The output
waveform in Figure 7. “Single versus Dual Line
Termination Waveforms” shows a step in the waveform,
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 8. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
ASM5I9658
OUTPUT BUFFER
IN
RS=22Ω
14Ω
RS=22Ω
Z0=50Ω
Z0=50Ω
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 8. Optimized Dual Line Termination
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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ASM5I9658
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ASM5I9658
Figure 9. PCLK ASM5I9658 AC test reference
Figure 16. Output Transition Time Test Reference
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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Package Information
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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32-lead TQFP Package
SECTION A-A
Symbol
Dimensions
Inches
Millimeters
Min
Max
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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rev 0.2
Ordering Information
Part Number
Marking
Package Type
Operating Range
ASM5I9658-32-ER
ASM5I9658
32-pin TQFP
Industrial
ASM5I9658-32-LR
ASM5I9658
32-pin LQFP –Tape and Reel
Industrial
ASM5I9658G-32-ER
ASM5I9658G
32-pin TQFP, Green
Industrial
ASM5I9658G-32-LR
ASM5I9658G
32-pin LQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M
5 I 9 6 5 8
F - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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rev 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9658
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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