Cypress CY7C1382CV25-200BGI 512k x 36/1m x 18 pipelined sram Datasheet

380CV25
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
512K x 36/1M x 18 Pipelined SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
Fast clock speed: 250, 225, 200, 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns
Optimal for depth expansion
Single 2.5V ±5% power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write cycle
Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down available using ZZ mode or CE
deselect
• Available in 119-ball bump BGA, 165-ball FBGA and
100-pin TQFP packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer
polysilicon, triple-layer metal technology. Each memory cell
consists of six transistors.
The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and
DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each
are of 8 bits wide in the case of DQ and 1 bit wide in the case
of DP.
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls
DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc,
and BWd can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the next
Read cycle. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
All inputs and outputs of the CY7C1380CV25 and the
CY7C1382CV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
2.8
3.0
3.4
ns
Maximum Operating Current
350
325
300
275
mA
Maximum CMOS Standby Current
70
70
70
70
mA
Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05240 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 20, 2002
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
CY7C1380CV25 - 512K x 36
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
Q
A[18:0]
19
GW
17
DQd, DPd
BYTEWRITE
REGISTERS
DQc, DPc
BYTEWRITE
REGISTERS
Q
D
DQb, DPb
BYTEWRITE
REGISTERS
Q
D
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
BWE
BW d
D
BWc
BWb
BWa
CE1
CE2
CE3
D
ENABLE CE
REGISTER
19
17
ADDRESS
CE REGISTER
D
512KX36
MEMORY
ARRAY
Q
36
36
Q
D ENABLE DELAY Q
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
SLEEP
CONTROL
ZZ
DQa,b,c,d
DPa,b
CY7C1382CV25 - 1M X 18
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[19:0]
GW
Q
20
BWE
BW b
18
DQb, DPb
BYTEWRITE
REGISTERS
DQa, DPa
BYTEWRITE
REGISTERS
Q
D
ENABLE CE
CE REGISTER
Q
D
D
BWa
CE1
CE2
CE3
ADDRESS
CE REGISTER
D
18
20
1M X 18
MEMORY
ARRAY
Q
18
D ENABLE DELAY Q
REGISTER
OUTPUT
REGISTERS
CLK
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b
DPa,b
Document #: 38-05240 Rev. *A
Page 2 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1382CV25
(1M x 18)
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
NC,DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
NC,DQPa
Document #: 38-05240 Rev. *A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
CY7C1380CV25
(512K X 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC,DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC,DQPd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
Top View
Page 3 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
CY7C1380CV25 (512K x 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
A
C
NC
NC
ADSP
ADSC
VDDQ
B
A
A
VDD
D
E
DQc
DQc
A
DQPc
DQc
A
VSS
VSS
NC
A
VSS
A
DQPb
CE1
VSS
OE
ADV
GW
VDD
VSS
BWb
VSS
DQb
DQb
F
VDDQ
DQc
VSS
G
H
J
DQc
DQc
VDDQ
K
DQd
BWc
VSS
NC
VSS
L
M
DQc
DQc
VDD
DQd
DQd
VDDQ
N
DQd
DQd
DQd
DQd
DQb
DQb
DQb
VDD
VDDQ
DQb
DQb
VDDQ
DQa
DQa
DQb
NC
VSS
NC
NC
BWd
VSS
CLK
NC
BWa
DQa
DQa
BWE
VSS
DQa
VSS
A1
VSS
DQa
VDDQ
DQa
A0
VDD
VSS
DQPa
DQa
A
A
NC
A
36M
NC
ZZ
TCK
TDO
NC
VDDQ
P
DQd
DQPd
VSS
R
NC
T
NC
A
72M
MODE
A
U
VDDQ
TMS
TDI
CY7C1382CV25 (1M x 18)
1
A
VDDQ
B
NC
NC
2
3
4
5
6
7
A
A
A
A
VDDQ
NC
A
VSS
CE1
VSS
VSS
VSS
VSS
A
DQPa
NC
DQa
A
A
A
ADSP
A
A
ADSC
VDD
VSS
VSS
VSS
C
D
DQb
E
NC
A
NC
DQb
F
VDDQ
NC
DQa
VDD
NC
DQa
DQa
NC
VSS
NC
VSS
DQa
VDDQ
NC
VSS
NC
DQa
36M
NC
A
A
A
NC
ZZ
TCK
TDO
NC
VDDQ
DQb
NC
VDD
DQb
NC
BWb
VSS
NC
VSS
VSS
CLK
NC
BWa
DQb
NC
VSS
VSS
BWE
DQb
A1
P
NC
DQPb
VSS
R
NC
T
72M
A
A
MODE
A
A0
VDD
U
VDDQ
TMS
TDI
VDDQ
K
NC
L
M
VDDQ
N
Document #: 38-05240 Rev. *A
NC
DQb
DQb
NC
DQa
VDDQ
DQa
NC
VDDQ
OE
ADV
GW
VDD
G
H
J
NC
NC
NC
VSS
NC
Page 4 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Configurations (continued)
165-Ball Bump FBGA
CY7C1380CV25 (512K x 36) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWc
BWb
CE3
BWE
ADSC
ADV
A
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
DPc
A
NC
CE2
VDDQ
BWd
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPb
DQb
R
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
DQd
VSS
DQd
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
DQa
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DPd
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
DPa
NC
72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
36M
A
A
TMS
A0
TCK
A
A
A
A
11
CY7C1382CV25 (1M x 18) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
9
10
A
NC
A
CE1
BWb
NC
CE3
BWE
ADSC
ADV
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
A
NC
CE2
VDDQ
NC
VSS
BWa
VSS
CLK
VSS
GW
VSS
OE
VSS
ADSP
VDDQ
A
NC
144M
DPa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VSS
NC
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
NC
DQb
DQb
NC
NC
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
NC
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DPb
NC
VDDQ
VSS
NC
A
VSS
VSS
VDDQ
NC
NC
NC
72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05240 Rev. *A
Page 5 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only)
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
MODE
Input-Pin
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time
critical “sleep” condition with data integrity preserved.
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A[X] during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP
a,b,c, and d are 1 bit wide.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. (BGA Only)
TDI
JTAG serial input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.(BGA
Only)
Document #: 38-05240 Rev. *A
Page 6 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the
rising edge of TCK. (BGA Only)
TCK
JTAG serial clock
Serial clock to the JTAG circuit. (BGA Only)
VDD
Power Supply
VSS
Ground
VDDQ
I/O Power Supply
VSSQ
I/O Ground
Power supply inputs to the core of the device. Should be connected to 2.5V
± 5% power supply.
Ground for the core of the device. Should be connected to ground of the
system.
Power supply for the I/O circuitry.
Ground for the I/O circuitry. Should be connected to ground of the system.
NC
-
No Connects.Pins are not internally connected.
36M
72M
144M
-
No Connects. Reserved for address expansion.
Document #: 38-05240 Rev. *A
Page 7 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Introduction
(GW, BWE, and BWx) and ADV inputs are ignored during this
first cycle.
Functional Overview
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx signals. The CY7C1380CV25/CY7C1382CV25 provides byte
write capability that is described in the write cycle description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1380CV25 and
BWa,b for CY7C1382CV25) input will selectively write to only
the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
The CY7C1380CV25/CY7C1382CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium® and
i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1380V25 and
BWa,b for CY7C1382V25) inputs. A Global Write Enable (GW)
overrides all byte write inputs and writes data to all four bytes.
All writes are simplified with on-chip synchronous self-timed
write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is loaded into the address register and the address advancement
logic while being delivered to the RAM core. The write signals
Document #: 38-05240 Rev. *A
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the output enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will threestate the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data
presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the output enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1380CV25/CY7C1382CV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel® Pentium applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Page 8 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Sleep Mode
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
tZZS
tZZREC
Max.
Unit
ZZ > VDD − 0.2V
60
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
Document #: 38-05240 Rev. *A
Min.
2tCYC
ns
Page 9 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Cycle Descriptions[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
0
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
0
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
0
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
0
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
0
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
0
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
0
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
0
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
0
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2 and CE3 are available only in the TQFP package. The BGA package has a single chip select, CE1.
Document #: 38-05240 Rev. *A
Page 10 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Write Cycle Descriptions[1, 5, 6]
Function (1380CV25)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQa
1
0
1
1
1
0
Write Byte 1 – DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1382CV25)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 – DQ[7:0] and DP0
1
0
1
0
Write Byte 1 – DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Notes:
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or
when the device is deselected, and DQ = data when OE is active.
Document #: 38-05240 Rev. *A
Page 11 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380CV25/CY7C1382CV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation of the device.
Test Access Port (TAP)—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions
are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuitDocument #: 38-05240 Rev. *A
Page 12 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the ShiftIR state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
Document #: 38-05240 Rev. *A
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05240 Rev. *A
Page 14 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −1.0 mA
1.7
V
VOH2
Output HIGH Voltage
IOH = −100 µA
2.1
V
VOL1
Output LOW Voltage
IOL = 1.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
−0.3
0.7
V
IX
Input Load Current
−5
5
µA
GND < VI < VDDQ
Notes:
7. All Voltage referenced to Ground.
8. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2, Undershoot: VIL(AC) > −0.5V for t < tTCYC/2.
Document #: 38-05240 Rev. *A
Page 15 of 33
PRELIMINARY
CY7C1380CV25
CY7C1382CV25
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameters
Description
Min.
Max
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
100
ns
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Set-up Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
ns
ns
Notes:
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
Document #: 38-05240 Rev. *A
Page 16 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z0 = 50Ω
1.25V
CL = 20 pF
0V
GND
(a)
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
Document #: 38-05240 Rev. *A
tTDOX
Page 17 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Identification Register Definitions
Instruction Field
512K x 36
1M x 18
Revision Number
(31:28)
0100
0100
Reserved for version number
Cypress Device ID
(27:24)
1011
1011
Reserved for internal use
Device Type
(23:18)
000000
000000
Defines memory type and architecture
Device Width and Density
(17:12)
100101
010101
Defines width and density
000001101001
000001101001
Cypress JEDEC ID
(11:0)
Description
Allows unique identification of SRAM
vendor
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
51
70
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05240 Rev. *A
Page 18 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Boundary Scan Order (512K x 36)
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Boundary Scan Order (1M x 18)
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
1
TBD
TBD
36
TBD
TBD
1
TBD
TBD
36
TBD
TBD
2
TBD
TBD
37
TBD
TBD
2
TBD
TBD
37
TBD
TBD
3
TBD
TBD
38
TBD
TBD
3
TBD
TBD
38
TBD
TBD
4
TBD
TBD
39
TBD
TBD
4
TBD
TBD
39
TBD
TBD
5
TBD
TBD
40
TBD
TBD
5
TBD
TBD
40
TBD
TBD
6
TBD
TBD
41
TBD
TBD
6
TBD
TBD
41
TBD
TBD
7
TBD
TBD
42
TBD
TBD
7
TBD
TBD
42
TBD
TBD
8
TBD
TBD
43
TBD
TBD
8
TBD
TBD
43
TBD
TBD
9
TBD
TBD
44
TBD
TBD
9
TBD
TBD
44
TBD
TBD
10
TBD
TBD
45
TBD
TBD
10
TBD
TBD
45
TBD
TBD
11
TBD
TBD
46
TBD
TBD
11
TBD
TBD
46
TBD
TBD
12
TBD
TBD
47
TBD
TBD
12
TBD
TBD
47
TBD
TBD
13
TBD
TBD
48
TBD
TBD
13
TBD
TBD
48
TBD
TBD
14
TBD
TBD
49
TBD
TBD
14
TBD
TBD
49
TBD
TBD
15
TBD
TBD
50
TBD
TBD
15
TBD
TBD
50
TBD
TBD
16
TBD
TBD
51
TBD
TBD
16
TBD
TBD
51
TBD
TBD
17
TBD
TBD
52
TBD
TBD
17
TBD
TBD
52
TBD
TBD
18
TBD
TBD
53
TBD
TBD
18
TBD
TBD
53
TBD
TBD
19
TBD
TBD
54
TBD
TBD
19
TBD
TBD
54
TBD
TBD
20
TBD
TBD
55
TBD
TBD
20
TBD
TBD
55
TBD
TBD
21
TBD
TBD
56
TBD
TBD
21
TBD
TBD
56
TBD
TBD
22
TBD
TBD
57
TBD
TBD
22
TBD
TBD
57
TBD
TBD
23
TBD
TBD
58
TBD
TBD
23
TBD
TBD
58
TBD
TBD
24
TBD
TBD
59
TBD
TBD
24
TBD
TBD
59
TBD
TBD
25
TBD
TBD
60
TBD
TBD
25
TBD
TBD
60
TBD
TBD
26
TBD
TBD
61
TBD
TBD
26
TBD
TBD
61
TBD
TBD
27
TBD
TBD
62
TBD
TBD
27
TBD
TBD
62
TBD
TBD
28
TBD
TBD
63
TBD
TBD
28
TBD
TBD
63
TBD
TBD
29
TBD
TBD
64
TBD
TBD
29
TBD
TBD
64
TBD
TBD
30
TBD
TBD
65
TBD
TBD
30
TBD
TBD
65
TBD
TBD
31
TBD
TBD
66
TBD
TBD
31
TBD
TBD
66
TBD
TBD
32
TBD
TBD
67
TBD
TBD
32
TBD
TBD
67
TBD
TBD
33
TBD
TBD
68
TBD
TBD
33
TBD
TBD
68
TBD
TBD
34
TBD
TBD
69
TBD
TBD
34
TBD
TBD
69
TBD
TBD
35
TBD
TBD
70
TBD
TBD
35
TBD
TBD
70
TBD
TBD
Document #: 38-05240 Rev. *A
Page 19 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –55°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND ....... –0.3V to +3.6V
DC Voltage Applied to Outputs
in High Z State[11] ................................ –0.5V to VDDQ + 0.5V
DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temp.[12]
VDD/VDDQ
0°C to 70°C
2.5V ± 5%
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
VDD/VDDQ
Description
Test Conditions
Power Supply Voltage
Min.
Max.
Unit
2.375
2.625
V
VOH
Output HIGH Voltage
VDD = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
VIH
Input HIGH Voltage
1.7
VDD +
0.3
VIL
Input LOW Voltage[11]
–0.3
0.7
IX
Input Load Current
except ZZ and MODE
–5
5
µA
IZZ
Input Current of MODE
2.0
V
0.4
GND < VI < VDDQ
−30
30
µA
Input Current of ZZ
Input = VSS
−30
30
µA
IOZ
Output Leakage Current
GND < VI < VDDQ, Output Disabled
–5
5
µA
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
350
mA
4.4-ns cycle, 225 MHz
325
mA
5.0-ns cycle, 200 MHz
300
mA
6.0-ns cycle, 167 MHz
275
mA
4.0-ns cycle, 250 MHz
120
mA
4.4-ns cycle, 225 MHz
110
mA
5.0-ns cycle, 200 MHz
100
mA
6.0-ns cycle, 167 MHz
90
mA
All speed grades
70
mA
ISB1
Automatic CE PowerMax. VDD, Device Deselected,
Down Current—TTL Inputs VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
ISB2
Automatic CE PowerDown Current—CMOS
Inputs
Max. VDD, Device Deselected,
VIN < 0.3V or VIN > VDDQ – 0.3V,
f=0
ISB3
Automatic CE PowerDown Current—CMOS
Inputs
Max. VDD, Device Deselected, or 4.0-ns cycle, 250 MHz
VIN < 0.3V or VIN > VDDQ – 0.3V
4.4-ns cycle, 225 MHz
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
105
mA
100
mA
95
mA
6.0-ns cycle, 167 MHz
85
mA
All Speeds
80
mA
ISB4
Automatic CE PowerMax. VDD, Device Deselected,
Down Current—TTL Inputs VIN > VIH or VIN < VIL, f = 0
Shaded areas contain advance information.
Notes:
11. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
12. TA is the temperature.
Document #: 38-05240 Rev. *A
Page 20 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Capacitance[13]
Max.
Parameter
Description
CIN
Input Capacitance
CCLK
CI/O
Test Conditions
TA = 25°C, f = 1 MHz
100-TQFP
119-BGA
165-FBGA
Unit
TBD
TBD
TBD
pF
Clock Input Capacitance
TBD
TBD
TBD
pF
Input/Output Capacitance
TBD
TBD
TBD
pF
AC Test Loads and Waveforms[14]
R = 1667Ω
VDDQ
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 = 50Ω
Rt = 50Ω
2.5V
10%
5 pF
Vt - Termination Voltage (a)
Rt - Termination Resistance
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
R = 1538Ω
≤ 1 ns
30 pF
Vt = 1.25
[10]
≤ 1 ns
(c)
(b)
Thermal Resistance[13]
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Symbol
TQFP
119 BGA
165 FBGA
Unit
Still Air, soldered on a 3
x 4.5 inch2, 2-layer
printed circuit board
ΘJA
31
45
46
°C/W
ΘJC
6
7
3
°C/W
Notes:
13. Tested initially and after any design or process changes that may affect these parameters.
14. Input waveform should have a slew rate of < 1 ns.
Document #: 38-05240 Rev. *A
Page 21 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Characteristics Over the Operating Range[15, 16, 17]
-250
Parameter
Description
Min.
Max.
-225
Min.
Max.
-200
Min.
Max.
-167
Min.
Max.
Unit
tCYC
Clock Cycle Time
4.0
4.4
5
6
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.2
ns
tCL
Clock LOW
1.7
2.0
2.0
2.2
ns
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.0
1.0
1.3
1.3
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.2
1.4
1.4
1.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tWES
BWE, GW, BWx Set-up Before CLK Rise
1.2
1.4
1.4
1.5
ns
tWEH
BWE, GW, BWx Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.4
1.4
1.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.4
1.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tCES
Chip Enable Set-up
1.2
1.4
1.4
1.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.4
0.5
ns
tCHZ
tCLZ
Clock to
High-Z[16]
Clock to
Low-Z[16]
1.0
High-Z[16, 17]
OE HIGH to Output
tEOLZ
OE LOW to Output Low-Z[16, 17]
OE LOW to Output
2.8
2.6
tEOHZ
tEOV
2.6
Valid[16]
2.8
1.0
2.6
0
2.8
3.4
1.3
3.0
0
2.8
3.4
3.0
1.3
0
2.6
3.0
ns
ns
3.4
0
3.0
ns
ns
ns
3.4
ns
Shaded areas contain preliminary information.
Notes:
15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steadystate voltage.
17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
Document #: 38-05240 Rev. *A
Page 22 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
1
Switching Waveforms
Write Cycle Timing[4, 18, 19, 20]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data High-Z
In
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
18. WE is the combination of BWE and BWx to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
20. Device originally deselected.
Document #: 38-05240 Rev. *A
Page 23 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[4, 18, 20, 21]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tCEH
tEOV
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
= DON’T CARE
tCHZ
= UNDEFINED
Note:
21. RDx stands for Read Data from Address X.
Document #: 38-05240 Rev. *A
Page 24 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 18, 19, 20, 21]
Single Read
tCYC
Single Write
Single Write
Single cycle
deselect
Burst Read
tCH
Pipelined Read
CLK
tADS
tADH
tCL
ADSP
ADSC
tADVS
ADV
tAS
ADD
tADVH
RD1
WD2
WD3
RD4
RD5
tAH
GW
tWS
tWS
tWH
WE
tCES
tWH
tCEH
CE1 Unselected
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tEOV
OE
Data In/Out
tEOHZ
tEOLZ
tCO
1a
1a
Out
2a
In
tDS
= DON’T CARE
Document #: 38-05240 Rev. *A
4a
Out
3a
In
= UNDEFINED
tDH
tDOH
4b
Out
4c
Out
4d
Out
tCHZ
I/O Disabled within one clock
cycle after deselect
Page 25 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read/Write Timing[4, 18, 19, 20, 21]
Selected
ADSP read
ADSC read
Unselected
ADSC write
ADSP write
CLK
ADSP
ADSC
ADV
ADD
RD1
RD2
RD3
RD4
WD5
WD6
5a
In
6a
In
WD8
WD7
GW
WE
CE1
CE2
CE3
OE
Data In/Out
1a
1a
Out
2a
Out
3a
Out
= DON’T CARE
Document #: 38-05240 Rev. *A
4a
Out
7a
In
= UNDEFINED
Page 26 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
I/Os
Three-State
tEOLZ
Document #: 38-05240 Rev. *A
Page 27 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing [4, 22, 23]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
23. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05240 Rev. *A
Page 28 of 33
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Ordering Information
Speed
(MHz)
250
225
200
167
225
200
167
Ordering Code
CY7C1382CV25-250AC
CY7C1380CV25-250AC
Package
Name
A101
Package Type
Operating
Range
100-Lead Thin Quad Flat Pack
Commercial
CY7C1382CV25-250BGC
CY7C1380CV25-250BGC
BG119
119 PBGA
CY7C1382CV25-250BZC
CY7C1380CV25-250BZC
BB165A
165 FBGA
CY7C1382CV25-225AC
CY7C1380CV25-225AC
A101
100-Lead Thin Quad Flat Pack
CY7C1382CV25-225BGC
CY7C1380CV25-225BGC
BG119
119 PBGA
CY7C1382CV25-225BZC
CY7C1380CV25-225BZC
BB165A
165 FBGA
CY7C1382CV25-200AC
CY7C1380CV25-200AC
A101
100-Lead Thin Quad Flat Pack
CY7C1382CV25-200BGC
CY7C1380CV25-200BGC
BG119
119 PBGA
CY7C1382CV25-200BZC
CY7C1380CV25-200BZC
BB165A
165 FBGA
CY7C1382CV25-167AC
CY7C1380CV25-167AC
A101
100-Lead Thin Quad Flat Pack
CY7C1382CV25-167BGC
CY7C1380CV25-167BGC
BG119
119 PBGA
CY7C1382CV25-167BZC
CY7C1380CV25-167BZC
BB165A
165 FBGA
CY7C1382CV25-225AI
CY7C1380CV25-225AI
A101
100-Lead Thin Quad Flat Pack
CY7C1382CV25-225BGI
CY7C1380CV25-225BGI
BG119
119 PBGA
CY7C1382CV25-225BZI
CY7C1380CV25-225BZC
BB165A
165 FBGA
CY7C1382CV25-200AI
CY7C1380CV25-200AI
A101
Industrial
100-Lead Thin Quad Flat Pack
CY7C1382CV25-200BGI
CY7C1380CV25-200BGI
BG119
119 PBGA
CY7C1382CV25-200BZI
CY7C1380CV25-200BZI
BB165A
165 FBGA
CY7C1382CV25-167AI
CY7C1380CV25-167AI
A101
100-Lead Thin Quad Flat Pack
CY7C1382CV25-167BGI
CY7C1380CV25-167BGI
BG119
119 PBGA
CY7C1382CV25-167BZI
CY7C1380CV25-167BZI
BB165A
165 FBGA
Shaded areas contain advance information and parts that may not be offered.
Document #: 38-05240 Rev. *A
Page 29 of 33
PRELIMINARY
CY7C1380CV25
CY7C1382CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05240 Rev. *A
Page 30 of 33
PRELIMINARY
CY7C1380CV25
CY7C1382CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
Document #: 38-05240 Rev. *A
Page 31 of 33
PRELIMINARY
CY7C1380CV25
CY7C1382CV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
may be trademarks of their respective holders.
Document #: 38-05240 Rev. *A
Page 32 of 33
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document History Page
Document Title: CY7C1380CV25/CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM
Document Number: 38-05240
Rev.
ECN No.
Issue
Date
Orig. of
Change
**
116280
08/29/02
SKX
New Data Sheet
*A
121543
11/21/02
DSG
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
Document #: 38-05240 Rev. *A
Description of Change
Page 33 of 33
Similar pages