TI CDC9841 Pc motherboard clock synthesizer/driver with 3-state output Datasheet

CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
D
D
D
Four CPU Clock Outputs With
Programmable Frequency
(50 MHz, 60 MHz, and 66 MHz)
Six Clock Outputs at Half-CPU Frequency
for PCI
One 24-MHz Clock Output
One 12-MHz Clock Output
Two 14.318-MHz Reference Outputs
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Lock Loops
Eliminate the Need for External
Components
Operates at 3.3 VCC
Distributed VCC and Ground Pins Reduce
Switching Noise
Packaged in Plastic Small-Outline Package
DW PACKAGE
(TOP VIEW)
VCC
X1
X2
GND
OE
PCLK0
PCLK1
VCC
PCLK2
PCLK3
GND
SEL1
SEL0
VCC
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
REF0
REF1
VCC
CLK12
CLK24
GND
BCLK2
BCLK3
VCC
BCLK4
BCLK5
GND
BCLK1
BCLK0
description
The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals
necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs
(PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1
control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency
of PCLKn and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, the four fixed-frequency
outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz
input reference (REF0, REF1).
The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be
provided at X1 instead of a crystal input.
Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop
filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock
frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can
be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
Because the CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the SELn inputs.
PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state
and are enabled via OE.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
FUNCTION TABLE
2
OE
SEL0
SEL1
X1
PCLKn
BCLKn
REFn
CLK24
CLK12
L
X
X
14.31818 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
L
14.31818 MHz
50 MHz
25 MHz
14.318 MHz
24 MHz
12 MHz
H
L
H
14.31818 MHz
60 MHz
30 MHz
14.318 MHz
24 MHz
12 MHz
H
H
L
14.31818 MHz
TCLK†
66 MHz
33 MHz
14.318 MHz
24 MHz
12 MHz
H
H
H
TCLK /2
† TCLK is a test clock input at the X1 input during test mode.
TCLK /4
TCLK
TCLK /4
TCLK /8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
functional block diagram
OE
X2
5
28
3
REF0
OSC
X1
2
27
24
÷2
REF1
CLK24
÷2
÷2
25
6
CLK12
PCLK0
24-MHZ
PLL
7
9
10
PCLK1
PCLK2
PCLK3
CPU CLK
PLL
÷2
15
16
SEL0
SEL1
BCLK0
BCLK1
13
12
Select
Logic
22
21
19
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
BCLK2
BCLK3
BCLK4
BCLK5
3
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
IOHmax
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level input voltage
MIN
MAX
3.135
3.6
2
VCC
– 12
V
REF0
REF1
–8
PCLKn
–6
BCLKn
– 12
CLK24, CLK12
–4
REF0
12
REF1
8
PCLKn
6
BCLKn
12
CLK24, CLK12
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
0
Low-level output current
V
0.8
Input voltage
High-level output current
UNIT
mA
mA
4
0
70
°C
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
TEST CONDITIONS
VCC = 3.135 V,
II = –18 mA
IOH = – 12 mA
VCC = 3.135 V
VCC = 3.135 V
UNIT
–1.2
V
REF0
2.5
REF1
2.5
PCLKn
2.5
IOH = – 12 mA
BCLKn
2.5
IOH = – 4 mA
CLK24 CLK12
CLK24,
25
2.5
IOL = 12 mA
IOL = 8 mA
REF0
0.4
REF1
0.4
IOL = 6 mA
IOL = 12 mA
PCLKn
0.4
BCLKn
0.4
IOL = 4 mA
CLK24 CLK12
CLK24,
04
0.4
VCC = 3.6 V,
VCC = 3.6 V,
VI = VCC or GND
VO = VCC or GND
ICC
VCC = 3.6 V,,
VI = VCC or GND
IO = 0,,
Co
MAX
IOH = – 8 mA
IOH = – 6 mA
II
IOZ
Ci
MIN
V
V
±1
µA
±10
µA
Outputs enabled†
50
Outputs disabled
1
VI = VCC or GND
VO = VCC or GND
mA
pF
pF
Cpd
VI = 3 V or 0
† Device in normal operating mode with no load on outputs
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
Stabilization time‡
MAX
After SEL1, SEL0
5
After OE↑
5
After power up
5
UNIT
ms
‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
switching characteristics (see Figures 1 and 2)
PARAMETER
FROM
(
)
(INPUT)
VCC = 3.135 V
to 3.6 V,
TA = 0°C to 70°C
TO
(
)
(OUTPUT)
MIN
tskew†
Offset†
Jitter†
Jitt
Duty cycle†
200
BCLKn (CL = 30 pF)
400
1
4
PCLKn (CL = 20 pF)
±250
BCLKn (CL = 30 pF)
±350
45%
Any output
PCLKn (CL = 20 pF)
tc
BCLKn (CL = 30 pF)
tr†‡
tf†‡
MAX
PCLKn (CL = 20 pF)
BCLKn (CL = 30 pF)
PCLKn (CL = 20 pF)
SEL0 = L, SEL1 = L
20
SEL0 = L, SEL1 = H
16.7
SEL0 = H, SEL1 = L
15
SEL0 = L, SEL1 = L
40
SEL0 = L, SEL1 = H
33.3
SEL0 = H, SEL1 = L
30
UNIT
ps
ns
ps
55%
ns
PCLKn (CL = 20 pF),
pF) BCLKn (CL = 30 pF)
2
ns
PCLKn (CL = 20 pF)
pF), BCLKn (CL = 30 pF)
† Specifications are applicable only after the PLL stabilization time has elapsed.
‡ Rise and fall times are characterized using the load circuits shown in Figure 1.
2
ns
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC9841
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
tc
Duty Cycle
From Output
Under Test
CL
(see Note A)
500 Ω
2.4 V
1.5 V
0.4 V
LOAD CIRCUIT
tr
tf
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
VOH
1.5 V
CPU Clock
(PCLK)
GND
VOH
1.5 V
CPU Clock
(PCLK)
GND
skew
PCLK-to-PCLK Skew
VOH
1.5 V
PCI Clock
(BCLK)
GND
VOH
1.5 V
PCI Clock
(BCLK)
GND
skew
BCLK-to-BCLK Skew
VOH
1.5 V
CPU Clock
(PCLK)
GND
VOH
1.5 V
PCI Clock
(BCLK)
GND
offset
offset
PCLK-to-BCLK Offset
Figure 2. Waveforms for Calculation of tskew and Offset
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDC9841DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
CDC9841DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2005, Texas Instruments Incorporated
Similar pages