Sony CXA3562R Lcd driver Datasheet

CXA3562R
LCD Driver
Description
The CXA3562R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports digital 2-parallel and single input, and the
input data is analog demultiplexed into 12 phases and
output. The CXA3562R can directly drive an LCD
panel, and the VCOM setting circuit and precharge
pulse waveform generator are also on-chip.
100 pin LQFP (Plastic)
Features
• Supports 10-bit 2-parallel and single input
• Supports signals up to UXGA
(1/2 clock when using UXGA signals)
• Low output deviation by on-chip output offset cancel circuit
• Supports both line inversion and dot and line inversion
• On-chip timing generator with ECL
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC
16
V
VDD
5.5
V
• Operating temperature
Topr
–20 to +70
°C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
2300
mW
Recommended Operating Conditions
• Supply voltage
VCC
15.0 to 15.5
VDD
4.75 to 5.25
• Operating temperature
Topr
–20 to +70
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01115-PS
CXA3562R
SH_OUT1
NC
VCOM_OUT
VCOM_OFST
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
Block Diagram and Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D_A9 76
50 PVCC
SID Gen.
D_A8 77
VCOM Gen.
49 SH_OUT2
Vref Gen.
D_A7 78
48 NC
Line Inv.
D_A6 79
Offset Cancel
47 SH_OUT3
D_A5 80
Line Inv.
46 NC
Offset Cancel
Line Inv.
45 SH_OUT4
Offset Cancel
Line Inv.
43 SH_OUT5
D_A4 81
D_A3 82
D_A2 83
D/A
D_A1 84
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
44 NC
42 NC
Offset Cancel
Line Inv.
D_A0 85
S/H
S/H
S/H
GND 86
S/H
S/H
S/H
S/H
S/H
S/H
Offset Cancel
38 PGND
GND 89
S/H
S/H
S/H
Line Inv.
37 GND
GND 90
S/H
S/H
S/H
36 GND
S/H
S/H
S/H
Offset Cancel
Line Inv.
S/H
S/H
S/H
D_B6 94
S/H
S/H
S/H
D_B5 95
S/H
S/H
S/H
D_B9 91
D_B8 92
D_B7 93
D/A
D_B4 96
D_B3 97
D_B2 98
D_B1 99
FRP_OD
FRP_EV
TG
40 GND
Offset Cancel
Line Inv.
GND 87
GND 88
41 SH_OUT6
39 GND
35 SH_OUT7
Offset Cancel
Line Inv.
34 NC
Offset Cancel
Line Inv.
32 NC
33 SH_OUT8
Offset Cancel
Line Inv.
31 SH_OUT9
Offset Cancel
Line Inv.
29 SH_OUT10
Offset Cancel
27 SH_OUT11
30 NC
28 NC
D_B0 100
26 PVCC
Offset Cancel Level Gen.
POSCTR3
SH_OUT12
POSCTR2
NC
POSCTR1
DCFBOFF
POSCTR0
CAL_IL
SHST
GND
FRP
CAL_IH
MCLKX
CAL_OH
TEST
–2–
CAL_OL
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SIG_OFST
8
SIG.C
7
GND
6
GND
5
GND
4
GND
3
GND
2
SHTEST
1
MCLK
CAL_PLS
CXA3562R
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
I
PECL
differential
(amplitude
0.4V or more
between
VDD to 2V)
or TTL input
Equivalent circuit
Description
VDD
2
3
MCLK
MCLKX
140k
8k
140k
100µ
60k
1k
2
1k
3
60k
Dot clock input.
PECL differential input or TTL
input. For TTL input, input to
MCLK and connect MCLKX to
GND through a capacitor.
GND
VDD
50k
4
FRP
I
High: ≥2.0V
Low: ≤0.8V
192
4
LCD panel AC drive inversion
timing input.
High: inverted
Low: non-inverted
See the Timing Chart.
GND
VDD
50k
5
SHST
I
192
High: ≥2.0V
Low: ≤0.8V
5
GND
VDD
6
7
8
9
POSCTR0
POSCTR1
POSCTR2
POSCTR3
50k
I
High: ≥2.0V
Low: ≤0.8V
192
6
8
7
9
Internal sample-and-hold timing
circuit reset pulse input.
This pin is also used as the
offset cancel level insertion
timing input.
A reset is applied to the internal
timing generator at the falling
edge.
Output phase adjustment.
The output phase is adjusted in
MCLK period units when
SL_DAT (Pin 72) is high, and in
1/2 MCLK period units when
SL_DAT is low.
GND
VDD
VCC
20µ
30k
16
SIG.C
I
1 to 5.0V
16
Signal center voltage (inversion
folded voltage) adjustment input.
The SH_OUT output center
voltage can be adjusted in the
range from 7.0 to 8.0V.
GND
VDD
VCC
10µ
30k
17
SIG_OFST
I
0 to 5.0V
17
GND
–3–
Output signal offset adjustment
from signal center voltage.
The SH_OUT output 100%
white level (at 3FF input) voltage
can be adjusted in the range
from 0 to 1V from the center
voltage.
CXA3562R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VCC
40µ
18
19
CAL_OL
CAL_OH
O
1k
3.0 to 6.0V
9.0 to 12.0V
Level output for canceling the
offset between channels.
Connect directly to CAL_IL and
CAL_IH, respectively.
145
18
19
GND
Level input for canceling the
offset between channels.
Connect directly to CAL_OL and
CAL_OH, respectively. When
using two CXA3562R, connect
the CAL_IL and CAL_IH of both
chips to the CAL_OL and
CAL_OH of only one CXA3562R.
VCC
20k
21
22
CAL_IH
CAL_IL
O
9.0 to 12.0V
3.0 to 6.0V
30k
21
22
20µ
GND
VDD
24k
24k
24
DCFBOFF
I
145
GND
24
Offset cancel function off.
Normally connect to GND to
use with the offset cancel
function on.
High (offset cancel function off)
when open.
GND
PVCC
25 27
25, 27,
29, 31,
SH_OUT12
33, 35,
to
41, 43,
SH_OUT1
45, 47,
49, 51
29 31
300
33 35
O
1.5 to 13.5V
41 43
300
45 47
Demultiplexed output of AC
inverse driven video signals.
Can be connected directly to
the LCD panel.
49 51
GND
VCC
80µ
100k
53
VCOM_OUT
O
500 145
53
5.0 to 8.0V
500
LCD panel common voltage
output.
Can be set in the range from
the SH_OUT center potential
Vsig.c to Vsig.c – 2V by
VCOM_OFST.
GND
VDD
VCC
80µ
2k
54
VCOM_OFST
I
0 to 5.0V
54
100
GND
–4–
LCD panel common voltage
adjustment.
VCOM_OUT can be set in the
range from the SH_OUT center
potential Vsig.c to Vsig.c – 2V
by inputting 0 to 5V.
CXA3562R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VCC
Precharge waveform output.
SID_OUTX outputs the inverse
of SID_OUT based on the
output center voltage. These
pins cannot directly drive the
LCD panel, so input to the LCD
panel with an external a buffer.
100k
0.2p
56
57
SID_OUTX
SID_OUT
O
145
1.5 to 13.5V
56
57
100k
0.2p
GND
VDD
VCC
Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
PRG_LV is reflected when the
PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.
29µ
58
59
PRG_LV
SID_LV
I
1.0 to 5.0V
50k
58
50k
59
GND
VDD
VCC
100k
60
PRG
I
10k
High: ≥2.0V
Low: ≤0.8V
60
50µ
Timing pulse input for switching
the Pins 56 and 57 output levels.
(See PRG_LV (Pin 58) and
SID_LV (Pin 59).)
GND
VDD
70µ
68
VREF_I
I
3.2V
10µ
68
1k
33.3k
Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.
280µ
GND
VDD
2k
69
VREF_O
O
69
3.2V
20k
20µ
Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.
12.4k
GND
VDD
50k
70
F/H_CNT
I
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
70
200k
GND
–5–
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT6
and SH_OUT7 to SH_OUT12
are output at different timing.
Low: SH_OUT1 to SH_OUT12
are output at the same timing.
CXA3562R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VDD
Power saving.
Power saving mode when set to
low level.
Low (power saving mode) when
open.
Normally connect to VDD.
70k
66
PS
I
66
5V
180k
30µ
GND
38
PGND
26, 50 PVCC
GND
Power GND.
15.5V
Power VCC.
55
VCC
15.5V
15V power supply.
67
VDD
5V
5V power supply.
11 to 15,
20, 36,
37, 39,
GND
40,
61 to 65,
86 to 90
GND.
GND
23, 28,
30, 32,
34, 42, NC
44, 46,
48, 52
VDD
2k
1µ
192
1, 75
TEST
O
DAC output monitor test.
Normally connect to VDD.
1
1.7 to 3.2V
75
20µ
GND
VDD
20k
250k
10
SHTEST
I
2.5V
20k
20k
20k
Test.
Leave open.
192
10
250k
10µ
10µ
GND
VDD
50k
71
DIRC
I
High: ≥2.0V
Low: ≤0.8V
192
71
GND
–6–
Scan direction setting.
High: output as a time series in
ascending order of output pin
symbol (in order from SH_OUT1
to SH_OUT12)
Low: output in descending order
CXA3562R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
VDD
50k
72
SL_DAT
I
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
72
200k
Digital input mode switch setting.
High: single input from the A port
Low: parallel input from both the
A and B ports
GND
VDD
73
SL_SCN
I
High: ≥2.0V
Low: ≤0.8V
Open: High
200k
50k
192
73
GND
VDD
50k
74
SL_INV
I
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
74
200k
GND
A and B port input switching
interlocked/non-interlocked
setting relative to scan direction
setting during parallel input.
High: A and B port switching
interlocked to DIRC
Low: fixed regardless of DIRC
SH_OUT odd-numbered and
even-numbered output polarity
inverted/non-inverted setting.
High: odd-numbered and evennumbered outputs inverted
Low: non-inverted
VDD
50k
76
to
85
D_A9
to
D_A0
I
High: ≥2.0V
Low: ≤0.8V
192
A port digital data input.
76 to 85
GND
VDD
50k
91
to
100
D_B9
to
D_B0
I
High: ≥2.0V
Low: ≤0.8V
192
91 to 100
GND
–7–
B port digital data input.
CXA3562R
Electrical Characteristics Measurement Circuit
VDD
1µ
47p
47p
VCC
SH_OUT1
NC
VCOM_OUT
VCOM_OFST
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PVCC
SH_OUT2
360p
NC
SH_OUT3
360p
NC
SH_OUT4
360p
NC
SH_OUT5
360p
NC
SH_OUT6
360p
GND
GND
PGND
GND
GND
SH_OUT7
360p
NC
SH_OUT8
360p
NC
SH_OUT9
360p
NC
SH_OUT10
360p
NC
SH_OUT11
360p
PVCC
A
25
SH_OUT12
1
DCFBOFF
D_B0
39
NC
D_B1
51
87
CAL_IL
D_B2
52
40
CAL_IH
D_B3
53
41
GND
D_B4
54
86
CAL_OH
D_B5
55
85
CAL_OL
D_B6
56
42
SIG_OFST
D_B7
57
84
SIG.C
D_B8
58
43
GND
D_B9
59
83
GND
GND
60
44
GND
GND
61
82
GND
GND
62
45
GND
GND
63
81
SHTEST
GND
64
46
POSCTR3
D_A0
65
47
POSCTR2
D_A1
66
80
POSCTR1
D_A2
67
79
POSCTR0
D_A3
68
48
SHST
D_A4
69
78
FRP
D_A5
70
49
MCLKX
D_A6
71
77
MCLK
D_A7
72
360p
50
TEST
D_A8
73
A
76
VDD
D_A9
74
SL_DAT
SL_INV
TEST
75
SL_SCN
VDD
A
VCC
360p
VCC
15.5V
–8–
VDD
5V
CXA3562R
Electrical Characteristics
No.
Item
Symbol
1
Digital input
resolution
n
2
Digital input
setup time
TS
3
Digital input
hold time
4
Measurement
points
Measurement conditions
Min. Typ. Max. Unit
—
10
—
bit
SHST, D_A[9:0] and D_B[9:0] minimum
setup time relative to MCLK input. (PELL)
2
—
—
ns
TH
SHST, D_A[9:0] and D_B[9:0] minimum
hold time relative to MCLK input. (PECL)
3
—
—
ns
MCLK input
frequency
range 1
fMCLK1
SL_DAT: 5V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.
30
—
80
MHz
5
MCLK input
frequency
range 2
fMCLK2
SL_DAT: 0V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.
60
—
100 MHz
6
VREF_O output
VVREF_O
voltage range
Measure the VREF_O (Pin 69)
voltage.
3.10 3.20
3.32
V
7
SH_OUT
amplitude 1
VSHOUT1p-p VOUT1
Measure the SH_OUT1 voltage
4.44 4.50
difference at D_A[9:0]: 000h and 3FFh.
4.83
V
8
SH_OUT
amplitude 2
VSHOUT2p-p VOUT2
Measure the SH_OUT2 voltage
4.44 4.50
difference at D_B[9:0]: 000h and 3FFh.
4.83
V
9
SH_OUT
minimum
amplitude
VOUTMINp-p VOUT1
Lower the VREF_I voltage and adjust
the amplitude; minimum amplitude at
which SH_OUT1 can be output at
D_B[9:0]: 000h and 3FFh.
4
—
—
160
300
—
V/µs
V
SROUT
VOUT1 to
VOUT12
Load capacitance = 360pF; measure
slew rate at 10 to 90% of output
waveform rise and fall when D_A[9:0]
is varied from 000h to 3FFh and from
3FFh to 000h.
VMIN
VOUT1 to
VOUT12
Minimum voltage at which sampleand-hold outputs VOUT1 to VOUT12 can
be output.
1.5
—
—
V
VMAX
VOUT1 to
VOUT12
Maximum voltage at which sampleand-hold outputs VOUT1 to VOUT12 can
be output.
—
—
13.6
V
Output deviation
13 between
DOUT1
channels 1
VOUT1 to
VOUT12
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 200h
and D_B[9:0]: 200h.
—
3
10 mVp-p
Output deviation
14 between
DOUT2
channels 2
VOUT1 to
VOUT12
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 000h
or 3FFh and D_B[9:0]: 000h or 3FFh.
—
10
40 mVp-p
VOUT1 to
VOUT12
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 200h
and D_B[9:0]: 200h. (when using two
CXA3562R)
—
10
—
10
SH_OUT
slew rate
SH_OUT
11 minimum
output voltage
SH_OUT
12 maximum
output voltage
15
Output deviation DIC1
between ICs 1
–9–
mVp-p
CXA3562R
No.
16
Item
Measurement
Symbol points
Measurement conditions
Min.
VOUT1 to
VOUT12
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 000h
or 3FFh and D_B[9:0]: 000h or 3FFh.
(when using two CXA3562R)
—
20
—
mVp-p
ASID1
VSID_LV
VSID
VSIDX
PRG: 0V; measure VSID_LV and VSID at
FRP: 0V, and VSID_LV and VSIDX at
FRP: 5V.
Calculate as ASID1 = VSID(X)/VSID_LV.
1.9
2.0
2.1
times
ASID2
VPRG_LV
VSID
VSIDX
PRG: 5V; measure VPRG_LV and VSID at
FRP: 0V, and VPRG_LV and VSIDX at
FRP: 5V.
Calculate as ASID2 = VSID(X)/VPRG_LV.
1.9
2.0
2.1
times
VSID
VSIDX
Load capacitance = 47pF, PRG: 0V;
input a repeating high/low pulse to FRP
(Pin 4), and apply DC input voltage so
that VSID and VSIDX are 2.5V/11.5V.
Measure slew rate at 10 to 90% of
output waveform rise and fall.
15
50
—
V/µs
VOUT1
VOUT1 center voltage when SIG.C
(Pin 16) is varied from 1 to 5V.
7
—
8
V
0
—
1
V
Output deviation
DIC2
between ICs 2
SID output
17
gain 1
SID output
18
gain 2
19
SID output
slew rate
20
Signal center
VSIG
adjustable range
SRSID
Typ. Max. Unit
21
SH_OUT offset
VSIGOFST
adjustable range
VOUT1
D_A[9:0]: 3FFh, FRP: 0V, D_B[9:0]:
3FFh; value obtained by subtracting
VOUT1 from VOUT1 center voltage when
SIG_OFST (Pin 17) is varied from 1 to
5V.
22
VCOM
VCOM
adjustable range
VCOM
VCOM_OUT voltage when VCOM_OFST Vc –
(Pin 54) is varied from 0 to 5V.
2.5
—
Vc
V
23
VDD current
consumption
IDD
IVDD
IDD = IVDD
59
85
112
mA
24
VCC current
consumption
ICC
IVCC1
IVCC2
ICC = IVCC1 + IVCC2
(no digital data input)
21
40
59
mA
Current
consumption in
25
IPS
power saving
mode
IVDD
IVCC1
IVCC2
GND (Pin 66),
ICC = IVDD + IVCC1 + IVCC2
4
8
15
mA
26
Differential
linearity error
27
Integral linearity
ILE
error
DLE
—
VVREF_I = 3.2V
–0.7
—
0.7
LSB
—
VVREF_I = 3.2V
–1.2
—
1.2
LSB
– 10 –
CXA3562R
Description of Operation
The flow of internal operations is described below.
The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately
1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is
amplified by a factor of three times, inverted at the signal center potential according to FRP, and output.
The output level relative to the digital input changes according to the following settings.
A: SIG_OFST voltage
B: VREF_I voltage
VCC
C: SIG.C voltage
B
A
Signal Center
A
1023
C
B
512
0
GND
Digital IN
SH_OUT
1. Digital input block
The CXA3562R can be set to single input from only the A port or parallel input from both the A and B ports,
and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to
support various systems.
In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter.
2. D/A converter block
The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input
from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a
maximum 1.5Vp-p with respect to input data of 000h to 3FFh.
3. Sample-and-hold (S/H) block
The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and evennumbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase
cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing
generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3
... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect
the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown
on the following pages. These pulses are not output and are used only inside the IC.
– 11 –
CXA3562R
Single input mode
DAC
10bit
D_A[9:0]
D_A1
D
D
DAC_O
D_A2
D
D
S/H
DAC
D_B2
S/H
D
MCLK
MCLK/2
D_A[9:0]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
MCLK
D_A1
0
1
2
D_A2
D_B2
DAC_O
0
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
DIRC: H
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
DIRC: L
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
– 12 –
CXA3562R
2-parallel input mode
DAC
10bit
D_A[9:0]
DAC_O
D_A2
D
D
D
S/H
DAC
10bit
D_B[9:0]
D_B2
D
S/H
D
MCLK
D_A[9:0]
–3
–1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
D_B[9:0]
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
MCLK
D_A2
–5
–3
–1
1
3
5
7
9
11
13
15
17
19
21
23
25
D_B2
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
–1
1
DAC_O
3
DIRC: H
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT : H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
DIRC: L
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
– 13 –
CXA3562R
4. Timing generator (TG) block
The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync
signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse
and output deviation cancel circuit. The various operating modes can be designated by the pin settings.
The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and
MCLKX input period as 1clk.
SHST
FRP
30clk or more
1µs or more
The CXA3562R can select various operating modes according to the timing generator block settings. These
settings are described below.
• SL_DAT (Pin 72)
Digital input selection. Single input from only the A port is selected when set to high level, and parallel input
from both the A and B ports is selected when set to low level. When inputting a 2-parallel processed digital
video signal in parallel input mode, input the earlier time series data to the A port and the later time series data
to the B port. Input a master clock having the same period as the input data rate to MCLK in both modes.
This pin is low level (2-parallel input mode) when left open.
• DIRC (Pin 71), SL_SCN (Pin 73)
Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending
order (SH_OUT1 to SH_OUT12) when set to low level. At this time if SL_SCN is set to high, the A and B port
data can be switched by switching DIRC between high and low. When SL_SCN is set to low, the A port data is
output from the odd-numbered SH_OUT and the B port data is output from the even-numbered SH_OUT
regardless of the DIRC setting.
Set SL_SCN to high when SL_DAT is high.
D_A[9:0]
A1
A2
A3
A4
A5
A6
D_B[9:0]
B1
B2
B3
B4
B5
B6
DIRC: L
DIRC: H
SL_SCN: L
SH_OUT1: A6, SH_OUT2: B6,
SH_OUT3: A5, SH_OUT4: B5,
SH_OUT5: A4, SH_OUT6: B4,
SH_OUT7: A3, SH_OUT8: B3,
SH_OUT9: A2, SH_OUT10: B2,
SH_OUT11: A1, SH_OUT12: B1
SH_OUT1: A1, SH_OUT2: B1,
SH_OUT3: A2, SH_OUT4: B2,
SH_OUT5: A3, SH_OUT6: B3,
SH_OUT7: A4, SH_OUT8: B4,
SH_OUT9: A5, SH_OUT10: B5,
SH_OUT11: A6, SH_OUT12: B6
SL_SCN: H
SH_OUT1: B6, SH_OUT2: A6,
SH_OUT3: B5, SH_OUT4: A5,
SH_OUT5: B4, SH_OUT6: A4,
SH_OUT7: B3, SH_OUT8: A3,
SH_OUT9: B2, SH_OUT10: A2,
SH_OUT11: B1, SH_OUT12: A1
SH_OUT1: A1, SH_OUT2: B1,
SH_OUT3: A2, SH_OUT4: B2,
SH_OUT5: A3, SH_OUT6: B3,
SH_OUT7: A4, SH_OUT8: B4,
SH_OUT9: A5, SH_OUT10: B5,
SH_OUT11: A6, SH_OUT12: B6
– 14 –
CXA3562R
• SL_INV (Pin 74)
Dot inversion and line inversion selection. When set to low level, all SH_OUT channels are output at the same
polarity as shown by the solid line in the figure below. When set to high level, the odd-numbered and evennumbered SH_OUT outputs are output at inverse polarities. At this time the odd-numbered outputs are
inverted when the FRP pulse is high, and non-inverted when the FRP pulse is low. Conversely, the evennumbered outputs are inverted when the FRP pulse is low, and non-inverted when the FRP pulse is high.
SH_OUT
GND
FRP
• F/H_CNT (Pin 70)
SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same
timing. When set to high level, SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at phases
offset by 1/2 clock period from each other.
SH_OUT7 to 12
SH_OUT7 to 12
SH_OUT1 to 6
SH_OUT1 to 6
GND
GND
F/H_CNT: H
F/H_CNT: L
• Output phase setting
The phase of each SH_OUT output can be adjusted in MCLK period units when SL_DAT is high or in 1/2 MCLK
period units when SL_DAT is low by POSCTR[3:0] (Pins 6 to 9). The phase can be set in 16 ways by 4-bit digital
input. The output phase shifts backward by the above unit each time this setting is increased by one bit.
– 15 –
CXA3562R
5. Calibration level generator block
The CXA3562R generates the offset cancel circuit reference with a calibration level generator in order to
minimize the deviation between channels at the center level.
The 200h output level is generated at both the AC output high and low sides, and these levels are DC output
from CAL_OH and CAL_OL, respectively. At the same time, 200h data is forcibly inserted into the video signal
while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all
SH_OUT channels conform to CAL_IH and CAL_IL during this period.
Video signal replacement period
SHST
FRP
200ns
CAL_PLS
(internal pulse)
Offset cancel operation
000h
200h
SH_OUT
Signal center
Delayed by sample-and-hold
200h
000h
6. SID signal generator block
This circuit generates the precharge signal waveform used by the LCD panel.
The voltage input from PRG_LV (Pin 58) and SID_LV (Pin 59) is switched by the PRG pulse (Pin 60). The
PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This
signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage
is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 57) is inverted when FRP is high,
and non-inverted when FRP is low. Conversely, SID_OUTX (Pin 56) is inverted when FRP is low, and noninverted when FRP is high.
SID_OUT and SID_OUTX cannot directly drive the precharge signal input of the LCD panel, so they should be
connected via a buffer having sufficient current supply capability.
7. VCOM potential generator block
This block sets the DC common potential for the LCD panel.
VCOM_OFST (Pin 54) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C.
– 16 –
CXA3562R
Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C)
Input data vs. SH_OUT voltage
VREF_I voltage vs. SH_OUT voltage white-black amplitude
14
4.7
<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V
4.6
12
FRP = High
4.5
SH_OUT voltage [V]
SH_OUT white-black amplitude voltage [V]
4.8
4.4
4.3
4.2
4.1
10
8
6
FRP = Low
4
2
3.9
0
000h
3.8
2.7
2.8
2.9
3.0
3.1
3.2
3.3
200h
300h
3FFh
SIG_OFST voltage vs. SH_OUT voltage
SIG.C voltage vs. SH_OUT center voltage
9.0
12
11
8.5
<Measurement conditions>
SIG_OFST = 3.6V
8.0
10
SH_OUT voltage [V]
SH_OUT center voltage [V]
100h
Input data (10 bits)
VREF_I voltage [V]
7.5
7.0
6.5
6.0
FRP = High
9
8
7
6
5
5.5
4
<Measurement conditions>
SIG.C = 3.75V
FRP = Low
DATA = 200h
3
5.0
2.5
3.0
3.5
4.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
4.5
SIG_OFST voltage [V]
SIG.C voltage [V]
VCOM_OFST voltage vs. VCOM_OUT voltage
6.00
<Measurement conditions>
SIG.C = 3.75V
5.95
VCOM_OUT voltage [V]
<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V
4.0
5.90
5.85
5.80
5.75
5.70
2.8
2.9
3.0
3.1
3.2
VCOM_OFST voltage [V]
– 17 –
CXA3562R
SID_LV voltage vs. SID_OUT voltage
PRG_LV voltage vs. SID_OUT voltage
16
16
<Measurement conditions>
SIG.C = 3.75V
14
12
12
SID_OUT voltage [V]
SID_OUT voltage [V]
<Measurement conditions>
SIG.C = 3.75V
14
FRP = High
10
8
6
FRP = Low
FRP = High
10
8
6
FRP = Low
4
4
2
2
0
0
0
1
2
3
0
4
SID_LV voltage [V]
1
2
PRG_LV voltage [V]
– 18 –
3
4
CXA3562R
Application Circuit 1 (to XGA Panel)
VDD
20kΩ
VDD
0.1µF
Buffer
20kΩ
1 Psig
DSD
CXD3511Q
VDD
10Ω
PRG 161
VDD
10Ω
RGT 136
20kΩ
0.1µF
VDD
47µF
VDD
1Ω
1µF
31 COM
0.1µF
VDD
1Ω
SH_OUT1
NC
3 Vsig1
VCOM_OUT
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
10kΩ
VCOM_OFST
VDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R1OUT9 122
R1OUT8 121
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
10Ω
D_A9
10Ω
D_A8
10Ω
D_A7
10Ω
D_A6
10Ω
D_A5
10Ω
D_A4
10Ω
D_A3
10Ω
D_A2
10Ω
D_A1
10Ω
D_A0
GND
GND
GND
GND
GND
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
CXA3562R
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
PVCC
1Ω
SH_OUT3
5 Vsig3
NC
1Ω
SH_OUT4
6 Vsig4
NC
1Ω
SH_OUT5
7 Vsig5
NC
1Ω
SH_OUT6
8
Vsig6
GND
GND
LCD Panel
LCX023
PGND
GND
GND
1Ω
SH_OUT7
9 Vsig7
NC
1Ω
SH_OUT8
10 Vsig8
NC
1Ω
SH_OUT9
11 Vsig9
NC
1Ω
SH_OUT10
12 Vsig10
NC
1Ω
SH_OUT11
PVCC
13 Vsig11
VCC
47µF
10kΩ
SH_OUT12
DCFBOFF
NC
CAL_IL
CAL_IH
GND
CAL_OL
CAL_OH
SIG_OFST
GND
SIG.C
GND
GND
GND
GND
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SHTEST
8
POSCTR3
7
POSCTR2
6
POSCTR1
5
POSCTR0
FRP
4
SHST
3
MCLKX
TEST
MCLK
2
4 Vsig2
NC
0.1µF
1
1Ω
SH_OUT2
1Ω
14 Vsig12
VDD
VDD
OPEN
1µF
1µF
20kΩ
10Ω
FRP 157
0.1µF
10Ω
SHST 159
VDD
CXA3266Q
VCC
20kΩ
82Ω
82Ω
130Ω
130Ω
15.5V
VDD
5V
0.1µF
CLKH 32
CLKL 31
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA3562R
Application Circuit 2 (to SXGA Panel)
VDD
20kΩ
VDD
0.1µF
Buffer
20kΩ
1 Psig
DSD
CXD3511Q
VDD
10Ω
PRG 161
2 COMR
VDD
10Ω
RGT 136
20kΩ
0.1µF
21 COML
VDD
47µF
VDD
1Ω
1µF
32 COM
0.1µF
VDD
SH_OUT1
NC
3 Vsig1
VCOM_OUT
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
10kΩ
VCOM_OFST
1Ω
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R1OUT9 122
R1OUT8 121
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
10Ω
D_A9
10Ω
D_A8
10Ω
D_A7
10Ω
D_A6
10Ω
D_A5
10Ω
D_A4
10Ω
D_A3
10Ω
D_A2
10Ω
D_A1
10Ω
D_A0
GND
GND
GND
GND
GND
R2OUT9 110
R2OUT8 109
R2OUT7 108
R2OUT6 107
R2OUT5 106
R2OUT4 105
R2OUT3 104
R2OUT2 103
R2OUT1 99
R2OUT0 98
10Ω
D_B9
10Ω
D_B8
10Ω
D_B7
10Ω
D_B6
10Ω
D_B5
10Ω
D_B4
10Ω
D_B3
10Ω
D_B2
10Ω
D_B1
10Ω
D_B0
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
CXA3562R
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
PVCC
1Ω
SH_OUT3
5 Vsig3
NC
1Ω
SH_OUT4
6 Vsig4
NC
1Ω
SH_OUT5
7 Vsig5
NC
1Ω
SH_OUT6
8
Vsig6
GND
GND
LCD Panel
LCX028
PGND
GND
GND
1Ω
SH_OUT7
9 Vsig7
NC
1Ω
SH_OUT8
10 Vsig8
NC
1Ω
SH_OUT9
11 Vsig9
NC
1Ω
SH_OUT10
12 Vsig10
NC
1Ω
SH_OUT11
13 Vsig11
PVCC
VCC
47µF
10kΩ
SH_OUT12
DCFBOFF
NC
CAL_IL
CAL_IH
GND
CAL_OL
CAL_OH
SIG_OFST
GND
SIG.C
GND
GND
GND
GND
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SHTEST
8
POSCTR3
7
POSCTR2
6
POSCTR1
5
POSCTR0
FRP
4
SHST
3
MCLKX
TEST
MCLK
2
4 Vsig2
NC
0.1µF
1
1Ω
SH_OUT2
1Ω
14 Vsig12
VDD
VDD
OPEN
1µF
1µF
20kΩ
10Ω
FRP 157
0.1µF
10Ω
SHST 159
VDD
CXA3266Q
VCC
20kΩ
82Ω
82Ω
130Ω
130Ω
15.5V
VDD
5V
0.1µF
CLK/2H 30
CLK/2L 29
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 20 –
CXA3562R
Application Circuit 3 (to WXGA Panel)
SID_OUTX
SID_OUT
Another
CXA3562R
56
57
Buffer
2 Psig1
3 Psig2
4 Psig3
5 Psig4
DSD
CXD3511Q
VDD
VDD
6 COMR
VDD
10Ω
RGT 136
20kΩ
20kΩ
0.1µF
25 COML
VDD
47µF
VDD
1Ω
1µF
34 COM
0.1µF
VDD
1Ω
SH_OUT1
7 Vsig-a1
NC
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
10kΩ
VCOM_OUT
VDD
VCOM_OFST
VDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R1OUT9 122
R1OUT8 121
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
10Ω
D_A9
10Ω
D_A8
10Ω
D_A7
10Ω
D_A6
10Ω
D_A5
10Ω
D_A4
10Ω
D_A3
10Ω
D_A2
10Ω
D_A1
10Ω
D_A0
GND
GND
GND
GND
GND
R2OUT9 110
R2OUT8 109
R2OUT7 108
R2OUT6 107
R2OUT5 106
R2OUT4 105
R2OUT3 104
R2OUT2 103
R2OUT1 99
R2OUT0 98
10Ω
D_B9
10Ω
D_B8
10Ω
D_B7
10Ω
D_B6
10Ω
D_B5
10Ω
D_B4
10Ω
D_B3
10Ω
D_B2
10Ω
D_B1
10Ω
D_B0
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
CXA3562R
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
PVCC
Vsig-a2
9
Vsig-a3
1Ω
SH_OUT3
NC
1Ω
SH_OUT4
10 Vsig-a4
NC
1Ω
SH_OUT5
11 Vsig-a5
NC
1Ω
SH_OUT6
12 Vsig-a6
GND
GND
LCD Panel
LCX037
PGND
GND
GND
1Ω
SH_OUT7
13 Vsig-b1
NC
1Ω
SH_OUT8
14 Vsig-b2
NC
1Ω
SH_OUT9
15 Vsig-b3
NC
1Ω
SH_OUT10
16 Vsig-b4
NC
1Ω
SH_OUT11
17 Vsig-b5
PVCC
VCC
47µF
10kΩ
SH_OUT12
DCFBOFF
NC
CAL_IL
CAL_IH
GND
CAL_OL
CAL_OH
SIG_OFST
GND
SIG.C
GND
GND
GND
GND
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SHTEST
8
POSCTR3
7
POSCTR2
6
POSCTR1
5
POSCTR0
FRP
4
SHST
3
MCLKX
TEST
MCLK
2
8
NC
0.1µF
1
1Ω
SH_OUT2
1Ω
18 Vsig-b6
VDD
VDD
OPEN
1µF
1µF
20kΩ
10Ω
FRP 157
0.1µF
10Ω
SHST 159
VDD
CXA3266Q
VCC
20kΩ
82Ω
82Ω
130Ω
130Ω
15.5V
VDD
5V
0.1µF
CLK/2H 30
CLK/2L 29
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 21 –
CXA3562R
Application Circuit 4 (to UXGA Panel)
VDD
0.1µF
20kΩ
VDD
0.1µF
DSD
CXD3511Q
20kΩ
10Ω
PRG 161
0.47µF
VDD
Buffer
VDD
10Ω
RGT 136
1 Psig1
2 Psig2
47µF
VDD
VDD
0.1µF
VDD
1Ω
SH_OUT1
NC
11 Vsig1
VCOM_OUT
VCC
SID_OUTX
SID_OUT
PRG
PRG_LV
GND
SID_LV
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
10kΩ
VCOM_OFST
VDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R1OUT9 122
R1OUT8 121
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
10Ω
D_A9
10Ω
D_A8
10Ω
D_A7
10Ω
D_A6
10Ω
D_A5
10Ω
D_A4
10Ω
D_A3
10Ω
D_A2
10Ω
D_A1
10Ω
D_A0
GND
GND
GND
GND
GND
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
CXA3562R
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
PVCC
1Ω
SH_OUT3
15 Vsig5
NC
1Ω
SH_OUT4
17 Vsig7
NC
1Ω
SH_OUT5
19 Vsig9
NC
1Ω
SH_OUT6
21 Vsig11
GND
GND
LCD Panel
LCX036
PGND
GND
GND
1Ω
SH_OUT7
23 Vsig13
NC
1Ω
SH_OUT8
25 Vsig15
NC
1Ω
SH_OUT9
27 Vsig17
NC
1Ω
SH_OUT10
29 Vsig19
NC
1Ω
SH_OUT11
PVCC
31 Vsig21
VCC
47µF
10kΩ
SH_OUT12
DCFBOFF
NC
CAL_IL
GND
CAL_IH
CAL_OH
CAL_OL
SIG_OFST
SIG.C
GND
GND
GND
GND
GND
SHTEST
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
POSCTR3
8
POSCTR2
7
POSCTR1
6
POSCTR0
5
SHST
4
FRP
TEST
MCLK
3
MCLKX
2
13 Vsig3
NC
0.1µF
1
1Ω
SH_OUT2
1Ω
33 Vsig23
OPEN
VDD
0.47µF
0.47µF
VDD
10Ω
FRP 157
10Ω
SHST 159
20kΩ
Buffer
0.1µF
4 Psig4
82Ω
82Ω
130Ω
130Ω
3 Psig3
VDD
VDD
20kΩ
0.1µF
VDD
0.1µF
20kΩ
VDD
0.47µF
VDD
47µF
56 COM1
1Ω
57 COM2
0.1µF
VDD
SH_OUT1
NC
VCC
SID_OUTX
SID_OUT
PRG_LV
SID_LV
PRG
GND
GND
GND
GND
GND
PS
VDD
VREF_I
VREF_O
F/H_CNT
DIRC
SL_DAT
SL_SCN
SL_INV
TEST
VCOM_OUT
12 VSig2
10kΩ
VCOM_OFST
VDD
1Ω
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
R2OUT9 110
R2OUT8 109
R2OUT7 108
R2OUT6 107
R2OUT5 106
R2OUT4 105
R2OUT3 104
R2OUT2 103
R2OUT1 99
R2OUT0 98
10Ω
D_A9
10Ω
D_A8
10Ω
D_A7
10Ω
D_A6
10Ω
D_A5
10Ω
D_A4
10Ω
D_A3
10Ω
D_A2
10Ω
D_A1
10Ω
D_A0
GND
GND
GND
GND
GND
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
39
CXA3562R
88
38
89
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
26
100
PVCC
1Ω
SH_OUT3
16 Sig6
NC
1Ω
SH_OUT4
18 Sig8
NC
1Ω
SH_OUT5
20 Sig10
NC
1Ω
SH_OUT6
22 Sig12
GND
GND
PGND
GND
GND
1Ω
SH_OUT7
24 Sig14
NC
1Ω
SH_OUT8
26 Sig16
NC
1Ω
SH_OUT9
28 Sig18
NC
1Ω
SH_OUT10
30 Sig20
NC
1Ω
SH_OUT11
PVCC
32 Sig22
VCC
47µF
10kΩ
SH_OUT12
DCFBOFF
NC
CAL_IL
GND
CAL_IH
CAL_OH
CAL_OL
SIG_OFST
SIG.C
GND
GND
GND
GND
GND
SHTEST
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
POSCTR3
8
POSCTR2
7
POSCTR1
6
POSCTR0
5
SHST
4
FRP
TEST
MCLK
10Ω
3
MCLKX
XFRP 158
2
14 Sig4
NC
0.1µF
1
1Ω
SH_OUT2
1Ω
34 Sig24
CXA3266Q
VDD
0.47µF
OPEN
0.47µF
VCC
VDD
VDD
CLK/2H 30
CLK/2L 29
15.5V
5V
20kΩ
0.1µF
0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXA3562R
Notes on Operation
The CXA3562R has high power consumption, so be sure to take the following radiation measures.
• Use four-layer substrate.
• GND lines connected between Pins 11 to 15, Pins 36 to 40, Pins 61 to 65 and Pins 86 to 90 should be as
thick as possible.
– 23 –
CXA3562R
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
76
50
(15.0)
B
26
100
1
0.5 ± 0.2
A
(0.22)
25
0.5
b
0.13 M
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0.5 ± 0.2
0˚ to 10˚
0.125 ± 0.04
b = 0.18 ± 0.03
DETAIL B : PALLADIUM
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
LQFP-100P-L01
P-LQFP100-14x14-0.5
JEDEC CODE
– 24 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
PALLADIUM PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.7g
Sony Corporation