Cypress CY7C1325G 4-mbit (256 k x 18) flow through sync sram synchronous self timed write Datasheet

CY7C1325G
4-Mbit (256 K × 18) Flow through Sync
SRAM
4-Mbit (256 K × 18) Flow through Sync SRAM
Features
Functional Description
■
256 K × 18 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
■
6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package, Pb-free and non
Pb-free 119-ball BGA Package
■
“ZZ” sleep mode option
The CY7C1325G[1] is a 256 K × 18 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1325G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1325G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
.
Logic Block Diagram
A 0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
BW A
DQ B ,DQP B
WRITE DRIVER
DQ B ,DQP B
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
DQ A ,DQP A
WRITE REGISTER
BWE
GW
CE 1
CE 2
CE 3
INPUT
REGISTERS
ENABLE
REGISTER
OE
ZZ
SLEEP
CONTROL
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05518 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2011
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CY7C1325G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................... 7
Linear Burst Address Table (MODE = GND) .................. 7
ZZ Mode Electrical Characteristics ................................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Document Number: 38-05518 Rev. *H
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Page 2 of 21
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CY7C1325G
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum access time
6.5
8.0
ns
Maximum operating current
225
205
mA
Maximum standby current
40
40
mA
Pin Configurations
A
45
46
47
48
49
50
A
A
A
A
A
44
NC/9M
A
A
43
41
42
40
VSS
VDD
NC/18M
37
A0
39
36
A1
38
35
A
NC/72M
NC/36M
34
A
Document Number: 38-05518 Rev. *H
81
82
83
84
BWE
OE
ADSC
ADSP
ADV
A
85
86
GW
89
87
CLK
91
88
VDD
VSS
93
90
BWA
CE3
94
92
NC
BWB
95
CE2
NC
96
98
97
A
CE1
99
A
31
VSS
VDDQ
NC
NC
NC
33
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1325G
A
BYTE B
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
32
VDDQ
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
NC
NC
NC
100
Figure 1. 100-pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
BYTE A
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 3 of 21
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CY7C1325G
Pin Configurations
(continued)
Figure 2. 119-ball BGA Pinout
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC/288M
NC/144M
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC/576M
NC/1G
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
F
NC
VDDQ
DQB
NC
VSS
VSS
CE1
OE
VSS
VSS
NC
DQA
DQA
VDDQ
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
ADV
GW
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
K
NC
DQB
VSS
CLK
VSS
NC
DQA
NC
BWA
DQA
NC
BWE
A1
VSS
VSS
NC
DQA
VDDQ
NC
L
DQB
NC
VSS
M
N
VDDQ
DQB
DQB
NC
VSS
VSS
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
NC
NC/72M
A
MODE
VDD
NC
NC
A
A
NC/36M
A
A
A
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
ZZ
Pin Definitions
Name
I/O
Description
A0, A1, A
Inputsynchronous
Address inputs used to select one of the 256 K address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.
A[1:0] feed the 2 bit counter.
BWA,BWB
Inputsynchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Inputsynchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (all bytes are written, regardless of the values on BW[A:B] and BWE).
BWE
Inputsynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
Inputsynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Inputsynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address
is loaded.
CE3
Inputsynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address
is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document Number: 38-05518 Rev. *H
Page 4 of 21
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CY7C1325G
Pin Definitions (continued)
Name
I/O
Description
ADV
Inputsynchronous
Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Inputsynchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Inputsynchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical
asynchronous “sleep” condition with data integrity preserved.During normal operation, this pin has to be low or
left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPB
I/Osynchronous
VDD
Power supply Power supply inputs to the core of the device.
VSS
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed in a tristate condition.
Ground
Ground for the core of the device.
VDDQ
I/O power
supply
Power supply for the I/O circuitry.
MODE
Inputstatic
NC
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode pin has an internal pull-up.
No connects. Not Internally connected to the die.
–
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
Document Number: 38-05518 Rev. *H
Page 5 of 21
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CY7C1325G
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1325G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:B]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs, a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW[A:B]) are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
Document Number: 38-05518 Rev. *H
appropriate data is latched and written into the device. Byte
writes are allowed. During byte writes, BWA controls DQA and
BWB controls DQB. All I/Os are tristated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[A:D] is written into the
specified address location. Byte writes are allowed. During byte
writes, BWA controls DQA, BWB controls DQB. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are
tristated after a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1325G provides an on-chip two bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Page 6 of 21
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CY7C1325G
Interleaved Burst Address Table
(MODE = Floating or VDD)
.
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05518 Rev. *H
Page 7 of 21
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CY7C1325G
Truth Table
The Truth Table for part CY7C1325G is as follows. [2, 3, 4, 5, 6]
Cycle Description
Address
Used
CE1 CE2 CE3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected cycle,
power-down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-state
Deselected cycle,
power-down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-state
Deselected cycle,
power-down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-state
Deselected cycle,
power-down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-state
Deselected cycle,
power-down
None
X
X
X
L
H
L
X
X
X
L-H
Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-state
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-state
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read cycle, continue burst
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-state
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-state
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-state
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-state
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
2. X = “Don’t Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't
care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05518 Rev. *H
Page 8 of 21
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CY7C1325G
Truth Table for Read/Write
The Truth Table for Read/Write for part CY7C1325G is as follows. [7]
Read
Function
GW
H
BWE
H
BWB
X
BWA
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Note
7. X = “Don’t Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05518 Rev. *H
Page 9 of 21
[+] Feedback
CY7C1325G
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Range
Ambient
Temperature]
Commercial 0 °C to +70 °C
Industrial
–40 °C to +85 °C
VDD
VDDQ
3.3 V5% /
+ 10%
2.5 V – 5%
to VDD
Supply voltage on VDD relative to GND ........–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ............................................–0.5 V to VDDQ + 0.5 V
DC input voltage .................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Neutron Soft Error Immunity
Test
Conditions
Typ
Logical
single bit
upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical multi
bit upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single event
latch up
85 °C
0
0.1
FIT/
Dev
Parameter
Description
LSBU
Max* Unit
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range [8, 9]
Parameter
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
3.135
3.6
V
VDDQ
I/O supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
VOL
VIH
VIL
IX
Output LOW voltage
Input HIGH voltage
Input LOW
voltage[8]
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
A
Input leakage current
except ZZ and MODE
GND  VI  VDDQ
5
5
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input current of ZZ
IOZ
Output leakage current
GND  VI  VDDQ, output disabled
–5
5
A
IDD
VDD operating supply
current
VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5 ns cycle, 133 MHz
–
225
mA
10 ns cycle, 100 MHz
–
205
mA
Notes
8. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
9. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05518 Rev. *H
Page 10 of 21
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CY7C1325G
Electrical Characteristics (continued)
Over the Operating Range [8, 9]
Parameter
ISB1
Description
Test Conditions
Min
Max
Unit
7.5 ns cycle, 133 MHz
–
90
mA
10 ns cycle, 100 MHz
–
80
mA
All speeds
Max VDD, device deselected,
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, inputs static
–
40
mA
Automatic CE
power-down
current—CMOS inputs
Max VDD, device deselected,
VIN  VDDQ – 0.3 V or
VIN  0.3 V,
f = fMAX, inputs switching
7.5 ns cycle, 133 MHz
–
75
mA
10 ns cycle, 100 MHz
–
65
mA
Automatic CE
power-down
current—TTL inputs
All speeds
Max VDD, device deselected,
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, inputs static
–
45
mA
Automatic CE
power-down
current—TTL inputs
Max VDD, device deselected,
VIN  VIH or VIN  VIL, f = fMAX,
inputs switching
ISB2
Automatic CE
power-down
current—CMOS inputs
ISB3
ISB4
Capacitance[10]
Parameter
119-ball BGA
Max
Test Conditions
100-pin TQFP
Max
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
5
5
pF
5
5
pF
5
7
pF
Test Conditions
100 TQFP
Package
119 BGA
Package
Unit
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
30.32
34.1
°C/W
6.85
14.0
°C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
Unit
Thermal Resistance[10]
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317 
Z0 = 50 
VT = 1.5 V
(a)
2.5 V I/O Test Load
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V
OUTPUT
GND
R = 351 
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1 ns
 1 ns
(b)
(c)
R = 1667 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
Z0 = 50 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
GND
R = 1538 
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
10. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05518 Rev. *H
Page 11 of 21
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CY7C1325G
Switching Characteristics
Over the Operating Range[11, 12]
Parameter
tPOWER
Description
VDD(Typical) to the first access[13]
–133
–100
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
2.5
–
4.0
–
ns
tCL
Clock LOW
2.5
–
4.0
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
8.0
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
Z[14, 15, 16]
tCLZ
Clock to low
0
–
0
–
ns
tCHZ
Clock to high Z[14, 15, 16]
–
3.5
–
3.5
ns
tOEV
OE LOW to output valid
–
3.5
–
3.5
ns
0
–
0
–
ns
–
3.5
–
3.5
ns
tOELZ
tOEHZ
OE LOW to output low
Z[14, 15, 16]
OE HIGH to output high
Z[14, 15, 16]
Setup Times
tAS
Address setup before CLK rise
1.5
–
2.0
–
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–
2.0
–
ns
tADVS
ADV setup before CLK rise
1.5
–
2.0
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
2.0
–
ns
tDS
Data input setup before CLK rise
1.5
–
2.0
–
ns
tCES
Chip enable setup
1.5
–
2.0
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
11. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
12. Test conditions shown in (a) of Figure 3 on page 11 unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
14. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 11. Transition is measured ± 200 mV from steady-state voltage.
15. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document Number: 38-05518 Rev. *H
Page 12 of 21
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CY7C1325G
Timing Diagrams
Figure 4. Read Cycle Timing[17]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
[A:B]
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05518 Rev. *H
Page 13 of 21
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CY7C1325G
Timing Diagrams (continued)
Figure 5. Write Cycle Timing[18, 19]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
[A:B]
BW
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document Number: 38-05518 Rev. *H
Page 14 of 21
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CY7C1325G
Timing Diagrams (continued)
Figure 6. Read/Write Timing[20, 21, 22]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
[A:B]
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
t CDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. The data bus (Q) remains in High Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Document Number: 38-05518 Rev. *H
Page 15 of 21
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CY7C1325G
Timing Diagrams (continued)
Figure 7. ZZ Mode Timing[23, 24]
CLK
t ZZ
ZZ
I
t
ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
24. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 38-05518 Rev. *H
Page 16 of 21
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CY7C1325G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
133
Ordering Code
CY7C1325G-133AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY 7C
1325
G - 133 AX C
Temperature Range:
C = Commercial
Package Type:
AX = 100-pin TQFP (Pb-free)
Speed Grade: 133 MHz
Process Technology  90nm
1325 = FT, 256 Kb × 18 (4 Mb)
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document Number: 38-05518 Rev. *H
Page 17 of 21
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CY7C1325G
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050
51-85050 *D
Figure 9. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115
51-85115 *C
Document Number: 38-05518 Rev. *H
Page 18 of 21
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CY7C1325G
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BGA
ball grid array
CMOS
complementary metal oxide semiconductor
ns
nano seconds
CE
chip enable
V
Volts
CEN
clock enable
µA
micro Amperes
I/O
input/output
mA
milli Amperes
OE
output enable
mm
milli meter
SRAM
static random access memory
ms
milli seconds
TQFP
thin quad flat pack
MHz
Mega Hertz
WE
write enable
pF
pico Farad
W
Watts
°C
degree Celcius
Document Number: 38-05518 Rev. *H
Symbol
Unit of Measure
Page 19 of 21
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CY7C1325G
Document History Page
Document Title: CY7C1325G, 4-Mbit (256 K × 18) Flow through Sync SRAM
Document Number: 38-05518
Revision
ECN
Orig. of
Change
Submission
Date
**
224366
RKF
See ECN
New datasheet
*A
283775
VBL
See ECN
Deleted 66 MHz
Changed TQFP package to Pb-Free TQFP in Ordering Information section
Added BG Pb-Free package
*B
333626
SYT
See ECN
Removed 117 MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for JA and JC to their respective values on the Thermal
Resistance table
Changed the package name for 100 TQFP from A100RA to A101
Removed comment on the availability of BG Pb-Free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
418633
RXU
See ECN
Converted From Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition in Footnote from VDDQ < VDD to VDDQ < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
480124
VKN
See ECN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
*E
2756998
VKN
08/28/09
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
*F
3036073
NJY
*G
3052903
NJY
*H
3208774
NJY
Description of Change
09/22/2010 Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
10/08/10
Removed the following pruned part from the ordering information table.
CY7C1325G-100AXI
03/29/2011 Updated Ordering Information.
Updated Package Diagrams.
Document Number: 38-05518 Rev. *H
Page 20 of 21
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CY7C1325G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05518 Rev. *H
Revised March 29, 2011
Page 21 of 21
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