AD AD1959 Pll/multibit dac Datasheet

a
PLL/Multibit - DAC
AD1959
FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with Data Directed
Scrambling
Single-Ended Output for Easy Application
–94 dB THD + N
108 dB SNR and Dynamic Range
75 dB Stopband Attenuation
Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis and
Output Phase
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Input/Oscillator
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)
SCLK2: 512 f S (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)/22.5792 MHz
Better than 100 ps RMS Clock Jitter
Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1959 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigmadelta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1959 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1959 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1959 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1959 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
XIN
XOUT MCLK
LOOP
FILTERS
CLOCK
OUTPUTS
2
AD1959
16-/20-/24BIT DIGITAL
DATA INPUT
3
3
OSC
PLL
CIRCUIT
ATTEN/MUTE
8 FS
INTERPOLATOR
CONTROL DATA
INPUT
3
SERIAL CONTROL
INTERFACE
MULTIBIT
SIGMA-DELTA
MODULATOR
VOLTAGE
REFERENCE
OUTPUT
BUFFER
DAC
SERIAL
DATA
INTERFACE
ANALOG
OUTPUTS
ATTEN/MUTE
8 FS
INTERPOLATOR
2
RESET
L
MUTE
ZERO FLAG
PLL SUPPLY
MULTIBIT
SIGMA-DELTA
MODULATOR
2
DIGITAL SUPPLY
OUTPUT
BUFFER
DAC
R
3
ANALOG SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD1959–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature
25°C
Input Clock
12.288 MHz
Input Signal
996.11 Hz
–0.5 dB Full Scale
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
20 Bits
Load Capacitance
100 pF
Load Impedance
47 kΩ
Input Voltage HI
3.5 V
Input Voltage LO
0.8 V
ANALOG PERFORMANCE
Min
Resolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
With A-Weighted Filter (Stereo)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Master Clock Input Frequency
Generated System Clocks
SCLK0
SCLK1
SCLK2
Jitter (SCLK0 and SCLK1)
Analog Outputs
Single-Ended Output Range (± Full Scale)
Output Capacitance at Each Output Pin
VREF (FILTR)
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
Out-of-Band Energy (0.5 × fS to 100 kHz)
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
De-Emphasis Gain Error
101
Typ
Max
24
Bits
105
108
dB
dB
105
108
–94
dB
dB
dB
–91
27
MHz
33.8688
12.288
22.5792
85
MHz
MHz
MHz
ps rms
125
3.17
2.34
–5
–0.15
–25
Unit
2.39
± 2.0
± 0.015
150
–5
–120
± 0.1
2
2.44
+5
+0.15
250
+15
–90
± 0.1
V p-p
pF
V
%
dB
ppm/°C
mV
dB
dB
Degrees
dB
NOTES
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (–40°C to +105°C )
Min
Input Voltage HI (VIH) Except XIN
Input Voltage HI (VIH) XIN
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA Except XOUT
Low Level Output Voltage (VOL) IOL = 1 mA XOUT
Input Capacitance
Typ
Max
2.2
2.7
0.8
10
10
2.0
0.4
1.2
20
Unit
V
V
V
µA
µA
V
V
V
pF
Specifications subject to change without notice.
–2–
REV. 0
AD1959
TEMPERATURE RANGE
Min
Specifications Guaranteed
Functionality Guaranteed
Storage
Typ
Max
Unit
+105*
+150
°C
°C
°C
25
–40
–55
NOTES
*105°C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85 °C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
POWER
Supplies
Voltage, Analog Digital PLL
Analog Current
Digital Current
PLL Current
Dissipation
Operation – All Supplies
Operation – Analog Supply
Operation – Digital Supply
Operation – PLL Supply
Min
Typ
Max
Unit
4.50
5
36
28
27
5.50
42
34
32
V
mA
mA
mA
455
180
140
135
540
mW
mW
mW
mW
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz)
Pass Band (kHz)
Stop Band (kHz)
Stopband Attenuation (dB)
Pass-Band Ripple (dB)
44.1
48
96
192
DC–20
DC–21.8
DC–39.95
DC–87.2
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
75
75
75
60
± 0.0002
± 0.0002
± 0.0005
0/–0.04 (DC–21.8 kHz)
0/–0.5 (DC–65.4 kHz)
0/–1.5 (DC–87.2 kHz)
Specifications subject to change without notice.
GROUP DELAY
Chip Mode
Group Delay Calculation
fS
Group Delay
Unit
INT8× Mode
INT4× Mode
INT2× Mode
24.625/fS
15.75/fS
14/fS
48 kHz
96 kHz
192 kHz
513
164
72.91
µs
µs
µs
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = 5.0 V ± 10%)
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tRSTL
MCLK Period (FMCLK = 256 × FLRCLK)
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
RST LO Pulsewidth
Specifications subject to change without notice.
REV. 0
–3–
Min
Unit
54
15
10
7
12
60
20
20
15
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD1959
ABSOLUTE MAXIMUM RATINGS*
PACKAGE CHARACTERISTICS
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs . . . . . . . . . . DGND – 0.3 V to DVDD + 0.3 V
Analog Inputs . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to + 0.3 V
Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
θJA (Thermal Resistance) Junction-to-Ambient
109.0°C/W Typ (2-Layer Board)
θJA (Thermal Resistance) Junction-to-Ambient
78.58°C/W Typ (4-Layer Board—2 Signal, 2 Planes)
θJA (Thermal Resistance) Junction-to-Case
39.0°C/W Typ
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1959 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
AD1959YRS
AD1959YRSRL
EVAL-AD1959EB
–40°C to +105 °C
–40°C to +105 °C
28-Lead Small Outline Package
28-Lead Small Outline Package
Evaluation Board
RS-28
RS-28 on 13" Reels
PIN CONFIGURATION
CCLK 1
28
CDATA
CLATCH 2
27
MUTE
RESET 3
26
ZERO
LRCLK 4
25
FILTB
BCLK 5
24
AVDD
SDATA 6
23
OUTL
AD1959
DVDD 7
22
SCLK0 9
20
OUTR
MCLK 10
19
AGND0
XOUT 11
18
LF1
XIN 12
17
LF0
SCLK1 13
16
PGND
SCLK2 14
15
PVDD
AGND1
TOP VIEW
DGND 8 (Not to Scale) 21 FLTR
–4–
REV. 0
AD1959
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Mnemonic
Description
1
I
CCLK
2
3
I
I
CLATCH
RESET
4
5
I
I
LRCLK
BCLK
6
I
SDATA
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I
I
O
I/O
O
I
O
O
DVDD
DGND
SCLK0
MCLK
XOUT
XIN
SCLK1
SCLK2
PVDD
PGND
LF0
LF1
AGND0
OUTR
FILTR
22
23
24
25
26
I
O
O
AGND1
OUTL
AVDD
FILTB
ZERO
27
I
MUTE
28
I
CDATA
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
Latch Input for Control Data.
Reset. The AD1959 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
Serial input, MSB first, containing two channels of 16/20/24 bits of two’scomplement data per channel.
Digital Power Supply Connect to Digital 5 V Supply.
Digital Ground.
33.8688 MHz Clock Output.
27 MHz Master Clock Output/256 fS DAC Clock Input.
27 MHz Crystal Oscillator Output.
27 MHz Crystal Oscillator/External Clock Input.
256/384 fS Output.
512 fS/22.5792 MHz Output.
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground.
PLL0 Loop Filter.
PLL1 Loop Filter.
Analog Ground.
Right Channel Positive Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
Analog Ground.
Left Channel Line Level Analog Output.
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection, Connect 10 µF Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial control input, MSB first, containing 16 bits of unsigned data
per channel.
REV. 0
O
O
–5–
AD1959
27 MHz clock is buffered out to the MCLK pin. When set to
Input, the MCLK is the 256 fS master clock input for the DAC.
SCLK0 produces a 33.8688 MHz output, SCLK1 is intended
to be used as a master audio clock and will be a multiple of the
sample rate set in the PLL control register. It can be set to
256 fS or 384 fS using Bit 5 and to 512 fS or 768 fS, with Bit 4.
SCLK2 can be set to a constant 22.5792 MHz (512 × 44.1 kHz)
or 512 fS by Bit 3 of the PLL Control Register. Please note that
SCLK2 is intended to operate a DSP and does not meet the
jitter specifications stated under Analog Performance. All the
generated clocks can be set to 1/2 their nominal rate by setting
REF_Div2, Bit 8 in the PLL Control Register.
FUNCTIONAL DESCRIPTION
DAC
The AD1959 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 16384
linear steps. Digital inputs are supplied through a serial data input
pin, SDATA, a frame clock, LRCLK and a bit clock, BLCK.
Each analog output pin sits at a dc level of VREF, and swings
± 1.585 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins. The output
phase can be changed in an SPI control register to accommodate inverting and noninverting filters. Note that the use of op
amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care
should be exercised in selecting these components.
Reset
RESET will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
Serial Control Port
The FILTD and FILTR pins should be bypassed by external
capacitors to ground. The FILTD pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR (~2.39 V) can
be used to bias external op amps used to filter the output signals.
The AD1959 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.
The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz
range. For the 96 kHz range this is 128 fS. It is supplied internally from the PLL clock system when MCLK mode is set to
Output in the PLL Control Register. When the MCLK mode is
changed to Input, it must be supplied from an external source
connected to MCLK. The output from the 27 MHz PLL clock
is disabled in this case.
The SPI control port is a 3-wire serial control port. The format
is similar to the Motorola SPI format except the input data word
is 16 bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the PLL system or the
DAC. Figure 1 shows the format of the SPI signal. Note that the
CCLK can be gated or continuous, CLATCH should be low
during the 16 active clocks.
PLL Clock System
The PLL clock system operates from a 27 MHz master clock
supplied by the on-board crystal oscillator or an external source
connected to XIN. With the MCLK mode set to Output, the
CLATCH
CCLK
CDATA
D15
D0
D14
Figure 1. Format of SPI Signal
–6–
REV. 0
AD1959
parallel combination of 10 µF and 100 nF The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog output signal pins. The current drawn
from the VREF pin should be limited to less than 50 µA.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1959 is designed for five-volt supplies. Separate power
supply pins are provided for the analog, digital, and PLL sections. These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise. A
bulk aluminum electrolytic capacitor of at least 22 µF should
also be provided on the same PC board. For best performance it
is recommended that the analog supply be separate from the
digital and PLL supply. It is recommended that all supplies be
isolated by ferrite beads in series with each supply. It is expected
that the digital and PLL sections will be run from a common
supply but isolated from one another. It is important that the
analog supply be as clean as possible.
SERIAL DATA PORTS – DATA FORMAT
The DAC serial data input mode defaults to I2S. By changing
Bits 4 and 5 in the DAC control register, the mode can be
changed to RJ, DSP, or LJ. The word width defaults to 24 bits
but can be changed by programming Bits 8 and 9 in the DAC
Control Register.
Figure 2 shows the serial mode formats.
The internal voltage reference is brought out on Pin 21 (FILTR)
and should be bypassed as close as possible to the chip with a
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
12S MODE – 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
MSB
SDATA
MSB
LSB
LSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
DSP MODE – 16 TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 fS.
3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 2. Stereo Serial Modes
REV. 0
–7–
LSB
AD1959
Table I. DAC Control Register
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Factor
Serial Data
Width
Output Phase
Soft Mute
Serial Data
Format
De-Emphasis
Filter
SPI Register
Address
00 = 8×*
01 = 4×
10 = 2×
11 = Not Allowed
00 = 24 Bits*
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
0 = Noninverted*
1 = Inverted
0 = No Mute*
1 = Muted
00 = I2S*
00 = Right Justified
10 = DSP
11 = Left Justified
00 = None*
01 = 44.1 kHz
10 =32 kHz
11 = 48 kHz
01
C00660–2.5–4/01(0)
Bit 11:10
*Default Setting.
Table II. DAC Volume Registers
Bit 15:2
Bit 1:0
Volume
SPI Register Address
14 Bits, Unsigned
14 Bits, Unsigned
00 = Left Volume
10 = Right Volume
Default is full volume.
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
PLL2
PowerDown
PLL1
PowerDown
XTAL
PowerDown
REF_Div2
PowerDown
0 = On*
1 = PowerDown
0 = No Div*
1 = Div by 2
0 = On*
0 = On*
1 = Power- 1 = PowerDown
Down
Bit 7:6
Bit 5
fS
SCLK1
Select
00 = 48 kHz* 0 =256*
01 = Not
1 =384
Allowed
10 = 32 kHz
11 = 44.1 kHz
Bit 4
Bit 3
Bit 2
Bit 1:0
Double
SCLK2
Select
MCLK
Mode
SPI
Register
Address
0 = f S*
1 = 2 × fS
0 = 512 × 4.1 kHz* 0 = Output* 11
1 = 512 × fS
1 = Input
*Default Setting.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Outline Package (SSOP)
(RS-28)
28
PRINTED IN U.S.A.
0.407 (10.34)
0.397 (10.08)
15
0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
0.301 (7.64)
PIN 1
1
0.078 (1.98)
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
14
0.07 (1.79)
0.066 (1.67)
0.015 (0.38)
SEATING
0.010 (0.25)
PLANE
–8–
0.009 (0.229)
0.005 (0.127)
8
0
0.03 (0.762)
0.022 (0.558)
REV. 0