Cypress CY7C4265-15ASC 8k/16k x 18 deep sync fifo Datasheet

CY7C4255
CY7C4265
8K/16K x 18 Deep Sync FIFOs
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 45 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
Functional Description
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and a Write Enable pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN). In addition, the CY7C4255/65 have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
D0 – 17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
READ
POINTER
WRITE
POINTER
RS
FL/RT
WXI
WXO/HF
RXI
RXO
FF
EF
PAE
PAF
SMODE
FLAG
LOGIC
RAM
ARRAY
8K x 18
16K x 18
RESET
LOGIC
THREE–STATE
OUTPUT REGISTER
EXPANSION
LOGIC
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *B
Q0 – 17
•
READ
CONTROL
OE
3901 North First Street
RCLK
•
REN
San Jose
4255–1
•
CA 95134 • 408-943-2600
Revised August 11, 2004
CY7C4255
CY7C4265
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REN
LD
OE
RS
VCC
GND
EF
Q17
Q16
GND
Q15
VCC/SMODE
CY7C4255
CY7C4265
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D16
D17
GND
RCLK
TQFP/STQFP
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full,
Almost Full, and Full. The Half Full flag shares the WXO pin. This flag
is valid in the stand-alone and width-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
Q3
Q0
Q1
GND
Q2
PAE
FL/RT
WCLK
WEN
WXI
VCC
PAF
RXI
FF
WXO/HF
RXO
4255–3
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the VCC/SMODE is tied to VSS.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65-10
7C4255/65-15
7C4255/65-25
7C4255/65-35
100
66.7
40
28.6
Maximum Access Time (ns)
8
10
15
20
Minimum Cycle Time (ns)
10
15
25
35
Maximum Frequency (MHz)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC1) (mA)
Density
Package
3
4
6
7
0.5
1
1
2
8
10
15
20
Commercial
45
45
45
45
Industrial
50
50
50
50
CY7C4255
CY7C4265
8K x 18
16K x18
64-pin TQFP, STQFP 64-pin TQFP, STQFP
Document #: 38-06004 Rev. *B
Page 2 of 22
CY7C4255
CY7C4265
Signal Name
Description
I/O
Function
D0 –17
Data Inputs
I
Data inputs for an 18-bit bus.
Q0–17
Data Outputs
O
Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK inpu.t
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V CC/SMODE is tied to
VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programmable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS.
RXO
Read Expansion
Output
O
Cascaded – Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Document #: 38-06004 Rev. *B
Page 3 of 22
CY7C4255
CY7C4265
Maximum Ratings [1]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................ –65°C to +150°C
Operating Range[2]
Ambient Temperature with Power Applied . –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
DC Input Voltage ..........................................−0.5V to VCC+0.5V
5V ± 10%
Industrial[3]
–40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
7C42X5–10
7C42X5–15
7C42X5–25
7C42X5– 35
Min.
Min.
Min.
Min.
Max.
Output HIGH Voltage
VCC = Min.,
IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH[4]
Input HIGH Voltage
2.0
VCC
2.0
VCC
2.0
VCC
VIL[5]
Input LOW Voltage
–0.5
0.8
–0.5
0.8
–0.5
0.8
IIX
Input Leakage
Current
VCC = Max.
–10
+10
–10
+10
–10
+10
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
–10
+10
–10
+10
–10
+10
ICC1[6]
Active Power Supply
Current
Com’l
45
45
Ind
50
50
Average Standby
Current
Com’l
10
Ind
15
ICC2
2.4
Max.
VOH
[7]
2.4
Max.
0.4
2.4
0.4
Max.
2.4
0.4
Unit
V
0.4
V
2.0
VCC
V
–0.5
0.8
V
–10
+10
µA
–10
+10
µA
45
45
mA
50
50
mA
10
10
10
mA
15
15
15
mA
Capacitance[8, 9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
5
pF
7
pF
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is the “Instant On” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. The VIH and V IL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or V SS.
5. The VIH and V IL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or V SS.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded. ICC1(typical) = (25 mA+(freq –20 MHz)*(1.0 mA/MHz)).
7. All inputs = VCC – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at Vss. All outputs are unloaded.
8. Tested initially and after any design changes that may affect these parameters.
9. Tested initially and after any process changes that may affect these parameters.
Document #: 38-06004 Rev. *B
Page 4 of 22
CY7C4255
CY7C4265
AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
3.0V
OUTPUT
CL
GND
≤ 3 ns
R2
680Ω
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
≤ 3 ns
4255–4
4255–5
Equivalent to:
THÉVENIN EQUIVALENT
410Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
Parameter
Description
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Min.
Min.
Min.
Max.
100
Max.
Unit
28.6
MHz
20
ns
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
tDH
Data Hold Time
tENS
Enable Set-Up Time
tENH
Enable Hold Time
2
10
40
Max.
Clock Cycle Frequency
8
66.7
Max.
tS
2
15
2
3
4
6
7
ns
0.5
1
1
2
ns
3
4
6
7
ns
0.5
1
1
2
ns
tRS
Reset Pulse
Width[12]
10
15
25
35
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
30
35
45
55
ns
tRTR
Retransmit Recovery Time
60
65
75
85
ns
tOLZ
Output Enable to Output in Low Z[12]
0
0
0
0
ns
tOE
Output Enable to Output Valid
3
7
3
8
3
12
3
15
ns
tOHZ
Output Enable to Output in High Z[13]
3
7
3
8
3
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
10
Flag[13]
15
25
35
ns
tPAFasynch
Clock to Programmable Almost-Full
(Asynchronous mode, VCC/SMODE tied to
VCC)
12
16
20
25
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
Notes:
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
14. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document #: 38-06004 Rev. *B
Page 5 of 22
CY7C4255
CY7C4265
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Min.
Min.
Min.
Max.
10
Max.
15
Max.
Unit
20
ns
Clock to Expansion Out
tXI
Expansion in Pulse Width
4.5
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
4
5
10
15
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write
Clock for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous
Mode only)
10
15
18
20
ns
Document #: 38-06004 Rev. *B
6
Max.
tXO
Page 6 of 22
CY7C4255
CY7C4265
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1 [15]
RCLK
REN
4255–6
Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 –Q17
tOLZ
tOHZ
tOE
OE
tSKEW2[16]
WCLK
WEN
4255–7
Notes:
15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
16. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06004 Rev. *B
Page 7 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Reset Timing [17]
tRS
RS
tRSR
REN, WEN,
LD
tRSF
EF,PAE
tRSF
FF,PAF,
HF
tRSF
[18]
OE=1
Q0 – Q17
OE=0
4255–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D17
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
tENS
[19]
tFRL
WEN
tSKEW2
RCLK
tREF
EF
REN
tA
Q0 –Q17
tA
D0
[19]
D1
tOLZ
tOE
OE
4255–9
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK +
tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06004 Rev. *B
Page 8 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
D0
D0 –D17
D1
tENH
tENS
tENH
tENS
WEN
tFRL[18]
tFRL[18]
RCLK
tREF
tSKEW2
tREF
tREF
tSKEW2
EF
REN
OE
tA
D0
Q0 –Q17
4255–10
Full FlagTiming
NO WRITE
NO WRITE
WCLK
tSKEW1
[15]
tDS
tSKEW1 [15]
DATA WRITE
DATA WRITE
D0 –D17
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
Q0 –Q17
DATA IN OUTPUT REGISTER
tA
DATA READ
NEXT DATA READ
4255–11
Document #: 38-06004 Rev. *B
Page 9 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Half-Full Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
HALF FULL + 1
OR MORE
HALF FULL OR LESS
HALF FULLOR LESS
tHF
RCLK
tENS
REN
4255–12
Programmable Almost Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tPAE
N + 1 WORDS
IN FIFO
tPAE
PAE [20]
n WORDS IN FIFO
RCLK
tENS
REN
4255–13
Note:
21. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06004 Rev. *B
Page 10 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKL
tCLKH
WCLK
tENS tENH
WEN
WEN2
tENS tENH
PAE
Note
22
tSKEW3 [23]
N + 1 WORDS
INFIFO
tPAE synch
Note
24
tPAE synch
RCLK
tENS
tENS tENH
REN
4255–14
Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note 25
WCLK
tENS tENH
WEN
tPAF
FULL– M WORDS
INFIFO [27]
PAF [26]
FULL– (M+1) WORDS
IN FIFO [28]
tPAF
RCLK
tENS
REN
4255–15
Notes:
22. PAE offset − n.
23. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and
the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
24. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265.
Document #: 38-06004 Rev. *B
Page 11 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 29
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note
30
WEN2
tPAF
tENS tENH
PAF
FULL– M WORDS
IN FIFO [27]
FULL– M + 1 WORDS
IN FIFO
tSKEW3[31]
tPAF synch
RCLK
tENS
tENS tENH
REN
4255–16
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0 –D17
PAE OFFSET
PAF OFFSET
D0 – D11
4255–17
Notes:
29. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and
the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document #: 38-06004 Rev. *B
Page 12 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
LD
tENS
WEN
tA
UNKNOWN
Q0 –Q17
PAE OFFSET
PAF OFFSET
PAE OFFSET
4255–18
Write Expansion Out Timing
tCLKH
WCLK
Note 31
tXO
Note 32
WXO
tXO
tENS
WEN
4255–19
Read Expansion Out Timing
tCLKH
WCLK
Note 33
tXO
RXO
tXO
tENS
REN
4255–20
Write Expansion In Timing
tXI
WXI
WCLK
tXIS
4255–21
Notes:
32. Write to Last Physical Location.
33. Read from Last Physical Location.
Document #: 38-06004 Rev. *B
Page 13 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Read Expansion In Timing
tXI
RXI
tXIS
RCLK
4255–22
Retransmit Timing
[34, 35, 36]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
4255–23
Notes:
34. Clocks are free-running in this case.
35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Document #: 38-06004 Rev. *B
Page 14 of 22
CY7C4255
CY7C4265
Architecture
operation. When the LD pin is set LOW, and WEN is LOW, the next
offset register in sequence is written.
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65 also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then, data
can be read on the LOW-to-HIGH transition of the Read Clock
(RCLK).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of RS
only if OE is asserted. In order for the FIFO to reset to its default state,
a falling edge must occur on RS and the user must not read or write
while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D0 – 17
pins is written into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0–17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is
LOW. REN must set up tENS before RCLK for it to be a valid read
function. WEN must occur tENS before WCLK for it to be a valid write
function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW), data in
the output register will be available to the Q0–17 outputs after tOE. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs
even after additional reads occur.
Programming
The CY7C4255/65 devices contain two 14-bit offset registers.
Data present on D0 – 13 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full) flags
become active. If the user elects not to program the FIFO’s flags, the
default offset values are used (see Table 2). When the Load LD pin
is set LOW and WEN is set LOW, data on the inputs D0–13 is written
into the Empty offset register on the first LOW-to-HIGH transition of
the Write Clock (WCLK). When the LD pin and WEN are held LOW
then data is written into the Full offset register on the second
LOW-to-HIGH transition of the Write Clock (WCLK). The third transition of the Write Clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then, by
bringing the LD pin HIGH, the FIFO is returned to normal read/write
Table 1. Write Offset Register
WCLK[37]
LD
WEN
Selection
0
0
Writing to offset registers:
Empty Offset
Full Offset
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Flag Operation
The CY7C4255/65 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to
VSS.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations
are inhibited whenever FF is LOW regardless of the state of WEN.
FF is synchronized to WCLK, i.e., it is exclusively updated by each
rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the state
of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by
each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See Table 2 for a
description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition is
caused by the rising edge of the write clock and the PAE flag transition
is caused by the rising edge of the read clock.
Notes:
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06004 Rev. *B
Page 15 of 22
CY7C4255
CY7C4265
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the inter-
nal read pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after retransmit,
previously accessed data is read and the read pointer is incremented
until it is equal to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during a
retransmit cycle. Data written to the FIFO after activation of RT are
transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in FIFO
CY7C4255 – 8K x 18
FF
PAF
HF
PAE
EF
H
H
H
L
L
1 to n
[38]
1 to n
H
H
H
L
H
(n+1) to 4096
(n+1) to 8192
H
H
H
H
H
4097 to (8192–(m+1))
8193 to (16384 –(m+1))
H
H
L
H
H
(8192–m)[39] to 8191
(16384–m)[39] to 16383
H
L
L
H
H
8192
16384
L
L
L
H
H
0
CY7C4265 – 16K x 18
0
[38]
Notes:
38. n = Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127).
39. m = Full Offset (Default Values: CY7C4255/CY7C4265 n = 127).
Document #: 38-06004 Rev. *B
Page 16 of 22
CY7C4255
CY7C4265
Width Expansion Configuration
the Empty (Full) flags of every FIFO; the PAE and PAF flags
can be detected from any one device. This technique will avoid
reading data from, or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width
by using two CY7C4255/65s.
The CY7C4255/65 can be expanded in width to provide word
widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags
are available. Empty (Full) flags should be created by ANDing
RESET (RS)
DATA IN (D) 36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE(PAE)
7C4255
7C4265
7C4255
7C4265
HALF FULL FLAG (HF)
PROGRAMMABLE (PAF)
EMPTY FLAG (EF)
FF
FF
EF
EF
18
FULL FLAG (FF)
DATA OUT (Q)
36
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4255–24
Figure 1. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
Document #: 38-06004 Rev. *B
Page 17 of 22
CY7C4255
CY7C4265
Depth Expansion Configuration
(with Programmable Flags)
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
The CY7C4255/65 can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 2
shows Depth Expansion using three CY7C42X5s. Maximum depth
is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
WXO RXO
7C4255
7C4265
VCC
FL
FF
EF
PAE
PAF
WXI RXI
WXO RXO
7C4255
7C4265
DATA IN(D)
DATA OUT (Q)
VCC
FL
FF
EF
PAF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WXO RXO
WRITE ENABLE(WEN)
READ CLOCK(RCLK)
READ ENABLE(REN)
7C4255
7C4265
RESET (RS)
OUTPUT ENABLE(OE)
LOAD (LD)
FF
FF
PAF
EF
EF
PAFWXI RXI PAE
PAE
FIRST LOAD (FL)
4255–25
Figure 2. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06004 Rev. *B
Page 18 of 22
CY7C4255
CY7C4265
Typical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs. SUPPLY
VOLTAGE
1.60
NORMALIZED t A
NORMALIZED t A
1.20
1.10
1.00
0.90
0.80
4.00
TA = 25°C
4.50
5.00
5.50
6.00
1.40
1.20
1.00
0.60
−55.00
VIN = 3.0V
TA = 25°C
f = 28 MHz
0.80
4.50
5.00
5.50
SUPPLY VOLTAGE (V)
Document #: 38-06004 Rev. *B
6.00
NORMALIZED I CC
NORMALIZED I CC
NORMALIZED I CC
1.00
125.00
1.75
1.20
1.20
65.00
NORMALIZED SUPPLYCURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
0.60
4.00
5.00
AMBIENT TEMPERATURE( °C)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VCC = 5.0V
0.80
1.10
1.00
VIN = 3.0V
VCC=5.0V
f = 28 MHz
0.90
0.80
−55.00
5.00
65.00
125.00
AMBIENT TEMPERATURE (°C)
1.50
1.25
1.00
VCC = 5.0V
TA = 25°C
VIN = 3.0V
0.75
0.50
20.00
30.00
40.00
50.00 60.00
FREQUENCY (MHz)
Page 19 of 22
CY7C4255
CY7C4265
Ordering Information
8Kx18 Deep Sync FIFO
Speed
(ns)
10
15
Ordering Code
Package
Name
Package
Type
CY7C4255–10AC
A65
64-Lead Thin Quad Flatpack
CY7C4255-10ASC
A64
64-Lead Small Thin Quad Flatpack
CY7C4255–15AC
A65
64-Lead Thin Quad Flatpack
Operating
Range
Commercial
Commercial
16Kx18 Deep Sync FIFO
Speed
(ns)
10
15
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4265–10AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4265-10ASC
A64
64-Lead Small Thin Quad Flatpack
CY7C4265–10AI
A65
64-Lead Thin Quad Flatpack
Industrial
CY7C4265–15AC
A65
64-Lead Thin Quad Flatpack
Commercial
CY7C4265-15ASC
A64
64-Lead Small Thin Quad Flatpack
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-A
Document #: 38-06004 Rev. *B
Page 20 of 22
CY7C4255
CY7C4265
Package Diagrams (continued)
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
Document #: 38-06004 Rev. *B
Page 21 of 22
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C4255
CY7C4265
Document Title: CY7C4255, CY7C4265 8K/16K X 18 Deep Sync FIFOs
Document Number: 38-06004
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106465
07/11/01
SZV
Change from Spec Number: 38-00468 to 38-06004
*A
122257
12/26/02
RBI
Power up requirements added to Maximum Ratings Information
*B
252889
See ECN
YDT
Removed PLCC package and pruned parts from Order Information
Document #: 38-06004 Rev. *B
Page 22 of 22