AD AD6630 Differential, low noise if gain block with output clamping Datasheet

a
Differential, Low Noise IF Gain
Block with Output Clamping
AD6630
FEATURES
24 dB Gain
4 dB Noise Figure
Easy Match to SAW Filters
Output Limiter Adjustable +8.5 dBm to +12 dBm
700 MHz Bandwidth
10 V Single or Dual 5 V Power Supply
300 mW Power Dissipation
FUNCTIONAL BLOCK DIAGRAM
AD6630
16
VCC
15
CD1
14
OP
13
VEE
IP1 5
12
CMD
IP2 6
11
OP
CLLO 7
10
CD2
CLHI 8
9
VCC
NC 1
NC 2
APPLICATIONS
ADC IF Drive Amp
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
IP2 3
+
IP1 4
+
+
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD6630 is an IF gain block designed to interface between
SAW filters and differential input analog-to-digital converters.
The AD6630 has a fixed gain of 24 dB and has been optimized
for use with the AD6600 and AD6620 in digitizing narrowband
IF carriers in the 70 MHz to 250 MHz range.
Taking advantage of the differential nature of SAW filters, the
AD6630 has been designed as a differential in/differential out
gain block. This architecture allows 100 dB of adjacent channel
blocking using low cost SAW filters. The AD6630 provides
output limiting for ADC and SAW protection with ⬍10° phase
variation in recovery from overdrive situations.
Designed for “narrow-band” cellular/PCS receivers, the high
linearity and low noise performance of the AD6630 allows for
implementation in a wide range of applications ranging from
GSM to CDMA to AMPS. The clamping circuitry also maintains the phase integrity of an overdriven signal. This allows
phase demodulation of single carrier signals with an overrange
signal.
While the AD6630 is optimized for use with the AD6600 Dual
Channel, Gain Ranging ADC with RSSI, it can also be used in
many other IF applications. The AD6630 is designed with an
input impedance of 200 Ω and an output of 400 Ω. In the typical application shown below, these values match the real portion
of a typical SAW filter. Other devices can be matched using
standard matching network techniques.
The AD6630 is built using Analog Devices’ high speed complementary bipolar process. Units are available in a 300 mil SOIC
(16 leads) plastic surface mount package and specified to operate
over the industrial temperature range (–40°C to +85°C).
AD6630
MAIN
LOCAL
OSCILLATOR
AD6600
AD6620
DSP
AD6630
DIVERSITY
Figure 1. Reference Design
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD6630–SPECIFICATIONS
NORMAL OPERATING CONDITIONS
Parameter (Conditions)
Min
Typ
SINGLE SUPPLY VOLTAGE
8.5
POSITIVE SUPPLY VOLTAGE
4.25
NEGATIVE SUPPLY VOLTAGE
–5.25
AMBIENT TEMPERATURE
–40
PACKAGE THERMAL RESISTANCE
Max
Units
10.5
V
5.0
5.25
V
–5.0
–4.25
V
+85
°C
°C/W
80
OPERATING FREQUENCY1
70
250
MHz
(TMIN = –40ⴗC, TMAX = +85ⴗC. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (–5 V)] = 0.
DC SPECIFICATIONS Inputs should be AC coupled.)
Parameter
Temp
Test
Level
SUPPLY CURRENT
Full
II
OUTPUT DC LEVEL
Full
II
Min
Typ
Max
Units
30
48
mA
VM+150
mV
VM–150
(TMIN = –40ⴗC, TMAX = +85ⴗC. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz
AC SPECIFICATIONS performance limits are correlated to 5 MHz testing based on characterization data.)
Parameter1
Temp
Test
Level
Min
Typ
Max
Units
GAIN (POWER) @ 70 MHz
Full
II
23
24
25
dB
GAIN (POWER) @ 250 MHz
Full
II
22
23
24
dB
+25°C
V
700
MHz
Full
V
22
dBm
Full
V
19
dBm
OUTPUT REFERRED IP2 @ 70 MHz2
Full
V
45
dBm
OUTPUT REFERRED IP2 @ 250 MHz2
Full
V
45
dBm
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 70 MHz LOW LEVEL CLAMP3
Full
II
8.5
dBm
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 250 MHz LOW LEVEL CLAMP3
Full
II
7.5
dBm
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 70 MHz HIGH LEVEL CLAMP4
Full
II
11
dBm
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 250 MHz HIGH LEVEL CLAMP4
Full
II
9
dBm
OUTPUT SLEW RATE
+25°C
V
3700
V/µs
INPUT IMPEDANCE (REAL)
+25°C
V
200
Ω
INPUT CAPACITANCE
+25°C
V
2
pF
OUTPUT IMPEDANCE (REAL)
+25°C
V
400
Ω
OUTPUT CAPACITANCE
+25°C
V
2
pF
NOISE FIGURE
+25°C
V
4
dB
–3 dB BANDWIDTH
OUTPUT REFERRED IP3 @ 70 MHz
2
OUTPUT REFERRED IP3 @ 250 MHz
2
LOW LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz3, 5
HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz
Full
IV
11
12.5
dBm
4, 5
Full
IV
13.8
14.3
dBm
3, 5
Full
IV
9.25
10.6
dBm
LOW LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz
–2–
REV. 0
AD6630
Parameter
HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz
4, 5
6
PHASE VARIATION
CMRR
PSRR
7
8
Temp
Test
Level
Full
Min
Typ
Max
Units
IV
11.2
12.2
dBm
+25°C
V
9
Degree
+25°C
V
50
dB
+25°C
V
30
dB
NOTES
1
All specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier’s input and output
impedance.
2
Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at –23 dBm per tone input.
3
Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin
CLLO and CLHI to the negative supply through an external resistor.
4
High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to
be utilized.
5
Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 Ω = 3.2 V p-p—differential.
6
Measured as the change in output phase when the input level is changed from –53 dBm to +8 dBm (i.e., from linear operation to clamping).
7
Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins.
8
Ratio of signal on supply to differential output (<500 kHz).
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Single Supply Voltage
Positive Supply Voltage
Negative Supply Voltage
Input Power
Storage Temperature
Junction Temperature
ESD Protection
–0.5
–0.5
–5.75
11.5
5.75
0.5
+8
+150
+150
V
V
V
dBm
°C
°C
kV
–65
1
I.
100% production tested.
II. 100% production tested at +25°C, and guaranteed by
design and analysis at temperature extremes.
III. Sample tested only.
IV. Parameter guaranteed by design and analysis.
V. Parameter is typical value only.
VI. 100% production tested at +25°C, and sample tested at
temperature extremes.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD6630AR
AD6630AR-REEL
AD6630R/PCB
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
16-Lead Wide Body SOIC
AD6630AR on 1000 PC Reel
Evaluation Board with AD6630AR
R-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD6630
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
Pin No
Pin Name
Description
1, 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
IP2
IP1
IP1
IP2
CLLO
CLHI
VCC
CD2
OP
CMD
VEE
OP
CD1
VCC
No Connect
Input
Input
Input
Input
Clamp Level Low Pin
Clamp Level High Pin
+VCC Supply
Clamp Decoupling
Output
DC Feedback Decoupling
–VEE Supply
Output
Clamp Decoupling
+VCC Supply
NC 1
16
VCC
NC 2
15
CD1
IP2 3
14
OP
IP1 4
AD6630
VEE
TOP VIEW
IP1 5 (Not to Scale) 12 CMD
13
IP2 6
11
OP
CLLO 7
10
CD2
CLHI 8
9
VCC
NC = NO CONNECT
Typical Performance Characteristics
13
24
1dB COMPRESSION POINT
INTERCEPT POINT – dBm
23
22
21
20
19
18
12
HIGH CLAMP
11
10
LOW CLAMP
9
17
16
70
100
8
70
300
100
INPUT FREQUENCY – MHz
300
INPUT FREQUENCY – MHz
Figure 2. 3rd Order Intercept (IP3) vs. Frequency
Figure 4. 1 dB Compression Point (Typical)
25
OUTPUT AMPLITUDE – dBm
14
–408C
GAIN – dB
24
+258C
+858C
23
13
HIGH CLAMP
12
11
LOW CLAMP
10
22
70
100
9
300
70
INPUT FREQUENCY – MHz
100
300
INPUT FREQUENCY – MHz
Figure 3. Gain vs. Frequency
Figure 5. Clamp Level vs. Frequency
–4–
REV. 0
AD6630
–1dB
15dB –9dB
Bm
Bm
9d
4d
–2
–1
LOCAL
OSCILLATOR
Bm
8d
–2
–2dB
15dB
–5dB
24dB
Bm dBm dBm dBm dBm
9
5
0
5
–1
–1
–2
Bm
4d
3d
–2
AD6630
SAW
ANTENNA
–104dBm
–43dBm
–28dBm
–16dBm
–15dBm
–5dB
AD6630 INPUT
–91dBm
–30dBm
–15dBm
–3dBm
–2dBm
SAW
AD6630 OUTPUT
–67dBm
–6dBm
+9dBm
+9dBm
+9dBm
MAIN
AD6600
AD6620
DSP
DIVERSITY
AD6600 INPUT
–71dBm
–10dBm
+4dBm
+4dBm
+4dBm
Figure 6. GSM Design Example
This equation is derived from measured data at 170 MHz. Clamp
levels vary with frequency, see Figure 5. Output clamp levels
less than 8.5 dBm will result in damage to the clamp circuitry
unless the absolute maximum input power is derated. Similarly,
the output clamp level cannot be set higher than 12 dBm.
THEORY OF OPERATION
The AD6630 amplifier consists of two stages of gain. The first
stage is differential. This differential amplifier provides good
common-mode rejection to common-mode signals passed by
the SAW filter. The second stage consists of matched current
feedback amplifiers on each side of the differential pair. These
amplifiers provide additional gain as well as output drive capability. Gain set resistors for these stages are internal to the device and cannot be changed, allowing fixed compensation for
optimum performance.
R
VEE
CLAMP
GENERATOR
Figure 7. Clamp Level Resistor
Clamping levels for the device are normally set by tying CLLO
or CLHI pins to the negative supply. This internally sets bias
points that generate symmetric clamping levels. Clamping is
achieved primarily in the output amplifiers. Additional input
stage clamping is provided for additional protection. Clamping
levels may be adjusted to lower levels as discussed below.
Matching SAW Filters
The AD6630 is designed to easily match to SAW filters. SAW
filters are largely capacitive in nature. Normally a conjugate
match to the load is desired for maximum power transfer.
Another way to treat the problem is to make the SAW filter look
purely resistive. If the SAW filter load looks resistive there is no
lead or lag in the current vs. voltage. This may not preserve
maximum power transfer, but maximum voltage swing will
exist. All that is required to make the SAW filter input or output
look real is a single inductor shunted across the input. When the
correct value is used, the impedance of the SAW filter becomes
real.
APPLICATIONS
The AD6630 provides several useful features to meet the needs
of radio designers. The gain and low noise figure of the device
make it perfect for providing interstage gain between differential
SAW filters and/or analog-to-digital converters (ADC). Additionally, the on-board clamping circuitry provides protection for
sensitive SAW filters or ADCs. The fast recovery of the clamp
circuit permits demodulation of constant envelope modulated
IF signals by preserving the phase response during clamping.
9.7V
The following topics provide recommendations for using the
AD6630 in narrowband, single carrier applications.
400V
3pF
47nH
15.2pF
Adjusting Output Clamp Levels
Normally, the output clamp level is set by tying either CLLO or
CLHI to ground or VEE . It is possible to set the limit between
8.5 dBm and 12 dBm levels by selecting the appropriate external resistor.
Figure 8. Saw Filter Model (170 MHz)
EVALUATION BOARD
To set to a different level, CLLO and CLHI should be tied
together and then through a resistor to ground. The value of the
resistor can be selected using the following equation.
R=
REV. 0
Figures 9, 10 and 12 refer to the schematic and layout of the
AD6630AR as used on Analog Devices’ GSM Diversity Receiver Reference Design (only the IF section is shown). Figure
14 references the schematic of the stand-alone AD6630 evaluation board and uses a similar layout. The evaluation board uses
center tapped transformers to convert the input to a differential
signal and AD6630 outputs to a single connector to simplify
evaluation. C8, C9 and L2 are optional reactive components to
tune the load for a particular IF frequency if desired.
14.4 – OUTPUTCLAMP
(dBm)
0.0014
–5–
AD6630
+10V
U100A
SMA
CHNA
L1A
C1
L1
11
VI
C2
VO
5
C100
0.1mF
SAW1
L2
12
VI
VO
6
C101
0.1mF
GND
1 2 3 4 7 8 9 10
NC1
VCC1
NC2
CD1
IP2
OP
IP1
VEE
IP1B
CMD
IP2B
OPB
CL1
CD2
CL2
VCC2
11
VI
VO
L4
12
AD6630
TO
AD6600
L6
SAW2
6
VI
C104
0.1mF
C103
0.1mF
5
VO
GND
1 2 3 4 7 8 9 10
C102
0.1mF
Figure 9. Reference Design Schematic (One Channel)
Figure 12. Reference Design Component Placement (Two
Channels Shown)
Figure 10. Reference Design PCB Layout
OUTPUT
AMP
VCC
+
+
–
+
DIFF
AMP
–
IP1
OUTPUT
AMP
TO OUTPUT
AMPLIFIER
–
200V
200V
IP1
TO OUTPUT
AMPLIFIER
BIAS
200V
200V
IP2
IP2
CLHI
CLLO
CLP
CLAMP
GENERATOR
VEE
CLN
Figure 13. Equivalent Input Circuit
Figure 11. Functional Block Diagram
–6–
REV. 0
AD6630
J1
PCTB3
3
2 1
C13
1mF
1
2
+ –
AGND
C18
1mF
J3
+
–
C21
10nF
AGND
11
2
AGND
C16
10nF
AGND
C17
10nF
1
J6
SMA
R3
R1
200V
TP1
2
AD6630
1
2
AGND
T1
1
J7
SMA
1
AGND
2
6
1
2
4
AGND
3
L1
470nH
3
TC4–1W
AT224
C12
10nF
4
5
C11
10nF
6
7
C1
10nF
8
AGND
U1
NC1
VCC1
NC2
CD1
IP2
OP
IP1
VEE
IP1B
CMD
IP2B
OPB
CL1
CL2
CD2
VCC2
16
15
C15
1nF
C5
C10
100nF
TEST P
C2
10nF
10nF
T2
14
3
13
12
C6
C8
10nF
C9
L2
2
11
1
10
TC 8-1
AT224
C7
10nF
C3
10nF
9
C14
1nF
J2
C20
1nF
C19
100nF
1
C4
100nF
AGND
TP2
TEST P
R2
200V
AGND
Figure 14. Evaluation Board Schematic
Table I. Typical S Parameters
Frequency
(MHz)
S11
S12
S21
S22
70
170
200
250
224.5 ∠ –4.52°
264.8 ∠ –32.9°
227.9 ∠ –34.8°
209.5 ∠ –36.2°
–41.0 ∠ –3.0°
–31.4 ∠ 0°
–41.0 ∠ –5°
–40.6 ∠ –2.3°
24.1 ∠ –8.8°
23.5 ∠ –22.5°
23.2 ∠ –26.4°
22.9 ∠ –38.9°
394.3 ∠ –8.6°
382.4 ∠ –21.9°
353.0 ∠ –25.4°
328.9 ∠ –29.2°
–7–
2
6
AGND
REV. 0
J8
SMA
1
4
AGND
AD6630
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide Body SOIC
(R-16)
1
8
0.0500
(1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.0192 (0.49)
SEATING
0.0138 (0.35) PLANE
0.0291 (0.74)
x 458
0.0098 (0.25)
88 0.0500 (1.27)
0.0125 (0.32) 08 0.0157 (0.40)
0.0091 (0.23)
PRINTED IN U.S.A.
PIN 1
0.0118 (0.30)
0.0040 (0.10)
C3412–8–10/98
9
0.4193 (10.65)
0.3937 (10.00)
16
0.2992 (7.60)
0.2914 (7.40)
0.4133 (10.50)
0.3977 (10.00)
–8–
REV. 0
Similar pages