a 50 MHz CMOS Complete DDS AD9835 FEATURES 5 V Power Supply 50 MHz Speed On-Chip COS Look-Up Table On-Chip 10-Bit DAC Serial Loading Power-Down Option 200 mW Power Consumption 16-Lead TSSOP GENERAL DESCRIPTION The AD9835 is a numerically controlled oscillator employing a phase accumulator, a COS Look-Up Table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 50 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the serial interface. A power-down bit allows the user to power down the AD9835 when it is not in use, the power consumption being reduced to 1.75 mW. The part is available in a 16-lead TSSOP package. APPLICATIONS DDS Tuning Digital Demodulation FUNCTIONAL BLOCK DIAGRAM DVDD MCLK FSELECT BIT DGND AVDD REFOUT AGND FS ADJUST REFIN SELSRC ON-BOARD REFERENCE FSELECT FULL-SCALE CONTROL SYNC FREQ0 REG PHASE ACCUMULATOR (32 BIT) MUX FREQ1 REG Σ 12 COS ROM 10-BIT DAC COMP IOUT PHASE0 REG PHASE1 REG AD9835 MUX PHASE2 REG SYNC PHASE3 REG SYNC 16-BIT DATA REGISTER SYNC 8 MSBs 8 LSBs DEFER REGISTER SELSRC CONTROL REGISTER DECODE LOGIC FSELECT/PSEL REGISTER PSEL0 BIT PSEL1 BIT SERIAL REGISTER FSYNC SCLK SDATA PSEL0 PSEL1 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 (VDD = +5 V ⴞ 5%; AGND = DGND = 0 V; TA = T MIN to TMAX; REFIN = REFOUT; SET = 3.9 k⍀; RLOAD = 300 ⍀ for IOUT, unless otherwise noted) AD9835–SPECIFICATIONS1 R Parameter AD9835B Units 10 50 4 4.75 1.35 Bits MSPS nom mA nom mA max V max ±1 ± 0.5 LSB typ LSB typ 50 –52 dB min dBc max –72 –50 –60 1 Yes dBc min dBc min dBc typ ms typ VOLTAGE REFERENCE Internal Reference @ +25°C TMIN to TMAX REFIN Input Impedance Reference TC REFOUT Output Impedance 1.21 1.21 ± 7% 10 100 300 V typ V min/max MΩ typ ppm/°C typ Ω typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance DVDD – 0.9 0.9 10 10 V min V max µA max pF max POWER SUPPLIES AVDD DVDD IAA IDD IAA + IDD4 Low Power Sleep Mode 4.75/5.25 4.75/5.25 5 2.5 + 0.33/MHz 40 0.35 V min/V max V min/V max mA max mA typ mA max mA max SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS2 Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range (SFDR)3 Narrow Band (± 50 kHz) Wide Band (± 2 MHz) Clock Feedthrough Wake-Up Time Power-Down Option Test Conditions/Comments fMCLK = 50 MHz, fOUT = 1 MHz fMCLK = 50 MHz, fOUT = 1 MHz fMCLK = 6.25 MHz, fOUT = 2.11 MHz fMCLK = 50 MHz NOTES 1 Operating temperature range is as follows: B Version: –40 °C to +85°C. 2 100% production tested. 3 f MCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4 Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. See Figure 5. Specifications subject to change without notice. RSET 3.9kV 10nF REFOUT ON-BOARD REFERENCE 12 COS ROM FS ADJUST REFIN FULL-SCALE CONTROL COMP 10-BIT DAC IOUT AD9835 AVDD 10nF 300V 50pF Figure 1. Test Circuit with Which Specifications Are Tested –2– REV. 0 AD9835 TIMING CHARACTERISTICS (V Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A1 DD = +5 V ⴞ 5%; AGND = DGND = 0 V, unless otherwise noted) Limit at TMIN to TMAX (B Version) Units Test Conditions/Comments 20 8 8 50 20 20 15 20 SCLK – 5 15 5 8 8 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min MCLK Period MCLK High Duration MCLK Low Duration SCLK Period SCLK High Duration SCLK Low Duration FSYNC to SCLK Falling Edge Setup Time FSYNC to SCLK Hold Time Data Setup Time Data Hold Time FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge NOTES 1 See Pin Description section. Guaranteed by design but not production tested. t1 MCLK t2 t3 Figure 2. Master Clock t5 t4 SCLK t7 t8 t6 FSYNC t 10 t9 SDATA D15 D14 D2 D1 D0 D15 Figure 3. Serial Timing MCLK t11A t11 FSELECT PSEL0, PSEL1 VALID DATA VALID DATA Figure 4. Control Timing REV. 0 –3– VALID DATA D14 AD9835 ABSOLUTE MAXIMUM RATINGS* TERMINOLOGY Integral Nonlinearity (TA = +25°C unless otherwise noted) This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . . 158°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V Differential Nonlinearity This is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. Signal to (Noise + Distortion) Signal to (Noise + Distortion) is measured signal to noise at the output of the DAC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fMCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Signal to (Noise + Distortion) = (6.02N + 1.76) dB where N is the number of bits. Thus, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB. ORDERING GUIDE Model Temperature Range Package Description Package Option* AD9835BRU –40°C to +85°C 16-Lead TSSOP RU-16 Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9835, THD is defined as *RU = Thin Shrink Small Outline Package (TSSOP). 2 THD = 20 log PIN CONFIGURATION FS ADJUST 1 16 COMP REFIN 2 15 AVDD REFOUT 3 DVDD 4 AD9835 2 2 2 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. 14 IOUT Output Compliance 13 AGND The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9835 may not meet the specifications listed in the data sheet. TOP VIEW DGND 5 (Not to Scale) 12 PSEL0 MCLK 6 11 PSEL1 SCLK 7 10 FSELECT SDATA 8 2 (V 2 +V 3 +V 4 +V 5 +V 6 ) V1 9 FSYNC Spurious Free Dynamic Range Along with the frequency of interest, harmonics of the fundamental frequency and images of the MCLK frequency are present at the output of a DDS device. The spurious free dynamic range (SFDR) refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth ± 2 MHz about the fundamental frequency. The narrow band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ± 50 kHz about the fundamental frequency. Clock Feedthrough There will be feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9835’s output spectrum. –4– REV. 0 AD9835 PIN FUNCTION DESCRIPTIONS Pin # Mnemonic Function ANALOG SIGNAL AND REFERENCE 1 FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE = 12.5 × VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical 2 REFIN Voltage Reference Input. The AD9835 can be used with either the onboard reference, which is available from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9835 accepts a reference of 1.21 V nominal. 3 REFOUT Voltage Reference Output. The AD9835 has an onboard reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND. 14 IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. 16 COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD. POWER SUPPLY 4 DVDD 5 13 15 DGND AGND AVDD Positive Power Supply for the Digital Section. A 0.1 µF decoupling capacitor should be connected between DVDD and DGND. DVDD can have a value of +5 V ± 5%. Digital Ground. Analog Ground. Positive Power Supply for the Analog Section. A 0.1 µF decoupling capacitor should be connected between AVDD and AGND. AVDD can have a value of +5 V ± 5%. DIGITAL INTERFACE AND CONTROL 6 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. 7 SCLK Serial Clock, Logic Input. Data is clocked into the AD9835 on each falling SCLK edge. 8 SDATA Serial Data In, Logic Input. The 16-bit serial data word is applied to this input. 9 FSYNC Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed that a new word is being loaded into the device. 10 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. The frequency register to be used can be selected using the pin FSELECT or the bit FSELECT. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. When the bit is being used to select the frequency register, the pin FSELECT should be tied to DGND. 11, 12 PSEL0, PSEL1 Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value being input to the COS ROM. The contents of the phase register are added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register to be used can be selected using bits PSEL0 and PSEL1. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. When the phase registers are being controlled by the bits PSEL0 and PSEL1, the pins should be tied to DGND. REV. 0 –5– AD9835 Table I. Control Registers Table V. Commands Register Size Description C3 C2 C1 C0 Command FREQ0 REG 32 Bits 0 0 0 0 FREQ1 REG 32 Bits 0 0 0 0 0 1 1 0 PHASE0 REG 12 Bits 0 0 0 1 1 0 1 0 PHASE1 REG 12 Bits Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = 1, as a fraction of the MCLK frequency. Phase Offset Register 0. When PSEL0 = PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 1. When PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 2. When PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 3. When PSEL0 = PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. 0 1 0 1 0 1 1 0 0 1 1 1 Write 16 Phase bits (Present 8 Bits + 8 Bits in Defer Register) to Selected PHASE REG. Write 8 Phase bits to Defer Register. Write 16 Frequency bits (Present 8 Bits + 8 Bits in Defer Register) to Selected FREQ REG. Write 8 Frequency bits to Defer Register. Bits D9 (PSEL0) and D10 (PSEL1) are used to Select the PHASE REG when SELSRC = 1. When SELSRC = 0, the PHASE REG is selected using the pins PSEL0 and PSEL1 Respectively. Bit D11 is used to select the FREQ REG when SELSRC = 1. When SELSRC = 0, the FREQ REG is selected using the pin FSELECT. This command is used to control the PSEL0, PSEL1 and FSELECT bits using only one write. Bits D9 and D10 are used to select the PHASE REG and Bit 11 is used to select the FREQ REG when SELSRC = 1. When SELSRC = 0, the PHASE REG is selected using the pins PSEL0 and PSEL1 and the FREQ REG is selected using the pin FSELECT. Reserved. Configures the AD9835 for Test Purposes. PHASE2 REG PHASE3 REG 12 Bits 12 Bits Table II. Addressing the Registers A3 A2 A1 A0 Destination Register 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FREG0 REG 8 L LSBs FREG0 REG 8 H LSBs FREG0 REG 8 L MSBs FREG0 REG 8 H MSBs FREG1 REG 8 L LSBs FREG1 REG 8 H LSBs FREG1 REG 8 L MSBs FREG1 REG 8 H MSBs PHASE0 REG 8 LSBs PHASE0 REG 8 MSBs PHASE1 REG 8 LSBs PHASE1 REG 8 MSBs PHASE2 REG 8 LSBs PHASE2 REG 8 MSBs PHASE3 REG 8 LSBs PHASE3 REG 8 MSBs Table VI. Controlling the AD9835 D15 D14 Command 1 0 1 1 Table III. 32-Bit Frequency Word 16 MSBs 8 H MSBs 8 L MSBs 16 LSBs 8 H LSBs 8 L LSBs Table IV. 12-Bit Frequency Word 4 MSBs (The 4 MSBs of the 8-Bit Word Loaded = 0) 8 LSBs –6– Selects source of Control for the PHASE and FREQ Registers and Enables Synchronization. Bit D13 is the SYNC Bit. When this bit is High, reading of the FSELECT, PSEL0 and PSEL1 bits/pins and the loading of the Destination Register with data is synchronized with the rising edge of MCLK. The latency is increased by 2 MCLK cycles when SYNC = 1. When SYNC = 0, the loading of the data and the sampling of FSELECT/PSEL0/PSEL1 occurs asynchronously. Bit D12 is the Select Source Bit (SELSRC). When this bit Equals 1, the PHASE/FREQ REG is Selected using the bits FSELECT, PSEL0 and PSEL1. When SELSRC = 0, the PHASE/FREQ REG is Selected using the pins FSELECT, PSEL0 and PSEL1. Sleep, Reset and Clear. D13 is the SLEEP bit. When this bit equals 1, the AD9835 is powered down, internal clocks are disabled and the DAC's current sources and REFOUT are turned off. When SLEEP = 0, the AD9835 is powered up. When RESET (D12) = 1, the phase accumulator is set to zero phase which corresponds to an analog output of full scale. When CLR (D11) = 1, SYNC and SELSRC are set to zero. CLR automatically resets to zero. REV. 0 AD9835 Table VII. Writing to the AD9835 Data Registers D15 D14 D13 D12 D11 D10 D9 D8 D7 C3 C2 C1 C0 A3 A2 A1 A0 MSB D6 D5 D4 D3 D2 D1 D0 LSB Table VIII. Setting SYNC and SELSRC D15 D14 1 0 D13 D12 SYNC SELSRC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X X X Table IX. Power-Down, Resetting and Clearing the AD9835 D15 D14 1 1 D13 D12 SLEEP RESET D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLR X X X X X X X X X X X Typical Performance Characteristics –64 0 AVDD = DVDD = +5V SFDR (650kHz) – dB SIGNAL ATTENUATION – dB –4 CL = 82pF –6 –8 –10 –12 CL = 150pF 0 2 4 6 8 10 12 OUTPUT FREQUENCY – MHz 14 –72 20 30 40 MCLK FREQUENCY – MHz 50 Figure 7. Narrow Band SFDR vs. MCLK Frequency 0 TA = +258C AVDD = DVDD = +5V fOUT /f MCLK = 1/3 –10 AVDD = DVDD = +5V SFDR (62MHz) – dB TOTAL CURRENT – mA –70 –76 10 16 20 15 10 5 0 10 –68 –74 30 25 AVDD = DVDD = +5V CL = 100pF Figure 5. Signal Attenuation vs. Output Frequency for Various Capacitive Load (RL = 300 Ω) –20 –30 –40 –50 20 30 40 MCLK FREQUENCY – MHz –60 50 10 20 30 40 MCLK FREQUENCY – MHz 50 Figure 8. Wide Band SFDR vs. MCLK Frequency Figure 6. Typical Current Consumption vs. MCLK Frequency REV. 0 fOUT /f MCLK = 1/3 –66 –2 –7– AD9835 –20 AVDD = DVDD = +5V –40 10dB/DIV SFDR (62MHz) – dB –30 50MHz –50 30MHz –60 –70 10MHz –80 0.044 0.084 0.124 0.164 0.204 0.244 fOUT /fMCLK 0.284 0.324 0Hz START RBW 1kHz 0.364 Figure 9. Wide Band SFDR vs. fOUT/f MCLK for Various MCLK Frequencies VBW 3kHz 25MHz STOP ST 50 SEC Figure 12. fMCLK = 50 MHz, fOUT = 2.1 MHz. Frequency Word = ACO8312 56 fOUT /f MCLK = 1/3 55 AVDD = DVDD = +5V 10dB/DIV SNR – dB 54 53 52 51 50 10 20 30 40 MCLK FREQUENCY – MHz 0Hz START RBW 1kHz 50 Figure 10. SNR vs. MCLK Frequency VBW 3kHz 25MHz STOP ST 50 SEC Figure 13. fMCLK = 50 MHz, fOUT = 3.1 MHz. Frequency Word = FDF3B64 70 10MHz 60 30MHz 50MHz 10dB/DIV SNR – dB 50 40 30 20 AVDD = DVDD = +5V 10 0.044 0.084 0.124 0.164 0.204 0.244 fOUT /fMCLK 0.284 0.324 0.364 0Hz START RBW 1kHz VBW 3kHz 25MHz STOP ST 50 SEC Figure 14. fMCLK = 50 MHz, fOUT = 7.1 MHz. Frequency Word = 245AICAC Figure 11. SNR vs. f OUT/fMCLK for Various MCLK Frequencies –8– REV. 0 0Hz START RBW 1kHz 10dB/DIV 10dB/DIV AD9835 VBW 3kHz 0Hz START RBW 1kHz 25MHz STOP ST 50 SEC 0Hz START RBW 1kHz 10dB/DIV VBW 3kHz 25MHz STOP ST 50 SEC 0Hz START RBW 1kHz Figure 16. f MCLK = 50 MHz, fOUT = 11.1 MHz. Frequency Word = 38D4FDF4 REV. 0 25MHz STOP ST 50 SEC Figure 17. fMCLK = 50 MHz, fOUT = 13.1 MHz. Frequency Word = 43126E98 10dB/DIV Figure 15. f MCLK = 50 MHz, fOUT = 9.1 MHz. Frequency Word = 2E978D50 VBW 3kHz VBW 3kHz 25MHz STOP ST 50 SEC Figure 18. fMCLK = 50 MHz, fOUT = 16.5 MHz. Frequency Word = 547AE148 –9– AD9835 component of the output signal. Continuous time signals have a phase range of 0 π to 2 π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9835 is implemented with 32 bits. Therefore, in the AD9835, 2 π = 232. Likewise, the ∆Phase term is scaled into this range of numbers 0 < ∆Phase < 232 – 1. Making these substitutions into the equation above CIRCUIT DESCRIPTION The AD9835 provides an exciting new level of integration for the RF/Communications system designer. The AD9835 combines the Numerical Controlled Oscillator (NCO), COS Look-Up Table, Frequency and Phase Modulators, and a Digital-toAnalog Converter on a single integrated circuit. The internal circuitry of the AD9835 consists of three main sections. These are: Numerical Controlled Oscillator (NCO) + Phase Modulator COS Look-Up Table Digital-to-Analog Converter f = ∆Phase × fMCLK/232 where 0 < ∆Phase < 232 The AD9835 is a fully integrated Direct Digital Synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor and eight decoupling capacitors to provide digitally created sine waves up to 25 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques. THEORY OF OPERATION Cos waves are typically thought of in terms of their magnitude form a(t) = cos (ωt). However, these are nonlinear and not easy to generate except through piece-wise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2 πf. MAGNITUDE +1 The input to the phase accumulator (i.e., the phase step) can be selected either from the FREQ0 Register or FREQ1 Register and this is controlled by the FSELECT pin or the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE Registers. The contents of this register are added to the most significant bits of the NCO. The AD9835 has four PHASE registers, the resolution of these registers being 2 π/4096. COS Look-Up Table (LUT) To make the output useful, the signal must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM LUT converts the phase information into amplitude. To do this, the digital phase information is used to address a COS ROM LUT. Although the NCO contains a 32-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 232 entries. It is necessary only to have sufficient phase resolution in the LUTs such that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the look-up table to have two more bits of phase resolution than the 10-bit DAC. 0 –1 PHASE 2π Digital-to-Analog Converter 0 Figure 19. Cos Wave Knowing that the phase of a cos wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. ∆Phase = ωδt Solving for ω ω = ∆Phase/δt = 2 πf Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = δt) f = ∆Phase × fMCLK/2 π The AD9835 includes a high impedance current source 10-bit DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (RSET). The DAC is configured for single-ended operation. The load resistor can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Since full-scale current is controlled by RSET , adjustments to RSET can balance changes made to the load resistor. However, if the DAC full-scale output current is significantly less than 4 mA, the DAC’s linearity may degrade. DSP and MPU Interfacing The AD9835 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits. Numerical Controlled Oscillator and Phase Modulator This consists of two frequency select registers, a phase accumulator and four phase offset registers. The main component of the NCO is a 32-bit phase accumulator which assembles the phase The AD9835 has a serial interface, with 16 bits being loaded during each write cycle. SCLK, SDATA and FSYNC are used to load the word into the AD9835. When FSYNC is taken low, the AD9835 is informed that a word is being written to the device. The first bit is read into the device on the next SCLK falling edge with the remaining bits being read into the device on the subsequent SCLK falling edges. FSYNC frames the 16 bits; therefore, when 16 SCLK falling edges have occurred, –10– REV. 0 AD9835 FSYNC should be taken high again. The SCLK can be continuous or, alternatively, the SCLK can idle high or low between write operations. register (defer register) to the 16-bit data register and the FSELECT/PSEL registers occur following a two-stage pipeline delay which is triggered on the MCLK falling edge. The pipeline delay ensures that the data is valid when the transfer occurs. Similarly, selection of the frequency/phase registers using the FSELECT/PSEL pins is synchronized with the MCLK rising edge when SYNC = 1. When SYNC = 0, the synchronizer is bypassed. When writing to a frequency/phase register, the first four bits identify whether a frequency or phase register is being written to, the next four bits contain the address of the destination register while the 8 LSBs contain the data. Table II lists the addresses for the phase/frequency registers while Table III lists the commands. Within the AD9835, 16-bit transfers are used when loading the destination frequency/phase register. There are two modes for loading a register—direct data transfer and a deferred data transfer. With a deferred data transfer, the 8-bit word is loaded into the defer register (8 LSBs or 8 MSBs). However, this data is not loaded into the 16-bit data register so the destination register is not updated. With a direct data transfer, the 8-bit word is loaded into the appropriate defer register (8 LSBs or 8 MSBs). Immediately following the loading of the defer register, the contents of the complete defer register are loaded into the 16-bit data register and the destination register is loaded on the next MCLK rising edge. When a destination register is addressed, a deferred transfer is needed first, followed by a direct transfer. When all 16 bits of the defer register contain relevant data, the destination register can then be updated using 8-bit loading rather than 16-bit loading, i.e., direct data transfers can be used. For example, after a new 16-bit word has been loaded to a destination register, the defer register will also contain this word. If the next write instruction is to the same destination register, the user can use direct data transfers immediately. When writing to a phase register, the 4 MSBs of the 16-bit word loaded into the data register should be zero (the phase registers are 12 bits wide). To alter the entire contents of a frequency register, four write operations are needed. However, the 16 MSBs of a frequency word are contained in a separate register to the 16 LSBs. Therefore, the 16 MSBs of the frequency word can be altered independent of the 16 LSBs. The phase and frequency registers to be used are selected using the pins FSELECT, PSEL0 and PSEL1 or the corresponding bits can be used. Bit SELSRC determines whether the bits or the pins are used. When SELSRC = 0, the pins are used while the bits are used when SELSRC = 1. When CLR is taken high, SELSRC is set to 0 so that the pins are the default source. Data transfers from the serial (defer) register to the 16-bit data register, and the FSELECT and PSEL registers, occur following the 16th falling SCLK edge. Transfer of the data from the 16-bit data register to the destination register or from the FSELECT/ PSEL register to the respective multiplexer occurs on the next MCLK rising edge. Since the SCLK and the MCLK are asynchronous, an MCLK rising edge may occur while the data bits are in transitional state, which will cause a brief spurious DAC output if the register being written to is generating the DAC output. To avoid such spurious outputs, the AD9835 contains synchronizing circuitry. When the SYNC bit is set to 1, the synchronizer is enabled and data transfers from the serial REV. 0 Selecting the frequency/phase registers using the pins is synchronized with MCLK internally also when SYNC = 1 to ensure that these inputs are valid at the MCLK rising edge. If times t11 and t 11A are met, the inputs will be at steady state at the MCLK rising edge. However, if times t11 and t11A are violated, the internal synchronizing circuitry will delay the instant at which the pins are sampled, ensuring that the inputs are valid at the sampling instant. A latency is associated with each operation. When inputs FSELECT/PSEL change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. When times t11 and t 11A are met, PSEL0, PSEL1 and FSELECT have latencies of six MCLK cycles when SYNC = 0. When SYNC = 1, the latency is increased to 8 MCLK cycles. When times t11 and t11A are not met, the latency can increase by one MCLK cycle. Similarly, there is a latency associated with each write operation. If a selected frequency/phase register is loaded with a new word, there is a delay of 6 to 7 MCLK cycles before the analog output will change (there is an uncertainty of one MCLK cycle regarding the MCLK rising edge at which the data is loaded into the destination register). When SYNC = 1, the latency will be 8 or 9 MCLK cycles. The flowchart in Figure 20 shows the operating routine for the AD9835. When the AD9835 is powered up, the part should be reset. This will reset the phase accumulator to zero so that the analog output is at full scale. To avoid spurious DAC outputs while the AD9835 is being initialized, the RESET bit should be set to 1 until the part is ready to begin generating an output. Taking CLR high will set SYNC and SELSRC to 0 so that the FSELECT/PSEL pins are used to select the frequency/phase registers and the synchronization circuitry is bypassed. A write operation is needed to the SYNC/SELSRC register to enable the synchronization circuitry or to change control to the FSELECT/PSEL bits. RESET does not reset the phase and frequency registers. These registers will contain invalid data and should therefore be set to a known value by the user. The RESET bit is then set to 0 to begin generating an output. A signal will appear at the DAC output 6 MCLK cycles after RESET is set to 0. The analog output is fMCLK /232 × FREG where FREG is the value loaded into the selected frequency register. This signal will be phase shifted by the amount specified in the selected phase register (2 π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register). Control of the frequency/phase registers can be interchanged from the pins to the bits. –11– AD9835 DATA WRITE** FREG<0> = fOUT0/fMCLK*232 FREG<1> = fOUT1/fMCLK*232 PHASEREG <3:0> = DELTA PHASE<0, 1, 2, 3> SELECT DATA SOURCES*** SET FSELECT SET PSEL0, PSEL1 INITIALIZATION* WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1) DAC OUTPUT VOUT = VREFIN*6.25*ROUT /RSET*(1 + COS(2p (FREG*fMCLK*t/232 + PHASEREG/212))) CHANGE PHASE? YES NO NO CHANGE fOUT? YES CHANGE FSELECT NO CHANGE FREG? CHANGE PHASEREG? NO CHANGE PSEL0, PSEL1 YES YES Figure 20. Flowchart for AD9835 Initialization and Operation INITIALIZATION* DATA WRITE** CONTROL REGISTER WRITE SET SLEEP RESET = 1 CLR = 1 DEFERRED TRANSFER WRITE WRITE 8 BITS TO DEFER REGISTER SET SYNC AND/OR SELSRC TO 1 DIRECT TRANSFER WRITE WRITE PRESENT 8 BITS AND 8 BITS IN DEFER REGISTER TO DATA REGISTER YES NO CONTROL REGISTER WRITE SYNC = 1 AND/OR SELSRC = 1 CHANGE 16 BITS YES NO WRITE ANOTHER WORD TO THIS YES CHANGE 8 BITS ONLY REGISTER? NO WRITE A WORD TO ANOTHER REGISTER WRITE INITIAL DATA FREG<0> = fOUT0/fMCLK*232 FREG<1> = fOUT1/fMCLK*232 PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3> Figure 22. Data Writes SET PINS OR FREQUENCY/PHASE REGISTER WRITE SET FSELECT, PSEL0 AND PSEL1 SELECT DATA SOURCES*** CONTROL REGISTER WRITE SLEEP = 0 RESET = 0 CLR = 0 FSELECT/PSEL PINS BEING USED? Figure 21. Initialization YES SELSRC = 0 SET PINS SET FSELECT SET PSEL0 SET PSEL1 NO SELSRC = 1 FREQUENCY/PHASE REGISTER WRITE SET FSELECT SET PSEL0 SET PSEL1 Figure 23. Selecting Data Sources –12– REV. 0 AD9835 APPLICATIONS The AD9835 contains functions that make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9835. In an FSK application, the two frequency registers of the AD9835 are loaded with different values; one frequency will represent the space frequency while the other will represent the mark frequency. The digital data stream is fed to the FSELECT pin, which will cause the AD9835 to modulate the carrier frequency between the two values. The AD9835 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9835. The AD9835 is also suitable for signal generator applications. With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. The printed circuit board that houses the AD9835 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9835 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9835. If the AD9835 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9835. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9835 to avoid noise coupling. The power supply lines to the AD9835 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. REV. 0 Interfacing the AD9835 to Microprocessors The AD9835 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 20 MHz maximum. The serial clock can be continuous or it can idle high or low between write operations. When data/ control information is being written to the AD9835, FSYNC is taken low and held low while the 16 bits of data are being written into the AD9835. The FSYNC signal frames the 16 bits of information being loaded into the AD9835. AD9835-to-ADSP-21xx Interface Grounding and Layout Good decoupling is important. The analog and digital supplies to the AD9835 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND respectively with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9835, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9835 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. Figure 24 shows the serial interface between the AD9835 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT Transmit Alternate Framing Mode (TFSW = 1). The ADSP-21xx is programmed through the SPORT control register and should be configured as follows: Internal clock operation (ISCLK = 1), Active low framing (INVTFS = 1), 16-bit word length (SLEN = 15), Internal frame sync signal (ITFS = 1), Generate a frame sync for each write operation (TFSR = 1). Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD9835 on the SCLK falling edge. ADSP-2101/ ADSP-2103 AD9835 TFS FSYNC DT SDATA SCLK SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. ADSP-2101/ADSP-2103-to-AD9835 Interface AD9835-to-68HC11/68L11 Interface Figure 25 shows the serial interface between the AD9835 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting bit MSTR in the SPCR to 1 and, this provides a serial clock on SCK while the MOSI output drives the serial data line SDATA. Since the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows: the SCK idles high between write operations (CPOL = 0), data is valid on the SCK falling edge (CPHA = 1). When data is being transmitted to the AD9835, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight –13– AD9835 falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data into the AD9835, PC7 is held low after the first eight bits are transferred and a second serial write operation is performed to the AD9835. Only after the second eight bits have been transferred should FSYNC be taken high again. 68HC11/68L11 FSYNC MOSI SDATA AD9835 DSP56002 AD9835 PC7 SCK The frame sync signal is available on pin SC2 but, it needs to be inverted before being applied to the AD9835. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002. SCLK SC2 FSYNC STD SDATA SCK SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 27. AD9835-to-DSP56002 Interface AD9835 Evaluation Board ADDITIONAL PINS OMITTED FOR CLARITY The AD9835 Evaluation Board allows designers to evaluate the high performance AD9835 DDS Modulator with a minimum of effort. Figure 25. 68HC11/68L11-to-AD9835 Interface AD9835-to-80C51/80L51 Interface Figure 26 shows the serial interface between the AD9835 and the 80C51/80L51 microcontroller. The microcontroller is operated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD9835 while RXD drives the serial data line SDATA. The FSYNC signal is again derived from a bit programmable pin on the port (P3.3 being used in the diagram). When data is to be transmitted to the AD9835, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes thus, only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9835, P3.3 is held low after the first eight bits have been transmitted and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/ 80L51 outputs the serial data in a format which has the LSB first. The AD9835 accepts the MSB first (the 4 MSBs being the control information, the next 4 bits being the address while the 8 LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first. 80C51/80L51 AD9835 P3.3 FSYNC RXD SDATA TXD SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 26. 80C51/80L51 to AD9835 Interface AD9835-to-DSP56002 Interface Figure 27 shows the interface between the AD9835 and the DSP56002. The DSP56002 is configured for normal mode asynchronous operation with a Gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0) and the frame sync signal will frame the 16 bits (FSL = 0). To prove that this device will meet the user’s waveform synthesis requirements, the user only requires a 5 V power supply, an IBM-compatible PC and a spectrum analyzer along with the evaluation board. The evaluation setup is shown below. The DDS Evaluation kit includes a populated, tested AD9835 printed circuit board along with the software that controls the AD9835 in a Windows® environment. IBM-COMPATIBLE PC AD9835.EXE PARALLEL PORT CENTRONICS PRINTER CABLE AD9835 EVALUATION BOARD Figure 28. AD9835 Evaluation Board Setup Using the AD9835 Evaluation Board The AD9835 Evaluation kit is a test system designed to simplify the evaluation of the AD9835. Provisions to control the AD9835 from the printer port of an IBM-compatible PC are included along with the necessary software. An application note is also available with the evaluation board which gives information on operating the evaluation board. Prototyping Area An area is available on the evaluation board where the user can add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. XO vs. External Clock The AD9835 can operate with master clocks up to 50 MHz. A 50 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and an external CMOS clock connected to the part, if required. Power Supply Power to the AD9835 Evaluation Board must be provided externally through the pin connections. The power leads should be twisted to reduce ground loops. Windows is a registered trademark of Microsoft Corporation. –14– REV. 0 AD9835 1 2 3 4 5 6 7 DVDD C2 0.1mF 4 DVDD FSYNC SCLK SDATA 10 FSYNC 11 12 AVDD COMP 20 4 16 7 6 14 8 11 9 9 REFIN 2 SCLK LK4 SDATA REFOUT 3 C4 10nF FSYNC FSADJUST 1 R5 3.9kV U2 U1 PSEL1 18 19 20 21 R2 10kV R1 10kV 24 25 26 DVDD C8 10mF C7 0.1mF J2 J3 AVDD C9 0.1mF C10 10mF AD9835 R3 10kV 11 LK1 PSEL0 LK2 FSELECT LK3 22 23 C3 10nF 16 REFIN 1 10 19 13 14 15 AVDD 15 DVDD C6 0.1mF J1 8 9 16 17 AVDD C1 0.1mF SCLK SDATA 12 10 6 PSEL1 IOUT IOUT 14 R6 300V PSEL0 FSELECT MCLK DGND AGND 5 13 DVDD SW 27 28 29 30 31 MCLK 32 33 34 R4 50V DVDD C5 0.1mF DVDD U3 35 36 OUT XTAL1 DGND Figure 29. Evaluation Board Layout Integrated Circuits XTAL1 U1 U2 Capacitors C1, C2 C3, C4 C5, C6, C7, C9 C8, C10 Links OSC XTAL 50 MHz AD9835 (16-Lead TSSOP) 74HCT244 Buffer 0.1 µF Ceramic Chip Capacitor 10 nF Ceramic Capacitor 0.1 µF Ceramic Capacitor 10 µF Tantalum Capacitor Resistors R1–R3 R4 R5 R6 REV. 0 10 kΩ Resistor 50 Ω Resistor 3.9 kΩ Resistor 300 Ω Resistor LK1–LK3 LK4 Three Pin Link Two Pin Link Switch SW End Stackable Switch (SDC Double Throw) Sockets MCLK, PSEL0, PSEL1, FSELECT, IOUT, REFIN Subminiature BNC Connector Connectors J1 J2, J3 –15– 36-Pin Edge Connector PCB Mounting Terminal Block AD9835 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) 9 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 16 C3309–8–7/98 0.201 (5.10) 0.193 (4.90) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 8° 0° 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 0.0256 SEATING (0.65) PLANE BSC 0.0433 (1.10) MAX –16– REV. 0