CMOS Low Power Dual 2:1 Mux/Demux USB 2.0 (480 Mbps)/USB 1.1 (12 Mbps) ADG772 FEATURES ADG772 S1A USB 2.0 (480 Mbps) and USB 1.1 (12 Mbps) signal switching compliant Tiny 10-lead 1.6 mm × 1.3 mm mini LFCSP package and 12-lead 3 mm × 3 mm LFCSP package 2.7 V to 3.6 V single-supply operation Typical power consumption: <0.1 μW RoHS compliant D1 S1B IN1 IN2 S2A D2 APPLICATIONS SWITCHES SHOWN FOR A LOGIC 0 INPUT USB 2.0 signal switching circuits Cellular phones PDAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems 06692-001 S2B Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG772 is a low voltage, CMOS device that contains two independently selectable single-pole, double throw (SPDT) switches. It is designed as a general-purpose switch and can be used for routing both USB 1.1 and USB 2.0 signals. 1. 1.6 mm × 1.3 mm mini LFCSP package. 2. USB 1.1 (12 Mbps) and USB 2.0 (480 Mbps) compliant. 3. Single 2.7 V to 3.6 V operation. This device offers a data rate of 1260 Mbps, making the part suitable for high frequency data switching. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG772 exhibits break-before-make switching action. 4. RoHS compliant. The ADG772 comes in a 12-lead LFCSP, and a 10-lead mini LFCSP. These packages make the ADG772 the ideal solution for space-constrained applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADG772 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications....................................................................................... 1 Truth Table .....................................................................................5 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................6 Product Highlights ........................................................................... 1 Test Circuits........................................................................................9 Revision History ............................................................................... 2 Terminology .................................................................................... 11 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 12 Absolute Maximum Ratings............................................................ 4 Ordering Guide .......................................................................... 12 ESD Caution.................................................................................. 4 REVISION HISTORY 8/07—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADG772 SPECIFICATIONS VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25°C −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 6.7 8.8 On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT (ON)) 0.04 0.2 3.3 3.6 LEAKAGE CURRENTS Source Off Leakage IS (Off ) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tON tOFF Propagation Delay Propagation Delay Skew, tSKEW Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Data Rate CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD ±0.2 ±0.2 nA typ nA typ VDD = 2.7 V, VS = 1.5 V, IS = 10 mA VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 22 VS = VD = 0.6 V or 3.3 V; see Figure 23 V min V max ±0.1 μA typ μA max pF typ VIN = VINL or VINH VIN = VINL or VINH ns typ ns max ns typ ns max ps typ ps typ ns typ ns min pC typ dB typ dB typ RL = 50 Ω, CL = 35 pF VS = 2 V; see Figure 24 RL = 50 Ω, CL = 35 pF VS = 2 V; see Figure 24 RL = 50 Ω, CL = 35 pF RL = 50 Ω, CL = 35 pF RL = 50 Ω, CL = 35 pF VS1 = VS2 = 2 V; see Figure 25 VD = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 30 2 13.5 10 2.9 −80 dB typ 630 1260 2.4 6.9 MHz typ Mbps typ pF typ pF typ 0.006 μA typ μA max 1 1 VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA; see Figure 21 2 0.8 0.005 9 12.5 6 9.5 250 20 5 3.4 0.5 73 −90 Test Conditions/Comments Guaranteed by design, not subject to production test. Rev. 0 | Page 3 of 12 VDD = 3.6 V Digital inputs = 0 V or 3.6 V ADG772 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VDD to GND Analog Inputs 1 , Digital Inputs Peak Current, Pin S1A, Pin S2A, Pin D1, or Pin D2 Continuous Current, Pin S1A, Pin S2A, Pin D1, or Pin D2 Operating Temperature Industrial Range (B version) Storage Temperature Range Junction Temperature 10-Lead Mini LFCSP (4-Layer Board) θJA Thermal Impedance 12-Lead LFCSP (4-Layer Board) θJA Thermal Impedance Pb-Free Temperature, Soldering, IR Reflow Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +4.6 V −0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 131.6°C/W 61°C/W 260(+0/−5)°C 10 sec to 40 sec Overvoltages at the IN1, IN2, S1A, S2A, D1, or D2 pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. 0 | Page 4 of 12 ADG772 9 S2A D1 1 S1B 2 NC 3 8 D2 11 GND 10 S2A ADG772 TOP VIEW (Not to Scale) 9 D2 8 S2B 7 NC 06692-003 VDD 6 IN1 4 7 S2B 006692-002 VDD 6 TOP VIEW (Not to Scale) IN1 4 S1B 3 ADG772 IN2 5 D1 2 PIN 1 INDICATOR IN2 5 1 S1A 10 GND 12 S1A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC = NO CONNECT Figure 3. 12-Lead LFCSP Pin Configuration Figure 2. 10-Lead Mini LFCSP Pin Configuration Table 3. Pin Function Descriptions 10-Lead Mini LFCSP 1 2 3 4 5 6 7 8 9 10 N/A 12-Lead LFCSP 12 1 2 4 5 6 8 9 10 11 3, 7 Mnemonic S1A D1 S1B IN1 IN2 VDD S2B D2 S2A GND NC Description Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Logic Control Input. Controls Switch S1A/S1B—D1. Login Control Input. Controls Switch S2A/S2B—D2. Most Positive Power Supply Potential. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Ground (0 V) Reference. No Connect. TRUTH TABLE Table 4. Logic (IN1/IN2) 0 1 Switch A (S1A or S2A) Off On Rev. 0 | Page 5 of 12 Switch B (S1B or S2B) On Off ADG772 TYPICAL PERFORMANCE CHARACTERISTICS 7 7 TA = 25°C VDD = 3.0V 6 VDD = 3.6V ON RESISTANCE (Ω) 4 3 2 0.5 1.0 1.5 2.0 2.5 VD, VS (V) 3.0 3.5 4.0 TA = –40°C 3 2 0 06692-024 0 Figure 4. On Resistance vs. VD (VS) VDD = 3.0 V to 3.6 V 0 0.5 1.0 1.5 2.0 VD, VS (V) 2.5 3.0 3.5 Figure 7. On Resistance vs. VD (VS) for Different Temperature, VDD = 3.3 V 10 8 TA = 25°C 9 VDD = 2.7V VDD = 2.3V 8 VDD = 2.5V 7 TA = +85°C 7 TA = +25°C 6 VDD = 2.7V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 4 1 1 0 TA = +25°C 5 06692-027 ON RESISTANCE (Ω) VDD = 3.3V 5 VDD = 3.3V TA = +85°C 6 6 5 4 3 5 4 TA = –40°C 3 2 2 0 0.5 1.0 1.5 2.0 VD, VS (V) 2.5 3.0 3.5 06692-023 0 0 0 1.0 1.5 VD, VS (V) 2.0 2.5 3.0 Figure 8. On Resistance vs. VD (VS) for Different Temperature, VDD = 2.7 V Figure 5. On Resistance vs. VD (VS) VDD = 2.5 V ± 0.2 V 25 30 VDD = 1.8V TA = 25°C 25 ON RESISTANCE (Ω) 20 VDD = 1.8V 15 TA = –40°C 20 VDD = 1.65V VDD = 1.95V 10 TA = +25°C TA = +85°C 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VD, VS (V) 1.4 1.6 1.8 Figure 6. On Resistance vs. VD (VS) VDD = 1.8 V ± 0.15 V 2.0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VD, VS (V) 1.4 1.6 1.8 2.0 06692-025 5 06692-022 ON RESISTANCE (Ω) 0.5 06692-026 1 1 Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 1.8 V Rev. 0 | Page 6 of 12 ADG772 2.5 2.0 VDD = 3.3V TA = 25°C 2.0 1.5 ID,S (ON)++ ID,S (OFF)+ 1.0 VCC = 2.5V 1.0 QINJ (pC) CURRENT (nA) VCC = 3.3V 1.5 0.5 0.5 VCC = 1.8V 0 0 –0.5 –0.5 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 –1 06692-028 ID,S (OFF) + –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VS (V) Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V 06692-018 ID,S (ON) Figure 13. Charge Injection vs. Source Voltage 12 0.9 VDD = 2.5V 0.8 10 0.7 tOFF (1.8V) 8 0.5 TIME (ns) ID,S (ON) 0.4 0.3 ID,S (OFF)+ tON (2.7V) tOFF (2.7V) 6 tOFF (3.3V) 4 0.2 0.1 2 0 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 06692-029 ID,S (OFF) + 0 –40 0 0.7 –2 0.6 –4 INSERTION LOSS (dB) 0.8 ID,S (ON)++ 0.5 0.4 0.3 –20 0 20 40 TEMPERATURE (°C) 60 80 85 Figure 14. tON/tOFF Times vs. Temperature Figure 11. Leakage Current vs. Temperature, VDD = 2.5 V ID,S (ON) 0.2 TA = 25°C VDD = 3.3V, 2.5V, 1.8V –6 –8 –10 –12 –14 0.1 ID,S (OFF)+ 0 –16 –0.1 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 –18 1 10 100 FREQUENCY (MHz) Figure 15. Bandwidth Figure 12. Leakage Current vs. Temperature, VDD = 1.8 V Rev. 0 | Page 7 of 12 1000 06692-014 ID,S (OFF) + 06692-030 CURRENT (nA) tON (3.3V) 06692-019 CURRENT (nA) 0.6 –0.1 tON (1.8V) ID,S (ON)++ ADG772 0 –10 TA = 25°C VDD = 3.3V, 2.5V, 1.8V ATTENUATION (dB) –20 –30 –40 –50 –60 –70 2 –80 1 10 100 FREQUENCY (MHz) 1000 Figure 19. USB 1.1 Eye Diagram Figure 16. Off Isolation vs. Frequency 0 –10 20.0ns/DIV 2.5GS/s ET 400ps/pt A C1 2.64V C2 835mV Ω 06692-021 –100 06692-016 –90 +500mV TA = 25°C VDD = 3.3V, 2.5V, 1.8V 1 –20 CROSSTALK (dB) –30 +100mV/ DIV –40 2 S1A-S1B –50 –60 S1A-S2A –70 –80 1 10 100 FREQUENCY (MHz) 1000 3 –500mV 37.37ns Figure 17. Crosstalk vs. Frequency 0 –20 Figure 20. USB 2.0 Eye Diagram TA = 25°C VDD = 3.3V –60 –80 –100 –120 100 1k 10k 100k 1M FREQUENCY (MHz) 10M 100M 1G 06692-017 PSRR (dB) –40 –140 10 250ps/DIV Figure 18. PSRR vs. Frequency Rev. 0 | Page 8 of 12 39.87ns 06692-020 –100 06692-015 –90 ADG772 TEST CIRCUITS A D ID (OFF) S NC A D ID (ON) A VD VS S VD 06692-005 V1 D RON = V1/IDS 06692-004 Figure 23. On Leakage Figure 22. Off Leakage Figure 21. On Resistance VDD 0.1µF VDD S1B S1A VS VOUT D RL 50Ω IN 50% VIN CL 35pF 50% 90% VOUT 90% tON tOFF 06692-007 GND Figure 24. Switching Times, tON, tOFF 0.1µF VDD VDD S1B S1A VS VIN D VOUT RL 50Ω IN 50% 0V VOUT 80% CL 35pF 50% 80% tBBM tBBM 06692-008 GND Figure 25. Break-Before-Make Time Delay, tBBM VDD SWITCH ON D VS SWITCH OFF VIN S1B NC S1A VOUT 1nF IN VOUT ΔVOUT GND QINJ = CL × ΔVOUT Figure 26. Charge Injection Rev. 0 | Page 9 of 12 06692-009 VS S 06692-006 IS (OFF) IDS ADG772 VDD NETWORK ANALYZER S1B S1A 50Ω 50Ω RL 50Ω 50Ω S1A VS D VOUT RL 50Ω GND 06692-010 GND OFF ISOLATION = 20 log S1B VS D NETWORK ANALYZER VDD VOUT VS INSERTION LOSS = 20 log VOUT 06692-012 VDD NC VDD 0.1µF 0.1µF VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 29. Channel-to-Channel Crosstalk (S1A–S1B) Figure 27. Off Isolation VDD 0.1µF NETWORK ANALYZER 50Ω D2 S2A NETWORK ANALYZER NC VOUT S2B VS D1 S1A S1B CHANNEL-TO-CHANNEL CROSSTALK = 20 log NC RL 50Ω D S1B 50Ω 50Ω VS VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 28. Channel-to-Channel Crosstalk (S1A–S2A) VOUT Figure 30. Bandwidth Rev. 0 | Page 10 of 12 RL 50Ω GND 06692-013 50Ω VDD S1A VS 06692-011 VOUT ADG772 TERMINOLOGY IDD Positive supply current. CIN Digital input capacitance. VD (VS) Analog voltage on Terminal D and Terminal S. tON Delay time between the 50% and 90% points of the digital input and switch on condition. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (On) The difference between the maximum and minimum values of on resistance as measured on the switch. ΔRON On resistance match between any two channels. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID, IS (On) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. Measured with reference to ground. CD (Off) Off switch drain capacitance. Measured with reference to ground. CD, CS (On) On switch capacitance. Measured with reference to ground. tOFF Delay time between the 50% and 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Off Isolation Measure of unwanted signal coupling through an off switch. Crosstalk Measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth Frequency at which the output is attenuated by 3 dB. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N Ratio of the harmonics amplitude plus noise of a signal to the fundamental. TSKEW The measure of the variation in propagation delay between each channel. Rev. 0 | Page 11 of 12 ADG772 OUTLINE DIMENSIONS 0.20 DIA TYP 0.55 0.40 0.30 1.30 PIN 1 IDENTIFIER 9 1 1.60 0.40 BSC 4 BOTTOM VIEW TOP VIEW 0.60 0.55 0.50 6 0.35 0.30 0.25 0.05 MAX 0.02 NOM 033007-A 0.20 BSC SEATING PLANE Figure 31. 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) 1.30 mm × 1.60 mm Body, Ultra Thin Quad (CP-10-10) Dimensions shown in millimeters 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR 9 2.75 BSC SQ TOP VIEW 0.75 0.55 0.35 10 11 12 8 12° MAX 1.00 0.85 0.80 *1.45 1.30 SQ 1.15 2 7 EXPOSED PAD (BOTTOM VIEW) 1 PIN 1 INDICATOR 6 5 4 3 0.25 MIN 0.50 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.20 REF 0.30 0.23 0.18 COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 32. 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 3 mm × 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADG772BCPZ-1REEL1 ADG772BCPZ-REEL1 ADG772BCPZ-REEL71 EVAL-ADG772EBZ1 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) 10-Lead Mini Lead Frame Chip Scale Package (LFCSP_UQ) Evaluation Board Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06692-0-8/07(0) Rev. 0 | Page 12 of 12 Package Option CP-12-1 CP-10-10 CP-10-10 Branding S2P B B