ATMEL AT49BV161-70CI 16-megabit (1m x 16/2m x 8) 3-volt only flash memory Datasheet

Features
• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)
• Access Time – 70 ns
• Sector Erase Architecture
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– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 300 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Byte/Word by Suspending Programming of Any Other
Byte/Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Description
The AT49BV/LV16X(T) is a 3.0-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for
erase operations. The device is offered in a 48-lead TSOP, 45-ball and 48-ball CBGA
packages. The device has CE and OE control signals to avoid any bus contention.
This device can be read or reprogrammed using a single 2.65V power supply, making
it ideally suited for in-system programming.
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV160
AT49LV160
AT49BV160T
AT49BV161
AT49LV161
AT49BV161T
AT49LV161T
Pin Configurations
Pin Name
Function
A0 - A19
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
READY/BUSY Output
VPP
Write Protection and Power Supply for Accelerated Program/Erase
Operations
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC
No Connect
VCCQ
Output Power Supply
Rev. 1427L–FLASH–02/03
1
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CBGA Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
A19
A7
A4
A17
A5
A2
A6
A3
A1
I/O2
I/O8
CE
A0
I/O12
I/O3
I/O9
I/O0
GND
I/O4
VCC
I/O10
I/O1
OE
2
3
4
5
A13
A11
A8
VPP
A14
A10
WE
RST
A15
A12
A9
A16
I/O14
I/O5
I/O11
VCCQ I/O15
I/O6
I/O7
I/O13
A
B
A18
C
D
AT49BV/LV160(T)
E
F
GND
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
VPP
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
6
1
CBGA Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
1
2
A3
3
4
5
6
A7 RDY/BUSY WE
A9
A13
A4
A17
NC
RESET
A8
A12
A2
A6
A18
VPP
A10
A14
A1
A5
NC
A19
A11
A15
A0
I/O0
I/O2
I/O5
I/O7
A16
CE
I/O8
I/O10
I/O12
I/O14
BYTE
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
VSS
I/O1
I/O3
I/O4
I/O6
VSS
A
B
C
D
AT49BV/LV161(T)
E
F
G
H
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector. (See “Sector Lockdown” section.)
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the Erase or Program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the
toggle bit.
The VPP pin provides data protection and faster programming. When the VPP input is below
0.8V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal
program and erase operations can be performed. With VPP at 5.0V or 12.0V, the program and
erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering
down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing
it back to VCC. Erase, Erase Suspend/Resume, and Program Suspend/Resume commands
will not work while in this mode; if entered they will result in data being programmed into the
device. It is not recommended that the six-byte code reside in the software of the final product
but only exist in external programming code.
When using the AT49BV/LV160(T) pinout configuration, the device always operates in the
word mode. In the AT49BV/LV161(T) configuration, the BYTE pin controls whether the device
data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the
device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tristated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
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1427L–FLASH–02/03
Block Diagram
I/O0 - I/O15/A-1
INPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
A0 - A19
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE
WE
OE
RESET
BYTE
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
Y-DECODER
Y-GATING
RDY/BUSY
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
4
MAIN
MEMORY
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
Device
Operation
READ: The AT49BV/LV16X(T) is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses.
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1427L–FLASH–02/03
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the AT49BV/LV16X(T) is designed so that the device can be programmed or erased from the VCC power supply or from the VPP input pin. When VPP is greater
than 1.65V and less than or equal to the VCC pin, the device selects the VCC supply for programming and erase operations. When the VPP pin is greater than the VCC supply, the device
will select the VPP input as the power supply for programming and erase operations. The
device will allow for some variations between the VPP input and the VCC power supply in its
selection of VCC or VPP for program or erase operations. If the VPP pin is within 0.3V of VCC for
2.65V < VCC < 3.6V, then the program or erase operations will use VCC and disregard the VPP
input signal. When the VPP signal is used for program and erase operations, the VPP must be
in the 5V ± 0.5V or 12V ± 0.5V range to ensure proper operation. The Vpp pin cannot be left
floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV/LV16X(T) contains a programmable configuration register.
The configuration register allows the user to specify the status bit operation. The configuration
register can be set to one of two different values, “00” or “01”. If the configuration register is set
to “00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 13, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The AT49BV/LV16X(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last byte/word loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. During a chip or sector erase operation, an attempt to read the device
will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read
from the device. Data Polling may begin at any time during the program cycle. Please see
“Status Bit Table” on page 12 for more details.
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AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 1 and 2 on page 10.
TOGGLE BIT: In addition to Data Polling, the AT49BV/LV16X(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on page 12 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 3 and 4 on page 11.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a byte/word program operation has been successfully performed. The device may also output a “1” on I/O5 if the system
tries to program a “1” to a location that was previously programmed to a “0”. Only an erase
operation can change a “0” back to a “1”. If a program (Sector Erase) command is issued to a
protected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. The
erase/program status bit is a “0” while the erase or program operation is still in progress.
Please see “Status Bit Table” on page 12 for more details.
VPP STATUS BIT: The AT49BV/LV16X(T) provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the
voltage on the VPP pin is not high enough to perform the desired operation successfully, the
I/O3 status bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must
write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status
bit will output a “0”. Please see “Status Bit Table” on page 12 for more details.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write-protected
region is optional to the user.
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification
mode (see “Software Product Identification Entry/Exit” sections on page 24), a read from
address location 00002H within a sector will show if programming the sector is locked down. If
the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program
lockdown feature has been enabled and the sector cannot be programmed. The software
product identification exit code should be used to return to standard operation.
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1427L–FLASH–02/03
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase or chip erase operation and then program or read data from a different
sector within the memory. After the Erase Suspend command is given, the device requires a
maximum time of 15 µs to suspend the erase operation. After the erase operation has been
suspended, the system can then read data or program data to any other sector within the
device. An address is not required during the Erase Suspend command. During a sector erase
suspend, another sector cannot be erased. To resume the sector erase operation, the system
must write the Erase Resume command. The Erase Resume command is a one-bus cycle
command. The device also supports an erase suspend during a complete chip erase. While
the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the
same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different byte/word
within the memory. After the Program Suspend command is given, the device requires a maximum of 15 µs to suspend the programming operation. After the programming operation has
been suspended, the system can then read data from any other byte/word within the device.
An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend
and resume are one-bus cycle commands. The command sequence for the erase suspend
and program suspend are the same, and the command sequence for the erase resume and
program resume are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” on page 17 (for hardware operation) or “Software Product
Identification Entry/Exit” on page 24. The manufacturer and device codes are the same for
both modes.
128-BIT PROTECTION REGISTER: The AT49BV/LV16X(T) contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the “Command Definition in Hex”
table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command
must be used as shown in the “Command Definition in Hex” table on page 13. Data bit D1
must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are
don’t cares. To determine whether block B is locked out, the Product ID Entry command is
given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked.
If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register
Addressing Table” on page 14 for the address locations in the protection register. To read the
protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is
protected or not, or reading the protection register, the Product ID Exit command must be
given prior to performing any other operation.
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AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
RDY/BUSY: For the AT49BV/LV161(T), an open-drain READY/BUSY output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line. Please see “Status Bit Table” on page 12 for more details.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49BV/LV16X(T) in the following ways: (a) VCC sense: if VCC is
below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will
not initiate a program cycle. (e) Program inhibit: VPP is less than VILPP. (f) VPP power-on delay:
once VPP has reached 1.65V, program and erase operations can occur after 100 ns.
INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the AT49BV/LV160(T), output high levels (VOH) are equal to VCCQ 0.2V (not VCC). For 2.65V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V ± 10%, while VCC must be regulated to 2.65V - 3.0V
(for minimum power).
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1427L–FLASH–02/03
Figure 1. Data Polling Algorithm
(Configuration Register = 00)
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
I/O7 = 1?
YES
I/O7 = Data?
YES
NO
I/O3, I/O5 = 1?
NO
NO
I/O3, I/O5 = 1?
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Notes:
10
Note:
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Program/Erase
Operation
Successful,
Device in
Read Mode
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
Figure 3. Toggle Bit Algorithm
(Configuration Register = 00)
Figure 4. Toggle Bit Algorithm
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
NO
Toggle Bit =
Toggle?
YES
NO
YES
NO
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Note:
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
11
1427L–FLASH–02/03
Status Bit Table
Status Bit
I/O7
I/O7
I/O6
I/O5(1)
I/O3(2)
I/O2
RDY/BUSY
00
01
00/01
00/01
00/01
00/01
00/01
I/O7
0
TOGGLE
0
0
1
0
Erasing
0
0
TOGGLE
0
0
TOGGLE
0
Erase Suspended & Read
Erasing Sector
1
1
1
0
0
TOGGLE
1
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
Erase Suspended &
Program Non-erasing Sector
I/O7
0
TOGGLE
0
0
TOGGLE
0
Configuration Register:
Programming
Notes:
12
1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
Command Definition in Hex(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AAA(2)
55
555
80
555
AA
AAA
55
555
10
Sector Erase
6
555
AA
AAA
55
555
80
555
AA
Byte/Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Enter Single Pulse
Program Mode
6
555
AA
AAA
55
555
80
555
Single Pulse
Byte/Word Program
1
Addr
DIN
Sector Lockdown
6
555
AA
AAA
55
555
80
Erase/Program
Suspend
1
XXX
B0
Erase/Program
Resume
1
XXX
30
Product ID Entry
3
555
AA
AAA
55
555
90
(5)
Product ID Exit
3
555
AA
AAA
55
555
F0
Product ID Exit(5)
1
XXX
F0
Program Protection
Register
4
555
AA
AAA
55
555
Lock Protection
Register - Block B
4
555
AA
AAA
55
Status of Block B
Protection
4
555
AA
AAA
Set Configuration
Register
4
555
AA
AAA
Notes:
6th Bus
Cycle
(3)(4)
SA
30
AAA
55
AA
AAA
55
555
A0
555
AA
AAA
55
SA(3)(4)
60
C0
Addr
DIN
555
C0
080
X0
55
555
90
80
DOUT(6)
55
555
D0
XXX
00/01(7)
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’t Care
in the word mode. Address A19 through A11 and A-1 are Don’t Care in the byte mode.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 15 and
16 for details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE and VPP
with Respect to Ground ...................................-0.6V to +13.0V
13
1427L–FLASH–02/03
Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
Note:
14
User
B
1
0
0
0
1
0
0
0
1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
AT49BV/LV160/161 – Sector Address Table
Size (Bytes/Words)
x8
Address Range (A19 - A-1)
x16
Address Range (A19 - A0)
SA0
8K/4K
000000 - 001FFF
00000 - 00FFF
SA1
8K/4K
002000 - 003FFF
01000 - 01FFF
SA2
8K/4K
004000 - 005FFF
02000 - 02FFF
SA3
8K/4K
006000 - 007FFF
03000 - 03FFF
SA4
8K/4K
008000 - 009FFF
04000 - 04FFF
SA5
8K/4K
00A000 - 00BFFF
05000 - 05FFF
SA6
8K/4K
00C000 - 00DFFF
06000 - 06FFF
SA7
8K/4K
00E000 - 00FFFF
07000 - 07FFF
SA8
64K/32K
010000 - 01FFFF
08000 - 0FFFF
SA9
64K/32K
020000 - 02FFFF
10000 - 17FFF
SA10
64K/32K
030000 - 03FFFF
18000 - 1FFFF
SA11
64K/32K
040000 - 04FFFF
20000 - 27FFF
SA12
64K/32K
050000 - 05FFFF
28000 - 2FFFF
SA13
64K/32K
060000 - 06FFFF
30000 - 37FFF
SA14
64K/32K
070000 - 07FFFF
38000 - 3FFFF
SA15
64K/32K
080000 - 08FFFF
40000 - 47FFF
SA16
64K/32K
090000 - 09FFFF
48000 - 4FFFF
SA17
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
SA18
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
SA19
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
SA20
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
SA21
64K/32K
0E0000 - 0EFFFF
70000 - 77FFF
SA22
64K/32K
0F0000 - 0FFFFF
78000 - 7FFFF
SA23
64K/32K
100000 - 10FFFF
80000 - 87FFF
SA24
64K/32K
110000 - 11FFFF
88000 - 8FFFF
SA25
64K/32K
120000 - 12FFFF
90000 - 97FFF
SA26
64K/32K
130000 - 13FFFF
98000 - 9FFFF
SA27
64K/32K
140000 - 14FFFF
A0000 - A7FFF
SA28
64K/32K
150000 - 15FFFF
A8000 - AFFFF
SA29
64K/32K
160000 - 16FFFF
B0000 - B7FFF
SA30
64K/32K
170000 - 17FFFF
B8000 - BFFFF
SA31
64K/32K
180000 - 18FFFF
C0000 - C7FFF
SA32
64K/32K
190000 - 19FFFF
C8000 - CFFFF
SA33
64K/32K
1A0000 - 1AFFFF
D0000 - D7FFF
SA34
64K/32K
1B0000 - 1BFFFF
D8000 - DFFFF
SA35
64K/32K
1C0000 - 1CFFFF
E0000 - E7FFF
SA36
64K/32K
1D0000 - 1DFFFF
E8000 - EFFFF
SA37
64K/32K
1E0000 - 1EFFFF
F0000 - F7FFF
SA38
64K/32K
1F0000 - 1FFFFF
F8000 - FFFFF
Sector
15
1427L–FLASH–02/03
AT49BV/LV160T/161T – Sector Address Table
Size (Bytes/Words)
x8
Address Range (A19 - A-1)
x16
Address Range (A19 - A0)
SA0
64K/32K
000000 - 00FFFF
00000 - 07FFF
SA1
64K/32K
010000 - 01FFFF
08000 - 0FFFF
SA2
64K/32K
020000 - 02FFFF
10000 - 17FFF
SA3
64K/32K
030000 - 03FFFF
18000 - 1FFFF
SA4
64K/32K
040000 - 04FFFF
20000 - 27FFF
SA5
64K/32K
050000 - 05FFFF
28000 - 2FFFF
SA6
64K/32K
060000 - 06FFFF
30000 - 37FFF
SA7
64K/32K
070000 - 07FFFF
38000 - 3FFFF
SA8
64K/32K
080000 - 08FFFF
40000 - 47FFF
SA9
64K/32K
090000 - 09FFFF
48000 - 4FFFF
SA10
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
SA11
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
SA12
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
SA13
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
SA14
64K/32K
0E0000 - 0EFFFF
70000 - 77FFF
SA15
64K/32K
0F0000 - 0FFFFF
78000 - 7FFFF
SA16
64K/32K
100000 - 10FFFF
80000 - 87FFF
SA17
64K/32K
110000 - 11FFFF
88000 - 8FFFF
SA18
64K/32K
120000 - 12FFFF
90000 - 97FFF
SA19
64K/32K
130000 - 13FFFF
98000 - 9FFFF
SA20
64K/32K
140000 - 14FFFF
A0000 - A7FFF
SA21
64K/32K
150000 - 15FFFF
A8000 - AFFFF
SA22
64K/32K
160000 - 16FFFF
B0000 - B7FFF
SA23
64K/32K
170000 - 17FFFF
B8000 - BFFFF
SA24
64K/32K
180000 - 18FFFF
C0000 - C7FFF
SA25
64K/32K
190000 - 19FFFF
C8000 - CFFFF
SA26
64K/32K
1A0000 - 1AFFFF
D0000 - D7FFF
SA27
64K/32K
1B0000 - 1BFFFF
D8000 - DFFFF
SA28
64K/32K
1C0000 - 1CFFFF
E0000 - E7FFF
SA29
64K/32K
1D0000 - 1DFFFF
E8000 - EFFFF
SA30
64K/32K
1E0000 - 1EFFFF
F0000 - F7FFF
SA31
8K/4K
1F0000 - 1F1FFF
F8000 - F8FFF
SA32
8K/4K
1F2000 - 1F3FFF
F9000 - F9FFF
SA33
8K/4K
1F4000 - 1F5FFF
FA000 - FAFFF
SA34
8K/4K
1F6000 - 1F7FFF
FB000 - FBFFF
SA35
8K/4K
1F8000 - 1F9FFF
FC000 - FCFFF
SA36
8K/4K
1FA000 - 1FBFFF
FD000 - FDFFF
SA37
8K/4K
1FC000 - 1FDFFF
FE000 - FEFFF
SA38
8K/4K
1FE000 - 1FFFFF
FF000 - FFFFF
Sector
16
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
DC and AC Operating Range
Operating Temperature (Case)
Ind.
VCC Power Supply
AT49BV/LV16X(T)-70
AT49BV/LV16X(T)-90
-40°C - 85°C
-40°C - 85°C
2.65V to 3.3V/3.0V to 3.6V
2.65V to 3.3V/3.0V to 3.6V
Operating Modes
Mode
CE
OE
WE
RESET
VPP
Ai
Read
VIL
VIL
VIH
VIH
X
Ai
DOUT
Program/Erase(2)
VIL
VIH
VIL
VIH
VIHPP(6)
Ai
DIN
Standby/Program Inhibit
VIH
X(1)
X
VIH
X
X
High-Z
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
VIH
VILPP(7)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
VIL
VIL
VIH
VIH
Program Inhibit
I/O
High-Z
X
High-Z
Product Identification
Hardware
Software(5)
Notes:
VIH
A1 - A19 = VIL, A9 = VH(3), A0 = VIL
Manufacturer Code(4)
A1 - A19 = VIL, A9 = VH(3), A0 = VIH
Device Code(4)
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A19 = VIL
Device Code(4)
1.
2.
3.
4.
X can be VIL or VIH.
Refer to AC programming waveforms on page 23.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV/LV16X; 00C0H (x16)-AT49BV/LV16X;
C2H (x8)-AT49BV/LV16XT; 00C2H (x16)-AT49BV/LV16XT.
5. See details under “Software Product Identification Entry/Exit” on page 24.
6. VIHPP (min) = 1.65V; VIHPP (max) = 3.6V. For faster erase/program operations, VPP can be set to 5.0V ± 0.5V or 12V ± 0.5V.
7. VILPP (max) = 0.8V.
17
1427L–FLASH–02/03
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
10
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ISB3
VCC Standby Current TTL
CE = 2.0V to VCC, VCC = 2.85V
10
µA
ICC (1)(2)
VCC Active Read Current
f = 5 MHz; IOUT = 0 mA, 3.3V≤ VCC
30
mA
ICC1
VCC Programming Current (VPP = VCC)
45
mA
µA
VPP Input Load Current
VPP = 0V, VCC = 3.0V
10
IPP1
VPP = VCC = 3.0V
10
µA
ICC2
VCC Programming Current (VPP = 5.0V ± 0.5V)
40
mA
IPP2
VPP Programming Current (VPP = 5.0V ± 0.5V)
5
mA
ICC3
VCC Programming Current (VPP = 12.0V ± 0.5V)
40
mA
IPP3
VPP Programming Current (VPP = 12.0V ± 0.5V)
6
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL1
Output Low Voltage
IOL = 2.1 mA
0.45
V
VOL2
Output Low Voltage
IOL = 1.0 mA
0.20
V
VOH1
Output High Voltage
Min
2.0
IOH = -400 µA
VCCQ < 2.6V
IOH = -400 µA
VCCQ ≥ 2.6V
IOH = -400 µA
VOH2
Output High Voltage
Notes:
18
2.4 [AT49BV/LV160(T)]
2.4 [AT49BV/LV161(T)]
IOH = -100 µA
VCCQ < 2.6V
IOH = -100 µA
VCCQ ≥ 2.6V
IOH = -100 µA
VCCQ - 0.2
[AT49BV/LV160(T)]
VCCQ - 0.1
[AT49BV/LV160(T)]
2.5 [AT49BV/LV160(T)]
2.5 [AT49BV/LV161(T)]
V
V
V
V
V
V
V
1. In the erase mode, ICC is 50 mA.
2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
.
AC Read Characteristics
AT49BV/LV16X(T)-70
Symbol
Parameter
tRC
Read Cycle Time
tACC
Min
Max
AT49BV/LV16X(T)-90
Min
Max
Units
70
90
ns
Address to Output Delay
70
90
ns
tCE(1)
CE to Output Delay
70
90
ns
tOE(2)
OE to Output Delay
0
35
0
40
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
ns
tOH
Output Hold from OE, CE or Address, whichever occurred
first
0
tRO
RESET to Output Delay
0
100
ns
100
ns
AC Read Waveforms(1)(2)(3)(4)
tRC
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
OUTPUT
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
19
1427L–FLASH–02/03
Input Test Waveforms and Measurement Level
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
20
1. This parameter is characterized and is not 100% tested
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
.
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
0
ns
tAH
Address Hold Time
40
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
40
ns
tDS
Data Setup Time
30
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
30
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
21
1427L–FLASH–02/03
Program Cycle Characteristics
Symbol
Parameter
Min
tBP
Byte/Word Programming Time (VIHPP < VPP < 4.5V)
Typ
Max
Units
20
200
µs
10
100
tBPVPP
Byte/Word Programming Time (VPP > 4.5V)
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
40
ns
tDS
Data Setup Time
30
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
40
ns
tWPH
Write Pulse Width High
30
ns
tWC
Write Cycle Time
70
ns
µs
tRP
Reset Pulse Width
500
ns
tRH
Reset High Time before Read
50
ns
tEC
Chip Erase Cycle Time (VPP < 4.5V)
12
seconds
tECVPP
Chip Erase Cycle Time (VPP > 4.5V)
6
seconds
tSEC
Sector Erase Cycle Time
400
ms
tEPS
Erase or Program Suspend Time
15
µs
300
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tBP
tWPH
WE
tAS
tAH
A0 -A19
tDH
555
555
AAA
tWC
555
ADDRESS
tDS
DATA
55
AA
INPUT
DATA
A0
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP
tWPH
WE
tAS
A0-A19
tAH
555
Notes:
22
555
555
AAA
tWC
DATA
tDH
Note 2
AAA
tEC
tDS
AA
55
80
AA
55
Note 3
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
tWR
Notes:
Typ
OE to Output Delay
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 19.
Units
ns
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 19.
Typ
Max
Units
ns
50
ns
0
ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
23
1427L–FLASH–02/03
Software Product Identification
Entry(1)
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA 90
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS AAA
Software Product Identification
Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 60
TO
SECTOR ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 555
PAUSE 200 µs(2)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A19
(Don’t Care).
2. Sector Lockdown feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
2.
3.
4.
5.
6.
24
Address Format: A11 - A0 (Hex), A-1, and A11 - A19
(Don’t Care).
A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH. Additional Device Code
is read for address 0003H
The device does not remain in identification mode if powered down.
The device returns to standard operation mode.
Manufacturer Code: 1FH(x8); 001FH(x16)
Device Code: C0H (x8) - AT49BV/LV16X;
00C0H (x16) - AT49BV/LV16X;
C2H (x8) - AT49BV/LV16XT;
00C2H (x16) - AT49BV/LV16XT.
Additional Device Code: 08H (x8) - AT49BV/LV16X(T)
0008H (x16) - AT49BV/LV16X(T)
Either one of the Product ID Exit commands can be used.
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
AT49BV160(T)/161(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.01
AT49BV160-70CI
AT49BV160-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
25
0.01
AT49BV160-90CI
AT49BV160-90TI
45C1
48T
Industrial
(-40° to 85°C)
70
25
0.01
AT49BV160T-70CI
AT49BV160T-70TI
45C1
48T
Industrial
(-40° to 85°C)
90
25
0.01
AT49BV160T-90CI
AT49BV160T-90TI
45C1
48T
Industrial
(-40° to 85°C)
70
25
0.01
AT49BV161-70CI
AT49BV161-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
25
0.01
AT49BV161-90CI
AT49BV161-90TI
48C5
48T
Industrial
(-40° to 85°C)
70
25
0.01
AT49BV161T-70CI
AT49BV161T-70TI
48C5
48T
Industrial
(-40° to 85°C)
90
25
0.01
AT49BV161T-90CI
AT49BV161T-90TI
48C5
48T
Industrial
(-40° to 85°C)
AT49LV160(T)/161(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
25
0.01
AT49LV160-90TI
48T
Industrial
(-40° to 85°C)
70
25
0.01
AT49LV161-70CI
AT49LV161-70TI
48C5
48T
Industrial
(-40° to 85°C)
70
25
0.01
AT49LV161T-70CI
AT49LV161T-70TI
48C5
48T
Industrial
(-40° to 85°C)
Package Type
45C1
45-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48C5
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48T
48-lead, Plastic Thin Small Outline Package (TSOP)
25
1427L–FLASH–02/03
Packaging Information
45C1 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.
6.60 (0.260)
6.40 (0.252)
A1 ID
7.60 (0.299)
7.40 (0.291)
0.15 (0.006)MIN
1.20 (0.047) MAX
5.25 (0.207)
0.625 (0.025) REF
8
7
6
5
4
3
2
1
1.875(0.074) REF
A
B
C
3.75 (0.148)
D
0.75 (0.0295) BSC
NON-ACCUMULATIVE
E
F
0.30 (0.014)
DIA BALL TYP
0.75 (0.0295) BSC
NON-ACCUMULATIVE
4/11/01
R
26
2325 Orchard Parkway
San Jose, CA 95131
TITLE
45C1, 45-ball (8 x 6 Array), 0.75 mm Pitch, 6.5 x 7.5 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
45C1
REV.
A
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
AT49BV/LV160(T)/161(T)
48C5 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: millimeters.
6.10 (0.240)
5.90 (0.232)
A1 ID
8.10 (0.319)
7.90 (0.311)
0.25 (0.010)MIN
1.20 (0.047) MAX
TOP VIEW
SIDE VIEW
1.00(0.039) REF
4.00(0.157)
6
5
4
3
2
1
1.20 (0.047) REF
A
B
C
0.80 (0.0315) BSC
NON-ACCUMULATIVE
D
5.60 (0.220)
E
F
G
H
0.40 (0.016)
DIA BALL TYP
0.80 (0.0315) BSC
NON-ACCUMULATIVE
BOTTOM VIEW
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C5
REV.
A
27
1427L–FLASH–02/03
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
11.90
12.00
12.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
48T
B
AT49BV/LV160(T)/161(T)
1427L–FLASH–02/03
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© Atmel Corporation 2003.
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1427L–FLASH–02/03
/xM