PRELIMINARY DATA SHEET 512M bits DDR2 SDRAM EDE5108AHBG (64M words × 8 bits) EDE5116AHBG (32M words × 16 bits) Features • Density: 512M bits • Organization 16M words × 8 bits × 4 banks (EDE5108AHBG) 8M words × 16 bits × 4 banks (EDE5116AHBG) • Package 60-ball FBGA (EDE5108AHBG) 84-ball FBGA (EDE5116AHBG) Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps/533Mbps/400Mbps (max.) • 1KB page size (EDE5108AHBG) Row address: A0 to A13 Column address: A0 to A9 • 2KB page size (EDE5116AHBG) Row address: A0 to A12 Column address: A0 to A9 • Four internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): Sequential (4, 8) Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation L EO Specifications t uc Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C od Pr • Refresh cycles: 8192 cycles/64ms Document No. E0933E30 (Ver. 3.0) Date Published September 2006 (K) Japan Printed in Japan URL: http://www.elpida.com This product became EOL in June, 2010. Elpida Memory, Inc. 2006 EDE5108AHBG, EDE5116AHBG Ordering Information Mask version Part number EDE5108AHBG-8E-E EDE5108AHBG-8G-E EDE5108AHBG-6E-E EDE5108AHBG-5C-E EDE5108AHBG-4A-E EDE5116AHBG-8E-E EDE5116AHBG-8G-E EDE5116AHBG-6E-E EDE5116AHBG-5C-E EDE5116AHBG-4A-E Organization (words × bits) 64M × 8 H Internal Banks Speed bin (CL-tRCD-tRP) Package DDR2-800 (5-5-5) DDR2-800 (6-6-6) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) DDR2-800 (5-5-5) DDR2-800 (6-6-6) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) 4 32M × 16 60-ball FBGA 84-ball FBGA EO Part Number E D E 51 08 A H BG - 8E - E Elpida Memory Type D: Monolithic Device L Product Family E: DDR2 Environment code E: Lead Free (RoHS compliant) Speed 8E: DDR2-800 (5-5-5) 8G: DDR2-800 (6-6-6) 6E: DDR2-667 (5-5-5) 5C: DDR2-533 (4-4-4) 4A: DDR2-400 (3-3-3) Density / Bank 51: 512Mb /4-bank Power Supply, Interface A: 1.8V, SSTL_18 Package BG: FBGA Die Rev. t uc od Pr Organization 08: x8 16: x16 Preliminary Data Sheet E0933E30 (Ver. 3.0) 2 EDE5108AHBG, EDE5116AHBG Pin Configurations /xxx indicates active low signal. 60-ball FBGA (×8 organization) 1 2 3 84-ball FBGA (×16 organization) 7 8 9 A VDD NU/ /RDQS VSS 1 2 3 VDD NC VSS VSSQ /UDQS VDDQ DQ14 VSSQ UDM UDQS VSSQ DQ15 VDDQ VDDQ 7 8 9 A VSSQ /DQS VDDQ B B DQ6 VSSQ DM/RDQS DQS VSSQ DQ7 C C VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ D D DQ4 VSSQ DQ3 EO DQ2 VSSQ DQ5 VSSDL CK VDD E VDDL VREF VSS BA0 /WE /RAS /CK ODT BA1 /CAS /CS VSS A3 A1 A2 A0 VDD A5 A6 A12 VDD NC VSS VSSQ /LDQS VDDQ DQ6 VSSQ LDM LDQS VSSQ VDDQ VDD A9 A11 NC NC A8 DQ7 DQ1 VDDQ VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 VDDL VREF VSS VSSDL CK VDD CKE /WE /RAS /CK ODT BA0 BA1 /CAS /CS A10 A1 A2 A0 A3 A5 A6 A4 A7 A9 A11 A8 A12 NC NC NC J A4 L A7 L DQ10 VSSQ DQ13 H J K DQ12 VSSQ DQ11 G H A10 VDDQ F G NC DQ8 E F CKE DQ9 VDDQ K VSS L A13 NC M (Top view) VDD N Pr VSS P VSS R VDD Function A0 to A13 Address inputs BA0, BA1 Bank select DQ0 to DQ15 Data input/output DQS, /DQS UDQS, /UDQS LDQS, /LDQS Differential data strobe Pin name Function ODT ODT control VDD Supply voltage for internal circuit VSS Ground for internal circuit VDDQ Supply voltage for DQ circuit od Pin name (Top view) Differential data strobe for read /CS Chip select VSSQ /RAS, /CAS, /WE Command input VDDL CKE Clock enable VSSDL CK, /CK Differential clock input NC* 1 DM UDM, LDM Write data mask NU* 2 VREF Ground for DQ circuit uc RDQS, /RDQS Input reference voltage Supply voltage for DLL circuit Ground for DLL circuit No connection Not usable t Notes: 1. Not internally connected with die. 2. Don’t use other than reserved functions. Preliminary Data Sheet E0933E30 (Ver. 3.0) 3 EDE5108AHBG, EDE5116AHBG CONTENTS L EO Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................23 Pin Function.................................................................................................................................................24 Command Operation ...................................................................................................................................26 Simplified State Diagram .............................................................................................................................33 Operation of DDR2 SDRAM ........................................................................................................................34 Package Drawing ........................................................................................................................................71 Recommended Soldering Conditions..........................................................................................................73 t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 4 EDE5108AHBG, EDE5116AHBG Electrical Specifications • All voltages are referenced to VSS (GND) • Execute power-up and Initialization sequence before proper device operation is achieved. Absolute Maximum Ratings Symbol Rating Unit Notes Power supply voltage VDD −1.0 to +2.3 V 1 Power supply voltage for output VDDQ −0.5 to +2.3 V 1 Input voltage VIN −0.5 to +2.3 V 1 Output voltage VOUT −0.5 to +2.3 V 1 Storage temperature Tstg −55 to +100 °C 1, 2 Power dissipation PD 1.0 W 1 Short circuit output current IOUT 50 mA 1 EO Parameter Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. Caution L Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Condition Operating case temperature Pr Parameter Symbol Rating Unit Notes TC 0 to +95 °C 1, 2 t uc od Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. Supporting 0°C to +85°C with full AC and DC specifications. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9µs) and higher temperature Self-Refresh entry via A7 "1" on EMRS (2). Preliminary Data Sheet E0933E30 (Ver. 3.0) 5 EDE5108AHBG, EDE5116AHBG Recommended DC Operating Conditions (SSTL_18) Parameter Symbol min. typ. max. Unit Notes Supply voltage VDD 1.7 1.8 1.9 V 4 Supply voltage for output VDDQ 1.7 1.8 1.9 V 4 Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 2 Termination voltage VTT VREF − 0.04 VREF VREF + 0.04 V 3 DC input logic high VIH (DC) VREF + 0.125 VDDQ + 0.3 V DC input low VIL (DC) −0.3 VREF – 0.125 V AC input logic high -8E, -8G, -6E VIH (AC) VREF + 0.200 V VIH (AC) VREF + 0.250 V VIL (AC) VREF − 0.200 V VIL (AC) VREF − 0.250 V -5C, -4A EO AC input low -8E, -8G, -6E -5C, -4A L Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together. t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 6 EDE5108AHBG, EDE5116AHBG DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) Parameter Symbol Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Precharge quiet standby current ×16 max. max. -8E, -8G -6E -5C -4A 75 70 65 60 90 85 80 75 mA IDD1 -8E, -8G -6E -5C -4A 85 80 75 70 105 100 90 85 mA IDD2P -8E, -8G -6E -5C -4A 10 10 10 8 10 10 10 8 IDD2Q -8E, -8G -6E -5C -4A 28 25 22 20 28 25 22 20 mA L Idle standby current mA -8E, -8G -6E -5C -4A 35 30 25 20 35 30 25 20 mA -8E, -8G -6E IDD3P-F -5C -4A 25 20 20 15 25 20 20 15 mA -8E, -8G -6E IDD3P-S -5C -4A 15 15 13 13 15 15 13 13 mA IDD2N all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING -8E, -8G -6E -5C -4A 50 45 40 35 50 45 40 35 mA Operating current (Burst read operating) IDD4R -8E, -8G -6E -5C -4A 135 115 95 75 175 150 125 105 mA IDD4W -8E, -8G -6E -5C -4A 140 120 100 80 195 170 130 110 mA t IDD3N uc Active standby current Operating current (Burst write operating) Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W od Pr Active power-down standby current Unit IDD0 EO Precharge powerdown standby current Grade ×8 Preliminary Data Sheet E0933E30 (Ver. 3.0) 7 EDE5108AHBG, EDE5116AHBG Parameter Symbol Auto-refresh current IDD5 Self-refresh current IDD7 ×16 max. max. 195 190 185 180 6 -8E, -8G -6E -5C -4A 170 160 150 140 195 190 185 180 6 250 240 230 220 Unit Test condition mA tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA Self Refresh Mode; CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING mA all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 × tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN ≤ VIL (AC) (max.) H is defined as VIN ≥ VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. L Notes: 1. 2. 3. 4. -8E, -8G -6E -5C -4A IDD6 EO Operating current (Bank interleaving) Grade ×8 od Pr AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. DDR2-800 Parameter 5-5-5 6-6-6 CL (IDD) 5 6 tRCD (IDD) 12.5 15 tRC (IDD) 57.5 60 DDR2-667 DDR2-533 DDR2-400 5-5-5 4-4-4 3-3-3 Unit 5 4 3 tCK 15 15 15 ns 60 60 55 ns uc DDR2-800 7.5 7.5 7.5 7.5 tRRD (IDD)-×16 10 10 10 10 tCK (IDD) 2.5 2.5 3 3.75 tRAS (min.)(IDD) 45 45 45 45 40 ns tRAS (max.)(IDD) 70000 70000 70000 70000 70000 ns tRP (IDD) 12.5 15 15 15 15 ns tRFC (IDD) 105 105 105 105 Preliminary Data Sheet E0933E30 (Ver. 3.0) 8 7.5 ns 10 ns 5 ns 105 t tRRD (IDD)-×8 ns EDE5108AHBG, EDE5116AHBG DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) Parameter Symbol Value Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO 5 µA VDDQ ≥ VOUT ≥ VSS VTT + 0.603 V 5 VTT − 0.603 V 5 Output timing measurement reference level VOTR 0.5 × VDDQ V 1 Output minimum sink DC current IOL +13.4 mA 3, 4, 5 Output minimum source DC current IOH −13.4 mA 2, 4, 5 Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Notes The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V. EO Notes: 1. 2. 3. 4. 5. Unit DC Characteristics 3 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) Symbol min. max. Unit Notes AC differential input voltage VID (AC) 0.5 VDDQ + 0.6 V 1, 2 AC differential cross point voltage VIX (AC) 0.5 × VDDQ − 0.175 0.5 × VDDQ + 0.175 V 2 AC differential cross point voltage VOX (AC) 0.5 × VDDQ − 0.125 0.5 × VDDQ + 0.125 V 3 L Parameter od Pr Notes: 1. VID (AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, RDQS) and VCP is the complementary input signal (such as /CK, /DQS, /RDQS). The minimum value is equal to VIH (AC) − VIL (AC). 2. The typical value of VIX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX (AC) is expected to track variations in VDDQ. VIX (AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and VOX (AC) is expected to track variations in VDDQ. VOX (AC) indicates the voltage at which differential output signals must cross. VDDQ VTR Crossing point VID VIX or VOX VCP t uc VSSQ Differential Signal Levels*1, 2 Preliminary Data Sheet E0933E30 (Ver. 3.0) 9 EDE5108AHBG, EDE5116AHBG ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) Parameter Symbol min typ max Unit Note Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω Rtt1 (eff) 60 75 90 Ω 1 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω Rtt2 (eff) 120 150 180 Ω 1 Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω Rtt3 (eff) 40 50 60 Ω 1 Deviation of VM with respect to VDDQ/2 ∆VM −6 +6 % 1 Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt (eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I(VIL (AC)) respectively. VIH (AC), and VDDQ values defined in SSTL_18. EO Rtt(eff) = VIH(AC) − VIL(AC) I(VIH(AC)) − I(VIL(AC)) Measurement Definition for ∆VM Measure voltage (VM) at test pin (midpoint) with no load. ∆VM = L 2 × VM VDDQ − 1 × 100% OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V) Parameter Pull-up and pull-down mismatch Output slew rate typ Pr Output impedance min max Unit Notes 23.4 Ω 1 12.6 18 0 4 Ω 1, 2 1.5 5 V/ns 3, 4 t uc od Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL (AC) to VIH (AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. Preliminary Data Sheet E0933E30 (Ver. 3.0) 10 EDE5108AHBG, EDE5116AHBG Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V) Parameter Symbol Pins min. max. Unit Notes CLK input pin capacitance CCK CK, /CK 1.0 2.0 pF 1 1.0 1.75 pF 1 CIN /RAS, /CAS, /WE, /CS, CKE, ODT, Address 1.0 2.0 pF 1 2.5 3.5 pF 2 2.5 4.0 pF 2 Input pin capacitance -8E, -8G -6E, -5C, -4A Input/output pin capacitance -8E, -8G, -6E CI/O -5C, -4A DQ, DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS, RDQS, /RDQS, DM, UDM, LDM L EO Notes: 1. Matching within 0.25pF. 2. Matching within 0.50pF. t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 11 EDE5108AHBG, EDE5116AHBG AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-800, 667] Frequency (Mbps) Parameter Symbol /CAS latency CL Active to read or write command delay tRCD Precharge command period tRP Active to active/auto-refresh command time tRC tAC EO DQ output access time from CK, /CK -8E, -8G -6E 800 667 min. max. min. max. Unit 5 (-8E) 6 (-8G) 12.5 (-8E) 15 (-8G) 12.5 (-8E) 15 (-8G) 57.5(-8E) 60 (-8G) 5 (-8E) 6 (-8G) 5 5 tCK 15 ns 15 ns 60 ns −400 +400 −450 +450 ps Notes tDQSCK −350 +350 −400 +400 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min. (tCL, tCH) min. (tCL, tCH) ps Clock cycle time tCK 2500 8000 3000 8000 ps DQ and DM input hold time tDH (base) 125 175 ps 5 DQ and DM input setup time tDS (base) 50 100 ps 4 0.6 0.6 tCK DQ and DM input pulse width for each input tDIPW 0.35 0.35 tCK Data-out high-impedance time from CK,/CK tHZ tAC max. tAC max. ps Data-out low-impedance time from CK,/CK tAC min. tAC max. tAC min. tAC max. ps ps L DQS output access time from CK, /CK Control and Address input pulse width for each input tIPW tLZ Pr 200 240 DQ hold skew factor tQHS 300 340 tQH tHP – tQHS tHP – tQHS ps DQS latching rising transitions to associated tDQSS clock edges −0.25 +0.25 −0.25 +0.25 tCK DQS input high pulse width tDQSH 0.35 0.35 tCK tDQSL 0.35 0.35 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK Mode register set command cycle time tMRD 2 2 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 0.35 tCK Address and control input hold time tIH (base) 250 275 ps 5 Address and control input setup time tIS (base) 175 200 ps 4 Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Active to precharge command tRAS 45 70000 45 70000 ns Active to auto precharge delay tRAP tRCD min. tRCD min. ns Active bank A to active bank B command period (EDE5108AH) tRRD 7.5 7.5 ns (EDE5116AH) tRRD 10 10 ns DQ/DQS output hold time from DQS DQS input low pulse width 12 t Preliminary Data Sheet E0933E30 (Ver. 3.0) ps uc od DQS-DQ skew for DQS and associated DQ tDQSQ signals EDE5108AHBG, EDE5116AHBG Frequency (Mbps) Parameter Symbol /CAS to /CAS command delay Write recovery time -8E, -8G -6E 800 667 min. max. min. max. Unit tCCD 2 2 tCK tWR 15 15 ns Auto precharge write recovery + precharge time tDAL (tWR/tCK) + (tRP/tCK) Internal write to read command delay tWTR 7.5 7.5 ns Internal read to precharge command delay tRTP 7.5 7.5 ns (tWR/tCK)+ (tRP/tCK) tCK Notes 1 tXSNR tRFC + 10 tRFC + 10 ns Exit self-refresh to a read command tXSRD 200 200 tCK Exit precharge power-down to any non-read tXP command 2 2 tCK Exit active power-down to read command tXARD 2 2 tCK 3 tXARDS 8 − AL 7 − AL tCK 2, 3 tCKE 3 3 tCK Output impedance test driver delay tOIT 0 12 0 12 ns MRS command to ODT update delay tMOD 0 12 0 12 ns tRFC 105 105 ns tREFI 7.8 7.8 µs tREFI 3.9 3.9 µs tIS + tCK + tIH tIS + tCK + tIH ns EO Exit self-refresh to a non-read command Exit active power-down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) L Auto-refresh to active/auto-refresh command time Average periodic refresh interval (0°C ≤ TC ≤ +85°C) (+85°C < TC ≤ +95°C) Minimum time clocks remains ON after CKE tDELAY asynchronously drops low t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 13 EDE5108AHBG, EDE5116AHBG AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-533, 400] Frequency (Mbps) Parameter Symbol -5C -4A 533 400 min. max. min. max. Unit CL 4 5 3 5 tCK Active to read or write command delay tRCD 15 15 ns Precharge command period tRP 15 15 ns Active to active/auto-refresh command time tRC 60 55 ns DQ output access time from CK, /CK tAC −500 +500 −600 +600 ps DQS output access time from CK, /CK tDQSCK −450 +450 −500 +500 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min. (tCL, tCH) min. (tCL, tCH) ps Clock cycle time tCK 3750 8000 5000 8000 ps tDH (base) 225 275 ps tDH1 (base) –25 +25 ps tDS (base) 100 150 ps tDS1 (base) –25 +25 ps tIPW 0.6 0.6 tCK 0.35 EO /CAS latency L DQ and DM input hold time (differential strobe) DQ and DM input hold time (single-ended strobe) DQ and DM input setup time (differential strobe) DQ and DM input setup time (single-ended strobe) Control and Address input pulse width for each input 0.35 tCK Data-out high-impedance time from CK,/CK tHZ tAC max. tAC max. ps Data-out low-impedance time from CK,/CK tLZ tAC min. tAC max. tAC min. tAC max. ps DQS-DQ skew for DQS and associated DQ signals tDQSQ 300 350 ps DQ hold skew factor tQHS 400 450 ps tQH tHP – tQHS DQ and DM input pulse width for each input tDIPW Pr DQ/DQS output hold time from DQS tHP – tQHS Notes 5 4 ps −0.25 +0.25 −0.25 +0.25 tCK DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK od DQS latching rising transitions to associated tDQSS clock edges tDSH 0.2 0.2 tCK Mode register set command cycle time tMRD 2 2 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 0.35 tCK Address and control input hold time tIH (base) 375 475 ps 5 Address and control input setup time tIS (base) 250 350 ps 4 uc DQS falling edge hold time from CK tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Active to precharge command tRAS 45 70000 40 70000 ns Active to auto precharge delay tRAP tRCD min. tRCD min. Preliminary Data Sheet E0933E30 (Ver. 3.0) 14 t Read preamble ns EDE5108AHBG, EDE5116AHBG Frequency (Mbps) -5C -4A 533 400 Parameter Symbol min. max. min. max. Unit Active bank A to active bank B command period (EDE5108AH) tRRD 7.5 7.5 ns (EDE5116AH) tRRD 10 10 ns /CAS to /CAS command delay tCCD 2 2 tCK Write recovery time 15 ns 15 tDAL (tWR/tCK)+ (tRP/tCK) Internal write to read command delay tWTR 7.5 10 ns Internal read to precharge command delay tRTP 7.5 7.5 ns Exit self-refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self-refresh to a read command tXSRD EO tWR Auto precharge write recovery + precharge time (tWR/tCK)+ (tRP/tCK) tCK Notes 1 200 200 tCK Exit precharge power-down to any non-read tXP command 2 2 tCK Exit active power-down to read command tXARD 2 2 tCK 3 tXARDS 6 − AL 6 − AL tCK 2, 3 tCKE 3 3 tCK L Exit active power-down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay tOIT 0 12 0 12 ns MRS command to ODT update delay tMOD 0 12 0 12 ns 105 105 ns 7.8 7.8 µs 3.9 3.9 µs tIS + tCK + tIH ns Pr Auto-refresh to active/auto-refresh command tRFC time Average periodic refresh interval tREFI (0°C ≤ TC ≤ +85°C) (+85°C < TC ≤ +95°C) tREFI Minimum time clocks remains ON after CKE tDELAY asynchronously drops low For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power-down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test. od Notes: 1. 2. 3. 4. tIS + tCK + tIH CK DQS /CK /DQS tDH tDS tIS tDH uc tDS tIH tIS tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS t Input Waveform Timing 1 (tDS, tDH) Input Waveform Timing 2 (tIS, tIH) Preliminary Data Sheet E0933E30 (Ver. 3.0) 15 EDE5108AHBG, EDE5116AHBG ODT AC Electrical Characteristics Parameter Symbol min max Unit ODT turn-on delay tAOND 2 2 tCK ODT turn-on -8E, -8G, -6E tAON tAC(min) tAC(max) + 700 ps 1 1 tAON tAC(min) tAC(max) + 1000 ps ODT turn-on (power-down mode) tAONPD tAC(min) + 2000 2tCK + tAC(max) + 1000 ps ODT turn-off delay tAOFD 2.5 2.5 tCK ODT turn-off tAOF tAC(min) tAC(max) + 600 ps ODT turn-off (power-down mode) tAOFPD tAC(min) + 2000 2.5tCK + tAC(max) + 1000 ps ODT to power-down entry latency tANPD 3 3 tCK tAXPD 8 8 tCK -5C, -4A EO ODT power-down exit latency Notes 2 Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. AC Input Test Conditions Symbol Value Unit Notes Input reference voltage VREF 0.5 × VDDQ V 1 Input signal maximum peak to peak swing VSWING(max.) 1.0 V 1 Input signal minimum slew rate SLEW 1.0 V/ns 2, 3 L Parameter Pr Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. Start of rising edge input timing Start of falling edge input timing od VDDQ VIH (AC)(min.) VIH (DC)(min.) VSWING(max.) VREF VIL (DC)(max.) VIL (AC)(max.) VIH (DC)(min.) − VIL (AC)(max.) Rising slew = ∆TF VIH (AC) min. − VIL (DC)(max.) AC Input Test Signal Wave forms Measurement point VTT RT =25 Ω Output Load Preliminary Data Sheet E0933E30 (Ver. 3.0) 16 ∆TR t DQ uc Falling slew = VSS ∆TR ∆TF EDE5108AHBG, EDE5116AHBG Input Slew Rate Derating For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the ∆tIS, ∆tDS and ∆tIH, ∆tDH derating value respectively. Example: tDS (total setup time) = tDS (base) + ∆tDS. EO Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure of Slew Rate Definition Tangent). L Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’, the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value (see the figure of Slew Rate Definition Tangent). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL (AC). Pr For slew rates in between the values listed in the tables below, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [Derating Values of tDS/tDH with Differential DQS (DDR2-400, 533)] DQS, /DQS differential slew rate 3.0 V/ns 2.0 V/ns 1.8 V/ns od 4.0 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH Unit +125 +45 +125 +45 +125 +45 ps 1.5 +83 +21 +83 +21 +83 +21 +95 +33 ps 1.0 0 0 0 0 0 0 +12 +12 +24 +24 ps 0.9 −11 −14 −11 −14 +1 −2 +13 +10 +25 +22 ps 0.8 −25 −31 −13 −19 −1 −7 11 +5 +23 +17 ps 0.7 −31 −42 −19 −30 −7 −18 +5 −6 +17 +6 ps 0.6 −43 −59 −31 −47 0.5 −74 −89 0.4 uc DQ slew rate (V/ns) 2.0 −19 −35 −7 −23 +5 −11 ps −62 −77 −50 −65 −38 −53 ps −127 −140 −115 −128 −103 −116 ps t Preliminary Data Sheet E0933E30 (Ver. 3.0) 17 EDE5108AHBG, EDE5116AHBG [Derating Values of tDS/tDH with Differential DQS (DDR2-667, 800)] DQS, /DQS differential slew rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH Unit 2.0 +100 +45 +100 +45 +100 +45 ps 1.5 +67 +21 +67 +21 +67 +21 +79 +33 ps 1.0 0 0 0 0 0 0 +12 +12 +24 +24 ps 0.9 −5 −14 −5 −14 +7 −2 +19 +10 +31 +22 ps 0.8 −13 −31 −1 −19 +11 −7 +23 +5 +35 +17 ps 0.7 −10 −42 +2 −30 +14 −18 +26 −6 +38 +6 ps 0.6 EO DQ slew rate (V/ns) −10 −59 +2 −47 +14 −35 +26 −23 +38 −11 ps 0.5 −24 −89 −12 −77 0 −65 +12 −53 ps 0.4 −52 −140 −40 −128 −28 −116 ps [Derating Values of tDS1/tDH1 with Single-Ended DQS (DDR2-400, 533)] DQS, /DQS single-ended slew rate 2.0 V/ns 1.5 V/ns 1.0V/ns 0.9V/ns 0.8V/ns 0.7 V/ns 0.6 V/ns 0.5 V/ns 0.4 V/ns ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Unit tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 tDS1 tDH1 L +188 +188 +167 +146 +125 +63 ps 1.5 +146 +167 +125 +125 +83 +42 +81 +43 ps 1.0 +63 +125 +42 +83 0 −2 +1 −7 −13 ps 0.9 +31 +69 −11 −14 −13 −13 −18 −27 −29 −45 ps 0.8 −25 −31 −27 −30 −32 −44 −43 −62 −60 −86 ps 0.7 −45 −53 −50 −67 −61 −85 −78 −109 −108 −152 ps 0.6 −74 −96 −85 −114 −102 −138 −132 −181 −183 −246 ps 0.5 −128 −156 −145 −180 −175 −223 −226 −288 ps 0.4 0 −210 −243 −240 −286 −291 −351 ps t uc od Pr DQ slew rate (V/ns) 2.0 Preliminary Data Sheet E0933E30 (Ver. 3.0) 18 EDE5108AHBG, EDE5116AHBG [Derating Values of tIS/tIH (DDR2-400, DDR2-533)] CK, /CK Differential Slew Rate 2.0 V/ns 1.0 V/ns ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH Unit Notes 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 60 ps 0.9 −11 −14 +19 +16 +49 +46 ps 0.8 −25 −31 +5 −1 +35 +29 ps 0.7 −43 −54 −13 −24 +17 +6 ps 0.6 −67 −83 −37 −53 −7 −23 ps 0.5 −110 −125 −80 −95 −50 −65 ps 0.4 −175 −188 −145 −158 −115 −128 ps 0.3 −285 −292 −255 −262 −225 −232 ps 0.25 −350 −375 −320 −345 −290 −315 ps 0.2 −525 −500 −495 −470 −465 −440 ps 0.15 −800 −708 −770 −678 −740 −648 ps 0.1 −1450 −1125 −1420 −1095 −1390 −1065 ps EO Command/address slew rate (V/ns) 1.5 V/ns L t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 19 EDE5108AHBG, EDE5116AHBG [Derating Values of tIS/tIH (DDR2-667, DDR2-800)] CK, /CK Differential Slew Rate 2.0 V/ns 1.0 V/ns ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH Unit 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +130 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 −5 −14 +25 +16 +55 +46 ps 0.8 −13 −31 +17 −1 +47 +29 ps 0.7 −22 −54 +8 −24 +38 +6 ps 0.6 −34 −83 −4 −53 +26 −23 ps 0.5 −60 −125 −30 −95 0 −65 ps 0.4 −100 −188 −70 −158 −40 −128 ps 0.3 −168 −292 −138 −262 −108 −232 ps 0.25 −200 −375 −170 −345 −140 −315 ps 0.2 −325 −500 −295 −470 −265 −440 ps 0.15 −517 −708 −487 −678 −457 −648 ps 0.1 −1000 −1125 −970 −1095 −940 −1065 ps EO Command/address slew rate (V/ns) 1.5 V/ns Notes L t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 20 EDE5108AHBG, EDE5116AHBG Single-ended DQS VDDQ VIH (AC) min. VIH (DC) min. VREF (DC) VIL (DC) max. VIL (AC) max. VSS DQS Differential DQS, /DQS CK, /CK DQS CK tDS1 tDH1 tDS1 tDH1 /DQS /CK EO tDS tIS tDH tIH tDS tIS tDH tIH VDD VIH (AC) min. L VREF to AC region VIH (DC) min. VIL (DC) max. VIL (AC) max. VSS ∆TFS ∆TFH uc = VREF to AC region ∆TRH ∆TRS VREF (DC) - VIL (AC) max. Setup slew rate = Falling signal ∆TFS Hold slew rate Rising signal nominal slew rate DC to VREF region od Pr VREF (DC) DC to VREF region nominal slew rate VIH (AC) min. - VREF (DC) Setup slew rate = Rising signal ∆TRS VREF (DC) - VIL (DC) max. Hold slew rate Falling signal ∆TRH Preliminary Data Sheet E0933E30 (Ver. 3.0) 21 VIH (DC) min. - VREF (DC) ∆TFH t Slew Rate Definition Nominal = EDE5108AHBG, EDE5116AHBG Single-ended DQS DQS VDDQ VIH (AC) min. VIH (DC) min. VREF (DC) VIL (DC) max. VIL (AC) max. VSS Differential DQS, /DQS CK, /CK DQS CK tDS1 tDH1 tDS1 tDH1 tDS tIS tDH tIH /DQS /CK EO tDS tIS tDH tIH VDD VIH (AC) min. VREF to AC region L nominal line nominal line VIH (DC) min. VIL (DC) max. nominal line VIL (AC) max. VSS ∆TFS ∆TRH VREF to AC region ∆TRS ∆TFH uc tangent line [VREF (DC) - VIL (AC) max.] Setup slew rate = Falling signal ∆TFS = DC to VREF region od nominal line Hold slew rate Rising signal tangent line Pr VREF (DC) DC to VREF region tangent line tangent line [VIH (AC) min. - VREF (DC)] Setup slew rate = Rising signal ∆TRS tangent line [VREF (DC) - VIL (DC) max.] Hold slew rate Falling signal ∆TRH Slew Rate Definition Tangent = tangent line [VIH (DC) min. - VREF (DC)] ∆TFH t Preliminary Data Sheet E0933E30 (Ver. 3.0) 22 EDE5108AHBG, EDE5116AHBG Clock generator Block Diagram Bank 3 Bank 2 Bank 1 A0 to A13, BA0, BA1 Memory cell array Bank 0 Control logic Sense amp. L Command decoder EO /CS /RAS /CAS /WE Mode register Row address buffer and refresh counter Row decoder CK /CK CKE Column decoder Column address buffer and burst counter Data control circuit Latch circuit Pr DLL CK, /CK Input & Output buffer DQS, /DQS RDQS, /RDQS ODT DM DQ t uc od Preliminary Data Sheet E0933E30 (Ver. 3.0) 23 EDE5108AHBG, EDE5116AHBG Pin Function CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. EO A0 to A13 (input pins) Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during mode register set commands. [Address Pins Table] Part number EDE5116AHBG Row address Column address L EDE5108AHBG Address (A0 to A13) AX0 to AX13 AY0 to AY9 AX0 to AX12 AY0 to AY9 Note 1 Note: 1. A13 pin is NC for × 16 organization. Pr A10 (AP) (input pin) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1. [Bank Select Signal Table] BA0 L Bank 1 H Bank 2 L Bank 3 H BA1 L L H uc Bank 0 od BA0, BA1 (input pins) BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS (1), EMRS (2) cycle. H Remark: H: VIH. L: VIL. t CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit, and for self-refresh entry. CKE is asynchronous for self-refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during selfrefresh. Preliminary Data Sheet E0933E30 (Ver. 3.0) 24 EDE5108AHBG, EDE5116AHBG DM, UDM and LDM (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by EMRS. In × 16 configuration, UDM controls upper byte (DQ8 to DQ15) and LDM controls lower byte (DQ0 to DQ7). In this datasheet, DM represents UDM and LDM. DQ (input/output pins) Bi-directional data bus. EO DQS, /DQS UDQS, /UDQS, LDQS, /LDQS (input/output pins) Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centered in write data. Used to capture write data. /DQS can be disabled by EMRS. In × 16 configuration, UDQS, /UDQS and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). In this datasheet, DQS represents UDQS and LDQS, /DQS represents /UDQS and /LDQS. RDQS, /RDQS (output pins) Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS. L ODT (input pins) ODT (On Die Termination control) is a registered high signal that enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for × 8 configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT. Any time the EMRS enables the ODT function; ODT may not be driven high until eight clocks after the EMRS has been enabled. Pr VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDDL and VSSDL (power supply) VDDL and VSSDL are power supply pins for DLL circuits. t uc od VREF (Power supply) SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ Preliminary Data Sheet E0933E30 (Ver. 3.0) 25 EDE5108AHBG, EDE5116AHBG Command Operation Command Truth Table The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. CKE Function Previou Current Symbol s cycle cycle /CS /RAS /CAS /WE BA0 BA1 A13 to A11 A10 Mode register set MRS H H L L L L L L MRS OPCODE 1 EMRS H H L L L L H L EMRS (1) OPCODE 1 EMRS H H L L L L L H EMRS (2) OPCODE 1 Extended mode register set (1) Extended mode register set (2) A0 to A9 Notes REF H H L L L H × × × × × 1 Self-refresh entry SELF H L L L L H × × × × × 1 Self-refresh exit SELFX L H H × × × × × × × × 1, 6 L H L H H H × × × × × Single bank precharge PRE H H L L H L BA × L × 1, 2 Precharge all banks PALL H H L L H L × × H × 1 Bank activate ACT H H L L H H BA RA Write WRIT H H L H L L BA CA L CA 1, 2, 3 Write with auto precharge WRITA H H L H L L BA CA H CA 1, 2, 3 Read L EO Auto-refresh 1, 2 H H L H L H BA CA L CA 1, 2, 3 Read with auto precharge READA H H L H L H BA CA H CA 1, 2, 3 No operation NOP H × L H H H × × × × × 1 Device deselect DESL H H Power-down mode entry PDEN PDEX × × × × × × × × 1 H L × H × × × × × × × × 1, 4 H L L H H H × × × × × L H H × × × × × × × × L H L H H H × × × × × Pr Power-down mode exit READ × 1, 4 t uc od Remark: H = VIH. L = VIL. × = VIH or VIL. BA = Bank Address, RA = Row Address, CA = Column Address Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. 2. Bank select (BA0, BA1), determine which bank is to be operated upon. 3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in burst read command [READ] or ″Writes interrupted by a Write″ in burst write command [WRIT]. 4. The power-down mode does not perform any refresh operations. The duration of power-down is therefore limited by the refresh requirements of the device. One clock delay is required for mode entry and exit. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 6. Self-refresh exit is asynchronous. Preliminary Data Sheet E0933E30 (Ver. 3.0) 26 EDE5108AHBG, EDE5116AHBG CKE Truth Table CKE *3 Previous 1 cycle (n-1)* Current *1 cycle (n) Command(n) /CS, /RAS, /CAS, /WE Operation (n) L L × Maintain power-down 11, 13, 15 L H DESL or NOP Power-down exit 4, 8, 11, 13 L L × Maintain self-refresh 11, 15 L H DESL or NOP Self-refresh exit 4, 5, 9 Bank Active H L DESL or NOP Active power-down entry 4, 8, 10, 11, 13 All banks idle H L DESL or NOP Precharge power-down entry 4, 8, 10, 11, 13 H L SELF Self-refresh entry 6, 9, 11, 13 H Refer to the Command Truth Table Current state* 2 Power-down Self-refresh EO Any state other than listed above H *3 Notes 7 L Remark: H = VIH. L = VIL. × = Don’t care Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On self-refresh exit, [DESL] or [NOP] commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self-refresh mode can only be entered from the all banks idle state. 7. Must be a legal command as defined in the command truth table. 8. Valid commands for power-down entry and exit are [NOP] and [DESL] only. 9. Valid commands for self-refresh exit are [NOP] and [DESL] only. 10. Power-down and self-refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. See section Power Down and Self Refresh Command for a detailed list of restrictions. 11. Minimum CKE high time is 3 clocks; minimum CKE low time is 3 clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. See section ODT (On Die Termination). 13. The power-down does not perform any refresh operations. The duration of power-down mode is therefore limited by the refresh requirements outlined in section automatic refresh command. 14. CKE must be maintained high while the SDRAM is in OCD calibration mode. 15. “×” means “don’t care” (including floating around VREF) in self-refresh and power-down. However ODT must be driven high or low in power-down if the ODT function is enabled (bit A2 or A6 set to “1” in EMRS(1) ). t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 27 EDE5108AHBG, EDE5116AHBG Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR2 SDRAM. Current state /CS /RAS /CAS /WE Address Idle H × × × L H H H L H L L H L L L L H Operation Notes × DESL Nop × NOP Nop H BA, CA, A10 (AP) READ/READA ILLEGAL 1 L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 H H BA, RA ACT Row activating L BA PRE Nop L H L A10 (AP) PALL Nop EO L Command L L L H × REF Auto-refresh 2 L L L H × SELF Self refresh 2 L L L L BA, MRS-OPCODE MRS Mode register accessing 2 L L L L BA, EMRS-OPCODE EMRS (1) (2) Extended mode register accessing 2 H × × × × DESL Nop Bank(s) active H H H × NOP Nop H L H BA, CA, A10 (AP) READ/READA Begin Read L H L L BA, CA, A10 (AP) WRIT/WRITA Begin Write L L L L H H BA, RA ACT ILLEGAL L H L BA PRE Precharge L L H L A10 (AP) PALL Precharge all banks L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) × × × × DESL L H H H × NOP L H L H BA, CA, A10 (AP) L H L L L L H H L L H L BA 1 ILLEGAL Continue burst to end -> Row active Continue burst to end -> Row active od H Pr Read L L READ/READA Burst interrupt BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 BA, RA ACT ILLEGAL 1 PRE ILLEGAL 1 L H L A10 (AP) L L H × PALL ILLEGAL REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS L L L L BA, EMRS-OPCODE EMRS (1) (2) uc L L 1, 4 ILLEGAL ILLEGAL t Preliminary Data Sheet E0933E30 (Ver. 3.0) 28 EDE5108AHBG, EDE5116AHBG Current state /CS /RAS /CAS /WE Address Command Write H × × × × DESL L H H H × NOP L H L H BA, CA, A10 (AP) READ/READA ILLEGAL L H L L BA, CA, A10 (AP) WRIT/WRITA Burst interrupt 1, 4 L L H H BA, RA ACT ILLEGAL 1 L L H L BA PRE ILLEGAL 1 Continue burst to end -> Write recovering Continue burst to end -> Write recovering 1 L L H L A10 (AP) PALL ILLEGAL L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL H × × × × DESL L H H H × NOP Continue burst to end -> Precharging Continue burst to end -> Precharging L H L H BA, CA, A10 (AP) READ/READA ILLEGAL 1 L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 ILLEGAL 1 1 L L L H H BA, RA ACT L L H L BA PRE ILLEGAL L L H L A10 (AP) PALL ILLEGAL L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L L L H × × L H H L H L Pr Write with auto Precharge Note L EO Read with auto precharge Operation L BA, MRS-OPCODE MRS ILLEGAL L BA, EMRS-OPCODE EMRS (1) (2) × × DESL H × NOP L H BA, CA, A10 (AP) READ/READA ILLEGAL 1 H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA PRE ILLEGAL 1 L L H L A10 (AP) PALL ILLEGAL L L L H × L L L H × SELF L L L L BA, MRS-OPCODE MRS L L L L BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL od Continue burst to end ->Write recovering with auto precharge Continue burst to end ->Write recovering with auto precharge ILLEGAL uc REF ILLEGAL ILLEGAL ILLEGAL t Preliminary Data Sheet E0933E30 (Ver. 3.0) 29 EDE5108AHBG, EDE5116AHBG /CS /RAS /CAS /WE Address Command Operation Precharging H × × × × DESL Nop -> Enter idle after tRP L H H H × NOP Nop -> Enter idle after tRP L H L H BA, CA, A10 (AP) READ/READA ILLEGAL 1 L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA PRE Nop -> Enter idle after tRP L L H L A10 (AP) PALL Nop -> Enter idle after tRP L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) EO Current state Row activating ILLEGAL Nop -> Enter bank active after tRCD Nop -> Enter bank active after tRCD H × × × × DESL L H H H × NOP L H L H BA, CA, A10 (AP) READ/READA ILLEGAL 1, 5 L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1, 5 L L H H 1 BA, RA ACT ILLEGAL L L H L BA PRE ILLEGAL L L H L A10 (AP) PALL ILLEGAL L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L Pr Write recovering Note L BA, EMRS-OPCODE × × L H H L H L L H L L L H L L H L BA ILLEGAL Nop -> Enter bank active after tWR Nop -> Enter bank active after tWR × × DESL H × NOP H BA, CA, A10 (AP) READ/READA L BA, CA, A10 (AP) WRIT/WRITA New write H BA, RA ACT ILLEGAL 1 PRE ILLEGAL 1 L H L A10 (AP) L L H × PALL ILLEGAL REF ILLEGAL L L L H × SELF ILLEGAL L L L L L L L L BA, MRS-OPCODE MRS ILLEGAL BA, EMRS-OPCODE EMRS (1) (2) 1, 6 uc L L ILLEGAL od H EMRS (1) (2) ILLEGAL t Preliminary Data Sheet E0933E30 (Ver. 3.0) 30 EDE5108AHBG, EDE5116AHBG Current state /CS /RAS /CAS /WE Address Command Operation Write recovering with auto precharge H × × × × DESL Nop -> Precharging after tWR L H H H × NOP Nop -> Precharging after tWR L H L H BA, CA, A10 (AP) READ/READA ILLEGAL 1 L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL 1 L L H H BA, RA ACT ILLEGAL 1 L L H L BA PRE ILLEGAL 1 L L H L A10 (AP) PALL ILLEGAL L L L H × REF ILLEGAL EO Refresh L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL H × × × × DESL Nop -> Enter idle after tRFC L H H H × NOP Nop -> Enter idle after tRFC L H L H BA, CA, A10 (AP) READ/READA ILLEGAL L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL BA PRE ILLEGAL L L L L H L L L H L A10 (AP) PALL ILLEGAL L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL H × × × × DESL Nop -> Enter idle after tMRD L H H H × NOP Nop -> Enter idle after tMRD L H L H BA, CA, A10 (AP) READ/READA ILLEGAL L H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA PRE ILLEGAL L H L A10 (AP) L L H × PALL ILLEGAL REF ILLEGAL L L L H × SELF ILLEGAL L L L L L L L L BA, MRS-OPCODE MRS ILLEGAL BA, EMRS-OPCODE EMRS (1) (2) uc L L od Pr Mode register accessing Note ILLEGAL t Preliminary Data Sheet E0933E30 (Ver. 3.0) 31 EDE5108AHBG, EDE5116AHBG Current state /CS /RAS /CAS /WE Address Command Operation Extended Mode H × × × × DESL Nop -> Enter idle after tMRD register accessing L H H H × NOP Nop -> Enter idle after tMRD H L H BA, CA, A10 (AP) READ/READA ILLEGAL H L L BA, CA, A10 (AP) WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA PRE ILLEGAL L L H L A10 (AP) PALL ILLEGAL L L L H × REF ILLEGAL L L L H × SELF ILLEGAL L L L L BA, MRS-OPCODE MRS ILLEGAL L L L L BA, EMRS-OPCODE EMRS (1) (2) ILLEGAL EO L L H = VIH. L = VIL. × = VIH or VIL This command may be issued for other banks, depending on the state of the banks. All banks must be in "IDLE". All AC timing specs must be met. Only allowed at the boundary of 4 bits burst. Burst interruptions at other timings are illegal. Available in case tRCD is satisfied by AL setting. Available in case tWTR is satisfied. L Remark: Notes: 1. 2. 3. 4. 5. 6. Note t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 32 EDE5108AHBG, EDE5116AHBG Simplified State Diagram INITALIZATION SEQUENCE OCD CALIBRATION CKE_L SELF REFRESH PRE MRS EMRS (1) EMRS (2) EMRS (3) LF SE (E)MRS H E_ IDLE CK REF ALL BANKS PRECHARGED AUTO REFRESH EO CK _L E_L E CK CK E_H ACT PRECHARGE POWER DOWN CKE_L ACTIVATING CKE_L _L L CKE ACTIVE POWER DOWN CKE _H CKE _L Pr BANK ACTIVE RE AD IT WR RI W WRITA READA ITA WR REA DA PRE, PALL WRITA READ od WRIT A READ AD WRITE READ RE TA WRIT PRE, PALL PRECHARGE Preliminary Data Sheet E0933E30 (Ver. 3.0) 33 Automatic sequence Command sequence t Simplified State Diagram READA uc PRE, PALL EDE5108AHBG, EDE5116AHBG Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command. The address bits registered coincident with the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A13 select the row). The address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization; register definition, command descriptions and device operation. Power On and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. EO L Power-Up and Initialization Sequence The following sequence is required for power up and initialization. 1 1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT * at a low state (all other inputs may be undefined.) VDD, VDDL and VDDQ are driven from a single power converter output, AND VTT is limited to 0.95V max, AND VREF tracks VDDQ/2. or Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200µs after stable power and clock (CK, /CK), then apply [NOP] or [DESL] and take CKE high. 4. Wait minimum of 400ns then issue precharge all command. [NOP] or [DESL] applied during 400ns period. 5. Issue EMRS (2) command. (To issue EMRS (2) command, provide low to BA0, high to BA1.) 6. Issue EMRS (3) command. (To issue EMRS (3) command, high to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue DLL enable command, provide low to A0, high to BA0 and low to BA1 and A13.) 8. Issue a mode register set command for DLL reset. (To issue DLL reset command, provide high to A8 and low to BA0, BA1 and A13.) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS OCD default command (A9 = A8 = A7 = 1) followed by EMRS OCD calibration mode exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS. 13. The DDR2 SDRAM is now ready for normal operation. Note: 1. To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. uc od Pr tCH tCL CK /CK tIS CKE Command PALL NOP tRP tMRD tMRD DLL enable MRS tMRD PALL tMRD REF REF tRP tRFC DLL reset MRS tRFC EMRS tMRD OCD default 200 cycles (min) Power up and Initialization Sequence Preliminary Data Sheet E0933E30 (Ver. 3.0) 34 Any command EMRS t 400ns EMRS EMRS(3) EMRS(2) Follow OCD Flowchart tOIT OCD calibration mode exit EDE5108AHBG, EDE5116AHBG Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, /CAS latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a mode register set command [MRS]. Additionally, DLL disable function, driver impedance, additive /CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (Off-Chip Driver Impedance Adjustment) are also user defined variables and must be programmed with an extended mode register set command [EMRS]. Contents of the Mode Register (MR) or Extended Mode Registers (EMR (#)) can be altered by reexecuting the MRS and EMRS commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. L EO DDR2 SDRAM Mode Register Set [MRS] The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls /CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins A0 to A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 to A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, /CAS latency is defined by A4 to A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 to A11. Refer to the table for specific codes. BA1 BA0 A13 A12 A11 A10 A9 A7 A6 A5 A4 MRS mode Pr Write recovery for autoprecharge 0*1 0 A8 DLL reset 0 No 1 Yes 0*1 PD WR DLL TM /CAS latency A3 A2 BT A1 A0 Address field Burst length Mode register Burst length A7 Mode A3 Burst type 0 Normal 0 Sequential 1 1 Test A2 A1 A0 BL 0 1 0 4 0 1 1 8 Interleave od BA1 BA0 A8 /CAS latency A11 A10 A9 WR A6 A5 A4 Latency 1 0 EMRS(2) 0 0 0 Reserved 0 0 0 Reserved 1 1 EMRS(3): Reserved 0 0 1 0 0 1 Reserved 0 1 0 0 1 0 Reserved 0 1 1 3 5 1 0 0 4 6 1 0 1 2 3 Active power down exit timing 0 1 1 0 Fast exit (use tXARD timing) 1 0 0 1 Slow exit (use tXARDS timing) 1 0 1 1 1 0 Reserved 1 1 1 Reserved 4 5 uc A12 DDR2 800 EMRS(1) DDR2 667 MRS 1 DDR2 533 0 0 DDR2 400 0 1 1 0 Reserved 1 1 1 Reserved Notes: 1. BA1 and A13 are reserved for future use and must be programmed to 0 when setting the mode register. 2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR [cycles] = tWR (ns) / tCK (ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL. Preliminary Data Sheet E0933E30 (Ver. 3.0) 35 t Mode Register Set (MRS) EDE5108AHBG, EDE5116AHBG DDR2 SDRAM Extended Mode Registers Set [EMRS] EMRS (1) Programming The extended mode register (1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, /DQS disable, OCD program, RDQS enable. The default value of the extended mode register (1) is not defined, therefore the extended mode register (1) must be written after power-up for proper operation. The extended mode register (1) is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all banks precharge with CKE already high prior to writing into the extended mode register (1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for /DQS disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting. EO BA1 BA0 A13 A12 A11 A10 A9 0 0*1 1 BA1 BA0 0 0 A6 A5 A4 MRS 1 EMRS(1) 0 EMRS(2) A3 A2 L A6 A2 Rtt (nominal ) 0 0 ODT Disabled 0 1 75Ω 1 0 150Ω 1 1 50Ω EMRS(3): Reserved A1 A0 Address field Rtt Additive latency Rtt D.I.C DLL MRS mode 1 1 A7 Qoff RDQS /DQS OCD program 0 1 A8 Extended mode register A0 DLL enable 0 Enable 1 Disable Driver impedance adjustment A8 A7 0 0 0 OCD calibration mode exit 0 0 1 Drive(1) 0 1 0 Drive(0) A5 A4 A3 Latency 1 0 0 Adjust mode* 2 0 0 0 0 1 1 1 OCD Calibration default* 3 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 Reserved Additive latency Qoff 0 Output buffers enabled 1 Output buffers disabled /DQS enable 0 Enable 1 Disable od Pr A12 A10 Operation A9 1 1 0 Reserved 1 1 1 Reserved Driver strength control Output driver A11 RDQS enable 0 Disable 1 Enable A10 impedance control size 0 Normal 100% 1 Weak 60% Strobe function matrix uc A11 (RDQS enable) Driver A1 (/DQS enable) RDQS/DM /RDQS DQS 0 (Disable) 0 (Enable) DM High-Z DQS /DQS 0 (Disable) 1 (Disable) DM High-Z DQS High-Z 1 (Enable) 0 (Enable) RDQS /RDQS DQS /DQS 1 (Enable) 1 (Disable) RDQS High-Z DQS High-Z EMRS (1) Preliminary Data Sheet E0933E30 (Ver. 3.0) 36 t Notes: 1. A13 is reserved for future use, and must be programmed to 0 when setting the extended mode register. 2 When adjust mode is issued, AL from previously set value must be applied. 3. After setting to default, OCD mode needs to be exited by setting A9 to A7 to 000. Refer to the chapter Off-Chip Driver (OCD)Impedance Adjustment for detailed information. /DQS EDE5108AHBG, EDE5116AHBG DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering selfrefresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. *1 EO EMRS (2) Programming The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The extended mode register (2) is written by asserting low on CS, /RAS, /CAS, /WE, high on BA1 and low on BA0, while controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. BA1 BA0 1 A13 A12 A11 0 A10 A9 A8 0*1 A7 A6 A5 A4 A2 A1 A0 Address field Extended mode register (2) 0*1 SRF L A7 A3 High Temperature Self-refresh rate Enable 0 Disable 1 Enable Pr Note: 1 The rest bits in EMRS (2) is reserved for future use and all bits in EMRS (2) except A7, BA0 and BA1 must be programmed to 0 when setting the extended mode register (2) during initialization. EMRS(2) EMRS (3) Programming: Reserved*1 BA1 BA0 A12 A11 A10 1 A9 A8 0*1 A7 A6 A5 A4 A3 A2 A1 A0 Address Field od 1 A13 Extended Mode Register(3) Note : 1. EMRS (3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. EMRS (3) t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 37 EDE5108AHBG, EDE5116AHBG Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the OCD Flow Chart is an example of sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive(0) DQ & DQS high ; /DQS low DQ & DQS low ; /DQS high EO EMRS: Drive(1) ALL OK ALL OK Test Test Need calibration Need calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit L EMRS : EMRS : Enter Adjust Mode Enter Adjust Mode Pr BL=4 code input to all DQs BL=4 code input to all DQs Inc, Dec, or NOP Inc, Dec, or NOP od EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit OCD Flow Chart t uc End Preliminary Data Sheet E0933E30 (Ver. 3.0) 38 EDE5108AHBG, EDE5116AHBG Extended Mode Register Set for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive (0) mode, all DQ, DQS (and RDQS) signals are driven low and all /DQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics follow approximate nominal V/I curve for 18Ω output drivers, but are not guaranteed. If tighter control is required, which is controlled within 18Ω ± 3Ω driver impedance range, OCD must be used. [OCD Mode Set Program] A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive (1) DQ, DQS, (RDQS) high and /DQS low 0 1 0 Drive (0) DQ, DQS, (RDQS) low and /DQS high 1 0 0 Adjust mode 1 1 1 OCD calibration default EO A9 L OCD Impedance Adjustment To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM as in OCD Adjustment Program table. For this operation, burst length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in OCD Adjustment Program table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16-step range. [OCD Adjustment Program] Operation Pr 4bits burst data inputs to all DQs DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength 0 0 0 0 NOP NOP 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 Other combinations od DT0 NOP Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Decrease by 1 step Reserved t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 39 EDE5108AHBG, EDE5116AHBG For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the Output Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS addressing mode (i.e. sequential or interleave). /CK CK Command EMRS NOP EMRS WL NOP tWR DQS, /DQS tDS tDH DQ_in DT0 DT1 DT2 DT3 EO OCD adjust mode OCD calibration mode exit Output Impedance Control Register Set Cycle Drive Mode Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance Measurement/Verify Cycle”. CK Command L /CK NOP EMRS Pr High-Z DQS, /DQS EMRS High-Z DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0) DQs high for drive (1) DQ DQs low for drive (0) Enter drivemode od tOIT tOIT OCD Calibration mode exit Output Impedance Measurement/Verify Cycle t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 40 EDE5108AHBG, EDE5116AHBG ODT (On Die Termination) On Die Termination (ODT), is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is turned off and not supported in self-refresh mode. VDDQ VDDQ VDDQ sw3 sw2 sw1 Rval3 Rval2 Rval1 EO DRAM input buffer Input Pin Rval1 sw1 Rval2 Rval3 sw2 sw3 VSSQ VSSQ VSSQ L Switch sw1, sw2 or sw3 is enabled by ODT pin. Selection between sw1, sw2 or sw3 is determined by Rtt (nominal) in EMRS Termination included on all DQs, DM, DQS, /DQS, RDQS and /RDQS pins. Target Rtt (Ω) = (Rval1) / 2, (Rval2) / 2 or (Rval3) / 2 Pr Functional Representation of ODT /CK CK Command EMRS od tAOFD ODT NOP tIS tMOD (max.) tMOD (min.) Rtt Old setting Updating New Setting uc Note: tAOFD must be met before issuing EMRS command. ODT must remain low for the entire duration of tMOD window. ODT update Delay Timing t Preliminary Data Sheet E0933E30 (Ver. 3.0) 41 EDE5108AHBG, EDE5116AHBG /CK T0 T1 T2 T3 T4 T5 T6 CK CKE tAXPD ≤ 6tCK tIS tIS ODT tAOFD tAOND Internal Term Res. EO /CK Rtt tAON min. tAOF min. tAON max. tAOF max. ODT Timing for Active and Standby Mode T0 T1 T2 T3 T4 T5 T6 CK CKE L tAXPD ≤ 6tCK tIS tIS ODT tAOFPD max. tAOFPD min. Pr Internal Term Res. tAONPD min. Rtt tAONPD max. ODT Timing for Power-Down Mode t uc od Preliminary Data Sheet E0933E30 (Ver. 3.0) 42 EDE5108AHBG, EDE5116AHBG T-5 T-4 T-3 T-2 T-1 T0 T1 T2 T3 T4 /CK CK tANPD tIS CKE Entering slow exit active power down mode or precharge power down mode. tIS ODT Active and standby mode timings to be applied. tAOFD EO Internal Term Res. Rtt tIS ODT Power down mode timings to be applied. tAOFPD(max.) Internal Term Res. Rtt L tIS ODT tAOND Active and standby mode timings to be applied. Rtt Pr Internal Term Res. tIS ODT Power down mode timings to be applied. tAONPD(max.) od Internal Term Res. Rtt ODT Timing Mode Switch at Entering Power-Down Mode t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 43 EDE5108AHBG, EDE5116AHBG T0 T1 T4 T5 T6 T7 T8 T9 T10 T11 /CK CK tIS tAXPD CKE Exiting from slow active power down mode or precharge power down mode. tIS EO Active and standby mode timings to be applied. ODT tAOFD Internal Term Res. Rtt tIS ODT Power down mode timings to be applied. tAOFPD (max.) L Internal Term Res. Active and standby mode timings to be applied. Rtt tIS ODT tAOND Pr Internal Term Res. Rtt tIS ODT tAONPD(max.) Internal Term Res. od Power down mode timings to be applied. Rtt ODT Timing Mode Switch at Exiting Power-Down Mode t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 44 EDE5108AHBG, EDE5116AHBG Bank Activate Command [ACT] The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A13 is used to determine which row to activate in the selected bank. The Bank activate command must be applied before any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.) is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is determined by (tRRD). EO /CK T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 PRE ACT CK Command Address ACT ROW: 0 Posted READ ACT Posted READ PRE tRCD(min.) COL: 0 ROW: 1 COL: 1 ROW: 0 L tCCD Additive latency (AL) Bank0 Read begins tRRD tRAS tRP Bank0 Active Pr tRC Bank1 Active Bank0 Precharge Bank1 Precharge Bank0 Active Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2) t uc od Preliminary Data Sheet E0933E30 (Ver. 3.0) 45 EDE5108AHBG, EDE5116AHBG Read and Write Access Modes EO After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high, /CS and /CAS low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high) or a write operation (/WE low). The DDR2 SDRAM provides a fast column access operation. A single read or write command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32M bits × 4 I/O × 4 banks chip has a page length of 2048 bits (defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device during the read or write command (CA0 to CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. -1 /CK CK Command L Posted /CAS Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a /CAS read or write command to be issued immediately after the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency (RL = AL + CL). 0 1 2 ACT READ 3 4 NOP 5 6 7 8 9 11 12 11 12 NOP WRIT WL = RL – 1 = 4 Pr AL = 2 DQS, /DQS 10 CL = 3 ≥ tRCD RL = AL + CL = 5 DQ out0 out1 out2 out3 in0 in1 in2 in3 ≥ tRAC od Read Followed by a Write to the Same Bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4] -1 0 1 2 3 /CK CK ACT NOP AL = 0 READ 5 NOP CL = 3 DQS, /DQS ≥ tRCD RL = AL + CL = 3 DQ 6 7 WRIT 8 46 NOP in0 in1 in2 in3 t Read Followed by a Write to the Same Bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2] Preliminary Data Sheet E0933E30 (Ver. 3.0) 10 WL = RL – 1 = 2 out0 out1 out2 out3 ≥ tRAC 9 uc Command 4 EDE5108AHBG, EDE5116AHBG Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or Write by Write at the boundary of Burst 4. Therefore the burst stop command is not supported on DDR2 SDRAM devices. [Burst Length and Sequence] Burst length Interleave addressing (decimal) 000 0, 1, 2, 3 0, 1, 2, 3 001 1, 2, 3, 0 1, 0, 3, 2 010 2, 3, 0, 1 2, 3, 0, 1 011 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 EO Starting address (A2, A1, A0) Sequential addressing (decimal) 4 8 L t uc od Pr Note: Page length is a function of I/O organization and column addressing 16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits 8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits Preliminary Data Sheet E0933E30 (Ver. 3.0) 47 EDE5108AHBG, EDE5116AHBG Burst Read Command [READ] The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set (EMRS). T0 T1 T2 T3 T4 T5 T6 T7 T8 T7 T8 /CK CK EO Command READ NOP ≤ tDQSCK DQS, /DQS CL = 3 RL = 3 DQ out0 out1 out2 out3 L Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3)) T0 CK Command READ T1 T2 T3 T4 T5 T6 Pr /CK NOP ≤ tDQSCK CL = 3 RL = 3 DQ od DQS, /DQS out0 out1 out2 out3 out4 out5 out6 out7 Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3)) t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 48 EDE5108AHBG, EDE5116AHBG T0 T1 T2 T3 T4 T5 T6 T7 T8 /CK CK Command Posted READ NOP ≤ tDQSCK DQS, /DQS AL = 2 CL = 3 RL = 5 out0 out1 out2 out3 DQ EO Burst Read Operation (RL = 5, BL = 4 (AL = 2, CL = 3)) T0 T1 T3 T4 T5 T6 T7 T8 T9 /CK CK Command Posted READ NOP Posted WRIT NOP NOP tRTW (Read to Write = 4 clocks) L DQS, /DQS RL = 5 WL = RL - 1 = 4 out0 out1 out2 out3 DQ in0 in2 in1 in3 Pr Burst Read Followed by Burst Write (RL = 5, WL = RL-1 = 4, BL = 4) The minimum time from the burst read command to the burst write command is defined by a read-to-write-turnaround-time, which is 4 clocks. T0 T1 T2 T3 CK Command Posted READ NOP A Posted READ AL = 2 T5 T6 T7 T8 NOP B DQS, /DQS T4 od /CK uc CL = 3 RL = 5 out A0 DQ out A1 out A2 out A3 out B0 out B1 out B2 Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3) t Preliminary Data Sheet E0933E30 (Ver. 3.0) 49 EDE5108AHBG, EDE5116AHBG Enabling a read command at every other clock supports the seamless burst read operation. This operation is allowed regardless of same or different banks as long as the banks are activated. T0 T1 T2 READ NOP READ T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Command A NOP B DQS, /DQS RL = 4 out A0 EO DQ out A1 out A2 out A3 out B0 out out B1 B2 out B3 out B4 out B5 out B6 out B7 Burst interrupt is only allowed at this timing. Burst Read Interrupt by Read L Notes: 1. Read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another read command. Read burst interruption by write command or precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with auto precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another read with auto precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum read to precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 50 EDE5108AHBG, EDE5116AHBG Burst Write Command [WRIT] The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR). T0 T1 T2 T3 T4 T5 T6 T7 T9 /CK CK EO Command WRIT NOP PRE NOP ACT ≤ tDQSS DQS, /DQS ≥tWR WL = RL –1 = 2 in0 DQ in1 in2 ≥tRP in3 L Completion of the burst write Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3)) Pr T0 T1 T2 /CK CK Command WRIT T3 T4 T6 T7 T8 PRE NOP DQS, /DQS od ≤ tDQSS ≥tWR WL = RL –1 = 2 DQ T5 in0 in1 in2 in3 in4 in5 in6 T9 NOP T11 ACT ≥tRP in7 uc Completion of the burst write Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3)) t Preliminary Data Sheet E0933E30 (Ver. 3.0) 51 EDE5108AHBG, EDE5116AHBG T0 T1 T2 T3 T4 T5 T6 T7 T9 /CK CK Posted WRIT Command PRE NOP ≤ tDQSS DQS, /DQS ≥tWR WL = RL −1 = 4 in0 DQ in1 in2 in3 EO Completion of the burst write Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3)) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 /CK CK DQS, /DQS Posted READ NOP L Command Write to Read = CL - 1 + BL/2 + tWTR (2) = 6 NOP CL = 3 AL = 2 WL = RL –1 = 4 RL = 5 >tWTR = Pr in0 DQ in1 in2 in3 out0 out1 Burst Write Followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3)) The minimum number of clock from the burst write command to the burst read command is CL - 1 + BL/2 + a write to-read-turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. T1 T2 CK Command Posted WRIT A NOP Posted WRIT B od T0 /CK T3 T4 T5 T6 T7 T8 NOP WL = RL − 1 = 4 in A0 DQ in A1 in A2 uc DQS, /DQS in A3 in B0 in B1 in B2 in B3 Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4) t Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Preliminary Data Sheet E0933E30 (Ver. 3.0) 52 EDE5108AHBG, EDE5116AHBG T0 T1 T2 WRIT NOP WRIT T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Command A NOP B DQS, /DQS WL = 3 in in in in A0 A1 A2 A3 DQ in B0 in in in in in in B1 B2 B3 B4 B5 B6 in B7 EO Burst interrupt is only allowed at this timing. Write Interrupt by Write (WL = 3, BL = 8) L Notes :1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another write command. Write burst interruption by read command or precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous write command. Any other write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with auto precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another write with auto precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum write to precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end. t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 53 EDE5108AHBG, EDE5116AHBG Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles. T1 T2 T3 T4 in in T5 Tn DQS /DQS DQ in in in in in in in EO DM Write mask latency = 0 Data Mask Timing [tDQSS(min.)] L /CK CK Command tWR WRIT NOP WL tDQSS DQS, /DQS DM Pr DQ in0 in2 in3 WL [tDQSS(max.)] DQ DM od DQS, /DQS tDQSS in0 in2 in3 Data Mask Function, WL = 3, AL = 0 shown t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 54 EDE5108AHBG, EDE5116AHBG Precharge Command [PRE] The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits] BA0 BA1 Precharged Bank(s) L L L Bank 0 only L H L Bank 1 only L L H Bank 2 only L H H Bank 3 only H × × All banks 0 to 3 EO A10 Remark: H: VIH, L: VIL, ×: VIH or VIL Burst Read Operation Followed by Precharge Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks For the earliest possible precharge, the precharge command may be issued on the rising edge that is “Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. T0 T1 T2 T3 T4 T5 T6 T7 T8 L /CK CK Command Posted READ NOP PRE ACT NOP NOP AL + BL/2 clocks Pr DQS, /DQS AL = 1 ≥tRP CL = 3 RL = 4 out0 DQ out1 out2 out3 ≥tRAS Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3)) T1 T2 T3 CK Command Posted READ od T0 /CK NOP T4 T5 T6 NOP PRE AL + /BL2 clocks ACT T8 NOP uc DQS, /DQS AL = 2 T7 ≥ tRP CL = 3 RL = 5 DQ out0 ≥ tRAS(min.) out1 out2 out3 Preliminary Data Sheet E0933E30 (Ver. 3.0) 55 t Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3)) EDE5108AHBG, EDE5116AHBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 /CK CK Command Posted READ NOP NOP PRE NOP ACT AL + BL/2 Clocks DQS, /DQS ≥ tRP CL = 4 AL = 2 RL = 6 out0 DQ out1 out2 out3 out4 out5 out6 out7 ≥ tRAS(min.) Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4, BL=8)) L EO t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 56 EDE5108AHBG, EDE5116AHBG Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR2 SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4. T0 T1 T2 T3 T4 T5 T6 T7 T8 /CK CK Command Posted WRIT NOP PRE EO ≥ tWR DQS, /DQS WL = 3 in0 DQ in2 in3 Completion of the burst write Burst Write Followed by Precharge (WL = (RL-1) =3) L T0 in1 T1 T2 T3 T4 T5 T6 T7 T9 /CK CK DQS, /DQS Posted WRIT Pr Command PRE NOP ≥ tWR WL = 4 od in0 DQ in1 in2 in3 Completion of the burst write Burst Write Followed by Precharge (WL = (RL-1) = 4) t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 57 EDE5108AHBG, EDE5116AHBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 /CK CK Command Posted WRIT NOP PRE ≥ tWR DQS, /DQS WL = 4 in0 DQ in1 in2 in3 in4 in5 in6 in7 Burst Write Followed by Precharge (WL = (RL-1) = 4,BL= 8) L EO Completion of the burst write t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 58 EDE5108AHBG, EDE5116AHBG Auto Precharge Operation EO Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR2 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto precharge function is engaged. During auto precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. L Burst Read with Auto Precharge [READA] If A10 is high when a Read Command is issued, the Read with Auto Precharge function is engaged. The DDR2 SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with AP command when tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point of auto precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. T0 T1 T2 T3 T4 T5 T6 T7 Tn /CK CK Posted READ Pr Command A10 = 1 NOP ACT NOP ACT AL + BL/2 DQS, /DQS AL = 2 ≥ tRP CL = 3 RL = 5 od out0 out1 out2 out3 DQ tRC (min.) Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit) (RL = 5, BL = 4 (AL = 2, CL = 3, tRTP ≤ 2tCK)) t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 59 EDE5108AHBG, EDE5116AHBG T-1 T0 T1 T2 T3 T4 T5 T6 T7 Tn /CK CK A10 = 1 Posted READ Command NOP ACT ≥ tRAS(min.) DQS, /DQS ≥ tRP CL = 3 AL = 2 RL = 5 out0 DQ out2 out1 out3 tRC (min.) EO Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRAS lockout case) (RL = 5, BL = 4 (AL = 2, CL = 3)) T0 T1 T2 T3 T4 T5 T6 T7 T8 /CK CK A10 = 1 L Command Posted READ ACT NOP NOP ≥ tRAS(min.) DQS, /DQS tRP (min.) AL = 2 CL = 3 Pr RL = 5 DQ out0 out1 out2 out3 ≥tRC Auto precharge begins T0 T1 T2 od Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit) (RL = 5, BL = 4 (AL = 2, CL = 3, tRTP ≤ 2tCK)) T3 T4 CK /CK A10 = 1 Command T5 T6 T7 T8 NOP READ DQS, /DQS AL = 2 CL = 3 T10 T11 ACT uc ≥tRAS (min.) T9 ≥tRP RL = 5 out0 out1 out2 out3 out4 out5 out6 out7 DQ ≥tRC Preliminary Data Sheet E0933E30 (Ver. 3.0) 60 t Auto precharge begins Burst Read with Auto Precharge Followed by an Activation to the Same Bank (RL = 5, BL = 8 (AL = 2, CL = 3, tRTP ≤ 2tCK)) EDE5108AHBG, EDE5116AHBG Burst Write with Auto Precharge [WRITA] If A10 is high when a write command is issued, the Write with auto precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time (tWR). The bank undergoing auto precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. T0 T1 T2 T3 T4 T5 T6 T7 Tm /CK CK A10 = 1 Posted WRIT NOP EO Command ACT DQS, /DQS ≥tWR WL = RL –1 = 2 in0 DQ in1 in2 ≥ tRP in3 tRC (min.) L Completion of the burst write Auto precharge begins Burst Write with Auto Precharge (tRC Limit) (WL = 2, tWR =2) T0 T3 CK Command DQS, /DQS A10 = 1 Posted WRIT NOP T4 T5 T6 T7 T8 T9 T10 T11 Pr /CK NOP in0 od tWR (min.) WL = RL –1 = 4 DQ ACT in1 in2 tRP (min.) in3 ≥ tRC Completion of the burst write Auto precharge begins Burst Write with Auto Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3) t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 61 EDE5108AHBG, EDE5116AHBG T0 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK A10 = 1 Command NOP WRIT ACT DQS, /DQS WL = RL − 1 = 4 ≥tWR in0 DQ in1 in2 in3 in4 in5 in6 ≥tRP in7 ≥tRC EO Auto precharge begins Burst Write with Auto Precharge Followed by an Activation to the Same Bank (WL = 4, BL = 8, tWR = 2, tRP = 3) L t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 62 EDE5108AHBG, EDE5116AHBG Refresh Requirements DDR2 SDRAM requires a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit automatic refresh command, or by an internally timed event in self-refresh mode. Dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing. Automatic Refresh Command [REF] EO When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the auto-refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the auto-refresh command (REF) and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto-refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any refresh command and the next Refresh command is 9 × tREFI. T0 T1 T2 T3 /CK CK VIH ≥ tRP L CKE Command PRE NOP ≥ tRFC ≥ tRFC REF NOP REF Any Command Automatic Refresh Command t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 63 EDE5108AHBG, EDE5116AHBG Self Refresh Command [SELF] The DDR2 SDRAM device has a built-in timer to accommodate self-refresh operation. The self-refresh command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. ODT must be turned off before issuing self-refresh command, by either driving ODT pin low or using EMRS command. Once the command is registered, CKE must be held low to keep the device in self-refresh mode. When the DDR2 SDRAM has entered self-refresh mode all of the external signals except CKE, are “don’t care”. The clock is internally disabled during self-refresh operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. Once self-refresh exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire self-refresh exit period tXSRD for proper operation. NOP or deselect commands must be registered on each positive clock edge during the self-refresh exit interval. ODT should also be turned off during tXSRD. EO T0 T1 T2 T3 T4 T5 T6 Tm Tn tCK tCH tCL /CK CK ≥ tXSNR tRP* ≥ tXSRD CKE L ODT tIS tIS tAOFD Pr tIS tIS tIH Comand SELF NOP NOP NOP Valid od Notes: 1. Device must be in the “All banks idle” state prior to entering self refresh mode. 2. ODT must be turned off tAOFD before entering self refresh mode, and can be turned on again when tXSRD timing is satisfied. 3. tXSRD is applied for a read or a read with autoprecharge command. 4. tXSNR is applied for any command except a read or a read with autoprecharge command. Self Refresh Command t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 64 EDE5108AHBG, EDE5116AHBG Power-Down [PDEN] EO Power-down is synchronously entered when CKE is registered low (along with NOP or deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power-down. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active powerdown. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC Characteristics table of this data sheet. CK /CK tIS tIH tIS tIH tIH tIS tIH tIS tIH CKE L VALID Command NOP NOP tCKE min VALID VALID VALID tXP, tXARD, tXARDS Pr tCKE min Enter power-down mode VIH or VIL Exit power-down mode Power Down Read to Power-Down Entry T0 T1 T2 Command Tx Tx+1 Tx+2 CKE DQS /DQS AL + CL DQ Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 T2 Tx out 0 Tx+1 out 1 out 2 Tx+2 out 3 Tx+3 READ Tx+4 Tx+5 BL=4 uc Command T1 Tx+4 Read operation starts with a read command and CKE should be kept high until the end of burst operation. READ VIH T0 Tx+3 od /CK CK Tx+6 Tx+7 Tx+8 Tx+9 CKE should be kept high until the end of burst operation. VIH CKE DQS /DQS out 0 out out 1 2 out 3 out 4 Preliminary Data Sheet E0933E30 (Ver. 3.0) 65 out out 5 6 out 7 t AL + CL DQ BL=8 EDE5108AHBG, EDE5116AHBG Read with Auto Precharge to Power-Down Entry T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 /CK CK Command READA PRE AL + BL/2 with tRTP = 7.5ns and tRAS min. satisfied BL=4 CKE CKE should be kept high until the end of burst operation. DQS /DQS AL + CL DQ EO T0 Command T1 T2 Tx out 0 out 1 Tx+1 out 2 Tx+2 out 3 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge READA BL=8 AL + BL/2 with tRTP = 7.5ns and tRAS min. satisfied PRE CKE should be kept high until the end of burst operation. CKE DQS /DQS AL + CL L DQ out 0 out 1 out 2 out 3 out 4 out out 5 6 out 7 Write to Power-Down Entry T1 /CK CK Command WRIT CKE Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Pr T0 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 tWTR DQS WL in 0 DQ T0 Command T1 Tm in 1 Tm+1 in 2 in 3 od /DQS Tm+2 Tm+3 WRIT Tm+4 Tm+5 Tx+1 Tx+2 Tx+3 Tx+4 uc CKE Tx BL=4 tWTR DQS /DQS WL DQ in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 BL=8 t Preliminary Data Sheet E0933E30 (Ver. 3.0) 66 EDE5108AHBG, EDE5116AHBG Write with Auto Precharge to Power-Down Entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 /CK CK Command WRITA PRE CKE WR*1 DQS /DQS WL in 0 DQ EO T0 T1 Tm in 1 Tm+1 in 2 BL=4 in 3 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 /CK CK Command WRITA PRE CKE DQS /DQS WL L DQ WR*1 in 0 in 1 in 2 in 3 in 4 in 5 in 6 BL=8 in 7 Note: 1. WR is programmed through MRS t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 67 EDE5108AHBG, EDE5116AHBG Refresh command to Power-Down Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 /CK CK Command REF CKE can go to low one clock after an auto-refresh command CKE Active command to power-down entry EO Command ACT CKE can go to low one clock after an active command CKE L Precharge/Precharge all command to power-down entry PRE or PALL Pr Command CKE can go to low one clock after a precharge or precharge all command CKE Command MRS or EMRS uc od MRS/EMRS command to power-down entry CKE tMRD t Preliminary Data Sheet E0933E30 (Ver. 3.0) 68 EDE5108AHBG, EDE5116AHBG Asynchronous CKE Low Event DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet. If CKE asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised high again. DRAM must be fully re-initialized (steps 4 through 13) as described in initialization sequence. DRAM is ready for normal operation after the initialization sequence. See AC Characteristics table for tDELAY specification Stable clocks tCK /CK CK EO CKE tDELAY CKE asynchronously drops low Clocks can be turned off after this point L t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 69 EDE5108AHBG, EDE5116AHBG Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power-down mode. ODT must be turned off and CKE must be at logic low level. A minimum of 2 clocks must be waited after CKE goes low before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable low levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power-down may be exited and DLL must be RESET via EMRS after precharge power-down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL and soon. During DLL relock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. Clock Frequency Change in Precharge Power Down Mode EO T0 T1 T2 NOP NOP T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4 Tz /CK CK Command NOP CKE DLL RESET Frequency change occurs here NOP Valid 200 clocks L ODT NOP tRP tXP tAOFD ODT is off during DLL RESET Minmum 2 clocks required before changing frequency Stable new clock before power down exit Pr Burst Interruption Interruption of a burst read or write cycle is prohibited. od No Operation Command [NOP] The no operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The purpose of the no operation command is to prevent the DDR2 SDRAM from registering any unwanted commands between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command [DESL] The deselect command performs the same function as a no operation command. Deselect Command occurs when /CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares. t uc Preliminary Data Sheet E0933E30 (Ver. 3.0) 70 EDE5108AHBG, EDE5116AHBG Package Drawing 60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Unit: mm 10.0 ± 0.1 0.2 S B INDEX MARK 10.5 ± 0.1 EO L 0.2 S A 0.2 S 1.20 max. S Pr 0.35 ± 0.05 0.1 S 60-φ0.45 ± 0.05 B φ0.15 M S A B 0.8 od 8.0 A INDEX MARK uc 1.6 6.4 0.8 t ECA-TS2-0181-01 Preliminary Data Sheet E0933E30 (Ver. 3.0) 71 EDE5108AHBG, EDE5116AHBG 84-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Unit: mm 10.0 ± 0.1 0.2 S B EO 12.5 ± 0.1 INDEX MARK L 0.2 S A 0.2 S 1.20 max. S Pr 0.1 S 0.35 ± 0.05 B 84-φ0.45 ± 0.05 φ0.15 M S A B 0.8 od 11.2 A 1.6 0.8 t 6.4 uc INDEX MARK ECA-TS2-0182-01 Preliminary Data Sheet E0933E30 (Ver. 3.0) 72 EDE5108AHBG, EDE5116AHBG Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDE51XXAHBG. Type of Surface Mount Device EDE5108AHBG: 60-ball FBGA < Lead free (Sn-Ag-Cu) > EDE5116AHBG: 84-ball FBGA < Lead free (Sn-Ag-Cu) > L EO t uc od Pr Preliminary Data Sheet E0933E30 (Ver. 3.0) 73 EDE5108AHBG, EDE5116AHBG NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. EO 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. L 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Pr Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 t uc od Preliminary Data Sheet E0933E30 (Ver. 3.0) 74 EDE5108AHBG, EDE5116AHBG The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 t uc od Preliminary Data Sheet E0933E30 (Ver. 3.0) 75