AD AD6645/PCB 14-bit, 80 msps a/d converter Datasheet

a
14-Bit, 80 MSPS
A/D Converter
AD6645
generation in a wideband ADC family, preceded by the
AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS,
IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).
FEATURES
80 MSPS Guaranteed Sample Rate
SNR = 75 dB, fIN 15 MHz @ 80 MSPS
SNR = 72 dB, fIN 200 MHz @ 80 MSPS
SFDR = 89 dBc, fIN 70 MHz @ 80 MSPS
100 dB Multitone SFDR
IF Sampling to 200 MHz
Sampling Jitter 0.1 ps
1.5 W Power Dissipation
Differential Analog Inputs
Pin-Compatible to AD6644
Two’s Complement Digital Output Format
3.3 V CMOS-Compatible
DataReady for Output Latching
Designed for multichannel, multimode receivers, the AD6645 is
part of Analog Device’s SoftCell™ transceiver chipset. The
AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode
digital receivers (software radios) that are typically limited by
the ADC. Noise performance is exceptional; typical signal-tonoise ratio is 74.5 dB through the first Nyquist band.
The AD6645 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are available in a thermally enhanced 52lead PowerQuad 4® (LQFP_ED) specified from –40∞C to +85∞C.
APPLICATIONS
Multichannel, Multimode Receivers
Base Station Infrastructure
AMPS, IS-136, CDMA, GSM, WCDMA
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation
PRODUCT HIGHLIGHTS
1. IF Sampling
The AD6645 maintains outstanding ac performance up to
input frequencies of 200 MHz. Suitable for multicarrier 3G
wideband cellular IF sampling receivers.
2. Pin Compatibility
The ADC has the same footprint and pin layout as the
AD6644, 14-Bit 40 MSPS/65 MSPS ADC.
PRODUCT DESCRIPTION
3. SFDR Performance and Oversampling
Multitone SFDR performance of –100 dBc can reduce the
requirements of high-end RF components and allows the use
of receive signal processors such as the AD6620 or AD6624/
AD6624A.
The AD6645 is a high-speed, high-performance, monolithic
14-bit analog-to-digital converter. All necessary functions,
including track-and-hold (T/H) and reference, are included on
the chip to provide a complete conversion solution. The AD6645
provides CMOS-compatible digital outputs. It is the fourth
FUNCTIONAL BLOCK DIAGRAM
DVCC
AVCC
AD6645
AIN
AIN
A1
TH1
TH2
A2
ADC1
VREF
TH3
TH4
DAC1
TH5
ADC2
ENCODE
6
DAC2
2.4V
5
ENCODE
ADC3
5
INTERNAL
TIMING
GND
DIGITAL ERROR CORRECTION LOGIC
DMID
OVR
DRY
D13
MSB
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
SoftCell is a trademark of Analog Devices, Inc.
PowerQuad 4 is a registered trademark of Amkor Technology, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD6645–SPECIFICATIONS
DC SPECIFICATIONS (AV
CC
= 5 V, DVCC = 3.3 V; TMIN = –40ⴗC, TMAX = +85ⴗC, unless otherwise noted.)
Parameter
Temp
Test Level
Min
AD6645ASQ-80
Typ
RESOLUTION
Max
14
Unit
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Full
Full
Full
Full
Full
II
II
II
II
V
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
V
V
1.5
48
ppm/∞C
ppm/∞C
POWER SUPPLY REJECTION (PSRR)
25∞C
V
± 1.0
mV/V
REFERENCE OUT (VREF)1
Full
V
2.4
V
ANALOG INPUTS (AIN, AIN)
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
Full
Full
25∞C
V
V
V
2.2
1
1.5
V p-p
kW
pF
Full
Full
II
II
Full
Full
II
II
Full
IV
Full
II
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
I AVCC (AVCC = 5.0 V)
I DVCC (DVCC = 3.3 V)
Rise Time2
AVCC
POWER CONSUMPTION
Guaranteed
+1.2
0
± 0.25
± 0.5
–10
–10
–1.0
4.75
3.0
+10
+10
+1.5
mV
% FS
LSB
LSB
5.0
3.3
5.25
3.6
V
V
275
32
320
45
mA
mA
TBD
ms
1.75
W
1.5
NOTES
1
VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.
2
Specified for dc supplies with linear rise-time characteristics. The use of dc supplies with linear rise-times of <45 ms is highly recommended.
Specifications subject to change without notice
DIGITAL SPECIFICATIONS (AV
CC
= 5 V, DVCC = 3.3 V; TMIN = –40ⴗC, TMAX = +85ⴗC, unless otherwise noted.)
Parameter (Conditions)
Temp
Test Level
Min
ENCODE INPUTS (ENC, ENC)
Differential Input Voltage1
Differential Input Resistance
Differential Input Capacitance
Full
25∞C
25∞C
IV
V
V
0.4
II
II
2.85
LOGIC OUTPUTS (D13–D0, DRY, OVR2)
Logic Compatibility
Full
Logic “1” Voltage (DVCC = 3.3 V)3
Logic “0” Voltage (DVCC = 3.3 V)3
Full
Output Coding
DMID
Full
AD6645ASQ-80
Typ
Max
10
2.5
V
CMOS
DVCC – 0.2
0.2
0.5
Two’s Complement
DVCC /2
Unit
V p-p
kW
pF
V
V
V
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially.
2
The functionality of the Over-Range bit is specified for a temperature range of 25 ∞C to 85∞C only.
3
Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads >10 pF will degrade performance.
Specifications subject to change without notice.
–2–
REV. 0
AD6645
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40ⴗC, TMAX = +85ⴗC, unless
AC SPECIFICATIONS1 otherwise noted.)
Parameter (Conditions)
Temp
Test Level
15.5 MHz
30.5 MHz
70.0 MHz
150.0 MHz
200.0 MHz
25∞C
25∞C
25∞C
25∞C
25∞C
V
II
II
V
V
15.5 MHz
30.5 MHz
70.0 MHz
150.0 MHz
200.0 MHz
25∞C
25∞C
25∞C
25∞C
25∞C
V
II
V
V
V
WORST HARMONIC (2nd or 3rd)
Analog Input
15.5 MHz
@ –1 dBFS
30.5 MHz
70.0 MHz
150.0 MHz
200.0 MHz
25∞C
25∞C
25∞C
25∞C
25∞C
V
II
V
V
V
WORST HARMONIC (4th or HIGHER)
Analog Input
15.5 MHz
@ –1 dBFS
30.5 MHz
70.0 MHz
150.0 MHz
200.0 MHz
25∞C
25∞C
25∞C
25∞C
25∞C
V
II
V
V
V
TWO TONE SFDR @ 30.5 MHz2, 3
55.0 MHz2, 4
25∞C
25∞C
TWO TONE IMD REJECTION3, 4
F1, F2 @ –7 dBFS
ANALOG INPUT BANDWIDTH
SNR
Analog Input
@ –1 dBFS
SINAD
Analog Input
@ –1 dBFS
Min
AD6645ASQ-80
Typ
Max
Unit
75.0
74.5
73.5
73.0
72.0
dB
dB
dB
dB
dB
75.0
74.5
73.0
68.5
62.5
dB
dB
dB
dB
dB
93.0
93.0
89.0
70.0
63.5
dBc
dBc
dBc
dBc
dBc
96.0
95.0
90.0
90.0
88.0
dBc
dBc
dBc
dBc
dBc
V
V
100
100
dBFS
dBFS
25∞C
V
90
dBc
25∞C
V
270
MHz
72.5
72.0
72.5
85.0
85.0
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially.
2
Analog input signal power swept from –10 dBFS to –100 dBFS.
3
F1 = 30.5 MHz, F2 = 31.5 MHz.
4
F1 = 55.25 MHz, F2 = 56.25 MHz.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40ⴗC, TMAX = +85ⴗC, unless
otherwise noted.)
Parameter (Conditions)
Temp
Test Level
Min
Maximum Conversion Rate
Minimum Conversion Rate
ENCODE Pulsewidth High (tENCH)*
ENCODE Pulsewidth Low (tENCL)*
Full
Full
Full
Full
II
IV
IV
IV
80
Max
30
5.625
5.625
*Several timing parameters are a function of t ENCL and tENCH.
Specifications subject to change without notice.
REV. 0
AD6645ASQ-80
Typ
–3–
Unit
MSPS
MSPS
ns
ns
AD6645
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40ⴗC,
TMAX = +85ⴗC, CLOAD = 10 pF, unless otherwise noted.)
SWITCHING SPECIFICATIONS (continued)
Parameter (Conditions)
Name
Temp
Test Level
Min
tENC
tENCH
tENCL
Full
Full
Full
V
V
V
ENCODE/DataReady
Encode Rising to DataReady Falling
Encode Rising to DataReady Rising
@ 80 MSPS (50% Duty Cycle)
tDR
tE_DR
Full
Full
Full
V
V
V
1.0
ENCODE/DATA (D13:0), OVR
ENC to DATA Falling Low
ENC to DATA Rising Low
ENCODE to DATA Delay (Hold Time)3
ENCODE to DATA Delay (Setup Time)4
Encode = 80 MSPS (50% Duty Cycle)
tE_FL
tE_RL
tH_E
tS_E
Full
Full
Full
Full
Full
V
V
V
V
V
2.4
1.4
1.4
Full
V
AD6645ASQ-80
Typ
Max
Unit
1
ENCODE Input Parameters
Encode Period1 @ 80 MSPS
Encode Pulsewidth High2 @ 80 MSPS
Encode Pulsewidth Low @ 80 MSPS
12.5
6.25
6.25
7.3
5.3
ns
ns
ns
2.0
tENCH + tDR
8.3
3.1
4.7
3.0
3.0
tENC – tE_FL
7.6
7.0
4.7
4.7
9.4
10.0
ns
ns
ns
ns
ns
ns
ns
ns
5
DataReady (DRY )/DATA, OVR
DataReady to DATA Delay (Hold Time)2
Encode = 80 MSPS (50% Duty Cycle)
DataReady to DATA Delay (Setup Time)2
Encode = 80 MSPS (50% Duty Cycle)
tH_DR
Note 6
7.2
Note 6
3.6
6.6
tS_DR
Full
V
2.1
ns
7.9
ns
5.1
APERTURE DELAY
tA
25∞C
V
–500
ps
APERTURE UNCERTAINTY (Jitter)
tJ
25∞C
V
0.1
ps rms
NOTES
1
Several timing parameters are a function of t ENC and tENCH.
2
To compensate for a change in duty cycle for t H_DR and tS_DR use the following equation:
NewtH_DR = (tH_DR – % Change(tENCH))
NewtS_DR = (tS_DR – % Change(t ENCH))
3
ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the Analog-to-Digital Converter, t E_RL = tH_E.
4
ENCODE TO DATA Delay (Setup Time) is calculated relative to 80 MSPS (50% duty cycle). To calculate t S_E for a given encode, use the following equation:
NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: Newt S_E(TYP) = 25 ¥ 10–9 – 15.38 ¥ 10–9 + 9.8 ¥ 10–9 = 19.4 ¥ 10 –9).
5
DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.
6
DataReady to DATA Delay (t H_DR and tS_DR) is calculated relative to 80 MSPS (50% duty cycle) and is dependent on t ENC and duty cycle. To calculate t H_DR and
tS_DR for a given encode, use the following equations:
NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 7.2 ¥ 10–9 = 13.45 ¥ 10–9
NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 3.6 ¥ 10–9 = 9.85 ¥ 10–9
Specifications subject to change without notice.
tA
N+3
N
AIN
N+1
N+2
t ENCH
t ENC
ENC, ENC
t E_RL
D[13:0], OVR
N
t ENCL
N+4
N+1
N+2
t E_FL
N+3
t E_DR
N–3
N–2
N–1
t S_DR
DRY
N+4
t S_E
t H_E
N
t H_DR
t DR
Figure 1. Timing Diagram
–4–
REV. 0
AD6645
ABSOLUTE MAXIMUM RATINGS*
Parameter
ELECTRICAL
AVCC Voltage
DVCC Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage
Digital Output Current
Min
Max
Unit
0
0
0
7
7
AVCC
25
AVCC
4
V
V
V
mA
V
mA
+85
150
300
+150
∞C
∞C
∞C
∞C
0
ENVIRONMENTAL
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
–40
–65
*Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability
of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute
maximum rating conditions for an extended period of time may affect device reliability.
THERMAL CHARACTERISTICS
52-Lead PowerQuad 4 . . . . . . . . . . . . . . . . . . . . . . LQFP_ED
JA = 23∞C/W . . . . . . . . . . . . . . . Soldered Slug, No Airflow
JA = 17∞C/W . . . . . . . . Soldered Slug, 200 LFPM Airflow
JA = 30∞C/W . . . . . . . . . . . . . Unsoldered Slug, No Airflow
JA = 24∞C/W . . . . . . Unsoldered Slug, 200 LFPM Airflow
JC = 2∞C/W . . . . . . . . . . . . . Bottom of Package (Heatslug)
Typical Four-Layer JEDEC Board Horizontal Orientation
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25∞C and guaranteed by design
and characterization at temperature extremes.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
ORDERING GUIDE
Model
Temperature Range
Package Description
AD6645ASQ-80
AD6645/PCB
–40∞C to +85∞C (Ambient)
25∞C
52-Lead PowerQuad 4 (LQFP_ED) SQ-52
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6645 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
Package Option
WARNING!
ESD SENSITIVE DEVICE
AD6645
D5
D4
D6
DVCC
GND
D7
D9
D8
D11
D10
D12
DRY
D13 (MSB)
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
DVCC 1
GND 2
VREF 3
39 D3
PIN 1
IDENTIFIER
38 D2
37 D1
GND 4
36 D0 (LSB)
35 DMID
ENC 5
ENC 6
AD6645
34 GND
GND 7
TOP VIEW
(Not to Scale)
33 DVCC
32 OVR
AVCC 8
AVCC 9
31 DNC
GND 10
AIN 11
30 AV
CC
29 GND
AIN 12
GND 13
28 AV
CC
27 GND
GND
AVCC
GND
C2
C1
GND
AVCC
GND
GND
AVCC
GND
AVCC
AVCC
14 15 16 17 18 19 20 21 22 23 24 25 26
DNC = DO NOT CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 33, 43
DVCC
3.3 V Power Supply (Digital) Output Stage Only
2, 4, 7, 10, 13,
15, 17, 19, 21,
23, 25, 27, 29,
34, 42
GND
Ground
3
VREF
2.4 V Reference. Bypass to ground with a 0.1 mF microwave chip capacitor.
5
ENC
Encode Input. Conversion initiated on rising edge.
6
ENC
Complement of ENC, Differential Input
8, 9, 14, 16, 18, AVCC
22, 26, 28, 30
5 V Analog Power Supply
11
AIN
Analog Input
12
AIN
Complement of AIN, Differential Analog Input
20
C1
Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor.
24
C2
Internal Voltage Reference. Bypass to ground with a 0.1 mF chip capacitor.
31
DNC
Do not connect this pin.
32
OVR*
Over-Range Bit. A logic-level high indicates analog input exceeds ± FS.
35
DMID
Output Data Voltage Midpoint. Approximately equal to (DVCC)/2.
36
D0 (LSB)
Digital Output Bit (Least Significant Bit); Two’s Complement
37–41, 44–50
D1–D5, D6–D12
Digital Output Bits in Two’s Complement
51
D13 (MSB)
Digital Output Bit (Most Significant Bit); Two’s Complement
52
DRY
DataReady Output
*The functionality of the Over-Range bit is specified for a temperature range of 25∞C to 85∞C only.
–6–
REV. 0
AD6645
Minimum Conversion Rate
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
Aperture Delay
The encode rate at which parametric testing is performed.
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Noise (For Any Range Within the ADC)
Ê FS dBm – SNR dBc - Signal dBFS ˆ
Á
˜
¯
10
VNOISE = | Z | ¥ 0.001 ¥ 10 Ë
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180 degrees and taking the peak measurement
again. Then the difference is computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these
specs define an acceptable ENCODE duty cycle.
Expressed in dBm. Computed using the following equation:
PowerFull Scale
È V 2Full Scale rms
Í
| Z |Input
= 10 log Í
Í 0.001
Í
ÍÎ
ù
ú
ú
ú
ú
úû
nd
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, 3 rd
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
REV. 0
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Power Supply Rise Time
The time from when the dc supply is initiated, until the supply
output reaches the minimum specified operating voltage for the
ADC. The dc level is measured at supply pin(s) of the ADC.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
Full-Scale Input Power
Harmonic Distortion, 2
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question; SNR is the value for the particular
input level; and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (i.e.,
degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Two Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
–7–
AD6645
EQUIVALENT CIRCUITS
DVCC
VCH AVCC
AIN
CURRENT
MIRROR
T/H
BUF
500⍀
VCL
VREF
BUF
VCH AVCC
500⍀
AIN
DVCC
T/H
BUF
D0–D13,
OVR, DRY
VREF
VCL
Figure 2. Analog Input Stage
LOADS
AVCC
AVCC
AVCC
AVCC
10k⍀
CURRENT
MIRROR
10k⍀
ENC
ENC
10k⍀
10k⍀
Figure 5. Digital Output Stage
AVCC
AVCC
LOADS
2.4V
Figure 3. Encode Inputs
VREF
AVCC
100␮A
Figure 6. 2.4 V Reference
VREF
AVCC
DVCC
AVCC
10k⍀
DMID
CURRENT
MIRROR
10k⍀
C1, C2
Figure 4. Compensation Pin, C1 or C2
Figure 7. DMID Reference
–8–
REV. 0
Typical Performance Characteristics–AD6645
0
0
ENCODE = 80MSPS
AIN = 2.2MHz @ –1dBFS
SNR = 75.0dB
SFDR = 93.0dBc
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
dBFS
dBFS
–20
–70
–70
–80
–90
2
–100
–80
3
–90
5
6
4
–110
–120
–120
5
10
15
20
25
FREQUENCY – MHz
30
35
–130
40
6
0
TPC 1. Single Tone @ 2.2 MHz
15
20
25
FREQUENCY – MHz
30
35
40
ENCODE = 80MSPS
AIN = 150MHz @ –1dBFS
SNR = 73.0dB
SFDR = 70.0dBc
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
dBFS
dBFS
10
0
ENCODE = 80MSPS
AIN = 15.5MHz @ –1dBFS
SNR = 75.0dB
SFDR = 93.0dBc
–20
–70
–80
3
–70
2
–80
–90
–90
3
5
–100
6
4
5
6
–100
2
4
–110
–110
–120
–120
–130
–130
0
0
5
10
15
20
25
FREQUENCY – MHz
30
35
40
TPC 2. Single Tone @ 15.5 MHz
10
15
20
25
FREQUENCY – MHz
30
35
40
35
40
0
ENCODE = 80MSPS
AIN = 29.5MHz @ –1dBFS
SNR = 74.5dB
SFDR = 93.0dBc
–20
–10
–20
–30
–40
–40
–50
–50
–60
–60
dBFS
–30
–70
–80
–70
ENCODE = 80MSPS
AIN = 200MHz @ –1dBFS
SNR = 72.0dB
SFDR = 64.0dBc
3
2
–80
–90
3
6
4
–110
–120
–120
5
10
15
20
25
FREQUENCY – MHz
30
35
6
5
–100
–110
0
4
–90
2
5
–100
–130
5
TPC 5. Single Tone @ 150 MHz
0
–10
dBFS
5
4
5
TPC 4. Single Tone @ 69.1 MHz
0
–10
–130
0
40
TPC 3. Single Tone @ 29.5 MHz
REV. 0
3
2
–100
–110
–130
0
ENCODE = 80MSPS
AIN = 69.1MHz @ –1dBFS
SNR = 73.5dB
SFDR = 89.0dBc
–10
5
10
15
20
25
FREQUENCY – MHz
30
TPC 6. Single Tone @ 200 MHz
–9–
AD6645
75.5
100
95
75.0
T = –40 C
WORST OTHER SPUR
90
HARMONICS – dBc
74.5
SNR – dB
T = +85 C
74.0
T = +25 C
73.5
73.0
0
10
20
30
40
FREQUENCY – MHz
50
60
60
70
TPC 7. Noise vs. Analog Frequency
WORST CASE SPURIOUS – dBFS AND dBc
T = +25 C
90
T = –40 C, +85 C
88
86
84
82
20
40
60
80
100 120 140
ANALOG FREQUENCY – MHz
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = –40 C, +25 C, +85 C
0
10
20
30
40
50
ANALOG INPUT FREQUENCY – MHz
60
110
160
180
200
dBFS
100
90
ENCODE = 80MSPS
AIN = 30.5MHz
80
70
dBc
60
50
SFDR = 90dB
REFERENCE LINE
40
30
20
10
0
–90
70
TPC 8. Harmonics vs. Analog Frequency
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT POWER LEVEL – dBFS
–10
0
TPC 11. Single Tone SFDR @ 30.5 MHz
76
WORST CASE SPURIOUS – dBFS AND dBc
120
75
74
SNR – dB
0
120
92
73
72
71
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = 25 C
70
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = 25 C
TPC 10. Harmonics vs. Analog Frequency (IF)
94
WORST CASE HARMONIC – dBc
HARMONICS (2ND, 3RD)
75
65
ENCODE = 80MSPS @ AIN = –1dBFS
TEMP = –40 C, +25 C, +85 C
80
80
70
72.5
72.0
85
0
20
40
60
80
100 120 140
ANALOG FREQUENCY – MHz
160
180
110
dBFS
100
90
80
ENCODE = 80MSPS
AIN = 69.1MHz
70
dBc
60
50
SFDR = 90dB
REFERENCE LINE
40
30
20
10
0
–90
200
TPC 9. Noise vs. Analog Frequency (IF)
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT POWER LEVEL – dBFS
–10
0
TPC 12. Single Tone SFDR @ 69.1 MHz
–10–
REV. 0
AD6645
0
ENCODE = 80MSPS
–10 AIN = 30.5MHz,
–20 31.5MHz (–7dBFS)
NO DITHER
–30
0
ENCODE = 80MSPS
–10 AIN = 55.25MHz,
56.25MHz (–7dBFS)
–20
NO DITHER
–30
–40
–40
–50
–60
2
F
1
+
F
2
–70 F
2
–80 –
F
–90
1
–100
2
F
2
+
F
1
2
F
1
–
F
2
F
1
+
F
2
dBFS
dBFS
–50
2
F
2
–
F
1
–60
F
–80 2
–
–90 F
–100 1
–120
–120
–130
0
–130
0
5
10
15
20
25
FREQUENCY – MHz
30
35
40
TPC 13. Two Tones @ 30.5 MHz and 31.5 MHz
WORST CASE SPURIOUS – dBFS AND dBc
WORST CASE SPURIOUS – dBFS AND dBc
dBFS
90
ENCODE = 80MSPS
F1 = 30.5MHz
F2 = 31.5MHz
70
dBc
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
–67
–57
–47
–37
–27
–17
INPUT POWER LEVEL – F1 = F2 dBFS
5
10
15
20
25
FREQUENCY – MHz
30
35
40
dBFS
90
80
70
ENCODE = 80MSPS
F1 = 55.25MHz
F2 = 56.25MHz
dBc
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
–67
–57
–47
–37
–27
–17
INPUT POWER LEVEL – F1 = F2 dBFS
–7
TPC 17. Two Tone SFDR @ 55.25 MHz and 56.25 MHz
100
95
WORST SPUR @ AIN = 2.2MHz
95
SNR, WORST CASE SPURIOUS – dB
AND dBc
SNR, WORST CASE SPURIOUS – dB
AND dBc
F
1
+
F
2
100
0
–77
–7
TPC 14. Two Tone SFDR @ 30.5 MHz and 31.5 MHz
90
85
80
SNR @ AIN = 2.2MHz
75
70
30
45
60
75
ENCODE FREQUENCY – MHz
90
WORST SPUR @ AIN = 69.1MHz
90
85
80
75
SNR @ AIN = 69.1MHz
70
65
15
105
TPC 15. SNR, Worst Spurious vs. Encode @ 2.2 MHz
REV. 0
2
F
2
–
F
1
110
100
65
15
2
F
1
–
F
2
TPC 16. Two Tone SFDR @ 55.25 MHz and 56.25 MHz
110
0
–77
2
F
2
+
F
1
–110
–110
80
2
F
1
+
F
2
–70
30
45
60
75
ENCODE FREQUENCY – MHz
90
105
TPC 18. SNR, Worst Spurious vs. Encode @ 69.1 MHz
–11–
AD6645
0
–20
–30
–30
–40
–40
–50
–50
–60
–60
dBFS
dBFS
0
ENCODE = 80.0MSPS
–10 AIN = 30.5MHz @ –29.5dBFS
WITH DITHER @ –19.2 dBm
–20
ENCODE = 80.0MSPS
AIN = 30.5MHz @ –29.5 dBFS
NO DITHER
–10
–70
–80
–70
–80
2
–90
–90
6
–100
3
–110
–100
4
–120
0
5
10
15
20
25
FREQUENCY – MHz
30
35
–130
0
40
TPC 19. 1 M FFT without Dither
WORST-CASE SPURIOUS dBc
WORST-CASE SPURIOUS dBc
70
60
50
40
SFDR = 90 dB
REFERENCE LINE
30
20
10
35
40
80
70
60
SFDR = 100 dB
REFERENCE LINE
50
40
SFDR = 90 dB
REFERENCE LINE
30
20
10
80
70
60
50
40
30
20
10
0
dBFS –90
0
–80
–70
ANALOG INPUT LEVEL
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT LEVEL
TPC 20. SFDR without Dither
TPC 23. SFDR with Dither
0
0
ENCODE = 76.8MSPS
AIN = 69.1MHz @
–1dBFS
SNR = 73.5dB
SFDR = 89.0dBc
–10
–20
–30
ENCODE = 76.8MSPS
AIN = WCDMA @ 69.1MHz
–10
–20
–30
–40
–40
–50
–50
–60
–60
dBFS
dBFS
30
ENCODE = 80.0MSPS
100 AIN = 30.5MHz
WITH DITHER @ –19.2 dBm
90
80
–70
–70
–80
–80
3
–90
5
2
6
–100
–90
–100
4
–110
–110
–120
–120
–130
0
15
20
25
FREQUENCY – MHz
110
ENCODE = 80.0MSPS
AIN = 30.5MHz
NO DITHER
90
0
dBFS 90
10
TPC 22. 1 M FFT with Dither
110
100
5
6
3
5
–120
–130
4
2
–110
5
5
10
15
20
25
FREQUENCY – MHz
30
35
–130
0
40
TPC 21. Single Tone 69.1 MHz: Encode = 76.8 MSPS
2
5
10
3
15
20
25
FREQUENCY – MHz
6
30
4
35
5
40
TPC 24. WCDMA Tone 69.1 MHz: Encode = 76.8 MSPS
–12–
REV. 0
AD6645
0
0
ENCODE = 76.8MSPS
AIN = 2WCDMA @ 59.6MHz
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
–130
–130
0
5
10
15
20
25
FREQUENCY – MHz
30
35
40
0
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
dBFS
dBFS
5
10
4
3
2
15
20
25
FREQUENCY – MHz
30
35
40
ENCODE = 61.44MSPS
AIN = WCDMA @ 190MHz
–10
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
2
3
6
4
5
–130
2.5
5.0
0
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
FREQUENCY – MHz
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
FREQUENCY – MHz
TPC 28. WCDMA Tone 190 MHz: Encode = 61.44 MSPS
TPC 26. 4 WCDMA Carriers @ AIN = 46.08 MHz:
Encode = 61.44 MSPS
REV. 0
5
0
ENCODE = 61.44MSPS
AIN = 4WCDMA @ 46.08MHz
–10
0
6
TPC 27. WCDMA Tone 140 MHz: Encode = 76.8 MSPS
TPC 25. 2 WCDMA Carriers @ AIN = 59.6 MHz:
Encode = 76.8 MSPS
–130
0
ENCODE = 76.8MSPS
AIN = WCDMA @ 140MHz
–10
dBFS
dBFS
–10
–13–
AD6645
If a low jitter clock is available, another option is to ac-couple a
differential ECL/PECL signal to the encode input pins as shown
below. The MC100EL16 (or same family) from ON-SEMI
offers excellent jitter performance.
THEORY OF OPERATION
The AD6645 analog-to-digital converter (ADC) employs a three
stage subrange architecture. This design approach achieves the
required accuracy and speed while maintaining low power and
small die size.
VT
As shown in the functional block diagram, the AD6645 has
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 V and should swing ± 0.55 V around this
reference (see Figure 2). Since AIN and AIN are 180 degrees out
of phase, the differential analog input signal is 2.2 V
peak-to-peak.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision,
which is achieved through laser trimming. The output of DAC1
is subtracted from the delayed analog signal at the input of TH3
to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.
The first residue signal is applied to a second conversion stage
consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4.
The second DAC requires 10 bits of precision, which is met
by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of
DAC2 from the first residue signal held by TH4. TH5 drives
a final 6-bit ADC3.
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as two’s complement.
APPLYING THE AD6645
Encoding the AD6645
The AD6645 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3–4 dB
with 70 MHz analog input signals when using a high jitter clock
source. See AN-501, “Aperture Uncertainty and ADC System
Performance” for complete details.
For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENC
and ENC pins via a transformer or capacitors. These pins are
biased internally and require no additional bias.
Shown below is one preferred method for clocking the AD6645.
The clock source (low jitter) is converted from single-ended to
differential using a RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD6645 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD6645, and limits the noise
presented to the encode inputs.
CLOCK
SOURCE
T1-4T
ENCODE
0.1␮F
AD6645
ENCODE
HSMS2812
DIODES
0.1␮F
ENCODE
ECL/
PECL
AD6645
ENCODE
0.1␮F
VT
Figure 9. Differential ECL for Encode
Driving the Analog Inputs
As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6645 is differential.
Differential inputs improve on-chip performance as signals are
processed through attenuation and gain stages. Most of the
improvement is a result of differential analog stages having high
rejection of even-order harmonics. There are also benefits at the
PCB level. First, differential inputs have high common-mode
rejection to stray signals such as ground and power noise. Second, they provide good rejection to common-mode signals such
as local oscillator feed-through.
The AD6645 analog input voltage range is offset from ground by
2.4 V. Each analog input connects through a 500 W resistor to the
2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the
followers for maximum linearity and range. Therefore, the analog
source driving the AD6645 should be ac-coupled to the input
pins. Since the differential input impedance of the AD6645 is 1 kW,
the analog input power requirement is only –2 dBm, simplifying
the driver amplifier in many cases. To take full advantage of this
high input impedance, a 20:1 transformer would be required.
This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The
recommended method for driving the analog input of the
AD6645 is to use a 4:1 RF transformer. For example, if RT
were set to 60.4 W and RS were set to 25 W, along with a 4:1
impedance ratio transformer, the input would match to a 50 W
source with a full-scale drive of 4.8 dBm. Series resistors (RS)
on the secondary side of the transformer should be used to
isolate the transformer from A/D. This will limit the amount of
dynamic current from the A/D flowing back into the secondary
of the transformer. The 50 W impedance matching can also be
incorporated on the secondary side of the transformer as shown
in the evaluation board schematic (Figure 13).
ADT4-1WT
ANALOG INPUT
SIGNAL
RS
RT
AIN
AD6645
RS
AIN
0.1␮F
Figure 10. Transformer-Coupled Analog Input Circuit
In applications where dc-coupling is required, a differential
output op amp such as the AD8138 from Analog Devices can
be used to drive the AD6645 (Figure 11). The AD8138 op amp
provides single-ended-to-differential conversion, which reduces
overall system cost and minimizes layout requirements.
Figure 8. Crystal Clock Oscillator, Differential Encode
–14–
REV. 0
AD6645
CF
Grounding
5V
499⍀
VIN
499⍀
VOCM
25⍀
AD8138
AD6645
25⍀
499⍀
AIN
AIN
VREF
DIGITAL
OUTPUTS
499⍀
CF
Figure 11. DC-Coupled Analog Input Circuit
Power Supplies
Care should be taken when selecting a power source. The use of
linear dc supplies with rise-times of <45 ms is highly recommended. Switching supplies tend to have radiated components
that may be “received” by the AD6645. Each of the power
supply pins should be decoupled as closely to the package as
possible using 0.1 mF chip capacitors.
For optimum performance, it is highly recommended that a common ground be utilized between the analog and digital power
planes. The primary concern with splitting grounds is that dynamic
currents may be forced to travel significant distances in the system before recombining back at the common source ground. This
can result in a large and undesirable ground loop. The most
common place for this to occur is on the digital outputs of the
ADC. Ground loops can contribute to digital noise being coupled
back onto the ADC front end. This can manifest itself as either
harmonic spurs, or very high order spurious products that can
cause excessive spikes on the noise floor. This noise coupling is
less likely to occur at lower clock speeds since the digital noise has
more time to settle between samples. In general, splitting the
analog and digital grounds can frequently contribute to undesirable EMI-RFI and should therefore be avoided.
The AD6645 has separate digital and analog power supply pins.
The analog supplies are denoted AVCC and the digital supply
pins are denoted DVCC. Although analog and digital supplies
may be tied together, best performance is achieved when the
supplies are separate. This is because the fast digital output
swings can couple switching current back into the analog supplies.
Note that AVCC must be held within 5% of 5 V. The AD6645 is
specified for DVCC = 3.3 V as this is a common supply for
digital ASICS.
Conversely, if not properly implemented, common grounding can
actually impose additional noise issues since the digital ground
currents are riding on top of the analog ground currents in close
proximity to the ADC input. To minimize the potential for
noise coupling further, it is highly recommended that multiple
ground return traces/vias be placed such that the digital output
currents do not flow back towards the analog front end, but are
routed quickly away from the ADC. This does not require a
split in the ground plane and can be accomplished by simply
placing substantial ground connections directly back to the
supply at a point between the analog front end and the digital
outputs. The judicious use of ceramic chip capacitors between
the power supply and ground planes will also help suppress
digital noise. The layout should incorporate enough bulk capacitance
to supply the peak current requirements during switching periods.
Digital Outputs
Layout Information
Care must be taken when designing the data receivers for the AD6645.
It is recommended that the digital outputs drive a series resistor
followed by a gate such as the 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin.
An example of this is shown in the evaluation board schematic
shown in Figure 13. The digital outputs of the AD6645 have a
constant output slew rate of 1 V/ns. A typical CMOS gate combined
with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches 10 mA (10 pF ¥ 1V ∏ 1 ns ) of
dynamic current per bit will flow in or out of the device. A fullscale transition can cause up to 140 mA (14 bits ¥ 10 mA/bit) of
current to flow through the output stages. The series resistors
should be placed as close to the AD6645 as possible to limit the
amount of current that can flow into the output stage. These
switching currents are confined between ground and the DVCC
pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD6645. It
should be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output
timing is guaranteed for output loads up to 10 pF.
The schematic of the evaluation board (Figure 13) represents a
typical implementation of the AD6645. A multilayer board is
recommended to achieve best results. It is highly recommended
that high quality, ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. The pinout of
the AD6645 facilitates ease of use in the implementation of
high-frequency, high-resolution design practices. All of the digital
outputs are segregated to two sides of the chip, with the inputs on
the opposite side for isolation purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog
portion of the AD6645, minimal capacitive loading should be
placed on these outputs. It is recommended that a fan-out of
only one gate should be used for all AD6645 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry will result in corruption in the digitization process and lower overall performance. The encode clock
must be isolated from the digital outputs and the analog inputs.
Digital output states for given analog input levels are shown in Table I.
Table I. Two’s Complement Output Coding
REV. 0
AIN
Level
AIN
Level
Output
State
Output
Code
VREF + 0.55 V
VREF
VREF – 0.55 V
VREF – 0.55 V
VREF
VREF + 0.55 V
Positive FS
Midscale
Negative FS
01 1111 1111 1111
00…0/11…1
10 0000 0000 0000
–15–
AD6645
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the above equation accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter.
For a complete discussion of aperture jitter, please consult
AN-501, “Aperture Uncertainty and ADC System Performance.”
80
AIN = 30MHz
75
FANALOG = analog input frequency
tj rms = rms jitter of the encode (rms sum of encode source and
internal encode circuitry)
= average DNL of the ADC (typically 0.41 LSB)
n = number of bits in the ADC
VNOISE rms = V rms thermal noise referred to the analog input of
the ADC (typically 0.9 LSB rms)
SNR – dBFS
AIN = 70MHz
70
AIN = 110MHz
65
AIN = 150MHz
AIN = 190MHz
60
For a 14-bit analog-to-digital converter, like the AD6645, aperture
jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrate the expected SNR performance of the AD6645 as
jitter increases. The chart is derived from the above equation.
55
0
0.1
0.2
0.3
JITTER – ps
0.4
0.5
0.6
Figure 12. Jitter vs. SNR
1
2 2
2
È
2
1 + e ˆ Ê 2 ¥ 2 ¥ VNOISE rms ˆ ù
Ê
SNR = 1.76 - 20 logÍ 2p ¥ FANALOG ¥ t j rms + Á n ˜ + Á
˜ ú
Ë 2 ¯ Ë
2n
¯ úû
ÍÎ
(
)
–16–
REV. 0
AD6645
Table II. AD6645ASQ/PCB Bill of Materials
Item
No.
Qty
Reference ID1
Description
Manufacturer
1
2
3
1
3
9
AD6644/AD6645 Evaluation Printed Circuit Board
Capacitor, Tantalum SMT T491C, 10 mF; 16 V; 10%
Capacitor, SMT 0508, 0.1 mF; 16 V; 10%
4
8
PCSM, Inc. (6645EE01C)
Kemet (T491C106M016AS)
Presidio Components
(0508X7R104K16VP6)
Panasonic (ECJ-2VB1E104K)
5
6
0
9
7
8
9
10
11
12
13
1
1
4
1
1
1
0
6645EE01C
C1, C2, C38
C3, C7–C11, C16,
C30, C32
C4, C22–C26, C29,
(C33), (C34), C39
(C5, C6)
C12–C14, C17–C21,
C40
CR1
E3, E4, E5
F1–F4
J1
J1
J2
(J3)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
2
0
0
0
2
1
1
0
0
1
1
2
2
1
1
1
J4, J5
(R1)
(R2)2
(R3, R4, R5, R8)
R6, R7
R9
R10
(R11), (R13)
(R12), (R14)
R152
R35
RN1, RN3
RN2, RN4
T2
T3
U1
30
31
32
33
34
35
36
37
2
0
2
1
4
0
4
1
U2, U7
(U3)
U4, U6
U53
U53
(U8)
See drawing
See drawing
Capacitor, SMT 0805, 0.1 mF; 25 V; 10%
Capacitor, SMT 0805, 0.01 mF; 50 V; 10%
Capacitor, SMT 0508, 0.01 mF; 16 V; 10%
Panasonic (ECJ-2YB1H103K)
Presidio Components
(0508X7R103M2P3)
Diode, Schottky Barrier, Dual
Panasonic (MA716-TX)
100" Straight Male Header (Single Row), 3 of 50 pins
Samtec (TSW-1-50-08-G-S)
EMI Suppression Ferrite Chip, SMT 0805
Steward (HZ0805E601R-00)
Connector, PCB Pin Strip; 5 pins; 5 mm pitch
Wieland (Z5.530.0525.0)
Connector, PCB Terminal; 5 pins; 5 mm pitch
Wieland (25.602.2553.0)
Terminal Strip, 50 pin; right angle
Samtec (TSW-125-08-T-DRA)
Connector, SMA; RF; Gold
Johnson Components, Inc.
(142-0701-201)
Connector, Coaxial RF Receptacle; 50 W
AMP (227699-2)
Resistor, SMT 0402; 100; 1/16w; 1%
Panasonic (ERJ-2RKF1000X)
Resistor, SMT 1206; 60.4; 1/8w; 1%
Panasonic (ERJ-8ENF60R4V)
Resistor, SMT 0805; 499; 1/10w; 1%
Panasonic (ERJ-6ENF4990V)
Resistor, SMT 0805; 25.5; 1/10w; 1%
Panasonic (ERJ-6ENF25R5V)
Resistor, SMT 0805; 348; 1/10w; 1%
Panasonic (ERJ-6ENF3480V)
Resistor, SMT 0805; 619; 1/10w; 1%
Panasonic (ERJ-6ENF6190V)
Resistor, SMT 0805; 66.5; 1/10w; 1%
Panasonic (ERJ-6ENF66R5V)
Resistor, SMT 0805; 100; 1/10w; 1%
Panasonic (ERJ-6ENF1000V)
Resistor, SMT 0402; 178; 1/16w; 1%
Panasonic (ERJ-2RKF1780X)
Resistor, SMT 0805; 49.9; 1/10w; 1%
Panasonic (ERJ-6ENF49R9V)
Resistor Array, SMT 0402; 470; 1/4w; 5%
Panasonic (EXB2HV471JV)
Resistor Array, SMT 0402; 220; 1/4w; 5%
Panasonic (EXB2HV221JV)
RF Transformer, SMT KK81, 0.2–350 MHz; 4:1 W Ratio Mini-Circuits (T4-1-KK81)
RF Transformer, SMT CD542, 2–775 MHz; 4:1 W Ratio Mini-Circuits (ADT4-1WT)
I.C., QFP-52; 14-Bit, 80 MSPS
Analog Devices (AD6645ASQ)
Wideband Analog-to-Digital Converter
I.C., SOIC-20; Octal D-Type Flip-Flop
Fairchild (74LCX574WM)
I.C., SOIC-8; Low Distortion Differential ADC Driver
Analog Devices (AD8138AR)
I.C., SMT SOT-23; TinyLogic UHS 2-Input OR Gate
Fairchild (NC7SZ32)
Clock Oscillator, Full Size MX045; 80 MHz
CTS Reeves (MXO45-80)
Connector, Miniature Spring Socket,
Amp (5-330808-3)
I.C., SOIC-8; Differential Receiver
Motorola (MC100EL16)
Circuit Board Support on Base
Richo (CBSB-14-01)
0.100" Shorting Block
Jameco (152670)
NOTES
1
Reference designators in parentheses are not installed on standard units. (AC-coupled AIN and ENCODE.)
AC-coupled AIN is standard, R3, R4, R5, R8, and U3 are not installed.
If dc-coupled AIN is required, C30, T3, and R15 are not installed.
AC-coupled ENCODE is standard. C5, C6, C33, C34, R1, R11–R14, and U8 are not installed.
If PECL ENCODE is required, CR1 and T2 are not installed.
2
R2 is installed for 50 W impedance input matching on the primary of T3. R15 is not installed.
R15 is installed for 50 W impedance input matching on the secondary of T3. R2 is not installed.
3
U5 Clock Oscillator is installed with pin sockets for removal if OPT_CLK input is used.
REV. 0
–17–
BNC 2
ENC
J4
1
SMA
J3
BNC 2
J5
AIN
R35
49.9⍀
C4
0.1␮F
4
T2
3
2
R21
60.4⍀
R8
R5
499⍀
R3
499⍀
1
2
3 CR1
C33
0.1␮F
R12
100⍀
R11
66.5⍀
+5VA
–5V
8
1
2
5
VREF
6
5
3
4
ADT4-1WT 4:1
IMPEDANCE
RATIO
1
2
T3
U3
+5VA
4
R5 499⍀
3
AD8138
6
R4 499⍀
+5VA
C30
0.1␮F
R151
176.4⍀
R6
25⍀
J1
4
3
2
1
5
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
ENC
AD6644/AD6645
37
38
39
D2
D1
D0
OUT_EN
Q4
Q3
Q2
Q1
Q0
VCC
4
5
3
17
15
2
18
16
1
19
20
1
2
U6
5
+3P3VD
B06
B07
B08
B09
B10
B12
B11
B13
F2
2
4
FERRITE
1
+5VA
+5VA
GND
3 NC7SZ32
+3P3VD
U2
RN3
RN4
(SEE NOTE 4) 1
20 (SEE NOTE 4)
OUT EN VCC
19
16
1
1
16 2 D0
Q0
18
15
15 3
2
2
Q1
D1
17
14 4
14
3
3
Q2
D2
16
13 5
4
13
4
Q3
D3
15
12 6
12
5
5
Q4
D4
6
11 7
11
6
Q5 14
D5
13
10 OVR
7
10 8
7
Q6
D6
8
9
9
9 D7
8
Q7 12
10
11
GND CLOCK
PREF
74LCX574
BUFLAT
+3P3V
BUFLAT
9
10
11
12
13
15
14
16
+3P3VIN
RN2
(SEE NOTE 4)
+3P3VD
14
6
Q5
13
7
Q6
12
8
Q7
11
CLOCK
BUFLAT
74LCX574
D3
6 D4
7
D5
8 D6
9 D7
10 GND
5
4
3
2
1
U7
B00
B01
B02
B03
B04
B05
2
37
46
48
50
45
47
49
44
43
41
42
36
38
40
35
39
32
34
33
30
31
29
26
28
27
25
22
24
21
23
14
16
12
10
8
6
4
18
20
J2
17
19
15
13
11
9
5
7
3
1
HEADER 50
+3P3V
+3P3V
–5V
+
C1
10␮F
C9
0.1␮F
C10
0.1␮F
C11
0.01␮F
C12
0.01␮F
C13
0.01␮F
F4
2
C14 FERRITE
0.01␮F
1
C23
0.1␮F
C24
0.1␮F
C25
0.1␮F
+3P3VD
C26
0.1␮F
14 15 16 17 18 19 20 21 22 23 24 25 26 NOTES
1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED.
R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3.
R2 IS NOT INSTALLED.
+5VA +5VA +5VA
+5VA
+5VA 2. AC-COUPLED AIN IS STANDARD. R3, R4, R5, R8, AND U3 ARE NOT INSTALLED.
IF DC-COUPLED AIN IS REQUIRED, C30, R15, AND T3 ARE NOT INSTALLED.
C8
C7
3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11–R14 AND U8 ARE NOT INSTALLED.
0.1␮F
0.1␮F
IF PECL ENCODE IS REQUIRED, CR1, AND T3 ARE NOT INSTALLED.
4. IF AD6644 IS USED: VALUE FOR RN1–RN4 IS 100 OHM.
IF AD6645 IS USED: VALUE FOR RN1–RN3 IS 470 OHM, VALUE FOR RN2 AND RN4 IS 220 OHM.
F1 2
1
+5VA
–5V
FERRITE
C2
C16
C17
C18
C19
C20
C21
C40
C39
C38
10␮F
0.1␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.1␮F + 10␮F
+3P3VIN
36
D0
35
DMID
34
GND
33
DVCC
32
OVR
31
DNC
30
AVCC
29
GND
28
AVCC
27
GND
D1
VREF
GND
ENC
D2
D3
10
7
GND
+3P3V
11
6
9
12
5
8
13
4
14
15
2
3
16
1
RN1
(SEE NOTE 4)
GND
AVCC
9
AVCC
10
GND
11
AIN
12
AIN
13
GND
8
7
6
5
4
3
2
1
V1
DVCC
C32
0.1␮F
DR_OUT
BUFLAT
+3P3V
VREF
E5
E3
+5VA
R7
25⍀
C34
0.1␮F
R14
100⍀
R13
66.5⍀
+5VA
PECL ENCODE OPTION3
U4 5 NC7SZ32
1
4 OPT_LAT
2
GND
E4
3
DR_OUT
+3P3VD
DC-COUPLED AIN OPTION2
HSMS2812
OPTIONAL
MC100EL16
VBB
6
Q
VEE 5
4
3D
VCC
8
Q 7
NC
U8
+5VA
R9
348⍀
2D
1
+3P3V
R10
619⍀
C6
0.01␮F
C3
0.1␮F
6 1:4 1
IMPEDANCE
RATIO C29
0.1␮F
1
C5
.01␮F
R1
100⍀
OPT_CLK
K1115
66.66MHz (AD6644)
80MHz (AD6645)
C22
0.1␮F
DRY
AVCC
8
D13
GND
GND OUT
D12
AVCC
7
D11
GND
+5VA
D10
AVCC
2
D9
GND
F3
D8
C1
1
D7
GND
FERRITE
DVCC
14
D6
AVCC
–18–
GND
VCC
GND
C2
U5
D5
GND
NC
D4
AVCC
1
AD6645
Figure 13. Evaluation Board Schematic
REV. 0
AD6645
REV. 0
Figure 14. Top Signal Level
Figure 16. Ground Plane Layer 2 and 5
Figure 15. 5.0 V/3.3 V Plane Layers 3 and 4
Figure 17. Bottom Signal Layer
–19–
AD6645
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
52-Lead PowerQuad 4 (LQFP_ED)
(SQ-52)
7.80 (0.307)
52
40
1
40
39
13
27
14
1
6.00 (0.236)
5.90 (0.232)
5.80 (0.228)
EXPOSED
HEATSINK
(CENTERED)
27
26
0.65 (0.026)
52
39
10.20 (0.402)
10.00 (0.394) SQ
9.80 (0.386)
TOP VIEW
(PINS DOWN)
C02647–0–2/02(0)
2.65 (0.104)
2.50 (0.098) (4 PLCS)
2.35 (0.093)
12.00 (0.472) SQ
2.35 (0.093)
2.20 (0.087) (4 PLCS)
2.05 (0.081)
13
26
14
6.00 (0.236)
5.90 (0.232)
5.80 (0.228)
0.38 (0.015)
0.32 (0.013)
0.22 (0.009)
BOTTOM VIEW
(PINS UP)
1.60
(0.063)
MAX
0.75 (0.030)
0.60 (0.024)
0.45 (0.018)
1.45 (0.057)
1.40 (0.055)
1.35 (0.053)
SEATING
PLANE
VIEW A
0.15 (0.006)
0.05 (0.002)
0.10 (0.004)
COPLANARITY
VIEW A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
PRINTED IN U.S.A.
THE AD6645 POWERQUAD 4 (LQFP_ED) HAS A THERMALLY AND ELECTRICALLY CONDUCTIVE HEAT SLUG EXPOSED ON THE
BOTTOM OF THE PACKAGE WHICH CAN BE UTILIZED FOR ENHANCED THERMAL MANAGEMENT. IT IS RECOMMENDED THAT
NO UNMASKED ACTIVE PCB TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME INTO CONTACT WITH
THE GROUNDED HEAT SLUG. ALTHOUGH NOT A REQUIREMENT FOR SPECIFIED OPERATION, SOLDERING THE SLUG TO A
GROUND PLANE WITH SUFFICIENT THERMAL CAPACITY WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE. THIS
MAY PROVE BENEFICIAL IN HIGH RELIABILITY APPLICATIONS WHERE LOWER JUNCTION TEMPERATURES TYPICALLY CONTRIBUTE
TO INCREASED SEMICONDUCTOR RELIABILITY.
–20–
REV. 0