AD ADP-I2C-USB-Z Digital power factor correction controller Datasheet

Digital Power Factor Correction Controller
with Accurate AC Power Metering
ADP1047/ADP1048
Data Sheet
FEATURES
GENERAL DESCRIPTION
Flexible digital power factor correction (PFC) controller
Single phase operation (ADP1047); interleaved and
bridgeless operation (ADP1048)
True rms ac power metering
Enhanced dynamic response
Optimized light load efficiency performance
Output voltage adjustment
Frequency reduction
Inrush current control
Switching frequency spread spectrum for improved EMI
External frequency synchronization
PMBus compliant
Programmable ac line fault detection and protection
Programmable output fault detection and protection
Extensive fault protection for high reliability systems
Frequency range from 30 kHz to 400 kHz
8 kB EEPROM
Programming via easy-to-use graphical user interface (GUI)
The ADP1047/ADP1048 are digital power factor correction
(PFC) controllers that provide accurate input power metering
capability and inrush current control for ac/dc systems. The
ADP1047 is designed for single phase PFC applications; the
ADP1048 is designed especially for interleaved and bridgeless
PFC applications.
The digital PFC function is based on a conventional boost PFC
with multiplication of the output voltage feedback combined with
the input current and voltage to provide optimum harmonic
correction and power factor for ac/dc systems. All signals are
converted into the digital domain to provide maximum flexibility;
all key parameters can be reported and adjusted via the PMBus™
interface. The ADP1047/ADP1048 allow users to optimize system
performance, maximize efficiency across the load range, and
reduce design time to market.
The ADP1047/ADP1048 provide accurate rms measurement
of input voltage, current, and power. This information can be
reported to the microcontroller of the power supply via the
PMBus interface.
APPLICATIONS
AC/DC power supplies for applications
Computing server and storage
Network and communication infrastructure
Industrial and medical
TYPICAL APPLICATIONS CIRCUIT
VREC
VOUT
RELAY
BULK
CAPACITOR
AC
INPUT
3.3V
1
AGND
VDD 24
2
VAC
RES 23
3
VFB
RTD 22
4
OVP
ADD 21
5
PGND
SDA 20
6
ILIM
7
NC
8
CS–
INRUSH 17
9
CS+
PGOOD 16
10
DGND
AC_OK 15
11
PSON
PWM2 14
12
VCORE
PMBus
SCL 19
PWM 13
ADP1047
09696-101
SYNC 18
Figure 1.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADP1047/ADP1048
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Advanced Features ......................................................................... 30
Applications ....................................................................................... 1
Frequency Dithering (Spread Spectrum) ................................ 30
General Description ......................................................................... 1
PWM Frequency Synchronization........................................... 30
Typical Applications Circuit............................................................ 1
Smart Output Voltage (Load Line) .......................................... 30
Revision History ............................................................................... 4
Smart Switching Frequency ...................................................... 31
Specifications..................................................................................... 6
Current Loop Filter for Light Load .......................................... 31
Absolute Maximum Ratings............................................................ 9
Phase Shedding (ADP1048 Only) ............................................ 31
Thermal Resistance ...................................................................... 9
Current Loop Feedforward ....................................................... 31
ESD Caution .................................................................................. 9
Bridgeless Boost Operation (ADP1048 Only)........................ 32
Pin Configurations and Function Descriptions ......................... 10
Power Supply System Calibration and Trim ............................... 33
Functional Block Diagrams ........................................................... 11
Output Voltage (VFB) Calibration and Trim ......................... 33
Controller Architecture ................................................................. 12
Input Voltage (VAC) Gain and Offset Trim............................ 33
Current Sense .............................................................................. 12
Current Sense Gain and Offset Trim ....................................... 33
RMS Input Overcurrent Protection ......................................... 12
Input Power Gain and Offset Trim .......................................... 33
Fast Overcurrent Protection (ILIM Pin) ................................. 12
PMBus Digital Communication ................................................... 34
Current Balancing (IBAL Pin, ADP1048 Only) ..................... 14
Features ........................................................................................ 34
Voltage Sense ............................................................................... 14
Overview ..................................................................................... 34
Overvoltage Protection .............................................................. 15
PMBus Address .......................................................................... 34
Power Factor Correction Control Loop ...................................... 17
Data Transfer............................................................................... 35
Digital Compensation Filters .................................................... 17
General Call Support ................................................................. 36
Pulse-Width Modulation........................................................... 18
Fast Mode .................................................................................... 36
Duty Cycle Minimum/Maximum Limits ................................ 18
Fault Conditions ......................................................................... 36
Auxiliary PWM Output (ADP1047 Only) .............................. 18
Timeout Condition .................................................................... 36
Switching Frequency Programming ........................................ 19
Data Transmission Faults .......................................................... 37
Line Fault Protections and Soft Start Sequencing ...................... 20
Data Content Faults ................................................................... 37
PSON Operation ........................................................................ 20
EEPROM ......................................................................................... 38
AC Line Detection ...................................................................... 20
Overview ..................................................................................... 38
Soft Start Procedure ................................................................... 22
Page Erase Operation ................................................................. 38
Line Fault Protections ................................................................ 22
Read Operation (Byte Read and Block Read) ........................ 38
Advanced Input Power Metering.................................................. 24
Write Operation (Byte Write and Block Write) ..................... 39
Power Supply System and Fault Monitoring ............................... 25
EEPROM Password .................................................................... 39
Flag Conventions ........................................................................ 25
Downloading EEPROM Settings to Internal Registers ......... 39
Manufacturer-Specific Flags ..................................................... 25
Saving Register Settings into EEPROM .................................. 40
Standard PMBus Flags ............................................................... 26
EEPROM CRC Checksum ........................................................ 40
PMBus Fault Flag Response ...................................................... 27
Software GUI .................................................................................. 41
Manufacturer-Specific Flag Response ..................................... 28
Monitoring Functions ................................................................ 29
Standard PMBus Commands Supported by the
ADP1047/ADP1048 ....................................................................... 42
First Error Fault .......................................................................... 29
Manufacturer-Specific PMBus Commands ................................ 43
Overtemperature Protection (OTP) ........................................ 29
Detailed Register Descriptions ..................................................... 45
AC_OK and PGOOD Signals ................................................... 29
OPERATION Register ............................................................... 45
Rev. 0 | Page 2 of 84
Data Sheet
ADP1047/ADP1048
ON_OFF_CONFIG Register .....................................................45
MFR_REVISION Register ......................................................... 56
CLEAR_FAULTS Command .....................................................45
WRITE_PROTECT Register .....................................................45
EEPROM_DATA_00 Through EEPROM_DATA_15
Commands ................................................................................... 56
RESTORE_DEFAULT_ALL Command ..................................45
EEPROM_CRC_CHKSUM Register ....................................... 57
STORE_USER_ALL Command................................................45
EEPROM_NUM_RD_BYTES Register ................................... 57
RESTORE_USER_ALL Command ..........................................46
EEPROM_ADDR_OFFSET Register ....................................... 57
CAPABILITY Register ...............................................................46
EEPROM_PAGE_ERASE Register ........................................... 57
VOUT_MODE Register .............................................................46
EEPROM_PASSWORD Register .............................................. 57
VOUT_COMMAND Register ..................................................46
TRIM_PASSWORD Register .................................................... 57
VOUT_SCALE_LOOP Register ...............................................46
EEPROM_INFO Command ..................................................... 57
VOUT_SCALE_MONITOR Register ......................................47
CS_FAST_OCP_RESPONSE Register ..................................... 58
VIN_ON Register........................................................................47
OVP_FAST_OVP_RESPONSE Register ................................. 58
VIN_OFF Register ......................................................................47
OLP_RESPONSE Register ......................................................... 58
VOUT_OV_FAULT_LIMIT Register ......................................47
VDD3P3_RESPONSE Register ................................................. 59
VOUT_OV_FAULT_RESPONSE Register .............................47
VCORE_RESPONSE Register................................................... 59
VOUT_OV_WARN_LIMIT Register ......................................48
PGOOD_AC_OK_DEBOUNCE_SET Register ..................... 59
VOUT_UV_WARN_LIMIT Register ......................................48
PSON_SET Register ................................................................... 60
VOUT_UV_FAULT_LIMIT Register ......................................48
FLAG_FAULT_ID Register ....................................................... 60
VOUT_UV_FAULT_RESPONSE Register .............................49
SOFTSTART_FLAGS_BLANK1 Register ............................... 61
OT_FAULT_RESPONSE Register ............................................49
SOFTSTART_FLAGS_BLANK2 Register ............................... 61
VIN_OV_FAULT_LIMIT Register...........................................50
PGOOD_FLAGS_LIST Register............................................... 61
VIN_OV_FAULT_RESPONSE Register ..................................50
AC_OK_FLAGS_LIST Register ................................................ 61
VIN_UV_WARN_LIMIT Register...........................................51
PWM and PWM2 Timing Registers ........................................ 62
VIN_UV_FAULT_LIMIT Register ..........................................51
PWM_SET Register .................................................................... 63
VIN_UV_FAULT_RESPONSE Register ..................................52
PWM_LIMIT Register ............................................................... 63
IIN_OC_FAULT_LIMIT Register ............................................52
RTD ADC Offset Trim Setting (MSB) Register ...................... 63
IIN_OC_FAULT_RESPONSE Register ...................................53
RTD ADC Offset Trim Setting (LSB) Register ....................... 63
IIN_OC_WARN_LIMIT Register ............................................53
RTD ADC Gain Trim Setting Register .................................... 64
PIN_OP_WARN_LIMIT Register ............................................54
OT_FAULT_LIMIT Register ..................................................... 64
STATUS_BYTE Register ............................................................54
OT_WARN_LIMIT Register ..................................................... 64
STATUS_WORD Register .........................................................54
Switching Frequency Setting Register ...................................... 65
STATUS_VOUT Register...........................................................55
Low Power Switching Frequency Setting Register ................. 66
STATUS_INPUT Register .........................................................55
Frequency Dithering Set Register ............................................. 67
STATUS_TEMPERATURE Register ........................................55
Frequency Synchronization Set Register ................................. 68
READ_VIN Register...................................................................55
Voltage Loop Filter Gain Register ............................................. 68
READ_IIN Register ....................................................................55
Voltage Loop Filter Zero Register ............................................. 68
READ_VOUT Register ..............................................................56
Fast Voltage Loop Filter Gain Register..................................... 68
READ_PIN Register ...................................................................56
Fast Voltage Loop Filter Zero Register ..................................... 68
PMBUS_REVISION Register ....................................................56
Fast Voltage Loop Enable Register............................................ 68
MFR_ID Register ........................................................................56
VAC_THRESHOLD_SET Register .......................................... 69
MFR_MODEL Register ..............................................................56
VAC_THRESHOLD_READ Register ...................................... 69
Rev. 0 | Page 3 of 84
ADP1047/ADP1048
Data Sheet
MIN_AC_PERIOD_SET Register ........................................... 69
Smart VOUT High Line (VOH1) Register ............................. 76
MAX_AC_PERIOD_SET Register .......................................... 69
Smart VOUT High Line (VOH2) Register ............................. 76
Current Loop Filter Gain for Low Line Input Register ......... 70
Smart VOUT Upper Limit (VOH) Register ........................... 76
Current Loop Filter Zero for Low Line Input Register ......... 70
Smart VOUT Super High Line Register .................................. 76
Current Loop Filter Gain for High Line Input Register ........ 70
SYNC Delay Register ................................................................. 76
Current Loop Filter Zero for High Line Input Register ........ 70
SMART_VOUT_SUPER_HIGH_LINE_HYS Register ........ 77
Soft Start Set Register ................................................................. 70
POWER_HYS Register .............................................................. 77
Inrush Set Register ..................................................................... 71
Advanced Feature Enable Register........................................... 77
FAST_OVP_FAULT_RISE Register ......................................... 71
VOUT_OV_FAULT_HYS Register ......................................... 77
FAST_OVP_FAULT_FALL Register ........................................ 71
VIN_UV_FAULT_HYS Register.............................................. 77
FAST OVP Debounce Time Setting Register ......................... 71
VAC ADC Offset Trim Register ............................................... 78
Low Power Mode Operation Threshold Register .................. 72
CS ADC Offset Trim for 500 mV Range Register ................. 78
Power Metering Offset Trim for Low Line Input Register.... 72
CS ADC Gain Trim for High (750 mV) Range Register....... 78
Power Metering Gain Trim for Low Line Input Register ...... 72
CS ADC Offset Trim for High (750 mV) Range Register .... 78
High Line Limit Register ........................................................... 72
Latched Flag Registers ............................................................... 78
Low Line Limit Register ............................................................ 72
PWM Value Register .................................................................. 79
ILIM_TRIM Register ................................................................. 72
VAC_LINE_PERIOD Register ................................................. 79
Voltage Loop Output Register .................................................. 72
Read Temperature ADC Register ............................................. 79
Exponent Register ...................................................................... 73
Power Metering Offset Trim for High Line Input Register .. 79
Read Update Rate Register ........................................................ 73
Power Metering Gain Trim for High Line Input Register .... 80
VIN Scale Monitor Register ...................................................... 73
Current Loop Filter Gain for Low Line Input and Light
Load Register .............................................................................. 80
IIN_GSENSE Register ............................................................... 73
CS Fast OCP Blank Register ..................................................... 74
CS Fast OCP Setting Register ................................................... 74
Temperature Hysteresis Register .............................................. 74
VAC ADC Gain Trim Register ................................................. 75
Current Loop Filter Zero for Low Line Input and Light
Load Register .............................................................................. 80
Current Loop Filter Gain for High Line Input and Light
Load Register .............................................................................. 80
VFB ADC Gain Trim Register .................................................. 75
Current Loop Filter Zero for High Line Input and Light
Load Register .............................................................................. 80
CS ADC Gain Trim for 500 mV Range Register .................... 75
Smart VOUT Power Reading Register .................................... 80
IBAL Gain Register (ADP1048 Only) ..................................... 75
IBAL Configuration Register (ADP1048 Only) ..................... 81
Smart VOUT Low Power Threshold (P1) Register ............... 75
Debug Flag Registers.................................................................. 81
Smart VOUT High Power Threshold (P2) Register .............. 75
Outline Dimensions ....................................................................... 83
Smart VOUT Low Line (VOL1) Register................................ 76
Ordering Guide .......................................................................... 83
Smart VOUT Low Line (VOL2) Register................................ 76
REVISION HISTORY
9/11—Revision 0: Initial Version
Rev. 0 | Page 4 of 84
Data Sheet
ADP1047/ADP1048
The combination of a flexible, digitally controlled PFC engine
and accurate input power metering facilitates the adoption
of intelligent power management systems that are capable of
making decisions to improve end-user system efficiency. The
device supports additional efficiency improvements through
programmable frequency reduction at light load and the
capability to reduce the output voltage at light load.
The devices are designed for high reliability, redundant power
supply applications and have extensive and robust protection
circuitry: independent overvoltage protection (OVP) and
overcurrent protection (OCP), ground continuity monitoring,
and ac sensing. Internal overtemperature protection (OTP)
is provided whereby the external temperature can be recorded
via an external sensing device.
The ADP1047/ADP1048 provide enhanced integrated features
and functions; the inrush current and soft start control functions
provide significant component count reduction with easy design
optimization.
The internal 8 kB EEPROM stores all programmed values
and allows standalone control without a microcontroller. All
parametric reporting and adjustments can be programmed via
an easy-to-use GUI. No complex programming is required.
The ADP1047/ADP1048 operate from a single 3.3 V supply. The
devices are available in a 24-lead QSOP package that is specified
over an ambient temperature range of −40°C to +85°C.
VOUT
RELAY
BULK
CAPACITOR
AC
INPUT
3.3V
1
AGND
VDD 24
2
VAC
RES 23
3
VFB
RTD 22
4
OVP
ADD 21
5
PGND
SDA 20
6
ILIM
SCL 19
7
IBAL
8
CS–
INRUSH 17
9
PMBus
SYNC 18
CS+
PGOOD 16
10
DGND
AC_OK 15
11
PSON
PWM2 14
12
VCORE
PWM 13
ADP1048
Figure 2. Typical Interleaved Application, ADP1048
Rev. 0 | Page 5 of 84
09696-102
VREC
ADP1047/ADP1048
Data Sheet
SPECIFICATIONS
VDD = 3.3 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY
Operating Supply Voltage
Supply Current
Symbol
Supply Current for Programming
Shutdown Current
POWER-ON RESET
Power-On Reset
Undervoltage Lockout
Overvoltage Lockout
VCORE PIN
Output Voltage Range
PWM OUTPUTS
Output Low Voltage
Output High Voltage
IDD_PK
IDD_SD
Rise Time
Fall Time
VAC ADC
Input Voltage Range
Leakage Current
Equivalent Resolution
Voltage Sense Measurement
Accuracy
VDD
IDD
UVLO
OVLO
VPWMOL
VPWMOH
Test Conditions/Comments
Current Source
High Input
Low Input
Current Source Resolution
RTD PIN
Input Voltage Range
Current Source Accuracy
Equivalent Resolution
Max
Unit
3.0
3.3
17
3.6
40
V
mA
IDD + 8
100
mA
μA
VDD rising
VDD falling
1.8
2.75
3.7
2.85
3.9
3
2.95
4.1
V
V
V
Temperature = 25°C
PWM, PWM2 pins
Sink current = 10 mA
Source current = 10 mA
2.26
2.45
2.65
V
0.4
V
V
VDD −
0.4
CLOAD = 50 pF
CLOAD = 50 pF
4
4
0
ns
ns
1.6
5
V
μA
Bits
+1.3
+1.99
% FSR
% FSR
1.6
V
Bits
−1.2
−1.72
+1.2
+1.72
% FSR
% FSR
0
0
750
500
mV
mV
Bits
+1.7
+2.06
% FSR
% FSR
11
From 2.5% to 97.5% of input voltage range
−1.3
−1.99
0
11
From 2.5% to 97.5% of input voltage range
VDD = 3.3 V
VDD varies from 3.0 V to 3.6 V
CURRENT SENSE ADC
High Input Voltage Range
Low Input Voltage Range
Equivalent Resolution
Current Sense Measurement
Accuracy
Typ
Normal operation (PSON high) and no load
on PWM output
During EEPROM programming (50 ms)
VDD = 3.3 V
VDD varies from 3.0 V to 3.6 V
VFB ADC
Input Voltage Range
Equivalent Resolution
Voltage Sense Measurement
Accuracy
Min
11
From 0% to 97.5% of input voltage range
VDD = 3.3 V
VDD varies from 3.0 V to 3.6 V
10 kΩ level shifting resistor, VCS+ − VCS− = 0 V
−1.7
−2.06
74
84
±0.03
0
9
Rev. 0 | Page 6 of 84
10
14
μA
μA
%
0.8
11
V
μA
Bits
Data Sheet
Parameter
Voltage Sense Measurement
Accuracy
ADP1047/ADP1048
Symbol
IBAL PIN (ADP1048 ONLY)
Input Voltage Range
Equivalent Resolution
Channel Mismatch
Min
VDD = 3.3 V
VDD varies from 3.0 V to 3.6 V
Interleaved operation mode
−1.52
−1.97
Typ
0
Max
Unit
+1.52
+1.97
% FSR
% FSR
0.8
−5
+5
V
Bits
% FSR
−2.3
−2.75
+2.3
+2.75
% FSR
% FSR
30
−3.85
400
+3.85
kHz
%
11
DC input and acquiring time window on
each channel is 526 μs
POWER METER
Measurement Accuracy
SWITCHING FREQUENCY
Frequency Range
Accuracy
OSCILLATOR, CLOCK, AND PLL
Oscillator Frequency
Digital Clock Frequency
PLL Frequency
RES PIN
Temperature Stability
PGOOD, AC_OK PINS
Output Low Voltage
Output High Voltage
FAST OVERCURRENT PROTECTION
Fast OCP Threshold
Positive Signal
Negative Signal
Current Source Accuracy
Current Source Resolution
Propagation Delay
RMS OVERCURRENT PROTECTION
RMS Accuracy
Propagation Delay
FAST OVERVOLTAGE PROTECTION
Fast OVP Threshold
Rising
Falling
OVP Threshold Minimum Step
Accuracy
Propagation Delay (Latency)
Blanking Time
ACCURATE OVERVOLTAGE
PROTECTION
Accuracy
Propagation Delay
OPEN-LOOP PROTECTION
VFB Error Threshold
Propagation Delay
Debounce Time
Common-Mode Input Range
Test Conditions/Comments
From 2.5% to 97.5% of input voltage range
From 2.5% to 97.5% of input voltage range
VDD = 3.3 V
VDD varies from 3.0 V to 3.6 V
Programmable
1.516
1.56
200
200
1.62
MHz
MHz
MHz
−120
0
+120
ppm/°C
0.8
V
V
1550
523
mV
mV
%
%
ns
2.0
1455
452
1500
500
±4.4
±3.2
From threshold trip to PWM disabled
VDD = 3.3 V
AC line frequency = 50 Hz
Fully programmable from 1 V to 1.5 V
Register 0xFE2F, Bits[6:0]
Register 0xFE30, Bits[6:0]
140
−1.7
+1.7
%
ms
1.5
1.5
V
V
mV
LSB
ns
μs
12
1
1
3.9
−4
Does not include blanking/debounce
Blanking after threshold reprogramming
VDD = 3.3 V
AC line frequency = 50 Hz
ΔVFB
10
−1.2
+1.2
%
ms
±242
mV
ns
μs
V
12
±33
−0.2
Rev. 0 | Page 7 of 84
+4
120
±111
200
10
+1.6
ADP1047/ADP1048
Parameter
SDA, SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Pull-Up Current
Leakage Current
SERIAL BUS TIMING
Clock Frequency
Glitch Immunity
Bus Free Time
Start Condition Hold Time
Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
SCL Low Timeout
SCL Low Time
SCL High Time
Clock Low Extend Time
SCL, SDA Rise Time
SCL, SDA Fall Time
EEPROM RELIABILITY
Endurance
Data Retention
Data Sheet
Symbol
Test Conditions/Comments
VDD = 3.3 V
Min
Typ
Max
Unit
0.8
V
V
V
μA
μA
2.2
0.4
350
+5
100
−5
10
tSW
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tTIMEOUT
tLOW
tHIGH
tLOW;SEXT
tR
tF
1.3
0.6
0.6
0.6
300
100
25
1.3
0.6
20
20
Temperature = 85°C
Rev. 0 | Page 8 of 84
10,000
20
100
400
50
35
25
300
300
kHz
ns
μs
μs
μs
μs
ns
ns
ms
μs
μs
ms
ns
ns
Cycles
Years
Data Sheet
ADP1047/ADP1048
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage (Continuous), VDD
Digital Core Supply Voltage, VCORE
Digital Pins
Analog Pins
AGND to DGND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
RoHS-Compliant Assemblies
(20 sec to 40 sec)
Rating
3.8 V
2.7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
24-Lead QSOP (RQ-24)
ESD CAUTION
240°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 84
θJA
44.4
θJC
6.4
Unit
°C/W
ADP1047/ADP1048
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND
1
24
VDD
AGND
1
24 VDD
VAC
2
23
RES
VAC
2
23 RES
22 RTD
VFB
3
22
RTD
VFB
3
OVP
4
21
ADD
OVP
4
PGND
5
ADP1047
20
SDA
PGND
5
ADP1048
20 SDA
ILIM
6
TOP VIEW
(Not to Scale)
19
SCL
ILIM
6
TOP VIEW
(Not to Scale)
19 SCL
NC
7
18
SYNC
IBAL
7
CS–
8
17
INRUSH
CS–
8
17 INRUSH
CS+
9
16
PGOOD
CS+
9
16 PGOOD
DGND 10
15
AC_OK
DGND 10
15 AC_OK
PSON 11
14
PWM2
PSON 11
14 PWM2
VCORE 12
13
PWM
13 PWM
Figure 3. ADP1047 Pin Configuration
09696-004
18 SYNC
09696-003
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
VCORE 12
21 ADD
Figure 4. ADP1048 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
AGND
VAC
VFB
4
5
OVP
PGND
6
7
ILIM
NC/IBAL
8
CS−
9
CS+
10
11
DGND
PSON
12
13
14
15
16
17
18
19
20
21
22
23
24
VCORE
PWM
PWM2
AC_OK
PGOOD
INRUSH
SYNC
SCL
SDA
ADD
RTD
RES
VDD
Description
Analog Ground. AGND should be connected directly to DGND.
Input Line Voltage Sense. The VAC signal is referred to PGND.
Feedback Voltage Sense. The VFB signal is referred to PGND. VFB is the feedback signal for PFC power circuit
regulation. It is used as the analog voltage input to the VFB ADC.
Overvoltage Protection. The OVP signal is referred to PGND. This signal is used for redundant overvoltage protection.
Power Ground. PGND is the connection for the ground line of the power rail. There should be a low impedance
path between PGND and AGND.
Fast Current Limiting. This pin is referred to PGND.
ADP1047: No Connect. Do not connect to this pin.
ADP1048: Current Balancing Input for Interleaved Operation. The IBAL input is referred to PGND.
Differential Current Sense Negative Input. The CS− signal is used for current measurement, monitoring, and
protection. A 0.1%, 10 kΩ resistor must be used to connect to this circuit.
Differential Current Sense Positive Input. The CS+ signal is used for current measurement, monitoring, and
protection. A 0.1%, 10 kΩ resistor must be used to connect to this circuit.
Digital Ground. DGND should be connected directly to AGND.
Power Supply Enable Signal. The PSON signal is used to enable/disable the PFC controller. The PSON signal is
referred to DGND.
Output of 2.5 V Regulator. Connect a 100 nF capacitor from VCORE to DGND.
PWM Output for PFC Regulation. The PWM signal is referred to AGND.
Auxiliary PWM Output (ADP1047) or Interleaved PWM Output (ADP1048). The PWM2 signal is referred to AGND.
Open-Drain Output. User-configurable signal from a combination of flags. The AC_OK signal is referred to AGND.
Open-Drain Output. User-configurable signal from a combination of flags. The PGOOD signal is referred to AGND.
Inrush Current Control Signal to an External Inrush Driver. This open-drain output is referred to AGND.
Allows parallel PFC controllers to synchronize to reduce interference. This pin is referred to DGND.
I2C Serial Clock Input. The SCL signal is referred to DGND.
I2C Serial Data Input and Output (Open-Drain). The SDA signal is referred to DGND.
Address Select Input. Connect a resistor from ADD to AGND (see the PMBus Address section).
Thermistor Input. A thermistor is placed from RTD to AGND. The RTD signal is referred to AGND.
Internal Voltage Reference. Connect a 0.1%, 50 kΩ resistor from RES to AGND.
Positive Supply Input. The range is from 3.0 V to 3.6 V. The VDD signal is referred to AGND.
Rev. 0 | Page 10 of 84
Data Sheet
ADP1047/ADP1048
FUNCTIONAL BLOCK DIAGRAMS
CS– CS+ ILIM
VAC
PGND
OVP
VFB
ADP1047
+ –
DAC
ADC
CS
OCP
ADC
ADC
VAC
VFB
OLP
PGND
OVP
INRUSH
PWM
PGOOD
PWM
ENGINE
PWM2
DIGITAL CORE
8kB EEPROM
VDD
AC_OK
I2C
INTERFACE
UVLO
LDO
ADC
OSC
VCORE
SYNC
PSON
VREF
SCL
SDA
ADD
RTD AGND
DGND
09696-001
RES
Figure 5. ADP1047 Functional Block Diagram
IBAL CS– CS+ ILIM
OVP
VAC PGND VFB
PGND
ADP1048
+ –
DAC
ADC
ADC
CS
CS
OCP
ADC
ADC
VAC
VFB
OLP
PGND
OVP
INRUSH
PWM
PGOOD
PWM
ENGINE
PWM2
DIGITAL CORE
8kB EEPROM
VDD
AC_OK
I2C
INTERFACE
UVLO
LDO
ADC
OSC
VCORE
SYNC
PSON
VREF
SCL
SDA
ADD
RTD AGND
DGND
Figure 6. ADP1048 Functional Block Diagram
Rev. 0 | Page 11 of 84
09696-002
RES
ADP1047/ADP1048
Data Sheet
CONTROLLER ARCHITECTURE
The ADP1047/ADP1048 integrate the following functions:
The output of the Σ-Δ ADC is used for the following purposes:
•
•
•
•
Power factor correction control loop (see the Power Factor
Correction Control Loop section)
Advanced input power metering (see the Advanced Input
Power Metering section)
PMBus digital communication (see the PMBus Digital
Communication section)
•
This section describes the internal architecture of the chip.
The output is decimated at the switching frequency for the
control loop. The effective number of bits (ENOB) is >7
when the current loop bandwidth is 10 kHz; the ENOB
is >10 when the current loop bandwidth is 1 kHz.
The 11-bit result is calculated and updated at each half line
cycle for high accuracy ac line current and input power
monitoring and for overcurrent protection (accurate OCP).
RMS INPUT OVERCURRENT PROTECTION
CURRENT SENSE
Current sensing is used for the control, protection, and monitoring of the PFC stage. For normal operation, the power factor
correction control loop requires inductor current information.
The typical implementation uses a sense resistor on the input
bus. A combination of two current transformers in series with
the power switch and the boost diode can be used to reconstruct
the inductor current and minimize losses in the resistive shunt,
but, in general, a good quality shunt resistor provides much
better accuracy in measuring input current and input power.
The inputs to the current sense ADC are differential. A pair of
matched current sources is provided to level shift the negative
signal across the current sense element in the input range of the
current sense ADC (see Figure 7).
The ADP1047/ADP1048 provide rms overcurrent protection
(OCP). RMS OCP (or accurate OCP) is distinct from the instantaneous pulse-by-pulse fast overcurrent protection and is based
on the rms value of the input ac current.
The measured value is compared to the limit set in the
IIN_OC_FAULT_LIMIT register (Register 0x5B) at the
end of each half cycle of the ac line. If the limit is exceeded,
the action programmed in the IIN_OC_FAULT_RESPONSE
register (Register 0x5C) is triggered.
In addition, an input current warning limit can be programmed
in the IIN_OC_WARN_LIMIT register (Register 0x5D). This
warning limit has no action attached to it, but it sets flags in the
STATUS_BYTE register (Register 0x78, Bit 0), the STATUS_WORD
register (Register 0x79, Bit 13), and the STATUS_INPUT register
(Register 0x7C, Bit 1).
FAST OVERCURRENT PROTECTION (ILIM PIN)
IL
10kΩ
A dedicated current limiting pin (ILIM) is provided to protect
the part from pulse-by-pulse overcurrent events. When the
threshold is crossed, the PWM pulse is terminated. This action
is independent of any programming of the fast OCP flag. The
next switching cycle resumes normally. Additional actions can
be programmed (see Table 5).
10kΩ
CS+
+
–
VDD
ADC
11-BIT
ADP1047/ADP1048
The OCP comparator on the ILIM pin can accept positive or
negative signals; the pin is referred to PGND (power ground) and
has programmable level shifting current sources (see Table 5).
These sources can be changed during normal operation to adapt
to the level at which the overcurrent protection is triggered.
09696-005
CS–
Figure 7. Current Sense Configuration
The current sense can be calibrated digitally to remove any
errors due to external components (see the Current Sense Gain
and Offset Trim section). This calibration can be performed in
the production environment; the settings are saved in the
EEPROM of the ADP1047/ADP1048.
The OCP comparator also features programmable blanking and
debounce times (see Table 5). If OCP is triggered, the PWM
signal is terminated and operation resumes at the next switching cycle unless a different action is specified for the fast OCP
response in Register 0xFE00.
Rev. 0 | Page 12 of 84
Data Sheet
ADP1047/ADP1048
IL
PGND
60µA TO
120µA
VDD
ILIM
OCP
PGND
20µA TO
80µA
500mV
VDD
ADP1047/ADP1048
OCP
1500mV
ADP1047/ADP1048
09696-006
ILIM
IM
Figure 8. Fast Overcurrent Protection Schemes
500mV
0mV
1500mV
LEVEL SHIFTING
10k × 120µA = 1.2V
0mV
09696-007
LEVEL SHIFTING
10k × 80µA = 0.8V
Figure 9. Level Shifting and Threshold for OCP
Table 5. Programmable Options for Fast Overcurrent Protection
Parameter
Debounce Time
Blanking Time
Values or Options
40 ns, 80 ns, 120 ns, 240 ns
40 ns, 80 ns, 120 ns, 160 ns, 200 ns, 400 ns, 600 ns, 800 ns
Propagation Delay
140 ns typical
Threshold Value and Polarity
Level Shifting Current Sources
500 mV (negative); 1500 mV (positive)
60 μA, 80 μA, 100 μA, 120 μA (negative)
20 μA, 40 μA, 60 μA, 80 μA (positive)
Ignore (still terminates the PWM pulse); allow n switching
cycles, then shut down and soft start; allow n switching
cycles, then shut down and wait for PSON signal
Actions for Fast OCP
Rev. 0 | Page 13 of 84
Comments
Register 0xFE3D, Bits[4:3]
Blanking from the leading edge;
Register 0xFE3D, Bits[2:0]
Fixed value; does not include blanking or
debounce
Fixed values
Register 0xFE3E, Bits[7:5]
n = 1, 2, 4, 8; Register 0xFE00, Bits[7:6]
ADP1047/ADP1048
Data Sheet
CURRENT BALANCING (IBAL PIN, ADP1048 ONLY)
The ADP1048 has a dedicated circuit to maintain current balance
in each interleaved phase when operating in interleaved PFC
topology. This ensures that each interleaved phase provides equal
power regardless of the tolerance of the inductor and the boost
switch driving circuitry.
The input is through the IBAL pin specifically provided for the
ADP1048. The current balancing circuit monitors the current
flowing in both switches of the interleaved PFC topology and
stores this information. It compensates the PWM signals,
ensuring equal current flow to balance the current between
interleaved phases. Several switching cycles are required for
the circuit to operate effectively. The current balance settings
are programmed in Register 0xFE43 and Register 0xFE95.
The voltage sense can be calibrated digitally to remove any
errors due to external components (see the Output Voltage
(VFB) Calibration and Trim section). This calibration can
be performed in the production environment; the settings
are saved in the EEPROM of the ADP1047/ADP1048.
Input Voltage Sensing (VAC Pin)
The VAC pin is used for the monitoring and protection of the
rectified power supply input voltage. The sense point on the
power rail requires an external resistor divider to bring the signal
within the operating input range of the ADC (0 V to 1.6 V).
This scaled-down signal is fed into a high speed Σ-Δ ADC.
The output of the Σ-Δ ADC goes to the digital filter and is used
for the following purposes:
•
•
IBAL
Output Voltage Sensing (VFB Pin)
PGND
0° TO 180°
The VFB pin is used for the control, monitoring, and protection
of the output voltage. This voltage is the main feedback loop for
the power supply control loop. The sense point on the power rail
requires an external resistor divider to bring the signal within the
operating input range of the ADC (0 V to 1.6 V). This scaleddown signal is fed into a high speed Σ-Δ ADC.
ADC
+
K
–
ADC
180° TO 360°
PWM
OUTPUT OF PFC
CURRENT LOOP
PWM
The output of the Σ-Δ ADC goes to the digital filter and is used
for the following purposes:
09696-008
ADP1048
PWM2
•
Figure 10. Current Balancing (IBAL) for the ADP1048
VOLTAGE SENSE
Voltage sensing is used for the control, protection, and monitoring of the PFC stage. Input and output voltages are sensed using
dedicated ADCs and references (see Figure 11).
VREC
VAC
PGND
+ –
VOUT
VFB
•
OVP
+ –
+ –
ADC
OLP
OVP
11-BIT
ADP1047/ADP1048
09696-009
7-BIT
11-BIT
The 11-bit result is used at each half line cycle for the
normal control loop to control the value of the output
voltage.
The 10-bit, 1.5 kHz update rate is used for the fast voltage
control loop to control the value of the output voltage
during large transients.
To reduce the current distortion from the output voltage feedback, a prefilter is implemented before the voltage loop filter.
The prefilter detects the zero-crossing point of the input voltage
to identify the half input line cycle. The prefilter then performs
an averaging function for the sampled VFB signal during this
half line cycle. In this way, the fundamental frequency of the
output bulk voltage ripple and its harmonics are significantly
attenuated.
DAC
ADC
The output is decimated at the switching frequency for the
control loop. The effective number of bits (ENOB) is >7
when the current loop bandwidth is 10 kHz; the ENOB
is >10 when the current loop bandwidth is 1 kHz.
The 11-bit result is calculated and updated at each half line
cycle for high accuracy input voltage and power monitoring.
Figure 11. Typical Voltage Sense Configuration
Rev. 0 | Page 14 of 84
Data Sheet
ADP1047/ADP1048
OVERVOLTAGE PROTECTION
Fast Overvoltage Protection (OVP Pin)
The ADP1047/ADP1048 have two OVP circuits: an ADC-based
comparator and a fast comparator.
A fast OVP mode is implemented using a programmable
comparator on the OVP pin. Fast OVP is used for overvoltage
protection of the bulk capacitors and to provide open-loop
protection. The sense point on the power rail requires an
external resistor divider to match the divider applied to VFB.
This separate divider introduces a level of redundancy in
sensing the output voltage to improve system reliability.
Accurate Overvoltage Protection (VFB Pin)
Overvoltage protection (OVP) is implemented using the information available on the output of the VFB ADC. The information
from the VFB ADC is averaged over one half the ac line frequency;
therefore, the response of this OVP is relatively slow.
The threshold for the accurate OVP is fully programmable
using the VOUT_OV_FAULT_LIMIT register (Register 0x40).
The programmed value is the dc average voltage.
When the accurate OVP threshold is crossed, the accurate OVP
flag is set. The response to this flag can be programmed for one
of several actions using the VOUT_OV_FAULT_RESPONSE
register (Register 0x41). If the disable PWM option is selected,
a voltage hysteresis can be programmed for the accurate OVP
threshold using Register 0xFE50.
If the voltage divider on the VFB pin is damaged or drifts in
value, the OVP pin can still detect an overvoltage condition
and take the appropriate programmed action.
The fast OVP signal is fed into a comparator with a programmable threshold to set the trip point for overvoltage. The
threshold is set using a DAC.
Table 6. Programmable Options for Fast Overvoltage Protection (Fast OVP)
Parameter
Debounce Time
Values or Options
120 ns, 240 ns, 480 ns, 640 ns
Blanking Time
10 μs (fixed)
Propagation Delay
Threshold Rising
Threshold Falling
Actions for Fast OVP
120 ns max (fixed)
1 V to 1.5 V
1 V to 1.5 V
Immediate shutdown and wait for PSON;
disable PWM until the flag is cleared;
shut down and soft start; ignore (do nothing)
Rev. 0 | Page 15 of 84
Comments
Minimum duration of pulse to be considered;
programmable using Register 0xFE31, Bits[1:0]
Duration of time while the comparator is blanked
and the threshold changes from rising to falling
Does not include blanking or debounce
Programmable using Register 0xFE2F, Bits[6:0]
Programmable using Register 0xFE30, Bits[6:0]
Register 0xFE01, Bits[7:6]
ADP1047/ADP1048
Data Sheet
Figure 12 shows an example of the output voltage and the OVP
thresholds set. The rising and falling thresholds, FAST_OVP_
FAULT_RISE and FAST_OVP_FAULT_FALL, respectively, are
used for fast OVP protection. FAST_OVP_FAULT_RISE
corresponds to OVPUP, which is the trip point for overvoltage
protection (see Figure 13). FAST_OVP_FAULT_FALL corresponds to OVPDOWN, which is the reset point for the fast OVP.
When the rising threshold is triggered, the programmed action
is applied and the threshold is switched to the programmed falling threshold (if the programmed falling threshold is different
from the rising threshold).
A blanking time is applied when the thresholds are switched to
avoid spurious signals (see the timing diagram in Figure 13). A
programmable debounce time is applied to the OVP signal as
well to avoid false triggering.
ADC INPUT RANGE = 1.6V
1.6V
VOUT_OV_FAULT_LIMIT = 450V (REG 0x40)
FAST_OVP_FAULT_RISE = 435V (REG 0xFE2F)
VOUT_OV_WARN_LIMIT = 420V (REG 0x42)
FAST OVP
PROGRAMMING
RANGE
FAST_OVP_FAULT_FALL = 400V (REG 0xFE30)
1.0V
VOUT_COMMAND = 385V (REG 0x21)
ADC
FULL
RANGE
0.5V
VOUT_UV_FAULT_LIMIT = 200V (REG 0x44)
The rising and falling thresholds are programmable from 1 V
to 1.5 V (at the OVP pin) using Register 0xFE2F and Register
0xFE30, respectively.
Open-loop protection detects differences between the OVP and
VFB pins. Identical resistor dividers are applied to these pins;
therefore, if a voltage difference is present, it means that one or
more resistors in the dividers have the wrong values or are not
connected. In this case, it is usually recommended that the user
shut down the system to prevent damage.
09696-020
Open-Loop Protection
Figure 12. Output Voltage Levels
OVPUP
OUTPUT
VOLTAGE
OVP PIN
OVPDOWN
The open-loop protection detects a difference in voltage in
excess of ~100 mV, which equates to approximately 6.6% of
the full-scale range.
DEBOUNCE
10µs
TIME
09696-021
A debounce time of 10 μs is added to avoid false triggering. If
filtering capacitors are applied to the OVP and VFB pins, care
must be taken to make sure that the time constant difference
does not exceed 10 μs.
OVPFLAG
Figure 13. OVP Thresholds and Timing
Table 7. Programmable Options for Open-Loop Protection (OLP)
Parameter
Debounce Time
Propagation Delay
Actions for OLP
Values or Options
10 μs (fixed)
200 ns (fixed)
Immediate shutdown and wait for PSON;
disable PWM until the flag is cleared;
shut down and soft start; ignore (do nothing)
Rev. 0 | Page 16 of 84
Comments
Minimum duration of pulse to be considered
Does not include debounce
Register 0xFE02, Bits[7:6]
Data Sheet
ADP1047/ADP1048
POWER FACTOR CORRECTION CONTROL LOOP
The ADP1047/ADP1048 implement the average current mode
power factor correction control loop using a traditional multiplier approach. The implementation of the loop is digital, and
all the signals are converted from analog to digital before they
are processed by the control loop. Σ-Δ ADCs are used to achieve
high performance, cost-effective implementation. Each ADC
has its own dedicated voltage reference.
The frequency gains and zero locations can all be programmed
individually to tailor the loop response to the application. It is
recommended that the Analog Devices, Inc., GUI software be
used to program the filter (see the Software GUI section). The
GUI displays the filter response in Bode plot format and can be
used to calculate all stability criteria for the power supply.
DIGITAL COMPENSATION FILTERS
Instead of a single programmable compensation filter, the
ADP1047/ADP1048 offer the following filter presets so that
the dynamic response of the control loop can be tailored to
optimize different operating conditions.
Optimized Compensation Filters
The ADP1047/ADP1048 are digital PFC controllers with ac power
monitoring. They are implemented in the digital domain using
a dedicated state machine, which allows the user to program the
loop response specifically, with no need for external loop
compensation.
•
•
•
The detailed control loop configuration is illustrated in Figure 14.
VREF is the digital reference voltage setting; VFB is the sensed feedback voltage of the output. The difference between VREF and VFB
is processed first by the voltage loop filter (HV). Its output, VEA,
is then multiplied by the instantaneous rectified input voltage,
VAC, and divided by the square of the rms value of VAC. The result,
IREF, is used as the reference signal for the current. The output of
the current loop filter (HI) is the duty cycle command. The
mathematical expression is
I REF =
Low line current filter
High line current filter
Fast voltage compensation filter
The ADP1047/ADP1048 can be configured to switch automatically between the high and low line filters when the rms
value of the ac line crosses the programmed threshold between
the high and low lines. (The high line threshold is programmed
in Register 0xFE35; the low line threshold is programmed in
Register 0xFE36.)
The ADP1047/ADP1048 check for the value of the rms input
voltage at each half line cycle. When a transition between the
high and low line threshold is detected, the part waits for four
full line cycles before switching to the correct filter at the zero
crossing of the input line cycle. This is done to avoid spurious
transitions due to a missing or distorted voltage line cycle.
VEA × VAC
2
VAC
_ RMS
Both the voltage loop and current loop digital compensating
filters, HV(z) and HI(z), are programmable. The filter transfer
function in the digital domain is
During soft start, one of four combinations of filters can be
used, depending on whether the fast loop mode is enabled
and whether the high line or low line is detected for soft start
(see Table 8).
⎛z − a ⎞
⎜
⎟
256 ⎠
H(z) = k × b × ⎝
(z − 1)
where:
a is the filter zero.
b is the filter gain.
k is related to the switching frequency.
VAC
–
VREF +
IL
V2AC_RMS
HV (z)
IREF
VEA
–
+
DUTY CYCLE
HI (z)
09696-010
VFB
Figure 14. Control Loop Digital Filters
Table 8. Summary of the PFC Digital Compensation Filters for Soft Start
Line Filter
High Line
Low Line
Normal Compensation Filter
High line current filter, normal voltage filter
Low line current filter, normal voltage filter
Rev. 0 | Page 17 of 84
Fast Voltage Compensation Filter
High line current filter, fast voltage filter
Low line current filter, fast voltage filter
ADP1047/ADP1048
Data Sheet
Fast Loop Mode
VFB
During transients, a fast loop mode is enabled to allow for faster
loop responses. Typical timing can be seen in Figure 15. The
fast loop mode has separate settings and can be programmed to
respond quickly to load transients. The user can disable the fast
loop mode if it is not required by the application.
VFB ERROR
FAST LOOP
VFB FAST ERROR
VREC
ILOAD
FAST FILTER
@ 1.5kHz
Figure 16. Fast Loop Operation
PROGRAMMABLE
RANGE
PROGRAMMABLE
DELAY
(0 TO 7
HALF LINE
CYCLES)
09696-011
VOUT
09696-012
NORMAL FILTER
@ 100Hz
FAST LOOP
Figure 15. Fast Loop for Transient Response Improvement
When fast loop mode is enabled and the feedback output voltage
is out of range from the desired reference value (programmable
band of 1.5%, 3%, 6%, or 12%, set in Register 0xFE24), the
ADP1047/ADP1048 enter fast loop mode.
To ensure a smooth transition, the ADP1047/ADP1048 switch
from the regular filter to the fast loop filter at the zero crossing
of the rectified input voltage. When the output voltage returns
to regulation within the programmed band, the controller
switches back (after a programmable delay of 0 to 7 half line
cycles) to the normal loop at the next zero crossing of the
rectified input voltage.
If the output voltage does not return to regulation within the
programmed band after a fixed time of 630 ms, the control loop
automatically switches back to the normal loop.
In the normal compensation loop, the sampling frequency of
the output voltage is the same as the ripple oscillation frequency
(which is commonly 100 Hz or 120 Hz).
During fast loop operation, the feedback voltage is sampled
at 1.5 kHz, and the fast filter is applied to regulate the output
voltage. The output voltage is averaged and decimated at
1.5 kHz (see Figure 16).
Based on the requirements of the application, the user can enable
or disable the fast loop mode by programming Register 0xFE24.
It is recommended that fast loop mode be enabled for the
ADP1047/ADP1048 during large load transients. The fast loop
mode settings are also used during soft start, even when the fast
loop is disabled.
PULSE-WIDTH MODULATION
The ADP1047/ADP1048 can implement either leading edge or
trailing edge modulation. Trailing edge modulation is the more
popular modulation scheme. Using trailing edge modulation,
the rms ripple current in the bulk capacitors can be reduced
when used with downstream converter synchronization. It is
recommended that the Analog Devices, Inc., GUI software be
used to program PWM (see the Software GUI section).
DUTY CYCLE MINIMUM/MAXIMUM LIMITS
The ADP1047/ADP1048 allow the user to program the minimum off time and the minimum on time for the PWM outputs
separately, thereby allowing the minimum and maximum duty
cycles to be set.
The minimum off time represents the minimum time that the
PWM is low during each switching cycle. It can be programmed
from 40 ns to 1.2 μs in steps of 80 ns using Register 0xFE15,
Bits[3:0]. In this way, the maximum duty cycle can be clamped
between 96% and 99.8% at the minimum frequency and
between 48.8% and 96.8% at the maximum frequency.
The minimum on time is the smallest PWM pulse that the modulator generates on the PWM output. It can be programmed
from 0 ns to 1200 ns in steps of 80 ns using Register 0xFE15,
Bits[7:4].
AUXILIARY PWM OUTPUT (ADP1047 ONLY)
For the ADP1047, the PWM2 pin is the output for the auxiliary
PWM, which can be independent of the main PWM output.
PWM2 can be used as the control signal for auxiliary switching
in the zero-voltage transition soft-switched PFC boost circuit.
Rev. 0 | Page 18 of 84
Data Sheet
ADP1047/ADP1048
SWITCHING FREQUENCY PROGRAMMING
The switching frequency of the PWM outputs can be programmed from 30 kHz to 400 kHz using Register 0xFE1B, Bits[5:0] (see Table 9).
Table 9. Switching Frequency Settings from 30 kHz to 400 kHz (Register 0xFE1B, Bits[5:0])
Frequency
Setting
(Decimal)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency
(kHz)
30.05
32.55
35.51
39.06
43.40
48.83
52.06
55.80
60.10
65.10
71.02
78.13
86.81
97.66
100.81
104.17
Frequency
Setting
(Decimal)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Frequency
(kHz)
107.76
111.61
115.74
120.19
125.00
130.21
135.87
142.05
148.81
156.25
164.47
173.61
183.82
195.31
198.41
201.61
Frequency
Setting
(Decimal)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Rev. 0 | Page 19 of 84
Frequency
(kHz)
204.92
208.33
211.86
215.52
219.30
223.21
227.27
231.48
235.85
240.38
245.10
250.00
255.10
260.42
265.96
271.74
Frequency
Setting
(Decimal)
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Frequency
(kHz)
277.78
284.09
290.70
297.62
304.88
312.50
320.51
328.95
337.84
347.22
357.14
367.65
378.79
390.63
403.23
403.23
ADP1047/ADP1048
Data Sheet
LINE FAULT PROTECTIONS AND SOFT START SEQUENCING
PSON OPERATION
AC Line Period and Zero Crossing
To comply with PMBus standards, the PFC circuit controlled
by the ADP1047/ADP1048 can be turned on and off by the
hardware PSON pin and/or the software PSON command. The
setting of Bit 2 in Register 0x02 determines whether the PSON
pin and/or the PSON command is used. If the PSON pin is used,
the pin can be configured to be either active high or active low
(see Table 18).
The input ac line period is measured every half period of the ac
line cycle and is reported in the VAC_LINE_PERIOD register
(Register 0xFE85).
During the first 40 ms, the ac line period is measured between
two consecutive falling crossings of the threshold value, which
is set in the VAC_THRESHOLD_SET register (Register 0xFE25,
Bits[6:0]). The ac line period is then measured between two
consecutive falling crossings and compared to the average value
of the input line voltage, which is calculated during each half line
period. The VAC average reading can be found in the VAC_
THRESHOLD_READ register (Register 0xFE26, Bits[6:0]).
AC LINE DETECTION
The ADP1047/ADP1048 are capable of detecting several
parameters of the ac line input voltage and taking the appropriate programmed actions when necessary. The detection is
a combination of time and voltage measurements and is
implemented via the VAC pin, which detects the rectified ac
input voltage. This allows early detection of ac line faults and
early warning for the host system, thereby increasing reliability.
If the measured period is larger than MAX_AC_PERIOD_SET
or smaller than MIN_AC_PERIOD_SET, the default, MAX_AC_
PERIOD_SET, is used as the value of the period.
As shown in Figure 17, the two consecutive crossing points,
B and C, are used to determine the zero-crossing point of the
ac line. The middle point between B and C is calculated as the
zero-crossing point.
Five main parameters are related to ac line detection.
VAC_LINE_PERIOD (Register 0xFE85)
VAC_THRESHOLD_SET (Register 0xFE25)
VAC_THRESHOLD_READ (Register 0xFE26)
MIN_AC_PERIOD_SET (Register 0xFE27)
MAX_AC_PERIOD_SET (Register 0xFE28)
VAC
THRESHOLD
(REG 0xFE25)
This information is used by the control loop, as well as the
power metering block.
A
B
HALF AC
LINE PERIOD
Figure 17. AC Line Period Detection
Rev. 0 | Page 20 of 84
C
VAC AVERAGE
(REG 0xFE26)
09696-013
•
•
•
•
•
Data Sheet
ADP1047/ADP1048
AC Line Value Detection
To operate, the controller must detect the ac line value. At
startup, the controller waits for the PSON signal (hardware
PSON, software PSON, or both, depending on how the part
is programmed).
VAC
When the PSON signal is present, the controller looks for the
ac line period and value (see Figure 18).
TIMER
1/4
TIMER
1/4
VIN_LOW FLAG
(REG 0x7C[3])
VIN_ON (REG 0x35)
Figure 19. AC Line Early Fault Detection
VAC
09696-014
BROWN_OUT FLAG
(REG 0xFE80[2])
Figure 18. VAC Detection for Startup
The start-up value for the ac line used by the controller to
initiate the start-up procedure is stored in the VIN_ON register
(Register 0x35). This value is the minimum rms value of the ac
line required for the system to start up. The controller measures
the value of VAC at every half line cycle and compares it with
VIN_ON. If VAC is larger than the value in the VIN_ON register,
the soft start procedure is initiated and the BROWN_OUT flag
is reset.
AC Line Early Fault Detection
After the VIN_ON limit is crossed and the system starts up, the
controller constantly monitors the condition of the ac line (see
Figure 19).
To provide early detection of ac line faults, the instantaneous
value of VAC is compared to the VIN_OFF value in Register
0x36. If VAC remains below the VIN_OFF threshold for a time
longer than the programmed period, the VIN_LOW flag is set
in Register 0x7C. The programmed period can be either a fraction of the detected ac line period (one-quarter or one-half) or
it can be an absolute time (2 ms or 4 ms); the value is set in
Register 0xFE2E.
The controller does not take any action, but the VIN_LOW
signal can be used to set the AC_OK signal and to trigger
immediate actions in the power system.
The VIN_OFF threshold is intended solely to provide early
warning of problems on the ac line; it is not used to shut down
the power supply. The VIN_UV_FAULT_LIMIT register
(Register 0x59) is used for that purpose.
ADC INPUT RANGE = 1.6V
VIN_OV_FAULT_LIMIT = 270VAC (REG 0x55)
VACMAX = 265VAC
HIGH LINE LIMIT (VACTH) = 180V (REG 0xFE35)
HYSTERESIS
ZONE
LOW LINE LIMIT (VACTH) = 150V (REG 0xFE36)
VACMIN = 90VAC
VIN_ON = 85VAC (REG 0x35)
VIN_UV_WARN_LIMIT = 80VAC (REG 0x58)
Figure 20. Input Voltage Limits
Rev. 0 | Page 21 of 84
09696-016
VIN_OFF = 70VAC (REG 0x36)
VIN_UV_FAULT_LIMIT = 70VAC (REG 0x59)
09696-015
VIN_OFF (REG 0x36)
ADP1047/ADP1048
Data Sheet
SOFT START PROCEDURE
The PSON signal is used to enable or disable the PFC stage.
After PSON is asserted, the ADP1047/ADP1048 start monitoring VAC and, if the ac line conditions are met, they initiate the
soft start procedure, as shown in Figure 21.
Startup is gated by the rms value of the ac line voltage measured
on one half period of the ac line frequency. When VAC is above
the VIN_ON value, the BROWN_OUT flag is reset and the soft
start sequence is initiated. At the same time, the inrush delay
time and soft start delay time timers begin. Both of these timers
can be programmed to count 0 to 7 line cycles (or 0 to 14 half
line cycles in steps of 2).
After the inrush delay time programmed in Register 0xFE2E,
Bits[2:0], the INRUSH flag is reset and the inrush signal (Pin 17)
is asserted, closing the inrush current relay. (Note that the INRUSH
flag is active low.) The inrush signal is set at the zero crossing of
the ac voltage, if this crossing is detected. This setting allows
zero voltage turn-on if a solid-state switch is used (zero voltage
turn-on is not relevant with mechanical relays).
After the soft start delay time (programmed in Register 0xFE2D,
Bits[5:3]), the output voltage is ramped up according to the soft
start time programmed in Register 0xFE2D, Bits[2:0].
When output voltage regulation is reached and all flags are OK, the
POWER_GOOD# flag is reset and the PGOOD signal (Pin 16)
is set to Logic Level 1. (Note that the POWER_GOOD# flag is
active low.)
The soft start time can be programmed to one of eight values:
112 ms, 168 ms, 224 ms, 280 ms, 392 ms, 504 ms, 616 ms, or
728 ms (set in Register 0xFE2D, Bits[2:0]).
The soft start delay time (Register 0xFE2D, Bits[5:3]) can be
programmed from 0 to 7 full line cycles in increments of 1
(that is, two of the rectified half line cycles).
The inrush delay time (Register 0xFE2E, Bits[2:0]) can be programmed from 0 to 7 full line cycles in increments of 1 (that is,
two of the rectified half line cycles).
If no zero crossings are detected, the programmed maximum ac
line period, MAX_AC_PERIOD_SET (Register 0xFE28), is used.
LINE FAULT PROTECTIONS
Line faults occur when the ac line is not behaving correctly
and include anomalies such as a missing ac line cycle (can be
partial), brownout, or high distortion levels. When a line fault
occurs, the ADP1047/ADP1048 can be programmed to react
according to the situation.
Some of the flags can be blanked during soft start so that the
programmed action of the flag does not take place if the flag
is set during the soft start period (see Register 0xFE08 and
Register 0xFE09).
VIN_ON (REG 0x35)
VIN_OFF (REG 0x36)
VAC
VIN_LOW FLAG
(REG 0x7C[3])
BROWN_OUT FLAG
(REG 0xFE80[2])
VOUT
INRUSH
DELAY TIME = 2
(REG 0xFE2E[2:0])
SOFT START
DELAY TIME = 3
(REG 0xFE2D[5:3])
SOFT START TIME
(REG 0xFE2D[2:0])
Figure 21. Soft Start and Inrush Current Control Timing
Rev. 0 | Page 22 of 84
09696-017
INRUSH PIN
Data Sheet
ADP1047/ADP1048
Missing AC Line Cycles
PSON Delay
Figure 22 shows examples of the typical missing ac line cycles
fault. The VIN_LOW flag is set when the instantaneous voltage
is below VIN_OFF for more than a quarter or half line cycle
(depending on how it is programmed). This flag can be used as
an early warning to the system via the AC_OK pin when more
than a half cycle is missing. The BROWN_OUT flag is also set;
this flag does not cause a shutdown.
The PSON start delay is programmable using Register 0xFE06,
Bits[3:2]. Four options are available: 0 ms, 50 ms, 250 ms, and
1000 ms.
If any other flag that is programmed for shut down is set (in this
example, VOUT_UV_FAULT), the power supply shuts down,
the INRUSH pin is asserted, and the controller prepares for the
next soft start cycle.
If the BROWN_OUT flag is cleared before VOUT drops below
the VOUT_UV_FAULT_LIMIT value (Register 0x44), operation resumes in normal mode (or fast loop mode if enabled);
otherwise, if VOUT drops below VOUT_UV_FAULT_LIMIT,
the INRUSH pin is reset and a new soft start cycle is started.
Brownout Conditions
Brownout is another typical line fault condition in which the
line drops below the minimum specified operating level. This
level can be set with VIN_UV_FAULT_LIMIT (Register 0x59).
This flag can be programmed according to the standard PMBus
flag response. For example, it can be programmed to shut down
and restart after a certain delay.
During brownout, there are other conditions that can occur,
such as input overcurrent or output undervoltage. Each of these
faults can be programmed to shut down or disable the output,
based on the response action.
VIN_ON (REG 0x35)
VAC
VIN_OFF (REG 0x36)
VIN_LOW FLAG
(REG 0x7C[3])
BROWN_OUT FLAG
(REG 0xFE80[2])
INRUSH DELAY TIME
(REG 0xFE2E[2:0])
INRUSH PIN
SOFT START TIME
(REG 0xFE2D[2:0])
09696-018
VOUT
VOUT_UV_FAULT_LIMIT
(REG 0x44)
Figure 22. Line Fault (Missing Cycles) Timing Diagram
VAC
VIN_ON (REG 0x35)
VIN_UV_FAULT_LIMIT
(REG 0x59)
BROWN_OUT FLAG
(REG 0xFE80[2])
VIN_UV_FAULT FLAG
(1 CYCLE DEBOUNCE)
SHUTDOWN
09696-019
INRUSH PIN
Figure 23. Brownout Timing Diagram (VIN_UV_FAULT_RESPONSE Register Programmed to Shut Down After a One-Cycle Debounce)
Rev. 0 | Page 23 of 84
ADP1047/ADP1048
Data Sheet
ADVANCED INPUT POWER METERING
available to be read back through the interface until it is
overwritten by the next averaged value at the end of the next
averaging period.
The ADP1047/ADP1048 monitor and communicate critical
information, including input and output voltage, input and
output current, temperature, and efficiency. They also monitor
and communicate OVP, UVP, OCP, OTP, and open-loop protection functions. An I2C interface reads all these values and flags
and programs their thresholds. The on-chip EEPROM can be
used to store all of the settings for the thresholds.
For this reason, the polling frequency used to read average
power through the PMBus interface must be equal to or higher
than the averaging window to maintain data integrity. The
averaging window is programmable over a wide range of times
to accommodate different situations.
True rms values are calculated at the end of each half ac line
cycle by integrating the instantaneous values across each line
cycle. These values have a resolution of 11 bits and are used to
calculate the average, but are not available to be read through
the PMBus interface.
Input voltage, input current, output voltage, and input power
are reported in linear format in the following registers:
•
•
•
•
VAC
ADC
PGND
CS+
ADC
CS–
RMS
AVG
RMS
AVG
RMS
AVG
1
2
AC
SYNC
VIN
PIN
IIN
3
0 LINE CYCLES
TO 4096
LINE CYCLES
09696-022
The averaging window is programmable from zero full line
cycles to 4096 full line cycles using Register 0xFE3A. At the
end of each averaging period, the new value for average power
is written to the READ_PIN register (Register 0x97) and is
Input voltage: READ_VIN (Register 0x88)
Input current: READ_IIN (Register 0x89)
Output voltage: READ_VOUT (Register 0x8B)
Input power: READ_PIN (Register 0x97)
Figure 24. Block Diagram of Power Monitoring
Table 10. Data Format and Range for VIN, IIN, PIN, and VOUT
Metering Data
VIN
IIN
PIN
VOUT
Mantissa (Bits)
11
11
11
11
Exponent (N)
−3 to −1
−10 to −5
−4 to +3
−3 to 0
Minimum Range
256 V
2A
256 W
256 V
Rev. 0 | Page 24 of 84
Minimum LSB
0.125 V
0.976 mA
125 mW
0.125 V
Maximum Range
1024 V
64 A
32.8 kW
2048 V
Maximum LSB
0.5 V
0.03125 A
16 W
1V
Data Sheet
ADP1047/ADP1048
POWER SUPPLY SYSTEM AND FAULT MONITORING
The ADP1047/ADP1048 have extensive system and fault monitoring capabilities. The system monitoring functions include
voltage, current, power, and temperature readings. The fault
conditions include out of limit for current, voltage, power, and
temperature. The limits for the fault conditions are programmable.
An extensive set of flags is set when certain thresholds or limits
are exceeded. These flags are described in Table 11 and Table 12.
FLAG CONVENTIONS
A flag indicates a fault condition; therefore, a flag is set (equal to
1, or high) when the fault or bad condition occurs. Good flags,
such as POWER_GOOD# and AC_OK, are active low flags. For
example, POWER_GOOD# = 1 indicates a problem.
Note that the signals relative to a flag are active high. For
example, if the POWER_GOOD# flag is set to 1, the PGOOD
pin is at Logic Level 0 because the POWER_GOOD# flag is
inverted at the pin to provide active high signals.
MANUFACTURER-SPECIFIC FLAGS
The manufacturer-specific flags are flags that are not covered by
the PMBus specification. Some flags simply indicate a condition
(typically, warning flags). The response to some of the flags is
individually programmable (typically, fault flags).
There is also a set of latched fault registers. These registers contain the same flags, but the flags remain set to allow users to detect
an intermittent fault. Reading a latched register resets the flags
in that register. The latched fault registers are Register 0xFE80,
Register 0xFE81, and Register 0xFE82.
Table 11. Summary of Manufacturer-Specific Flags
Bit Name
MAX_MODULATION
MIN_MODULATION
OLP
Address
0xFE80[7]
0xFE80[6]
0xFE80[5]
Description (1 = Flag Set)
The maximum modulation limit is reached.
The minimum modulation limit is reached.
Signals a difference of more than ~100 mV between the VFB and OVP signals
(one of the two voltage dividers is probably disconnected or malfunctioning).
The threshold set for the comparator on the OVP pin has been crossed.
The controller is not able to detect the ac line period; the maximum value of
the period is used and this flag is set.
VAC is lower than the value stored in VIN_ON (Register 0x35).
The system is in soft start sequence; fast loop filter is in use.
INRUSH control relay is off.
FAST_OVP
AC_PERIOD
0xFE80[4]
0xFE80[3]
BROWN_OUT
SOFT_START
INRUSH
0xFE80[2]
0xFE80[1]
0xFE80[0]
EEPROM_UNLOCKED
EEPROM_CRC
I2C_ADDRESS
0xFE81[6]
0xFE81[5]
0xFE81[4]
LOW_LINE
FAST_OCP
SYNC_LOCK
AC_OK
0xFE81[3]
0xFE81[2]
0xFE81[1]
0xFE81[0]
LOW_POWER
0xFE82[5]
FAST_LOOP
0xFE82[4]
EEPROM is unlocked and its contents can be written.
The downloaded contents of the EEPROM are incorrect.
The resistor on the ADD pin has a value that can cause an error in the address
assignment (the address falls too close to the threshold between two
addresses).
The input voltage is higher than the high line threshold.
The threshold set for the comparator on the ILIM pin has been crossed.
External synchronization frequency is locked.
The output of the AC_OK pin is low. (This flag is a programmable combination
of other internal flags and refers to the condition of the input voltage.)
The input power has dropped below the threshold for low power mode
operation.
The fast loop compensation filter is in use.
VCORE_OV
VDD_3.3V_OV
VDD_3.3V_UV
0xFE82[3]
0xFE82[2]
0xFE82[1]
An overvoltage condition is present on the VCORE rail.
An overvoltage condition is present on the VDD rail.
An undervoltage condition is present on the VDD rail.
Rev. 0 | Page 25 of 84
Action
Programmable
Programmable
Can set AC_OK flag
INRUSH pin (can also
set AC_OK flag)
Programmable
Programmable
AC_OK pin
Programmable
Can set
POWER_GOOD# flag
Programmable
Programmable
Shutdown
ADP1047/ADP1048
Data Sheet
Figure 25 shows the bits in the six standard PMBus fault
response registers: Register 0x41, Register 0x45, Register 0x50,
Register 0x56, Register 0x5A, and Register 0x5C. All six PMBus
fault response registers follow the same format. For more information, see the PMBus Fault Flag Response section.
STANDARD PMBus FLAGS
When the corresponding bit of a standard PMBus flag is
set in the STATUS_WORD or STATUS_BYTE register,
the programmed action takes place as shown in Figure 25.
RESPONSE (BITS[7:6])
RETRY SETTING (BITS[5:3])
DELAY TIME (BITS[2:0])
00 =
DO
NOTHING
FAULT CLEARED
OUTPUT
DISABLED
11 = DISABLE OUTPUT
RETRY SETTING (BITS[5:3])
000 = NO RETRIES (OFF)
001 TO 110 = TRY 1 TO 6 TIMES
111 = RETRY FOREVER
FLAGS ARE
IGNORED
IF BLANKED
DELAY
TIME
(BITS[2:0])
SHUT
DOWN
FAULT
NOT
CLEARED
IF FLAG STILL ACTIVE
01 = SHUT DOWN (AFTER DEBOUNCE)
10 = IMMEDIATE SHUTDOWN
SOFT
START
09696-023
10
01 = S
= HU
C
O TD
N
TI OW
N
U N
E T
TH HE
EN N
R
R ET
ET R
RY Y
NORMAL
OPERATION
Figure 25. Standard PMBus Fault Response
Table 12. Summary of Standard PMBus Flags Implemented on the ADP1047/ADP1048
Name
STATUS_BYTE (0x78)
PSON_OFF
Address
Description
0x78[6]
VOUT_OV
0x78[5]
VIN_UV
TEMPERATURE
CML
NONE_OF_THE_ABOVE
STATUS_WORD (0x79)
VOUT
0x78[3]
0x78[2]
0x78[1]
0x78[0]
Power supply on signal: this flag indicates that the PSON signal (hardware
or software) is inactive.
General output overvoltage fault. This flag is a combination (OR) of any output
overvoltage flag: Register 0x7A[7] and Register 0xFE80[4] (FAST_OVP).
General input undervoltage fault (same data as in Register 0x7C[4]).
Temperature fault or warning.
Communications, memory, or logic fault.
A fault or warning not listed in Register 0x78[7:1].
INPUT
0x79[13]
MFR
0x79[12]
POWER_GOOD#
0x79[11]
UNKNOWN
0x79[8]
0x79[15]
Action
Any fault or warning on the output voltage (overvoltage, undervoltage, fast
OVP, or accurate OVP).
Input voltage, input current, or input power fault or warning (same data as
in Register 0x7C, Bits[7:0]).
Manufacturer-specific fault or warning (same data as in Register 0xFE80,
Register 0xFE81, and Register 0xFE82).
Power good. This flag is a programmable combination of other internal flags
and refers to the condition of the output voltage. This flag sets the PGOOD
pin. The POWER_GOOD# flag is an inverted version of the PGOOD pin.
A fault or warning not listed in Bits[15:1].
Rev. 0 | Page 26 of 84
Programmable
Programmable
Programmable
PGOOD pin
Data Sheet
Name
STATUS_VOUT (0x7A)
VOUT_OV_FAULT
VOUT_OV_WARN
VOUT_UV_WARN
VOUT_UV_FAULT
STATUS_INPUT (0x7C)
VIN_OV_FAULT
VIN_UV_WARN
VIN_UV_FAULT
VIN_LOW
ADP1047/ADP1048
Address
Description
Action
0x7A[7]
0x7A[6]
0x7A[5]
0x7A[4]
The output voltage is above the VOUT_OV_FAULT_LIMIT.
The output voltage is above the VOUT_OV_WARN_LIMIT.
The output voltage is below the VOUT_UV_WARN_LIMIT.
The output voltage is below the VOUT_UV_FAULT_LIMIT.
Programmable
0x7C[7]
0x7C[5]
0x7C[4]
0x7C[3]
The input voltage on VAC is larger than the value in VIN_OV_FAULT_LIMIT.
The input voltage on VAC is smaller than the value in VIN_UV_WARN_LIMIT.
The input voltage on VAC is smaller than the value in VIN_UV_FAULT_LIMIT.
VAC is lower than VIN_OFF. This signal shuts down the power supply.
IIN_OC_FAULT
0x7C[2]
IIN_OC_WARN
0x7C[1]
PIN_OP_WARN
STATUS_TEMPERATURE
(0x7D)
OT_FAULT
OT_WARN
0x7C[0]
The input current measured on the CS ADC is larger than the value in
IIN_OC_FAULT_LIMIT.
The input current measured on the CS ADC is larger than the value in
IIN_OC_WARN_LIMIT.
Input overpower warning.
0x7D[7]
0x7D[6]
The measured temperature is above the value set in OT_FAULT_LIMIT.
The measured temperature is above the value set in OT_WARN_LIMIT.
Programmable
Programmable
Programmable
Can set AC_OK
flag
Programmable
Can set AC_OK
flag
Programmable
PMBus FAULT FLAG RESPONSE
Concurrent Faults
All standard PMBus fault response registers follow the same
format. The six standard PMBus fault response registers are
When multiple faults occur at the same time, the state machine
executes the response that has the highest priority. Flag priority
is determined by the response of the faults as determined by
Bits[7:6]. The higher the number in these two bits, the higher
the priority.
•
•
•
•
•
•
VOUT_OV_FAULT_RESPONSE (Register 0x41)
VOUT_UV_FAULT_RESPONSE (Register 0x45)
OT_FAULT_RESPONSE (Register 0x50)
VIN_OV_FAULT_RESPONSE (Register 0x56)
VIN_UV_FAULT_RESPONSE (Register 0x5A)
IIN_OC_FAULT_RESPONSE (Register 0x5C)
The standard PMBus fault response registers are composed of
eight bits: Bits[7:6] define the response type, Bits[5:3] define the
retry settings, and Bits[2:0] contain the delay information.
Bits[7:6] define the response type as follows:
•
•
•
Bits[7:6] = 00 (ignore). When the corresponding fault flag
is set, no action is taken and the power supply continues to
operate normally.
Bits[7:6] = 01 or 10 (shutdown and retry). When the corresponding fault flag is set, the system shuts down and then
retries for the number of times programmed in Bits[5:3].
The difference between the 01 and 10 options is that when
Bits[7:6] = 01, a debounce (programmed in Bits[2:0]) is
applied to the flag.
Bits[7:6] = 11 (disable output). When the corresponding
fault flag is set, the system does not enter a shutdown/soft
start sequence. Instead, the output is disabled indefinitely
until the flag is cleared. Care must be taken when selecting
this option because it may cause the system to stall in an
endless loop.
For example, if OVP is programmed to disable the output
(Bits[7:6] = 11) and OCP is programmed to shut down and
retry after a delay (Bits[7:6] = 01), and both faults occur at the
same time, the OVP action is executed first. If the OVP condition is cleared and the OCP flag is still set, the programmed
action for OCP is executed.
If two or more faults occur at the same time and all the faults
have the same response priority, the fault with the smallest retry
setting takes priority. For example, if one fault has a retry setting
programmed to 011 and the other has a retry setting of 001, the
lower number of retries is executed.
Rev. 0 | Page 27 of 84
ADP1047/ADP1048
Data Sheet
MANUFACTURER-SPECIFIC FLAG RESPONSE
Four different actions can be programmed for this flag.
Manufacturer-specific flags follow a different response from the
standard PMBus flags because these flags are much faster and,
in some cases, operate on a pulse-by-pulse basis.
•
•
00 (ignore, do nothing). No action is taken.
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
programmed in the VOUT_OV_FAULT_RESPONSE
register (Register 0x41, Bits[2:0]).
10 (immediate shutdown and wait for PSON). The power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). The PWM is
disabled until the flag is cleared; no soft start is done.
FAST OCP Flag Response (Register 0xFE00)
The fast OCP flag responds to an overcurrent condition that
occurs on the comparator connected to the ILIM pin. This
comparator performs a pulse-by-pulse current limiting function (see the Fast Overcurrent Protection (ILIM Pin) section).
Four different actions can be programmed for this flag using
Bits[7:6]. Regardless of the programmed flag response, the PWM
pulse is always terminated when the threshold programmed for
the comparator is crossed.
•
•
•
00 (ignore, do nothing). No action is taken. The PWM
pulses are still terminated as long as the OCP condition
persists.
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
that is programmed in the IIN_OC_FAULT_RESPONSE
register (Register 0x5C, Bits[2:0]).
10 (shutdown and wait for PSON). After the number
of switching cycles programmed in Bits[5:4], the power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). After the
number of switching cycles programmed in Bits[5:4], the
PWM is disabled until the flag is cleared; no soft start is
initiated.
FAST OVP Flag Response (Register 0xFE01)
The fast OVP flag responds to an overvoltage condition on
the programmable comparator connected to the OVP pin.
This comparator constantly monitors the output voltage and
its operation (see the Fast Overvoltage Protection (OVP Pin)
section).
•
OLP Flag Response (Register 0xFE02)
The OLP flag responds to differences between the OVP and
VFB pins. Open-loop protection detects a difference in voltage
in excess of ~100 mV, which equates to approximately 6.6% of
the full-scale range (see the Open-Loop Protection section).
Four different actions can be programmed for this flag.
•
•
00 (ignore, do nothing). No action is taken.
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
programmed in the VOUT_OV_FAULT_RESPONSE
register (Register 0x41, Bits[2:0]).
10 (immediate shutdown and wait for PSON). The power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). The PWM is
disabled until the flag is cleared; no soft start is done.
•
•
VDD and VCORE OV Flag Response (Register 0xFE03 and
Register 0xFE04)
These two flags respond to an overvoltage condition on the
VDD (3.3 V) and VCORE (2.5 V) rails. These rails must be
properly decoupled and filtered to guarantee proper operation
of the digital controller. The controller can be programmed to
ignore the flags or to shut down and restart. A debounce time
of 2.56 μs or 660 μs can be set.
The controller can also be instructed to reload the contents
of the EEPROM upon restart or to resume operation without
reloading the EEPROM contents. Reloading the contents of the
EEPROM to RAM prevents device malfunction if the RAM
contents have been corrupted during the overvoltage condition.
ILIM
FAST OCP
BLANKING AND
DEBOUNCE
TERMINATE
PWM PULSE
TIMEOUT
1 TO 8 TIMES
Figure 26. Fast OCP Flag
Rev. 0 | Page 28 of 84
FLAG SET,
PROGRAMMED
ACTIONS
09696-024
•
•
Data Sheet
ADP1047/ADP1048
MONITORING FUNCTIONS
OVERTEMPERATURE PROTECTION (OTP)
Voltage, current, power, and temperature measurements are
taken by the ADP1047/ADP1048. These values are stored in
the following registers and can be read through the PMBus
interface.
If the temperature sensed at the RTD pin exceeds the programmable fault threshold, the OTP flag is set, and the power supply
can be programmed to shut down. A PTC or NTC thermistor
can be used.
•
•
•
•
•
To set the fault and warning thresholds for OTP, program
Register 0xFE19 and Register 0xFE1A, respectively. To set the
temperature hysteresis for the fault and warning thresholds,
program Register 0xFE3F. The response to an OTP fault flag
is programmable in Register 0x50.
Input voltage measurement (Register 0x88)
Output voltage measurement (Register 0x8B)
Input current measurement (Register 0x89)
Input power measurement (Register 0x97)
Temperature measurement (Register 0xFE86)
AC_OK AND PGOOD SIGNALS
The ADP1047/ADP1048 provide a FLAG_FAULT_ID register
(Register 0xFE07) that records the first fault that causes a system
shutdown. For example, if the overtemperature (OT) fault causes
the system to shut down, the OT_FAULT flag (0011) is stored in
the FLAG_ FAULT_ID register (Register 0xFE07, Bits[3:0]). In
addition, the flag ID of the fault that occurred before the fault
that caused the system shutdown is included in Bits[7:4] of
Register 0xFE07.
The contents of this register are stored until read by the user. The
flag ID is also saved in EEPROM when the shutdown occurs. In
this way, it is possible to determine the cause of a shutdown in
case of system failure.
The ADP1047/ADP1048 have two digital status pins: AC_OK
and PGOOD. Both signals represent an OR function for a programmable list of internal flags. Users can blank some of these
flags to tailor the AC_OK and PGOOD signals to their needs
using Register 0xFE0B and Register 0xFE0A, respectively.
When the signals on the AC_OK and PGOOD pins are set,
the corresponding internal flag is also set.
The programmable delay block acts like a debounce. That is, the
signal must be active for at least the duration of the programmed
delay before the flag is set. The debounce times for the AC_OK and
PGOOD pins can be programmed separately in Register 0xFE05.
PGOOD_FLAGS_LIST
(PROGRAMMABLE
LIST OF FLAGS)
REG 0xFE0A
PROGRAMMABLE
DELAY BLOCK
PGOOD
AC_OK_FLAGS_LIST
(PROGRAMMABLE
LIST OF FLAGS)
REG 0xFE0B
PROGRAMMABLE
DELAY BLOCK
AC_OK
09696-025
FIRST ERROR FAULT
Figure 27. AC_OK and PGOOD Signals
Table 13. Flags Available to Program the AC_OK and PGOOD Pins
AC_OK_FLAGS_LIST (Register 0xFE0B)1
VIN_LOW (always checked)
VIN_UV_FAULT (Bit 7)
VIN_UV_WARN (Bit 6)
IIN_OC_FAULT (Bit 5)
IIN_OC_WARN (Bit 4)
FAST_OCP (Bit 3)
AC_LINE_PERIOD (Bit 2)
BROWN_OUT (Bit 1)
INRUSH (Bit 0)
1
PGOOD_FLAGS_LIST (Register 0xFE0A)1
VOUT_OV_FAULT (always checked)
VOUT_UV_FAULT (Bit 7)
VOUT_OV_WARN (Bit 6)
FAST_OVP (Bit 5)
OLP (Bit 4)
FAST_OCP (Bit 3)
IIN_OC_FAULT (Bit 2)
OT_FAULT (Bit 1)
FAST_LOOP (Bit 0)
To blank one or more flags so that the AC_OK or PGOOD pin ignores it, set the corresponding bit to 1 in Register 0xFE0A or Register 0xFE0B.
Rev. 0 | Page 29 of 84
ADP1047/ADP1048
Data Sheet
ADVANCED FEATURES
The advanced features of the ADP1047/ADP1048 include
PWM FREQUENCY SYNCHRONIZATION
•
•
•
The part can synchronize the internal PWM clock with an
external clock frequency; the external source must be within the
minimum and maximum synchronization range programmed
in the part. To enable PWM frequency synchronization, set
Register 0xFE4F, Bit 1, to 1.
•
•
•
•
All advanced features other than bridgeless boost operation are
enabled by setting the appropriate bit in Register 0xFE4F.
FREQUENCY DITHERING (SPREAD SPECTRUM)
The PWM signal can be altered digitally to optimize for EMI
reduction (see Figure 28). For a wider but lower EMI spectrum,
the switching frequency varies with the rectified line voltage.
The switching cycle changes linearly with time from 87.5% to
112.5% of the nominal value, resulting in a frequency variation
of 114% to 89% of the nominal value.
To enable frequency dithering, set Register 0xFE4F, Bit 0, to 1.
To configure the dithering period, program Register 0xFE1D.
VREC
The capture range for the SYNC period is 87.5% to 112.5% of
the programmed switching period. The switching frequency
synchronized to the SYNC pin is limited by the frequency set
in Register 0xFE1B. The maximum range for the synchronized
frequency is from 89% to 114% of the programmed switching
frequency. The delay between the external SYNC signal and the
start of the internal switching cycle can be programmed using
Register 0xFE4C.
The part synchronizes to the external clock frequency as follows:
1.
2.
3.
The part attempts to determine the external clock period,
averaging it over seven cycles (frequency capture mode).
After the period of the SYNC signal is determined, the
internal PWM clock is adjusted until the phase is also
aligned. At that point, internal and external clocks are
synchronized (phase capture mode).
Each internal switching cycle is terminated after the SYNC
rising edge is detected (pulse-by-pulse synchronization).
If the external SYNC signal is lost at any time or if the period
exceeds the minimum/maximum limit, the internal clock goes
back to the maximum period set in Register 0xFE1B.
During the soft start phase, the SYNC pin is ignored and the
clock frequency is not synchronized.
Interleaved operation of a multiphase PFC circuit is realized by
using the SYNC pin of several ADP1047/ADP1048 controllers.
The frequency synchronization feature is optional. When
enabled, the switching frequency can be programmed to 1,
1/2, 1/3, or 1/4 of the SYNC frequency using Register 0xFE1E.
TIME
SWITCHING
CYCLE
SMART OUTPUT VOLTAGE (LOAD LINE)
112.5% t SW
To achieve higher efficiency, the output voltage can be
programmed according to the load power and input voltage
condition (see Figure 29). To enable the smart output voltage
feature, set Register 0xFE4F, Bit 2, to 1.
tSW
87.5% tSW
OUTPUT
VOLTAGE
TIME
VOH
SUPER HIGH LINE
VOH2
SWITCHING
FREQUENCY
114% f SW
VOH1
fSW
89% fSW
VOL2
HIGH LINE
LOW LINE
VOL1
TIME
1/f DITHER
2/f DITHER
09696-026
POWER
Figure 28. Switching Frequency Dithering Control
Rev. 0 | Page 30 of 84
P1
P2
100%
Figure 29. Smart Output Voltage Control (Load Line)
09696-027
•
Frequency dithering for EMI noise minimization
PWM frequency synchronization with external source
Smart output voltage: real-time efficiency optimization by
changing the output voltage based on ac line and output power
Smart switching frequency: real-time efficiency
optimization by changing the switching frequency
Current loop filter for light load: real-time THD
optimization at light load conditions
Phase shedding (ADP1048 only): real-time efficiency
optimization by shutting down one phase
Current loop feedforward: power factor and THD
optimization at light load conditions
Bridgeless boost operation (ADP1048 only)
Data Sheet
ADP1047/ADP1048
When the rms value of the input voltage is higher than the super
high line input (for example, 250 V), the load line is flat, that is,
the output voltage remains at VOH, which is independent of the
power. To avoid output voltage oscillation when the input voltage
is around the super high line level, voltage hysteresis can be
programmed using Register 0xFE4D. It is recommended that
at least 16 V of hysteresis be programmed.
CURRENT LOOP FILTER FOR LIGHT LOAD
To achieve low THD under light load conditions, the ADP1047/
ADP1048 offer current loop filter presets for light load operation under both high line input and low line input (see Figure 31).
To enable the current loop filter for light load feature, set
Register 0xFE4F, Bit 5, to 1.
AC LINE
HIGH LINE
LIGHT LOAD
When the rms value of the input voltage is lower than the super
high line input but higher than the high line threshold, there is
a load line between P1 and P2 in terms of power. The output
voltage varies between VOH1 and VOH2 as a linear function
of the output power when the output power falls within the
range between P1 and P2. The power levels of P1 and P2 are
programmable using Register 0xFE44 and Register 0xFE45,
respectively. When the power is below P1, the output voltage
remains unchanged at VOH1. When the power is higher than
P2, the output voltage remains unchanged at VOH2.
The bottom load line in Figure 29 applies when the rms value of
the input voltage is lower than the low line threshold. The output
voltage varies between VOL1 and VOL2 as a linear function of
the output power when the output power falls within the range
between P1 and P2. When the power is below P1, the output
voltage remains unchanged at VOL1. When the power is higher
than P2, the output voltage remains unchanged at VOL2.
The user can program values for VOH, VOH2, VOH1, VOL2, and
VOL1 using Register 0xFE4A, Register 0xFE49, Register 0xFE48,
Register 0xFE47, and Register 0xFE46, respectively.
SMART SWITCHING FREQUENCY
For higher efficiency, the switching frequency of the ADP1047/
ADP1048 can be programmed according to the load power condition (see Figure 30). To enable the smart switching frequency
feature, set Register 0xFE4F, Bit 3, to 1.
SWITCHING
FREQUENCY
HIGH LINE
HIGH/LOW LINE
THRESHOLD
LOW LINE
LIGHT LOAD
LIGHT LOAD
LOW LINE
POWER
THRESHOLD
INPUT POWER
09696-029
Three load lines address super high line, high line, and low line
input voltage conditions.
Figure 31. Current Loop Filter at Light Load Condition
When the input power drops below the low power threshold, PTH
(set in Register 0xFE32), the current loop filter switches to the
light load filter after four full line cycles. When the input power
goes above PTH plus the programmed hysteresis, the current loop
filter switches back to the normal mode filter immediately. This
applies to both high line and low line input.
PHASE SHEDDING (ADP1048 ONLY)
To achieve high efficiency at light load, the ADP1048 can shut
down one PWM output under light load conditions. When the
input power drops below the low power threshold, PTH (set in
Register 0xFE32), one PWM output is disabled. When the input
power goes above the low power threshold plus power hysteresis
(set in Register 0xFE4E), the PWM resumes operation. To enable
phase shedding for the ADP1048, set Register 0xFE4F, Bit 4, to 1.
CURRENT LOOP FEEDFORWARD
fS
Current loop feedforward is implemented in the ADP1047/
ADP1048 to improve the power factor and reduce THD under
light load conditions (see Figure 32). To enable current loop
feedforward, set Register 0xFE4F, Bit 6, to 1.
FULL POWER
IL
Figure 30. Smart Switching Frequency Control
The smart switching frequency feature uses two different
switching frequencies for heavy load and light load conditions.
When the output power is lower than the low power threshold,
PTH, the PFC circuit switches at the fSL frequency. When the output power is higher than PTH plus power hysteresis, the circuit
switches at the normal set frequency, fS.
Hysteresis can be programmed in Register 0xFE4E. The user
can program the values for fSL and PTH in Register 0xFE1C and
Register 0xFE32, respectively.
Rev. 0 | Page 31 of 84
IREF
+
–
HI (z)
DUTY CYCLE
+
+
VAC
–VREF
Figure 32. Current Loop Feedforward
09696-030
POWER
PTH
09696-028
fSL
ADP1047/ADP1048
Data Sheet
During the positive ac line phase, only one boost stage is effectively working. The second one is passive, and the current flows in
Q2 from the source to the drain. Turning the Q2 FET fully on
during this phase allows conduction losses in Q2 to be minimized.
BRIDGELESS BOOST OPERATION (ADP1048 ONLY)
The bridgeless boost configuration allows removal of the conduction losses caused by the input bridge of the PFC converter.
In this configuration, it is necessary to drive the two power
MOSFETs separately to achieve the highest efficiency. The
ADP1048 can provide such signals. The IBAL pin is used to
detect the ac line phase and zero crossings. Note that the maximum rating on the IBAL pin is VDD + 0.3 V; therefore, a clamp
circuit must be connected to the IBAL pin.
AC
INPUT
When the ac line phase becomes negative, the roles of Q1 and Q2
are reversed, and Q2 actively switches while Q1 is always on. The
phase information is detected from the ac line via the IBAL pin.
During the soft start phase, both FETs are switching as a precautionary measure; the same happens when the phase information
on the IBAL pin becomes corrupted or inaccurate.
T3
VOUT
RELAY
T1
T2
BULK
CAPACITOR
VREC
Q1
Q2
3.3V
AGND
VDD 24
VAC
RES 23
3
VFB
RTD 22
4
OVP
ADD 21
5
PGND
SDA 20
6
ILIM
SCL 19
7
IBAL
8
CS–
INRUSH 17
9
PMBus
SYNC 18
CS+
PGOOD 16
10
DGND
AC_OK 15
11
PSON
PWM2 14
12
VCORE
PWM 13
09696-031
T1 + T2 + T3
1
2
ADP1048
Figure 33. Schematic of Bridgeless PFC Circuit with the ADP1048
VAC
IBAL PIN
09696-032
PWM
PWM2
Figure 34. Bridgeless Boost Operation
Rev. 0 | Page 32 of 84
Data Sheet
ADP1047/ADP1048
POWER SUPPLY SYSTEM CALIBRATION AND TRIM
The ADP1047/ADP1048 allow the entire power supply to be
calibrated and trimmed digitally in the production environment. The device can calibrate items including the output
voltage, input voltage, input current, and input power, and it
can trim for tolerance errors introduced by sense resistors,
current transformers, and resistor dividers, as well as for its
own internal circuitry.
The part comes factory trimmed at 90% of the input range at a
3.3 V supply, but it can be re-trimmed by the user to compensate for the errors introduced by external components. With the
exception of the gain and offset trim registers for input power,
the trim registers must be unlocked for write access. To unlock
the trim registers, write to the TRIM_PASSWORD register
(Register 0xD6).
2.
For VAC offset trim, adjust the value in Register 0xFE53.
CURRENT SENSE GAIN AND OFFSET TRIM
The current sense can be calibrated digitally to remove any
errors due to external components.
1.
2.
OUTPUT VOLTAGE (VFB) CALIBRATION AND TRIM
The voltage sense inputs are optimized for sensing signals at
90% of the input range and cannot sense signals greater than
1.6 V. In a high voltage system, a resistor divider is required to
reduce the high voltage signal to below 1.6 V. It is recommended
that the high voltage signal be reduced to 1 V for best performance. The resistor divider can introduce errors, which must be
trimmed out as follows:
1.
2.
3.
Apply the maximum load to the output with the low line
input voltage.
To match the input current reading at the maximum
nominal input current, adjust the CS ADC gain trim
register until the CS value (Register 0x89, READ_IIN)
equals the measured result of the input current from
calibrated equipment.
If the 500 mV input range is used, adjust Register 0xFE42.
If the 750 mV range is used, adjust Register 0xFE7E.
For CS offset trim, adjust the values in Register 0xFE54 (500 mV
input range) or Register 0xFE7F (750 mV input range).
INPUT POWER GAIN AND OFFSET TRIM
Turn on the power supply with no load attached.
The input power trim has separate trim registers for high line
and low line input.
The output voltage is divided down by the feedback resistor
divider to supply 1 V across the VFB and AGND pins.
1.
Use a calibrated multimeter to perform the output voltage
reading.
Adjust the VFB ADC gain trim register (Register 0xFE41)
until the power supply outputs the exact value in the
READ_VOUT register (Register 0x8B).
INPUT VOLTAGE (VAC) GAIN AND OFFSET TRIM
The input voltage sense point on the power rail requires an
external resistor divider to bring the signal within the operating
input range of the VAC ADC (0 V to 1.6 V). The resistor divider
can introduce errors, which must be trimmed out as follows:
1.
Adjust the VAC ADC gain trim register (Register 0xFE40)
until the VAC value (Register 0x88, READ_VIN) equals
the input voltage reading from a calibrated multimeter.
This step trims for errors in the resistor divider network.
Apply the maximum line voltage value to the input of the
power supply.
The VAC resistor divider divides this voltage down at the VAC
pin. The VAC resistor divider is programmed in linear format
using the VIN scale monitor register (Register 0xFE3B).
2.
3.
4.
Apply the maximum load to the output with the low line
input voltage.
Adjust the power metering gain trim for low line input
register (Register 0xFE34) until the input power value in
the READ_PIN register (Register 0x97) equals the
measured result of the input power from calibrated
equipment.
Apply the maximum load to the output with the high line
input voltage.
Adjust the power metering gain trim for high line input
register (Register 0xFE8F) until the input power value in
the READ_PIN register (Register 0x97) equals the
measured result of the input power from the calibrated
equipment.
For input power offset trim, adjust the values in Register 0xFE33
(for low line input) and Register 0xFE8E (for high line input).
Rev. 0 | Page 33 of 84
ADP1047/ADP1048
Data Sheet
PMBus DIGITAL COMMUNICATION
The PMBus slave allows a device to interface to a PMBuscompliant master device as specified by the PMBus Power
System Management Protocol Specification (Revision 1.1,
February 5, 2007). The PMBus slave is a 2-wire interface that
can be used to communicate with other PMBus-compliant
devices and is compatible in a multimaster, multislave bus
configuration.
FEATURES
The function of the PMBus slave is to decode the command sent
from the master device and respond as requested. Communication is established using an I2C-like 2-wire interface with
a clock line (SCL) and data line (SDA). The PMBus slave is
designed to externally move chunks of 8-bit data (bytes) while
maintaining compliance with the PMBus protocol. The PMBus
protocol is based on the SMBus Specification (Version 2.0,
August 2000). The SMBus specification is, in turn, based on
the Philips I2C Bus Specification (Version 2.1, January 2000).
The PMBus incorporates the following features:
•
•
•
•
•
•
•
Slave operation on multiple device systems
7-bit addressing
100 kHz and 400 kHz data rates
General call address support
Support for clock low extension
Separate multiple byte receive and transmit FIFO
Extensive fault monitoring
When communicating with the master device, it is possible
for illegal or corrupted data to be received by the PMBus slave
device. In this case, the PMBus slave device should respond to
the invalid command or data, as defined by the PMBus specification, and indicate to the master device that an error or fault
condition has occurred. This method of handshaking can be
used as a first level of defense against programming of the slave
device that can potentially damage the chip or system.
The PMBus specification defines a set of generic PMBus
commands that is recommended for a power management
system. However, each PMBus device manufacturer can choose
to implement and support certain commands as it deems fit for
its system. In addition, the PMBus device manufacturer can
choose to implement manufacturer-specific commands whose
functions are not included in the generic PMBus command set.
The list of standard PMBus and manufacturer-specific commands
can be found in the Standard PMBus Commands Supported by
the ADP1047/ADP1048 section and the Manufacturer-Specific
PMBus Command section.
PMBus ADDRESS
Control of the ADP1047/ADP1048 is implemented via the I2C
interface. The ADP1047/ADP1048 are connected to the bus as
slave devices under the control of a master device.
The PMBus address of the ADP1047/ADP1048 is set by
connecting an external resistor from the ADD pin to ground.
Table 14 lists the recommended resistor values and associated
PMBus addresses. Eight different addresses can be used.
OVERVIEW
The PMBus slave module is a 2-wire interface that can be used
to communicate with other PMBus-compliant devices. Its transfer protocol is based on the Philips I2C transfer mechanism. The
ADP1047/ADP1048 are always configured as slave devices in the
overall system. The ADP1047/ADP1048 communicate with the
master device using one data pin (SDA) and one clock pin (SCL).
Because the ADP1047/ADP1048 are slave devices, they cannot
generate the clock signal. However, they are capable of clockstretching the SCL line to put the master device in a wait state
when they are not ready to respond to the master’s request.
Communication is initiated when the master device sends a
command to the PMBus slave device. Commands can be read
or write commands, in which case, data is transferred between
the devices in a byte wide format. Commands can also be send
commands, in which case, the command is executed by the
slave device upon receiving the stop bit. The stop bit is the last
bit in a complete data transfer, as defined in the PMBus/I2C
communication protocol. During communication, the master
and slave devices send acknowledge (A) or no acknowledge
(A) bits as a method of handshaking between devices. See the
PMBus specification for a more detailed description of the
communication protocol.
Table 14. PMBus Address Settings
Address
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
ADD Pin Resistor Value (kΩ)
10 (or connect directly to AGND)
30
50
69
89
109
128
148 (or connect directly to VDD)
If an incorrect resistor value is used and the resulting I2C address is
close to a threshold between two addresses, the I2C_ADDRESS
flag is set (Bit 4 of Register 0xFE81). The recommended resistor
values in Table 14 can vary by ±2 kΩ. Therefore, it is recommended that 1% tolerance resistors be used on the ADD pin.
The part responds to the standard PMBus broadcast address
(general call) of 0x00.
Rev. 0 | Page 34 of 84
Data Sheet
ADP1047/ADP1048
“A” represents the ACK (acknowledge) bit. The ACK bit is typically active low (Logic 0) if the transmitted byte is successfully
received by a device. However, when the receiving device is the
bus master, the acknowledge bit for the last byte read is a Logic 1,
indicated by A.
DATA TRANSFER
Format Overview
The PMBus slave follows the transfer protocol of the SMBus
specification, which is based on the fundamental transfer
protocol format of the Philips I2C Bus Specification, dated
January 2000. Data transfers are byte wide, lower byte first.
Each byte is transmitted serially, most significant bit (MSB)
first. A typical transfer is diagrammed in Figure 35. See the
SMBus and I2C specifications for an in-depth discussion of
the transfer protocols.
7-BIT SLAVE
ADDRESS
W
A
8-BIT DATA
A
Data transfer using the PMBus slave is established using PMBus
commands. The PMBus specification requires that all PMBus
commands start with a slave address with the R/W bit cleared
(set to 0), followed by the command code. All PMBus commands
supported by the ADP1047/ADP1048 follow one of the protocol
types shown in Figure 36 through Figure 42.
P
09696-135
S
Command Overview
MASTER TO SLAVE
SLAVE TO MASTER
The PMBus slave module also supports manufacturer-specific
extended commands. These commands follow the same protocol
as the standard PMBus commands. However, the command
code consists of the following two bytes:
Figure 35. Basic Data Transfer
Figure 35 through Figure 42 use the following abbreviations:
S = start condition
Sr = repeated start condition
P = stop condition
R = read bit
W = write bit
A = acknowledge bit (0)
A = acknowledge bit (1)
•
•
The command code extension, 0xFE
The extended command code, 0x00 to 0xFF
Using the manufacturer-specific extended commands, the
PMBus device manufacturer can add an additional 256
manufacturer-specific commands to its PMBus command set.
SLAVE ADDRESS
W
A
COMMAND CODE
A
P
09696-136
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 36. Send Byte Protocol
W
A
COMMAND
CODE
A
DATA BYTE
A
P
09696-137
SLAVE
ADDRESS
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 37. Write Byte Protocol
W
COMMAND
CODE
A
DATA BYTE
LOW
A
A
DATA BYTE
HIGH
A
P
09696-138
SLAVE
ADDRESS
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 38. Write Word Protocol
W
A
COMMAND
CODE
A Sr
SLAVE
ADDRESS
R
A
DATA BYTE
A
P
09696-139
SLAVE
ADDRESS
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 39. Read Byte Protocol
SLAVE
ADDRESS
W
A
COMMAND
CODE
A Sr
SLAVE
ADDRESS
R
A
DATA BYTE
LOW
A
DATA BYTE
HIGH
A
P
09696-140
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 40. Read Word Protocol
SLAVE
ADDRESS
W
A
COMMAND
CODE
A
BYTE COUNT
=N
A
DATA BYTE 1
A
DATA BYTE N
A
P
09696-141
S
MASTER TO SLAVE
SLAVE TO MASTER
Figure 41. Block Write Protocol
Rev. 0 | Page 35 of 84
ADP1047/ADP1048
SLAVE
ADDRESS
W
A
COMMAND
CODE
A Sr
SLAVE
ADDRESS
R
A
BYTE COUNT
=N
A
DATA BYTE 1 A
DATA BYTE N A
P
09696-142
S
Data Sheet
MASTER TO SLAVE
SLAVE TO MASTER
Figure 42. Block Read Protocol
Clock Generation and Stretching
FAST MODE
The ADP1047/ADP1048 are always PMBus slave devices in the
overall system; therefore, the device never needs to generate the
clock, which is done by the master device in the system. However, the PMBus slave device is capable of clock stretching to
put the master in a wait state. By stretching the SCL signal
during the low period, the slave device communicates to the
master device that it is not ready and that the master device
must wait.
Fast mode (400 kHz) uses essentially the same mechanics as
the standard mode of operation; the electrical specifications
and timing are most affected. The PMBus slave is capable of
communicating with a master device operating in standard
mode (100 kHz) or fast mode.
Conditions where the PMBus slave device stretches the SCL line
low include the following:
•
•
•
The master device is transmitting at a higher baud rate
than the slave device.
The receive buffer of the slave device is full and must be
read before continuing. This prevents a data overflow
condition.
The slave device is not ready to send data that the master
has requested.
Note that the slave device can stretch the SCL line only during
the low period. Also, whereas the I2C specification allows
indefinite stretching of the SCL line, the PMBus specification
limits the maximum time that the SCL line can be stretched,
or held low, to 25 ms, after which the device must release the
communication lines and reset its state machine.
GENERAL CALL SUPPORT
The PMBus slave is capable of decoding and acknowledging
a general call address. The PMBus device responds to both its
own address and the general call address (0x00). The general
call address enables all devices on the PMBus to be written to
simultaneously.
FAULT CONDITIONS
The PMBus protocol provides a comprehensive set of fault
conditions that must be monitored and reported. These fault
conditions can be grouped into two major categories: communication faults and monitoring faults.
Communication faults are error conditions associated with the
data transfer mechanism of the PMBus protocol. Monitoring
faults are error conditions associated with the operation of the
PMBus device, such as output overvoltage protection, and are
specific to each PMBus device. These fault conditions are
described in the Power Supply System and Fault Monitoring
section.
TIMEOUT CONDITION
A timeout condition occurs if any single SCL clock pulse is held
low for longer than the tTIMEOUT of 25 ms (min). Upon detecting
the timeout condition, the PMBus slave device has 10 ms to abort
the transfer, release the bus lines, and be ready to accept a new
start condition. The device initiating the timeout is required to
hold the SCL clock line low for at least tTIMEOUT MAX = 35 ms,
guaranteeing that the slave device is given enough time to reset
its communication protocol.
Note that all PMBus commands must start with the slave
address with the R/W bit cleared (set to 0), followed by the
command code. This is also true when using the general call
address to communicate with the PMBus slave device.
Rev. 0 | Page 36 of 84
Data Sheet
ADP1047/ADP1048
DATA TRANSMISSION FAULTS
DATA CONTENT FAULTS
Data transmission faults occur when two communicating devices
violate the PMBus communication protocol, as specified in the
PMBus specification. See the PMBus specification for more
information about each fault condition.
Data content faults occur when data transmission is successful,
but the PMBus slave device cannot process the data that is
received from the master device.
Corrupted Data, PEC (Item 10.8.1)
All PMBus commands start with a slave address with the R/W
bit cleared (set to 0), followed by the command code. If a host
starts a PMBus transaction with R/W set in the address phase
(equivalent to an I2C read), the PMBus slave considers this a
data content fault and responds as follows:
Parity error checking. Not supported.
Sending Too Few Bits (Item 10.8.2)
Transmission is interrupted by a start or stop condition before
a complete byte (eight bits) has been sent. Not supported; any
transmitted data is ignored.
Reading Too Few Bits (Item 10.8.3)
Transmission is interrupted by a start or stop condition before
a complete byte (eight bits) has been read. Not supported; any
received data is ignored.
Improperly Set Read Bit in the Address Byte (Item 10.9.1)
•
•
•
•
ACKs the address byte
NACKs the command and data bytes
Sends all 1s (0xFF) as long as the host continues to
request data
Sets the CML bit in the STATUS_BYTE register
Host Sends or Reads Too Few Bytes (Item 10.8.4)
Invalid or Unsupported Command Code (Item 10.9.2)
If a host ends a packet with a stop condition before the required
bytes are sent/received, it is assumed that the host intended to
stop the transfer. Therefore, the PMBus does not consider this
to be an error and takes no action, except to flush any remaining bytes in the transmit FIFO.
If an invalid or unsupported command code is sent to the
PMBus slave, the code is considered to be a data content fault,
and the PMBus slave responds as follows:
Host Sends Too Many Bytes (Item 10.8.5)
•
•
If a host sends more bytes than are expected for the corresponding command, the PMBus slave considers this a data
transmission fault and responds as follows:
•
•
•
NACKs all unexpected bytes as they are received
Flushes and ignores the received command and data
Sets the CML bit in the STATUS_BYTE register
•
NACKs the illegal/unsupported command byte and data
bytes
Flushes and ignores the received command and data
Sets the CML bit in the STATUS_BYTE register
Reserved Bits (Item 10.9.5)
Accesses to reserved bits are not a fault. Writes to reserved bits
are ignored, and reads from reserved bits return 0.
Write to Read-Only Commands
Host Reads Too Many Bytes (Item 10.8.6)
If a host performs a write to a read-only command, the PMBus
slave considers this a data content fault and responds as follows:
If a host reads more bytes than are expected for the corresponding command, the PMBus slave considers this a data
transmission fault and responds as follows:
•
•
•
•
•
Sends all 1s (0xFF) as long as the host continues to
request data
Sets the CML bit in the STATUS_BYTE register
Device Busy (Item 10.8.7)
The PMBus slave device is too busy to respond to a request
from the master device. Not supported.
NACKs all unexpected data bytes as they are received
Flushes and ignores the received command and data
Sets the CML bit in the STATUS_BYTE register
Note that this is the same error described in the Host Sends Too
Many Bytes (Item 10.8.5) section.
Read from Write-Only Commands
If a host performs a read from a write-only command, the
PMBus slave considers this a data content fault and responds
as follows:
•
•
Sends all 1s (0xFF) as long as the host continues to
request data
Sets the CML bit in the STATUS_BYTE register
Note that this is the same error described in the Host Reads Too
Many Bytes (Item 10.8.6) section.
Rev. 0 | Page 37 of 84
ADP1047/ADP1048
Data Sheet
EEPROM
The ADP1047/ADP1048 have a built-in EEPROM controller
that is used to communicate with the embedded 8K × 8-byte
EEPROM. The EEPROM, also called Flash®/EE, is partitioned
into two major blocks: the INFO block and the main block.
The INFO block contains 128 8-bit bytes, and the main block
contains 8K 8-bit bytes. The main block is further partitioned
into 16 pages, each page containing 512 bytes.
OVERVIEW
The EEPROM controller provides an interface between the
ADP1047/ADP1048 core logic and the built-in Flash/EE. The
user can control data access to and from the EEPROM through
this controller interface. Separate PMBus commands are available for the read, write, and erase operations to the EEPROM.
Communication is initiated by the master device sending a
command to the PMBus slave device to access data from or
send data to the EEPROM. Read, write, and erase commands
are supported. Data is transferred between devices in a byte
wide format. Using a read command, data is received from the
EEPROM and transmitted to the master device. Using a write
command, data is received from the master device and stored
in the EEPROM through the EEPROM controller.
The EEPROM allows erasing of whole pages only; therefore, to
change the data of any single byte in a page, the entire page
must first be erased (set high) for that byte to be writable.
Subsequent writes to any bytes in that page are allowed as long
as that byte has not been written to a low previously.
READ OPERATION (BYTE READ AND BLOCK READ)
Read from Page 0 and Page 1
Page 0 and Page 1 of the main block are reserved for storing the
default settings and user settings, respectively, and are meant to
prevent third-party access to this data. To read from Page 0 or
Page 1, the user must first unlock the EEPROM (see the Unlock
EEPROM section). After they are unlocked, Page 0 and Page 1
are readable using the EEPROM_DATA_xx commands, as
described in the Read from Page 2 to Page 15 section. Note that
when the EEPROM is locked, a read from Page 0 and Page 1
returns invalid data.
Read from Page 2 to Page 15
PAGE ERASE OPERATION
Data in Page 2 to Page 15 is always readable, even with the
EEPROM locked. The data in the EEPROM main block can
be read one byte at a time or in multiple bytes in series using
the EEPROM_DATA_xx commands (Command Code 0xB0
to Command Code 0xBF).
The main block consists of 16 equivalent pages of 512 bytes
each, numbered Page 0 to Page 15. Page 0 and Page 1 of the
main block are reserved for storing the default settings and user
settings, respectively. The user cannot perform a page erase
operation to Page 0 or Page 1.
Before executing this command, the user must program the
number of bytes to read using the EEPROM_NUM_RD_BYTES
command (Register 0xD2). Also, the user can program the offset
from the page boundary where the first read byte is returned
using the EEPROM_ADDR_OFFSET command (Register 0xD3).
Main Block Page Erase (Page 2 to Page 15)
In the following example, three bytes from Page 4 are read from
EEPROM, starting from the fifth byte of that page.
W
A
COMMAND
CODE
A
DATA BYTE
A
MASTER TO SLAVE
SLAVE TO MASTER
W
A
0xD2
A
0x03
A
P
0x00
A
0x05
MASTER TO SLAVE
SLAVE TO MASTER
2.
Set address offset = 5.
SLAVE
ADDRESS
S
P
SLAVE
ADDRESS
W
A
0xD3
A
A
P
MASTER TO SLAVE
SLAVE TO MASTER
Figure 43. Example Erase Command
3.
In this example, Command Code = 0xD4 and Data Byte =
0x0A.
Read three bytes from Page 4.
S
Note that it is important to wait at least 35 ms for the page
erase operation to complete before executing the next PMBus
command.
SLAVE
ADDRESS
W
BYTE COUNT =
0x03
MASTER TO SLAVE
SLAVE TO MASTER
A
A
0xB4
DATA BYTE
1
A
A
Sr
...
SLAVE
ADDRESS
DATA BYTE
3
R
A
A
P
09696-145
SLAVE
ADDRESS
S
09696-137
S
Set number of return bytes = 3.
09696-144
Page 2 to Page 15 of the main block can be individually erased
using the EEPROM_PAGE_ERASE command (Register 0xD4).
For example, to perform a page erase of Page 10, execute the
following command:
1.
09696-143
To erase any page from Page 2 to Page 15 of the main block, the
EEPROM must first be unlocked for access. For instructions on
how to unlock the EEPROM, see the Unlock EEPROM section.
Note that the block read command can read a maximum of 256
bytes for any single transaction.
Rev. 0 | Page 38 of 84
Data Sheet
ADP1047/ADP1048
On power-up, Page 0 and Page 1 are also protected from read
access, and the EEPROM must first be unlocked to read these
pages.
WRITE OPERATION (BYTE WRITE AND BLOCK
WRITE)
Before performing a write to Page 2 through Page 15 of the
main block, the user must first unlock the EEPROM (see the
Unlock EEPROM section).
Unlock EEPROM
To unlock the EEPROM, perform two consecutive writes with
the correct password (default = 0xFF) using the EEPROM_
PASSWORD command (Register 0xD5). The EEPROM_
UNLOCKED flag (Bit 6 of Register 0xFE81) is set to indicate
that the EEPROM is unlocked for write access.
Write to Page 0 and Page 1
Page 0 and Page 1 of the main block are reserved for storing the
default settings and user settings, respectively. The user cannot
perform a direct write operation to Page 0 or Page 1 using the
EEPROM_DATA_xx commands. If the user writes to Page 0,
Page 1 returns a no acknowledge. To program the register contents of Page 1 of the main block, it is recommended that the
STORE_USER_ALL command be used (Command Code 0x15).
See the Save Register Settings to the User Scratch Pad section.
Lock EEPROM
To lock the EEPROM, write any byte other than the correct
password using the EEPROM_PASSWORD command
(Register 0xD5). The EEPROM unlock flag is cleared to
indicate that the EEPROM is locked from write access.
Write to Page 2 Through Page 15
Change EEPROM Password
The data in the EEPROM main block can be programmed
(written to) one byte at a time or in multiple bytes in series using
the EEPROM_DATA_xx commands (Command Code 0xB0 to
Command Code 0xBF). Before executing this command, the
user can program the offset from the page boundary where
the first byte is written using the EEPROM_ADDR_OFFSET
command (Register 0xD3).
To change the EEPROM password, the EEPROM must first be
unlocked. To change the EEPROM password, first write the
correct password using the EEPROM_PASSWORD command
(Register 0xD5). Immediately write the new password using the
EEPROM_PASSWORD command. The password is now
changed to the new password.
DOWNLOADING EEPROM SETTINGS TO INTERNAL
REGISTERS
If the targeted page has not yet been erased, the user can erase
the page as described in the Main Block Page Erase (Page 2 to
Page 15) section.
Download User Settings to Registers
The user settings are stored in Page 1 of the EEPROM main
block. These settings are downloaded from the EEPROM into
the registers under the following conditions:
In the following example, four bytes are written to Page 9,
starting from the 256th byte of that page.
S
Set address offset = 256.
SLAVE
ADDRESS
W
A
•
A
0xD3
A
0x01
A
0x00
P
09696-146
1.
MASTER TO SLAVE
SLAVE TO MASTER
S
Write four bytes to Page 9.
SLAVE
ADDRESS
W
A
DATA BYTE 1
0xB9
A
...
A
DATA BYTE 4
BYTE COUNT =
4
A
A
Download Factory Settings to Registers
P
09696-147
2.
•
On power-up. The user settings are automatically downloaded into the internal registers, powering the part up in
a state previously saved by the user.
On execution of the RESTORE_USER_ALL command
(Command Code 0x16). This command allows the user
to force a download of the user settings from the EEPROM
main block, Page 1, into the internal registers.
MASTER TO SLAVE
SLAVE TO MASTER
Note that the block write command can write a maximum of
256 bytes for any single transaction.
The factory default settings are stored in Page 0 of the EEPROM
main block. The factory settings can be downloaded from the
EEPROM into the internal registers using the RESTORE_
DEFAULT_ALL command (Command Code 0x12).
When this command is executed, the EEPROM password is also
reset to the factory default setting of 0xFF.
EEPROM PASSWORD
On power-up, the EEPROM is locked and protected from
accidental writes or erases. Only reads from Page 2 to Page 15
are allowed when the EEPROM is locked. Before any data can
be written (programmed) to the EEPROM, the EEPROM must
be unlocked for write access. After it is unlocked, the EEPROM
is opened for reading, writing, and erasing.
Rev. 0 | Page 39 of 84
ADP1047/ADP1048
Data Sheet
SAVING REGISTER SETTINGS INTO EEPROM
EEPROM CRC CHECKSUM
The register settings cannot be saved to the factory scratch pad
located in Page 0 of the EEPROM main block. This is to prevent
the user from accidentally overriding the factory trim settings
and default register settings.
As a simple method of checking that the values downloaded
from EEPROM and the internal registers are consistent, a CRC
checksum is implemented.
•
Save Register Settings to the User Scratch Pad
The register settings can be saved to the user scratch pad located in
Page 1 of the EEPROM main block using the STORE_USER_ALL
command (Command Code 0x15). Before this command can be
executed, the EEPROM must first be unlocked for writing (see
the Unlock EEPROM section).
After the register settings are saved to the user scratch pad,
any subsequent power cycle automatically downloads the latest
stored user information from the EEPROM into the internal
registers.
Note that execution of the STORE_USER_ALL command
automatically performs a page erase to Page 1 of the EEPROM
main block, after which the registers are stored in EEPROM.
Therefore, it is important to wait at least 35 ms for the operation
to complete before executing the next PMBus command.
•
When the data from the internal registers is saved to the
EEPROM (Page 1 of the main block), the total number
of 1s from all the registers is counted and written into the
EEPROM as the last byte of information. This is called
the CRC checksum.
When the data is downloaded from the EEPROM into the
internal registers, a similar counter that sums all 1s from
the values loaded into the registers is saved. This value is
compared with the CRC checksum from the previous
upload operation.
If the values match, the download operation was successful. If
the values differ, the EEPROM download operation failed, and
the EEPROM_CRC fault flag is set (Register 0xFE81, Bit 5).
To read the EEPROM CRC checksum value, execute the
EEPROM_CRC_CHKSUM command (Register 0xD1). This
command returns the CRC checksum accumulated in the
counter during the download operation.
Note that the CRC checksum is an 8-bit cyclical accumulator
that wraps around to 0 when 255 is reached.
Rev. 0 | Page 40 of 84
Data Sheet
ADP1047/ADP1048
SOFTWARE GUI
For more information about the GUI, contact Analog Devices
for the latest software and a user guide.
09696-044
A free software GUI is available for programming and configuring the ADP1047/ADP1048. The GUI is designed to be
intuitive and dramatically reduces power supply design and
development time.
The software includes filter design and power supply PWM
topology windows. The GUI is also an information center,
displaying the status of all readings, monitoring, and flags on
the ADP1047/ADP1048.
Figure 44. ADP1047/ADP1048 GUI Main Window
Rev. 0 | Page 41 of 84
ADP1047/ADP1048
Data Sheet
STANDARD PMBus COMMANDS SUPPORTED BY THE ADP1047/ADP1048
Table 15 lists the standard PMBus commands that are implemented on the ADP1047/ADP1048. Many of these commands are
implemented in registers, which share the same hexadecimal value as the PMBus command code.
Table 15. Standard PMBus Commands
Command Code
0x01
0x02
0x03
0x10
0x12
0x15
0x16
0x19
0x20
0x21
0x29
0x2A
0x35
0x36
0x40
0x41
0x42
0x43
0x44
0x45
0x50
0x55
0x56
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x6B
0x78
0x79
0x7A
Command Name
OPERATION
ON_OFF_CONFIG
CLEAR_FAULTS
WRITE_PROTECT
RESTORE_DEFAULT_ALL
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
VOUT_MODE
VOUT_COMMAND
VOUT_SCALE_LOOP
VOUT_SCALE_MONITOR
VIN_ON
VIN_OFF
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
OT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
IIN_OC_FAULT_LIMIT
IIN_OC_FAULT_RESPONSE
IIN_OC_WARN_LIMIT
PIN_OP_WARN_LIMIT
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
Command Code
0x7C
0x7D
0x88
0x89
0x8B
0x97
0x98
0x99
0x9A
0x9B
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xF1
Rev. 0 | Page 42 of 84
Command Name
STATUS_INPUT
STATUS_TEMPERATURE
READ_VIN
READ_IIN
READ_VOUT
READ_PIN
PMBUS_REVISION
MFR_ID
MFR_MODEL
MFR_REVISION
EEPROM_DATA_00
EEPROM_DATA_01
EEPROM_DATA_02
EEPROM_DATA_03
EEPROM_DATA_04
EEPROM_DATA_05
EEPROM_DATA_06
EEPROM_DATA_07
EEPROM_DATA_08
EEPROM_DATA_09
EEPROM_DATA_10
EEPROM_DATA_11
EEPROM_DATA_12
EEPROM_DATA_13
EEPROM_DATA_14
EEPROM_DATA_15
EEPROM_CRC_CHKSUM
EEPROM_NUM_RD_BYTES
EEPROM_ADDR_OFFSET
EEPROM_PAGE_ERASE
EEPROM_PASSWORD
TRIM_PASSWORD
EEPROM_INFO
Data Sheet
ADP1047/ADP1048
MANUFACTURER-SPECIFIC PMBus COMMANDS
Table 16 lists the manufacturer-specific PMBus commands that are implemented on the ADP1047/ADP1048. These commands are
implemented in registers, which share the same hexadecimal value as the PMBus command code.
Table 16. Manufacturer-Specific Commands
Command Code
0xFE00
0xFE01
0xFE02
0xFE03
0xFE04
0xFE05
0xFE06
0xFE07
0xFE08
0xFE09
0xFE0A
0xFE0B
0xFE0C
0xFE0D
0xFE0E
0xFE0F
0xFE10
0xFE11
0xFE12
0xFE13
0xFE14
0xFE15
0xFE16
0xFE17
0xFE18
0xFE19
0xFE1A
0xFE1B
0xFE1C
0xFE1D
0xFE1E
0xFE20
0xFE21
0xFE22
0xFE23
0xFE24
0xFE25
0xFE26
0xFE27
0xFE28
0xFE29
0xFE2A
0xFE2B
0xFE2C
0xFE2D
0xFE2E
Command Name
CS_FAST_OCP_RESPONSE
OVP_FAST_OVP_RESPONSE
OLP_RESPONSE
VDD3P3_RESPONSE
VCORE_RESPONSE
PGOOD_AC_OK_DEBOUNCE_SET
PSON_SET
FLAG_FAULT_ID
SOFTSTART_FLAGS_BLANK1
SOFTSTART_FLAGS_BLANK2
PGOOD_FLAGS_LIST
AC_OK_FLAGS_LIST
PWM rising edge timing (PWM pin)
PWM rising edge setting (PWM pin)
PWM falling edge timing (PWM pin)
PWM falling edge setting (PWM pin)
PWM2 rising edge timing (PWM2 pin)
PWM2 rising edge setting (PWM2 pin)
PWM2 falling edge timing (PWM2 pin)
PWM2 falling edge setting (PWM2 pin)
PWM_SET
PWM_LIMIT
RTD ADC offset trim setting (MSB)
RTD ADC offset trim setting (LSB)
RTD ADC gain trim setting
OT_FAULT_LIMIT
OT_WARN_LIMIT
Switching frequency setting
Low power switching frequency setting
Frequency dithering set
Frequency synchronization set
Voltage loop filter gain
Voltage loop filter zero
Fast voltage loop filter gain
Fast voltage loop filter zero
Fast voltage loop enable
VAC_THRESHOLD_SET
VAC_THRESHOLD_READ
MIN_AC_PERIOD_SET
MAX_AC_PERIOD_SET
Current loop filter gain for low line input
Current loop filter zero for low line input
Current loop filter gain for high line input
Current loop filter zero for high line input
Soft start set
Inrush set
Command Code
0xFE2F
0xFE30
0xFE31
0xFE32
0xFE33
0xFE34
0xFE35
0xFE36
0xFE37
0xFE38
0xFE39
0xFE3A
0xFE3B
0xFE3C
0xFE3D
0xFE3E
0xFE3F
0xFE40
0xFE41
0xFE42
0xFE43
0xFE44
0xFE45
0xFE46
0xFE47
0xFE48
0xFE49
0xFE4A
0xFE4B
0xFE4C
0xFE4D
0xFE4E
0xFE4F
0xFE50
0xFE51
0xFE53
0xFE54
0xFE7E
0xFE7F
0xFE80
0xFE81
0xFE82
0xFE84
0xFE85
0xFE86
0xFE8E
Rev. 0 | Page 43 of 84
Command Name
FAST_OVP_FAULT_RISE
FAST_OVP_FAULT_FALL
Fast OVP debounce time setting
Low power mode operation threshold
Power metering offset trim for low line input
Power metering gain trim for low line input
High line limit
Low line limit
ILIM_TRIM
Voltage loop output
Exponent
Read update rate
VIN scale monitor
IIN_GSENSE
CS fast OCP blank
CS fast OCP setting
Temperature hysteresis
VAC ADC gain trim
VFB ADC gain trim
CS ADC gain trim for 500 mV range
IBAL gain (ADP1048 only)
Smart VOUT low power threshold (P1)
Smart VOUT high power threshold (P2)
Smart VOUT low line (VOL1)
Smart VOUT low line (VOL2)
Smart VOUT high line (VOH1)
Smart VOUT high line (VOH2)
Smart VOUT upper limit (VOH)
Smart VOUT super high line
SYNC delay
SMART_VOUT_SUPER_HIGH_LINE_HYS
POWER_HYS
Advanced feature enable
VOUT_OV_FAULT_HYS
VIN_UV_FAULT_HYS
VAC ADC offset trim
CS ADC offset trim for 500 mV range
CS ADC gain trim for high (750 mV) range
CS ADC offset trim for high (750 mV) range
Latched Flag 0
Latched Flag 1
Latched Flag 2
PWM value
VAC_LINE_PERIOD
Read temperature ADC
Power metering offset trim for high line input
ADP1047/ADP1048
Command Code
0xFE8F
0xFE90
0xFE91
0xFE92
0xFE93
Data Sheet
Command Name
Power metering gain trim for high line input
Current loop filter gain for low line input and
light load
Current loop filter zero for low line input and
light load
Current loop filter gain for high line input
and light load
Current loop filter zero for high line input
and light load
Command Code
0xFE94
0xFE95
0xFE96
0xFE97
0xFE98
0xFE99
0xFE9A
0xFE9B
Rev. 0 | Page 44 of 84
Command Name
Smart VOUT power reading
IBAL configuration (ADP1048 only)
Debug Flag 0
Debug Flag 1
Debug Flag 2
Debug Flag 3
Debug Flag 4
Debug Flag 5
Data Sheet
ADP1047/ADP1048
DETAILED REGISTER DESCRIPTIONS
OPERATION REGISTER
Table 17. Register 0x01—OPERATION
Bits
7
Bit Name
Enable
R/W
R/W
6
[5:4]
[3:2]
RSVD
Margin control
Margin fault
response
RSVD
R
R
R
[1:0]
R
Description
This bit determines the device response to the OPERATION command.
0 = immediate off (no sequencing).
1 = device on.
Always reads as 0.
These bits set the output voltage margin level and are hardcoded to a value of 00.
These bits set the device response to an output OVP/UVP warning or fault after the output is
margined. These bits are hardcoded to a value of 01.
Reserved.
ON_OFF_CONFIG REGISTER
Table 18. Register 0x02—ON_OFF_CONFIG
Bits
[7:5]
4
Bit Name
RSVD
Power-up control
R/W
R
R/W
3
Command
enable
R/W
2
Pin enable
R/W
1
Control pin
polarity
R/W
0
Power-down
delay
R
Description
Reserved.
Set the device power-up response.
0 = device powers up when power is present.
1 = device powers up only when commanded by the control pin (PSON) and the OPERATION
command.
Control how the device responds to the OPERATION command.
0 = ignore the OPERATION command.
1 = the OPERATION command must be set to 1 to enable the device (in addition to setting Bit 2).
Control how the device responds to the value of the control pin (PSON).
0 = ignore the control pin (PSON).
1 = the control pin must be asserted to enable the device (in addition to setting Bit 3).
Set the polarity of the control pin (PSON).
0 = active low.
1 = active high.
Actions to take on power-down. This bit always reads as 1 (turn off the output and stop energy
transfer to the output as fast as possible).
CLEAR_FAULTS COMMAND
Code 0x03, send byte, no data. This command clears all fault bits in all registers simultaneously.
WRITE_PROTECT REGISTER
Table 19. Register 0x10—WRITE_PROTECT
Bits
7
6
Bit Name
Write Protect 1
Write Protect 2
R/W
R/W
R/W
5
Write Protect 3
R/W
[4:0]
RSVD
R
Description
Setting this bit disables writes to all commands except for WRITE_PROTECT.
Setting this bit disables writes to all commands except for WRITE_PROTECT, OPERATION, and
EEPROM_PAGE_ERASE.
Setting this bit disables writes to all commands except for WRITE_PROTECT, OPERATION,
EEPROM_PAGE_ERASE, ON_OFF_CONFIG, and VOUT_COMMAND.
Reserved.
RESTORE_DEFAULT_ALL COMMAND
Code 0x12, send byte, no data. This command downloads the factory default parameters from EEPROM into operating memory.
STORE_USER_ALL COMMAND
Code 0x15, send byte, no data. This command copies the entire contents of operating memory into EEPROM (Page 1 of the main block).
Rev. 0 | Page 45 of 84
ADP1047/ADP1048
Data Sheet
RESTORE_USER_ALL COMMAND
Code 0x16, send byte, no data. This command downloads the stored user settings from EEPROM into operating memory.
CAPABILITY REGISTER
This register allows host systems to determine the capabilities of the PMBus device.
Table 20. Register 0x19—CAPABILITY
Bits
7
[6:5]
4
[3:0]
Bit Name
Packet error
checking
Maximum bus
speed
SMBALERT#
RSVD
R/W
R
Description
Always reads as 0. Packet error checking (PEC) is not supported.
R
Return the device PMBus speed capability. These bits are hardcoded to a value of 01 (use the
400 kHz maximum bus speed).
Always reads as 0. SMBALERT# pin and SMBus alert response protocol not supported.
Reserved.
R
R
VOUT_MODE REGISTER
This register sets and reads the format (linear, VID, direct) and exponents for VOUT related commands.
Table 21. Register 0x20—VOUT_MODE
Bits
[7:5]
[4:3]
[2:0]
Bit Name
Mode
RSVD
Exponent
R/W
R
R
R/W
Description
Return the output voltage data format. This bit is hardcoded to use linear format.
Reserved.
Specify the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent is in twos
complement format.
VOUT_COMMAND REGISTER
This register sets VOUT to the configured value.
Table 22. Register 0x21—VOUT_COMMAND
Bits
[15:12]
[11:0]
Bit Name
RSVD
Mantissa
R/W
R
R/W
Description
Reserved. Always reads as 0000.
Mantissa (Y[11:0]) used in VOUT linear mode format (X = Y × 2N).
VOUT_SCALE_LOOP REGISTER
This register sets the K factor = VADC/VOUT.
Table 23. Register 0x29—VOUT_SCALE_LOOP
Bits
[15:11]
10
[9:0]
Bit Name
Exponent
RSVD
Mantissa
R/W
R/W
R
R/W
Description
Write the exponent (N) in twos complement format for K = Y × 2N.
Always reads as 0.
Mantissa (Y[9:0]) used in K linear mode format (K = Y × 2N).
Rev. 0 | Page 46 of 84
Data Sheet
ADP1047/ADP1048
VOUT_SCALE_MONITOR REGISTER
This register sets the Kr factor = VOUT/VADC.
Table 24. Register 0x2A—VOUT_SCALE_MONITOR
Bits
[15:14]
[13:11]
10
[9:0]
Bit Name
RSVD
Exponent
RSVD
Mantissa
R/W
R
R/W
R
R/W
Description
Reserved.
Write the exponent (N) in twos complement format for Kr = Y × 2N.
Always reads as 0.
Mantissa (Y[9:0]) used in Kr linear mode format (Kr = Y × 2N).
VIN_ON REGISTER
This register sets the value of the input voltage to start power conversion.
Table 25. Register 0x35—VIN_ON
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
VIN_OFF REGISTER
This register sets the value of the input voltage to stop power conversion.
Table 26. Register 0x36—VIN_OFF
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
VOUT_OV_FAULT_LIMIT REGISTER
This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage fault condition.
Table 27. Register 0x40—VOUT_OV_FAULT_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in
the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format.
Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).
VOUT_OV_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an output overvoltage fault condition.
Table 28. Register 0x41—VOUT_OV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
These bits determine the device response to an output overvoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Rev. 0 | Page 47 of 84
ADP1047/ADP1048
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Data Sheet
Description
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
VOUT_OV_WARN_LIMIT REGISTER
This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage warning condition.
Table 29. Register 0x42—VOUT_OV_WARN_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in
the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format.
Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).
VOUT_UV_WARN_LIMIT REGISTER
This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage warning condition.
Table 30. Register 0x43—VOUT_UV_WARN_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in
the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format.
Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).
VOUT_UV_FAULT_LIMIT REGISTER
This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage fault condition.
Table 31. Register 0x44—VOUT_UV_FAULT_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in
the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format.
Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).
Rev. 0 | Page 48 of 84
Data Sheet
ADP1047/ADP1048
VOUT_UV_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an output undervoltage fault condition.
Table 32. Register 0x45—VOUT_UV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
These bits determine the device response to an output undervoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
OT_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an overtemperature fault condition.
Table 33. Register 0x50—OT_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
These bits determine the device response to an overtemperature fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Rev. 0 | Page 49 of 84
ADP1047/ADP1048
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Data Sheet
Description
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
VIN_OV_FAULT_LIMIT REGISTER
This register sets the overvoltage threshold measured at the PFC input that causes an overvoltage fault condition.
Table 34. Register 0x55—VIN_OV_FAULT_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
VIN_OV_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an input overvoltage fault condition.
Table 35. Register 0x56—VIN_OV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
These bits determine the device response to an input overvoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Rev. 0 | Page 50 of 84
Data Sheet
ADP1047/ADP1048
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Description
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
VIN_UV_WARN_LIMIT REGISTER
This register sets the undervoltage threshold measured at the PFC input that causes an undervoltage warning condition.
Table 36. Register 0x58—VIN_UV_WARN_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
VIN_UV_FAULT_LIMIT REGISTER
This register sets the undervoltage threshold measured at the PFC input that causes an undervoltage fault condition.
Table 37. Register 0x59—VIN_UV_FAULT_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Rev. 0 | Page 51 of 84
ADP1047/ADP1048
Data Sheet
VIN_UV_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an input undervoltage fault condition.
Table 38. Register 0x5A—VIN_UV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
These bits determine the device response to an input undervoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
IIN_OC_FAULT_LIMIT REGISTER
This register sets the accurate overcurrent threshold measured at the PFC input that causes an overcurrent fault condition.
Table 39. Register 0x5B—IIN_OC_FAULT_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in current linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[10:6]).
Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).
Rev. 0 | Page 52 of 84
Data Sheet
ADP1047/ADP1048
IIN_OC_FAULT_RESPONSE REGISTER
This register instructs the device on actions to take due to an input overcurrent fault condition.
Table 40. Register 0x5C—IIN_OC_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
These bits determine the device response to an input overcurrent fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the time specified by Delay Time 1 (Bits[2:0]). If the fault
persists, retry the number of times specified by the retry setting (Bits[5:3]).
1
0
Shut down, disable the output, and retry the number of times specified by the
retry setting (Bits[5:3]).
1
1
Disable the output and wait for the fault to clear. After the fault is cleared,
reenable the output.
Number of retry attempts following a fault condition. If the fault persists after the programmed
number of attempts, the output is disabled and remains off until the fault is cleared. A fault
condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The
time between restart attempts is specified by Delay Time 2 (Bits[2:0]).
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Delay Time 1 is the delay before the device disables the output after a fault condition is detected.
Delay Time 2 is the time between restart attempts.
Bit 2
Bit 1
Bit 0
Delay Time 1
Delay Time 2
0
0
0
10 ms
252 ms
0
0
1
20 ms
558 ms
0
1
0
40 ms
924 ms
0
1
1
80 ms
1260 ms
1
0
0
160 ms
1596 ms
1
0
1
320 ms
1932 ms
1
1
0
640 ms
2268 ms
1
1
1
1280 ms
2604 ms
IIN_OC_WARN_LIMIT REGISTER
This register sets the accurate overcurrent threshold measured at the PFC input that causes an overcurrent warning condition.
Table 41. Register 0x5D—IIN_OC_WARN_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in current linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[10:6]).
Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).
Rev. 0 | Page 53 of 84
ADP1047/ADP1048
Data Sheet
PIN_OP_WARN_LIMIT REGISTER
This register sets the upper input power (W) threshold that causes an input overpower warning condition.
Table 42. Register 0x6B—PIN_OP_WARN_LIMIT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R/W
R/W
Description
Return the exponent (N) used in power linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[2:0]).
Mantissa high bits (Y[10:8]) used in power linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in power linear mode format (X = Y × 2N).
STATUS_BYTE REGISTER
This register returns the lower byte of the STATUS_WORD register. A value of 1 in this register indicates that a fault has occurred.
Table 43. Register 0x78—STATUS_BYTE
Bits
7
6
5
4
3
2
1
0
Bit Name
BUSY
PSON_OFF
VOUT_OV
IOUT_OC
VIN_UV
TEMPERATURE
CML
NONE_OF_THE_
ABOVE
R/W
R
R
R
R
R
R
R
R
Description
1 = device was busy and unable to respond.
1 = device is not providing power to the output.
1 = output overvoltage fault.
1 = output overcurrent fault.
1 = input undervoltage fault.
1 = temperature fault or warning.
1 = communications, memory, or logic fault.
1 = fault or warning not listed in Bits[7:1].
STATUS_WORD REGISTER
A value of 1 in this register indicates that a fault has occurred.
Table 44. Register 0x79—STATUS_WORD
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
VOUT
IOUT/POUT
INPUT
MFR
POWER_GOOD#
FANS
OTHER
UNKNOWN
BUSY
PSON_OFF
VOUT_OV
IOUT_OC
VIN_UV
TEMPERATURE
CML
NONE_OF_THE_
ABOVE
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
1 = output voltage fault or warning.
1 = output current or output power fault or warning.
1 = input voltage, input current, or input power fault or warning.
1 = manufacturer-specific fault or warning.
1 = POWER_GOOD is negated.
1 = fan or airflow fault or warning.
Always reads as 0.
1 = fault or warning not listed in Bits[15:1].
1 = device was busy and unable to respond.
1 = device is not providing power to the output.
1 = output overvoltage fault.
1 = output overcurrent fault.
1 = input undervoltage fault.
1 = temperature fault or warning.
1 = communications, memory, or logic fault.
1 = fault or warning not listed in Bits[7:1].
Rev. 0 | Page 54 of 84
Data Sheet
ADP1047/ADP1048
STATUS_VOUT REGISTER
A value of 1 in this register indicates that a fault has occurred.
Table 45. Register 0x7A—STATUS_VOUT
Bits
7
6
5
4
Bit Name
VOUT_OV_FAULT
VOUT_OV_WARN
VOUT_UV_WARN
VOUT_UV_FAULT
R/W
R
R
R
R
Description
1 = output overvoltage fault.
1 = output overvoltage warning.
1 = output undervoltage warning.
1 = output undervoltage fault.
STATUS_INPUT REGISTER
A value of 1 in this register indicates that a fault has occurred.
Table 46. Register 0x7C—STATUS_INPUT
Bits
7
5
4
3
2
1
0
Bit Name
VIN_OV_FAULT
VIN_UV_WARN
VIN_UV_FAULT
VIN_LOW
IIN_OC_FAULT
IIN_OC_WARN
PIN_OP_WARN
R/W
R
R
R
R
R
R
R
Description
1 = input overvoltage fault.
1 = input undervoltage warning.
1 = input undervoltage fault.
1 = device is off due to insufficient input voltage; that is, input voltage is below the turn-off threshold.
1 = input overcurrent fault.
1 = input overcurrent warning.
1 = input overpower warning.
STATUS_TEMPERATURE REGISTER
A value of 1 in this register indicates that a fault has occurred.
Table 47. Register 0x7D—STATUS_TEMPERATURE
Bits
7
6
[5:0]
Bit Name
OT_FAULT
OT_WARN
RSVD
R/W
R
R
R
Description
1 = overtemperature fault.
1 = overtemperature warning.
Reserved.
READ_VIN REGISTER
This register returns the input voltage (V) in VIN linear mode format (X = Y × 2N).
Table 48. Register 0x88—READ_VIN
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R
R
Description
Return the exponent (N) used in VIN linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[5:3]).
Mantissa high bits (Y[10:8]) used in VIN linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VIN linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[5:3]).
READ_IIN REGISTER
This register returns the input current (A) in current linear mode format (X = Y × 2N).
Table 49. Register 0x89—READ_IIN
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R
R
Description
Return the exponent (N) used in current linear mode format (X = Y × 2N). The exponent is set in the
exponent register (Register 0xFE39, Bits[10:6]).
Mantissa high bits (Y[10:8]) used in current linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in current linear mode format (X = Y × 2N).
Rev. 0 | Page 55 of 84
ADP1047/ADP1048
Data Sheet
READ_VOUT REGISTER
This register returns the output voltage (V) in VIN linear mode format (X = Y × 2N).
Table 50. Register 0x8B—READ_VOUT
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R
R
Description
Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in the
VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format.
Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N).
READ_PIN REGISTER
This register returns the input power (W) in power linear mode format (X = Y × 2N).
Table 51. Register 0x97—READ_PIN
Bits
[15:11]
Bit Name
Exponent
R/W
R
[10:8]
[7:0]
High bits
Low byte
R
R
Description
Return the exponent (N) used in power linear mode format (X = Y × 2N). The exponent (N) is set in the
exponent register (Register 0xFE39, Bits[2:0]).
Mantissa high bits (Y[10:8]) used in power linear mode format (X = Y × 2N).
Mantissa low byte (Y[7:0]) used in power linear mode format (X = Y × 2N).
PMBUS_REVISION REGISTER
Table 52. Register 0x98—PMBUS_REVISION
Bits
[7:0]
Bit Name
Revision
R/W
R
Description
Return the revision of PMBus that the device is compliant with.
MFR_ID REGISTER
Table 53. Register 0x99—MFR_ID
Bits
[7:0]
Bit Name
MFR_ID
R/W
R
Description
Return the manufacturer’s ID.
MFR_MODEL REGISTER
Table 54. Register 0x9A—MFR_MODEL
Bits
[7:0]
Bit Name
Model
R/W
R
Description
Return the manufacturer’s model number.
MFR_REVISION REGISTER
Table 55. Register 0x9B—MFR_REVISION
Bits
[7:0]
Bit Name
Revision
R/W
R
Description
Return the manufacturer’s revision number.
EEPROM_DATA_00 Through EEPROM_DATA_15 COMMANDS
Code 0xB0 through Code 0xBF, read/write block. The EEPROM_DATA_00 through EEPROM_DATA_15 commands are used to read
data from the EEPROM and write data to the EEPROM. EEPROM_DATA_00 reads from and writes to Page 0 of the EEPROM main
block; EEPROM_DATA_01 reads from and writes to Page 1 of the EEPROM main block, and so on.
Rev. 0 | Page 56 of 84
Data Sheet
ADP1047/ADP1048
EEPROM_CRC_CHKSUM REGISTER
Table 56. Register 0xD1—EEPROM_CRC_CHKSUM
Bits
[7:0]
Bit Name
CRC checksum
R/W
R
Description
Return the CRC checksum value from the EEPROM download operation.
EEPROM_NUM_RD_BYTES REGISTER
Table 57. Register 0xD2—EEPROM_NUM_RD_BYTES
Bits
[7:0]
Bit Name
Number of read
bytes returned
R/W
R/W
Description
These bits set the number of read bytes returned when using the EEPROM_DATA_xx commands.
EEPROM_ADDR_OFFSET REGISTER
Table 58. Register 0xD3—EEPROM_ADDR_OFFSET
Bits
[15:0]
Bit Name
Address offset
R/W
R/W
Description
These bits set the address offset of the current EEPROM page.
EEPROM_PAGE_ERASE REGISTER
Table 59. Register 0xD4—EEPROM_PAGE_ERASE
Bits
[7:0]
Bit Name
Page erase
R/W
W
Description
Perform a page erase on the selected EEPROM page. (Wait 35 ms after each page erase operation.)
EEPROM must first be unlocked. Page 0 and Page 1 erase are allowed only in manufacturing test mode.
EEPROM_PASSWORD REGISTER
Table 60. Register 0xD5—EEPROM_PASSWORD
Bits
[7:0]
Bit Name
EEPROM
password
R/W
W
Description
Write the password to this register to unlock EEPROM and/or to change the EEPROM password.
TRIM_PASSWORD REGISTER
Table 61. Register 0xD6—TRIM_PASSWORD
Bits
[7:0]
Bit Name
Trim password
R/W
W
Description
Write the password to this register to unlock the trim registers for write access. Write the trim password
twice (default 0x00) to unlock the register; write any other value to exit.
EEPROM_INFO COMMAND
Code 0xF1, block read/write. This command reads the manufacturer’s data from the EEPROM.
Rev. 0 | Page 57 of 84
ADP1047/ADP1048
Data Sheet
CS_FAST_OCP_RESPONSE REGISTER
This register instructs the device on actions to take due to a fast overcurrent protection condition.
Table 62. Register 0xFE00—CS_FAST_OCP_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:4]
N-time
R/W
[3:0]
RSVD
R
Description
These bits determine the device response to a fast overcurrent protection condition.
Bit 7
Bit 6
Response
0
0
Ignore (still terminate the PWM pulse).
0
1
Allow the number of switching cycles specified in Bits[5:4], then shut down and
soft start (use the soft start delay time specified in Register 0x5C, Bits[2:0]).
1
0
Allow the number of switching cycles specified in Bits[5:4] (terminating the PWM
pulse each time), then shut down and wait for the PSON signal to soft start.
1
1
Disable the PWM output after the number of switching cycles specified in Bits[5:4]
and wait for the flag to be cleared.
These bits determine the number of switching cycles allowed before the device disables the PWM
output after a fast overcurrent condition is detected.
Bit 5
Bit 4
Number of Switching Cycles
0
0
1
0
1
2
1
0
4
1
1
8
Reserved.
OVP_FAST_OVP_RESPONSE REGISTER
This register instructs the device on actions to take due to a fast overvoltage fault condition.
Table 63. Register 0xFE01—OVP_FAST_OVP_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:0]
RSVD
R
Description
These bits determine the device response to a fast overvoltage condition.
Bit 7
Bit 6
Response
0
0
Ignore (do nothing; PWM continues).
0
1
Shut down and soft start.
1
0
Shut down immediately and wait for the PSON signal.
1
1
Disable the PWM output until the unlatched flag is cleared.
Reserved.
OLP_RESPONSE REGISTER
This register instructs the device on actions to take due to an open-loop fault condition.
Table 64. Register 0xFE02—OLP_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:0]
RSVD
R
Description
These bits determine the device response to an open-loop fault condition.
Bit 7
Bit 6
Response
0
0
Ignore (do nothing; PWM continues).
0
1
Shut down and soft start.
1
0
Shut down immediately and wait for the PSON signal.
1
1
Disable the PWM output until the unlatched flag is cleared.
Reserved.
Rev. 0 | Page 58 of 84
Data Sheet
ADP1047/ADP1048
VDD3P3_RESPONSE REGISTER
This register instructs the device on actions to take due to a VDD overvoltage fault condition.
Table 65. Register 0xFE03—VDD3P3_RESPONSE
Bits
7
6
Bit Name
RSVD
Save first flag ID
to EEPROM
R/W
R
R/W
[5:3]
2
Retry wait time
Reload EEPROM
R/W
R/W
1
Debounce time
R/W
0
Ignore VDD OV
R/W
Description
Reserved.
1 = save the first flag ID to EEPROM when the device shuts down.
0 = do not save the first flag ID to EEPROM when the device shuts down.
These bits determine the retry wait time before the next soft start. Each LSB = 588 ms.
1 = reload the contents of EEPROM.
0 = do not reload the contents of EEPROM.
1 = 2.56 μs.
0 = 660 μs.
1 = ignore the VDD 3.3 V overvoltage fault.
0 = do not ignore the VDD 3.3 V overvoltage fault.
VCORE_RESPONSE REGISTER
This register instructs the device on actions to take due to a VCORE overvoltage fault condition.
Table 66. Register 0xFE04—VCORE_RESPONSE
Bits
7
6
Bit Name
RSVD
Save first flag ID
to EEPROM
R/W
R
R/W
[5:3]
2
Retry wait time
Reload EEPROM
R/W
R/W
1
Debounce time
R/W
0
Ignore VCORE OV
R/W
Description
Reserved.
1 = save the first flag ID to EEPROM when the device shuts down.
0 = do not save the first flag ID to EEPROM when the device shuts down.
These bits determine the retry wait time before the next soft start. Each LSB = 588 ms.
1 = reload the contents of EEPROM.
0 = do not reload the contents of EEPROM.
1 = 2.56 μs.
0 = 660 μs.
1 = ignore the VCORE overvoltage fault.
0 = do not ignore the VCORE overvoltage fault.
PGOOD_AC_OK_DEBOUNCE_SET REGISTER
This register sets the debounce times for the PGOOD and AC_OK pins.
Table 67. Register 0xFE05—PGOOD_AC_OK_DEBOUNCE_SET
Bits
[7:6]
Bit Name
Debounce time,
AC_OK pin
(low to high)
R/W
R/W
[5:4]
Debounce time,
AC_OK pin
(high to low)
R/W
Description
Debounce from low to high for the AC_OK pin.
Bit 7
Bit 6
Time
0
0
0 ms
0
1
200 ms
1
0
320 ms
1
1
600 ms
Debounce from high to low for the AC_OK pin.
Bit 5
Bit 4
Time
0
0
0 ms
0
1
200 ms
1
0
320 ms
1
1
600 ms
Rev. 0 | Page 59 of 84
ADP1047/ADP1048
Bits
[3:2]
Bit Name
Debounce time,
PGOOD pin
(low to high)
R/W
R/W
[1:0]
Debounce time,
PGOOD pin
(high to low)
R/W
Data Sheet
Description
Debounce from low to high for the PGOOD pin.
Bit 3
Bit 2
Time
0
0
0 ms
0
1
200 ms
1
0
320 ms
1
1
600 ms
Debounce from high to low for the PGOOD pin.
Bit 1
Bit 0
Time
0
0
0 ms
0
1
200 ms
1
0
320 ms
1
1
600 ms
PSON_SET REGISTER
This register sets the delay time for PSON and PSOFF.
Table 68. Register 0xFE06—PSON_SET
Bits
[7:4]
[3:2]
Bit Name
RSVD
PSON delay
R/W
R
R/W
[1:0]
PSOFF delay
R/W
Description
Reserved.
These bits specify the time from when the PSON signal is active to when soft start begins.
Delay Time
Min
Typ
Max
Bit 3
Bit 2
0
0
0 ms
0 ms
0 ms
0
1
40 ms
50 ms
82 ms
1
0
209 ms
250 ms
252 ms
1
1
964 ms
1000 ms
1007 ms
These bits specify the time from when the PSON signal is cleared to when the device is turned off.
Delay Time
Min
Typ
Max
Bit 1
Bit 0
0
0
0 ms
0 ms
0 ms
0
1
40 ms
50 ms
82 ms
1
0
209 ms
250 ms
252 ms
1
1
964 ms
1000 ms
1007 ms
FLAG_FAULT_ID REGISTER
This register records the first fault ID that caused the system to shut down.
Table 69. Register 0xFE07—FLAG_FAULT_ID
Bits
[7:4]
[3:0]
Bit Name
Previous fault
flag ID
Fault flag ID
R/W
R
R
Description
Return the flag fault ID value of the fault that occurred just before the flag that caused the shutdown
(identified in Bits[3:0]).
Return the flag fault ID value of the fault that caused the shutdown.
Bit 3
Bit 2
Bit 1
Bit 0
Fault
0
0
0
1
VOUT_OV_FAULT
0
0
1
0
VOUT_UV_FAULT
0
0
1
1
OT_FAULT
0
1
0
0
VIN_OV_FAULT
0
1
0
1
VIN_UV_FAULT
0
1
1
0
IIN_OC_FAULT
0
1
1
1
OLP_FAULT
1
0
0
0
FAST_OVP_FAULT
1
0
0
1
FAST_OCP_FAULT
1
0
1
0
VDD_33V_OV_FAULT
1
0
1
1
VCORE_25V_OV_FAULT
Rev. 0 | Page 60 of 84
Data Sheet
ADP1047/ADP1048
SOFTSTART_FLAGS_BLANK1 REGISTER
This register blanks the specified flags during soft start (1 = blank, 0 = don’t blank).
Table 70. Register 0xFE08—SOFTSTART_FLAGS_BLANK1
Bits
7
6
5
4
3
2
1
0
Bit Name
BLANK_FAST_OVP
BLANK_OLP
BLANK_IIN_OC
BLANK_VIN_OFF
BLANK_VIN_OV
BLANK_OT
BLANK_VOUT_UV
BLANK_VOUT_OV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = ignore fast OVP flag.
1 = ignore OLP flag.
1 = ignore IIN_OC_FAULT flag.
1 = ignore VIN_OFF flag.
1 = ignore VIN_OV flag.
1 = ignore OT flag.
1 = ignore VOUT_UV flag.
1 = ignore VOUT_OV flag.
SOFTSTART_FLAGS_BLANK2 REGISTER
This register blanks the specified flag during soft start (1 = blank, 0 = don’t blank).
Table 71. Register 0xFE09—SOFTSTART_FLAGS_BLANK2
Bits
0
Bit Name
BLANK_FAST_OCP
R/W
R/W
Description
1 = ignore fast OCP flag.
PGOOD_FLAGS_LIST REGISTER
This register specifies the flags that are checked to determine the PGOOD pin voltage (1 = ignore flag, 0 = check flag).
Table 72. Register 0xFE0A—PGOOD_FLAGS_LIST
Bits
7
6
5
4
3
2
1
0
Bit Name
VOUT_UV_FAULT
VOUT_OV_WARN
FAST_OVP
OLP
FAST_OCP
IIN_OC_FAULT
OT_FAULT
FAST_LOOP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = ignore VOUT_UV_FAULT flag.
1 = ignore VOUT_OV_WARN flag.
1 = ignore FAST_OVP flag.
1 = ignore OLP flag.
1 = ignore FAST_OCP flag.
1 = ignore IIN_OC_FAULT flag.
1 = ignore OT_FAULT flag.
1 = ignore FAST_LOOP flag.
AC_OK_FLAGS_LIST REGISTER
This register specifies the flags that are checked to determine the AC_OK pin voltage (1 = ignore flag, 0 = check flag).
Table 73. Register 0xFE0B—AC_OK_FLAGS_LIST
Bits
7
6
5
4
3
2
1
0
Bit Name
VIN_UV_FAULT
VIN_UV_WARN
IIN_OC_FAULT
IIN_OC_WARN
FAST_OCP
AC_LINE_PERIOD
BROWN_OUT
INRUSH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = ignore VIN_UV_FAULT flag.
1 = ignore VIN_UV_WARN flag.
1 = ignore IIN_OC_FAULT flag.
1 = ignore IIN_OC_WARN flag.
1 = ignore FAST_OCP flag.
1 = ignore AC_LINE_PERIOD flag.
1 = ignore BROWN_OUT flag.
1 = ignore INRUSH flag.
Rev. 0 | Page 61 of 84
ADP1047/ADP1048
Data Sheet
PWM AND PWM2 TIMING REGISTERS
Register 0xFE0C through Register 0xFE13 configure the rising and falling edges of the PWM outputs.
Table 74. Register 0xFE0C—PWM Rising Edge Timing (PWM Pin)
Bits
[7:0]
Bit Name
t1
R/W
R/W
Description
This register contains the eight MSBs of the 10-bit t1 time.
Table 75. Register 0xFE0D—PWM Rising Edge Setting (PWM Pin)
Bits
[7:4]
[3:2]
Bit Name
RSVD
t1
R/W
R
R/W
1
Modulate enable
R/W
0
t1 sign
R/W
Description
Reserved.
These bits contain the two LSBs of the 10-bit t1 time. This value is always used with the eight bits of
Register 0xFE0C, which contains the eight MSBs of the t1 time.
1 = PWM modulation acts on the t1 edge.
0 = no PWM modulation of the t1 edge.
1 = positive sign. Increase of PWM modulation moves t1 right.
0 = negative sign. Increase of PWM modulation moves t1 left.
Table 76. Register 0xFE0E—PWM Falling Edge Timing (PWM Pin)
Bits
[7:0]
Bit Name
t2
R/W
R/W
Description
This register contains the eight MSBs of the 10-bit t2 time.
Table 77. Register 0xFE0F—PWM Falling Edge Setting (PWM Pin)
Bits
[7:4]
[3:2]
Bit Name
RSVD
t2
R/W
R
R/W
1
Modulate enable
R/W
0
t2 sign
R/W
Description
Reserved.
These bits contain the two LSBs of the 10-bit t2 time. This value is always used with the eight bits of
Register 0xFE0E, which contains the eight MSBs of the t2 time.
1 = PWM modulation acts on the t2 edge.
0 = no PWM modulation of the t2 edge.
1 = positive sign. Increase of PWM modulation moves t2 right.
0 = negative sign. Increase of PWM modulation moves t2 left.
Table 78. Register 0xFE10—PWM2 Rising Edge Timing (PWM2 Pin)
Bits
[7:0]
Bit Name
t1
R/W
R/W
Description
This register contains the eight MSBs of the 10-bit t1 time.
Table 79. Register 0xFE11—PWM2 Rising Edge Setting (PWM2 Pin)
Bits
[7:4]
[3:2]
Bit Name
RSVD
t1
R/W
R
R/W
1
Modulate enable
R/W
0
t1 sign
R/W
Description
Reserved.
These bits contain the two LSBs of the 10-bit t1 time. This value is always used with the eight bits of
Register 0xFE10, which contains the eight MSBs of the t1 time.
1 = PWM modulation acts on the t1 edge.
0 = no PWM modulation of the t1 edge.
1 = positive sign. Increase of PWM modulation moves t1 right.
0 = negative sign. Increase of PWM modulation moves t1 left.
Table 80. Register 0xFE12—PWM2 Falling Edge Timing (PWM2 Pin)
Bits
[7:0]
Bit Name
t2
R/W
R/W
Description
This register contains the eight MSBs of the 10-bit t2 time.
Rev. 0 | Page 62 of 84
Data Sheet
ADP1047/ADP1048
Table 81. Register 0xFE13—PWM2 Falling Edge Setting (PWM2 Pin)
Bits
[7:4]
[3:2]
Bit Name
RSVD
t2
R/W
R
R/W
1
Modulate enable
R/W
0
t2 sign
R/W
Description
Reserved.
These bits contain the two LSBs of the 10-bit t2 time. This value is always used with the eight
bits of Register 0xFE12, which contains the eight MSBs of the t2 time.
1 = PWM modulation acts on the t2 edge.
0 = no PWM modulation of the t2 edge.
1 = positive sign. Increase of PWM modulation moves t2 right.
0 = negative sign. Increase of PWM modulation moves t2 left.
PWM_SET REGISTER
Table 82. Register 0xFE14—PWM_SET
Bits
[7:5]
4
Bit Name
RSVD
ADP1048 operation
R/W
R
R/W
3
PWM resolution
R/W
2
PWM enable
R/W
1
PWM2 enable
R/W
0
Go button
R/W
Description
Reserved.
Reserved for the ADP1048 only.
1 = bridgeless PFC operation.
0 = interleaved PFC operation.
1 = 5 ns.
0 = 40 ns.
1 = disable the PWM output.
0 = enable the PWM output.
1 = disable the PWM2 output.
0 = enable the PWM2 output.
The PWM settings are updated during the transition of this bit from low to high.
PWM_LIMIT REGISTER
Table 83. Register 0xFE15—PWM_LIMIT
Bits
[7:4]
[3:0]
Bit Name
Limit minimum
on time
Limit minimum
off time
R/W
R/W
R/W
Description
These bits set the minimum on time for the PWM outputs in steps of 80 ns: 0000 = 0 ns and
1111 = 1200 ns.
These bits set the minimum off time for the PWM outputs: 0000 = 40 ns, 0001 = 80 ns, 1111 =
1200 ns.
RTD ADC OFFSET TRIM SETTING (MSB) REGISTER
This register must be unlocked for write access; see Table 61.
Table 84. Register 0xFE16—RTD ADC Offset Trim Setting (MSB)
Bits
[7:2]
1
Bit Name
RSVD
Trim polarity
R/W
R/W
R/W
0
RTD ADC offset trim
R/W
Description
Reserved.
1 = negative offset trim is introduced.
0 = positive offset trim is introduced.
This bit is the MSB of the 9-bit value that sets the amount of offset trim applied to the RTD ADC
reading. The LSBs are specified in Register 0xFE17.
RTD ADC OFFSET TRIM SETTING (LSB) REGISTER
This register must be unlocked for write access; see Table 61.
Table 85. Register 0xFE17—RTD ADC Offset Trim Setting (LSB)
Bits
[7:0]
Bit Name
RTD ADC offset trim
R/W
R/W
Description
These eight bits are the LSBs of the 9-bit value that sets the amount of offset trim applied to
the RTD ADC reading. The MSB is specified in Register 0xFE16, Bit 0.
Rev. 0 | Page 63 of 84
ADP1047/ADP1048
Data Sheet
RTD ADC GAIN TRIM SETTING REGISTER
This register must be unlocked for write access; see Table 61.
Table 86. Register 0xFE18—RTD ADC Gain Trim Setting
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
RTD ADC gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value sets the amount of gain trim that is applied to the RTD sensing gain.
OT_FAULT_LIMIT REGISTER
This register sets the overtemperature fault threshold. The debounce time of the overtemperature fault flag is 100 ms.
Table 87. Register 0xFE19—OT_FAULT_LIMIT
Bits
[7:0]
Bit Name
OT fault threshold
R/W
R/W
Description
Overtemperature fault threshold. This register, adding 0 as the MSB, results in a 9-bit threshold
value. This 9-bit value is compared to the nine MSBs of the RTD ADC reading. If the RTD ADC
reading is lower than the threshold set by these bits, the overtemperature fault flag is set.
These eight bits provide 256 threshold settings from 0 mV to 800 mV (one LSB = 800 mV/256 =
3.125 mV). However, the lowest allowed value is 9.375 mV (0x03), and the highest allowed
value is 781.25 mV (0xFA).
Bit 7
Bit 6
…
Bit 3
Bit 2
Bit 1
Bit 0
OTP Threshold (mV)
0
0
…
0
0
1
1
9.375
0
0
…
0
1
0
0
12.5
0
0
…
0
1
0
1
15.875
…
…
…
…
…
…
…
…
1
1
…
1
0
0
1
778.125
1
1
…
1
0
1
0
781.25
OT_WARN_LIMIT REGISTER
This register sets the overtemperature warning threshold. The debounce time of the overtemperature warning flag is 100 ms.
Table 88. Register 0xFE1A—OT_WARN_LIMIT
Bits
[7:0]
Bit Name
OT warning threshold
R/W
R/W
Description
Overtemperature warning threshold. This register, adding 0 as the MSB, results in a 9-bit threshold
value. This 9-bit value is compared to the nine MSBs of the RTD ADC reading. If the RTD ADC
reading is lower than the threshold set by these bits, the overtemperature warning flag is set.
These eight bits provide 256 threshold settings from 0 mV to 800 mV (one LSB = 800 mV/256 =
3.125 mV). However, the lowest allowed value is 9.375 mV (0x03), and the highest allowed
value is 781.25 mV (0xFA).
Bit 7
Bit 6
…
Bit 3
Bit 2
Bit 1
Bit 0
OTP Threshold (mV)
0
0
…
0
0
1
1
9.375
0
0
…
0
1
0
0
12.5
0
0
…
0
1
0
1
15.875
…
…
…
…
…
…
…
…
1
1
…
1
0
0
1
778.125
1
1
…
1
0
1
0
781.25
Rev. 0 | Page 64 of 84
Data Sheet
ADP1047/ADP1048
SWITCHING FREQUENCY SETTING REGISTER
Table 89. Register 0xFE1B—Switching Frequency Setting
Bits
[7:6]
[5:0]
Bit Name
RSVD
Switching frequency
R/W
R
R/W
Description
Reserved.
This register sets the switching frequency of the PWM outputs.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
Rev. 0 | Page 65 of 84
Frequency (kHz)
30.05
32.55
35.51
39.06
43.40
48.83
52.06
55.80
60.10
65.10
71.02
78.13
86.81
97.66
100.81
104.17
107.76
111.61
115.74
120.19
125.00
130.21
135.87
142.05
148.81
156.25
164.47
173.61
183.82
195.31
198.41
201.61
204.92
208.33
211.86
215.52
219.30
223.21
227.27
231.48
235.85
240.38
245.10
250.00
255.10
260.42
265.96
ADP1047/ADP1048
Bits
[5:0]
Bit Name
Switching frequency
Data Sheet
R/W
R/W
Description
Bit 5
Bit 4
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 3
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Frequency (kHz)
271.74
277.78
284.09
290.70
297.62
304.88
312.50
320.51
328.95
337.84
347.22
357.14
367.65
378.79
390.63
403.23
403.23
LOW POWER SWITCHING FREQUENCY SETTING REGISTER
This register sets the PFC switching frequency when the PFC is running under low power mode and the smart switching frequency
operation is enabled.
Table 90. Register 0xFE1C—Low Power Switching Frequency Setting
Bits
[7:6]
[5:0]
Bit Name
RSVD
Switching frequency
R/W
R
R/W
Description
Reserved.
This register sets the switching frequency when the power is lower than the low power
threshold set in Register 0xFE32 and the smart switching frequency is enabled.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frequency (kHz)
0
0
0
0
0
0
30.05
0
0
0
0
0
1
32.55
0
0
0
0
1
0
35.51
0
0
0
0
1
1
39.06
0
0
0
1
0
0
43.40
0
0
0
1
0
1
48.83
0
0
0
1
1
0
52.06
0
0
0
1
1
1
55.80
0
0
1
0
0
0
60.10
0
0
1
0
0
1
65.10
0
0
1
0
1
0
71.02
0
0
1
0
1
1
78.13
0
0
1
1
0
0
86.81
0
0
1
1
0
1
97.66
0
0
1
1
1
0
100.81
0
0
1
1
1
1
104.17
0
1
0
0
0
0
107.76
0
1
0
0
0
1
111.61
0
1
0
0
1
0
115.74
0
1
0
0
1
1
120.19
0
1
0
1
0
0
125.00
0
1
0
1
0
1
130.21
0
1
0
1
1
0
135.87
0
1
0
1
1
1
142.05
Rev. 0 | Page 66 of 84
Data Sheet
Bits
[5:0]
Bit Name
Switching frequency
ADP1047/ADP1048
R/W
R/W
Description
Bit 5
Bit 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Frequency (kHz)
148.81
156.25
164.47
173.61
183.82
195.31
198.41
201.61
204.92
208.33
211.86
215.52
219.30
223.21
227.27
231.48
235.85
240.38
245.10
250.00
255.10
260.42
265.96
271.74
277.78
284.09
290.70
297.62
304.88
312.50
320.51
328.95
337.84
347.22
357.14
367.65
378.79
390.63
403.23
403.23
FREQUENCY DITHERING SET REGISTER
Table 91. Register 0xFE1D—Frequency Dithering Set
Bits
7
[6:0]
Bit Name
RSVD
Dithering period
R/W
R
R/W
Description
Reserved.
Sets the period for updating the switching frequency. Each LSB corresponds to 40 μs.
Rev. 0 | Page 67 of 84
ADP1047/ADP1048
Data Sheet
FREQUENCY SYNCHRONIZATION SET REGISTER
Table 92. Register 0xFE1E—Frequency Synchronization Set
Bits
[7:2]
[1:0]
Bit Name
RSVD
Frequency division
R/W
R/W
R/W
Description
Reserved.
Sets the frequency division between the switching frequency and the external SYNC clock
(fSW/fSYNC_EXT).
Bit 1
Bit 0
Frequency Division
0
0
1
0
1
1/2
1
0
1/3
1
1
1/4
VOLTAGE LOOP FILTER GAIN REGISTER
Table 93. Register 0xFE20—Voltage Loop Filter Gain
Bits
[7:0]
Bit Name
Voltage loop filter
gain
R/W
R/W
Description
Determines the digital filter gain of the PFC voltage loop.
VOLTAGE LOOP FILTER ZERO REGISTER
Table 94. Register 0xFE21—Voltage Loop Filter Zero
Bits
[7:0]
Bit Name
Voltage loop filter
zero
R/W
R/W
Description
Determines the position of the digital filter zero of the PFC voltage loop.
FAST VOLTAGE LOOP FILTER GAIN REGISTER
Table 95. Register 0xFE22—Fast Voltage Loop Filter Gain
Bits
[7:0]
Bit Name
Fast voltage loop
filter gain
R/W
R/W
Description
Determines the digital filter gain of the PFC fast voltage loop.
FAST VOLTAGE LOOP FILTER ZERO REGISTER
Table 96. Register 0xFE23—Fast Voltage Loop Filter Zero
Bits
[7:0]
Bit Name
Fast voltage loop
filter zero
R/W
R/W
Description
Determines the position of the digital filter zero of the PFC fast voltage loop.
FAST VOLTAGE LOOP ENABLE REGISTER
Table 97. Register 0xFE24—Fast Voltage Loop Enable
Bits
7
Bit Name
Enable fast loop
for line transient
R/W
R/W
[6:5]
Regulation band
limit
R/W
Description
Enables fast loop mode immediately after the overshoot becomes larger than the regulation band
plus 3%.
1 = enable fast loop mode.
0 = disable fast loop mode.
Sets the threshold of the regulation band limit for switching from the normal filter to the fast loop
filter.
Bit 6
Bit 5
Threshold
0
0
±1.5625%
0
1
±3.125%
1
0
±6.25%
1
1
±12.5%
Rev. 0 | Page 68 of 84
Data Sheet
ADP1047/ADP1048
Bits
[4:2]
Bit Name
Delay time
R/W
R/W
1
Enable fast loop
during soft start
R/W
0
Enable fast loop
R/W
Description
Delay time before switching from the fast loop filter back to the normal filter after the output
voltage is within the regulation band (Bits[6:5]).
Bit 4
Bit 3
Bit 2
Number of Half AC Line Cycles
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Enables the fast loop filter during soft start.
1 = fast loop filter is used during soft start.
0 = normal filter is used during soft start.
Enables the fast loop filter with a delay. The threshold is programmed in Bits[6:5].
1 = enable fast loop filter.
0 = disable fast loop filter.
VAC_THRESHOLD_SET REGISTER
This register sets the input voltage threshold for input ac line period measurement and zero-crossing detection.
Table 98. Register 0xFE25—VAC_THRESHOLD_SET
Bits
7
[6:0]
Bit Name
Enable automatic
threshold
Threshold voltage
R/W
R/W
R/W
Description
1 = enable automatic threshold.
0 = disable automatic threshold.
These bits set the threshold voltage to detect the ac line frequency and period if Bit 7 is set to 0.
VAC_THRESHOLD_READ REGISTER
Table 99. Register 0xFE26—VAC_THRESHOLD_READ
Bits
7
[6:0]
Bit Name
RSVD
VAC average
reading
R/W
R
R
Description
Reserved.
Return the reading of the threshold voltage to detect the ac line frequency and period if the
automatic threshold is enabled in Register 0xFE25, Bit 7.
MIN_AC_PERIOD_SET REGISTER
Table 100. Register 0xFE27—MIN_AC_PERIOD_SET
Bits
[7:0]
Bit Name
Minimum ac line
period
R/W
R/W
Description
These bits set the minimum ac line period of the input voltage. Each LSB corresponds to 163.84 μs
resolution.
MAX_AC_PERIOD_SET REGISTER
Table 101. Register 0xFE28—MAX_AC_PERIOD_SET
Bits
[7:0]
Bit Name
Maximum ac line
period
R/W
R/W
Description
These bits set the maximum ac line period of the input voltage. Each LSB corresponds to 163.84 μs
resolution.
Rev. 0 | Page 69 of 84
ADP1047/ADP1048
Data Sheet
CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT REGISTER
Table 102. Register 0xFE29—Current Loop Filter Gain for Low Line Input
Bits
[7:0]
Bit Name
Current loop filter
gain for low line
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the low line input
voltage.
CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT REGISTER
Table 103. Register 0xFE2A—Current Loop Filter Zero for Low Line Input
Bits
[7:0]
Bit Name
Current loop filter
zero for low line
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the low line input
voltage.
CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT REGISTER
Table 104. Register 0xFE2B—Current Loop Filter Gain for High Line Input
Bits
[7:0]
Bit Name
Current loop filter
gain for high line
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the high line
input voltage.
CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT REGISTER
Table 105. Register 0xFE2C—Current Loop Filter Zero for High Line Input
Bits
[7:0]
Bit Name
Current loop filter
zero for high line
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the high line
input voltage.
SOFT START SET REGISTER
Table 106. Register 0xFE2D—Soft Start Set
Bits
[7:6]
[5:3]
Bit Name
RSVD
Soft start delay time
R/W
R
R/W
[2:0]
Soft start time
R/W
Description
Reserved.
These bits set the delay time between the inrush signal and the beginning of the soft start.
Bit 5
Bit 4
Bit 3
Number of Full AC Line Cycles
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
These bits set the soft start time.
Bit 2
Bit 1
Bit 0
Time
0
0
0
112 ms
0
0
1
168 ms
0
1
0
224 ms
0
1
1
280 ms
1
0
0
392 ms
1
0
1
504 ms
1
1
0
616 ms
1
1
1
728 ms
Rev. 0 | Page 70 of 84
Data Sheet
ADP1047/ADP1048
INRUSH SET REGISTER
Table 107. Register 0xFE2E—Inrush Set
Bits
[7:5]
[4:3]
Bit Name
RSVD
Timer
R/W
R
R/W
[2:0]
Inrush delay time
R/W
Description
Reserved.
These bits set the timer for the VIN_LOW flag measurement.
Bit 4
Bit 3
Timer
0
0
Quarter line cycle
0
1
Half line cycle
1
0
2 ms
1
1
4 ms
These bits set the inrush signal delay time after the BROWN_OUT flag goes low.
Bit 2
Bit 1
Bit 0
Number of Full AC Line Cycles
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
FAST_OVP_FAULT_RISE REGISTER
Table 108. Register 0xFE2F—FAST_OVP_FAULT_RISE
Bits
7
[6:0]
Bit Name
RSVD
Fast OVP rise threshold
R/W
R
R/W
Description
Reserved.
These bits set the rising threshold for the analog comparator at the OVP pin input as follows:
OVP threshold = (Code × 0.492/128) + 1.
This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV.
A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold.
FAST_OVP_FAULT_FALL REGISTER
Table 109. Register 0xFE30—FAST_OVP_FAULT_FALL
Bits
7
[6:0]
Bit Name
RSVD
Fast OVP fall threshold
R/W
R
R/W
Description
Reserved.
These bits set the falling threshold for the analog comparator at the OVP pin input as follows:
OVP threshold = (Code × 0.492/128) + 1.
This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV.
A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold.
FAST OVP DEBOUNCE TIME SETTING REGISTER
Table 110. Register 0xFE31—Fast OVP Debounce Time Setting
Bits
[7:2]
[1:0]
Bit Name
RSVD
OVP debounce time
R/W
R
R/W
Description
Reserved.
These bits set the fast OVP debounce time.
Bit 1
Bit 0
Time
0
0
120 ns
0
1
240 ns
1
0
480 ns
1
1
640 ns
Rev. 0 | Page 71 of 84
ADP1047/ADP1048
Data Sheet
LOW POWER MODE OPERATION THRESHOLD REGISTER
Table 111. Register 0xFE32—Low Power Mode Operation Threshold
Bits
[7:0]
Bit Name
Low power threshold
R/W
R/W
Description
These bits set the threshold value (PTH) for low power mode detection. When the input power is
lower than this value, the PFC enters low power mode.
POWER METERING OFFSET TRIM FOR LOW LINE INPUT REGISTER
Table 112. Register 0xFE33—Power Metering Offset Trim for Low Line Input
Bits
7
Bit Name
Offset trim polarity
R/W
R/W
[6:0]
Power meter offset
trim
R/W
Description
1 = negative offset trim is introduced.
0 = positive offset trim is introduced.
This value calibrates the power meter offset at the low line input voltage. Each LSB corresponds
to 0.0625/128 of the full input power.
POWER METERING GAIN TRIM FOR LOW LINE INPUT REGISTER
Table 113. Register 0xFE34—Power Metering Gain Trim for Low Line Input
Bits
7
Bit Name
Gain trim polarity
R/W
R/W
[6:0]
Power meter gain trim
R/W
Description
1 = negative gain trim is introduced.
0 = positive gain trim is introduced.
This value calibrates the power meter gain at the low line input voltage. Each LSB corresponds
to 0.0625/128 of the input power.
HIGH LINE LIMIT REGISTER
Table 114. Register 0xFE35—High Line Limit
Bits
[7:0]
Bit Name
VAC high line
threshold
R/W
R/W
Description
When the input voltage is higher than this value, the current loop filter for high line input is used.
LOW LINE LIMIT REGISTER
Table 115. Register 0xFE36—Low Line Limit
Bits
[7:0]
Bit Name
VAC low line threshold
R/W
R/W
Description
When the input voltage is lower than this value, the current loop filter for low line input is used.
ILIM_TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 116. Register 0xFE37—ILIM_TRIM
Bits
[7:5]
4
Bit Name
RSVD
Trim current direction
R/W
R
R/W
[3:0]
ILIM trim
R/W
Description
Reserved.
1 = source trim current (ILIM + ILIM_TRIM).
0 = sink trim current (ILIM − ILIM_TRIM).
These bits set the trim current. Each LSB corresponds to ILIM/64.
VOLTAGE LOOP OUTPUT REGISTER
Table 117. Register 0xFE38—Voltage Loop Output
Bits
[7:0]
Bit Name
Voltage loop output
R/W
R
Description
Return the output of the voltage control loop.
Rev. 0 | Page 72 of 84
Data Sheet
ADP1047/ADP1048
EXPONENT REGISTER
This register reads and writes exponents (N) for PIN, VIN, and IIN.
Table 118. Register 0xFE39—Exponent
Bits
[15:11]
[10:6]
[5:3]
[2:0]
Bit Name
RSVD
Input current
exponent
Input voltage
exponent
Input power exponent
R/W
R
R/W
Description
Reserved.
Sets the exponent for the input current.
R/W
Sets the exponent for the input voltage.
R/W
Sets the exponent for the input power.
READ UPDATE RATE REGISTER
Table 119. Register 0xFE3A—Read Update Rate
Bits
[7:3]
[2:0]
Bit Name
RSVD
Averaging window
R/W
R
R/W
Description
Reserved.
These bits set the averaging window for the power current and voltage readings; rms values
from one half ac line cycle are averaged over the programmed number of half ac line cycles.
Bit 2
Bit 1
Bit 0
Number of Half AC Line Cycles
0
0
0
0
0
0
1
16
0
1
0
64
0
1
1
128
1
0
0
512
1
0
1
1024
1
1
0
4096
1
1
1
8192
VIN SCALE MONITOR REGISTER
Table 120. Register 0xFE3B—VIN Scale Monitor
Bits
[15:14]
[13:11]
10
[9:0]
Bit Name
RSVD
Exponent
RSVD
Mantissa
R/W
R
R/W
R
R/W
Description
Reserved.
Write the exponent (N) in twos complement format (KVIN = Y × 2N).
Reserved.
Mantissa (Y[9:0]) used in KVIN linear mode format (KVIN = Y × 2N).
IIN_GSENSE REGISTER
Table 121. Register 0xFE3C—IIN_GSENSE
Bits
[15:11]
10
[9:0]
Bit Name
Exponent
RSVD
Mantissa
R/W
R/W
R
R/W
Description
Write the exponent (N) in twos complement format (IIN_GSENSE = Y × 2N).
Reserved.
Mantissa (Y[9:0]) used in IIN linear mode format (IIN_GSENSE = Y × 2N).
Rev. 0 | Page 73 of 84
ADP1047/ADP1048
Data Sheet
CS FAST OCP BLANK REGISTER
Table 122. Register 0xFE3D—CS Fast OCP Blank
Bits
[7:5]
[4:3]
Bit Name
RSVD
CS OCP debounce
time
R/W
R
R/W
[2:0]
Leading edge
blanking time
R/W
Description
Reserved.
These bits set the CS OCP debounce time. This value is the minimum time that the CS signal must
be constantly above the ILIM threshold (set in Register 0xFE3E, Bits[7:5]). When the CS OCP debounce
time is exceeded, all PWM outputs are disabled for the remainder of the switching cycle.
Bit 4
Bit 3
Fast OCP Debounce Time
0
0
40 ns
0
1
80 ns
1
0
120 ns
1
1
240 ns
These bits determine the leading edge blanking time. During this time, the OCP comparator
output is ignored.
Bit 2
Bit 1
Bit 0
Leading Edge Blanking Time
0
0
0
40 ns
0
0
1
80 ns
0
1
0
120 ns
0
1
1
160 ns
1
0
0
200 ns
1
0
1
400 ns
1
1
0
600 ns
1
1
1
800 ns
CS FAST OCP SETTING REGISTER
Table 123. Register 0xFE3E—CS Fast OCP Setting
Bits
[7:5]
Bit Name
ILIM absolute value
R/W
R/W
[4:2]
1
RSVD
CS_RANGE_SELECT
R
R/W
0
SEL_RESVI_REF
R/W
Description
These bits determine the ILIM absolute value. Bit 7 = 0 is positive sensing, and Bit 7 = 1 is
negative sensing.
Bit 7
Bit 6
Bit 5
ILIM Current Value
0
0
0
20 μA
0
0
1
40 μA
0
1
0
60 μA
0
1
1
80 μA
1
0
0
60 μA
1
0
1
80 μA
1
1
0
100 μA
1
1
1
120 μA
Reserved.
CS ADC input range.
0 = 750 mV.
1 = 500 mV.
This bit sets the reference current for the CS+ and CS− common-mode level shift.
1 = select the RES VI reference current (changing RRES changes this current).
0 = select the band gap generated reference current.
TEMPERATURE HYSTERESIS REGISTER
Table 124. Register 0xFE3F—Temperature Hysteresis
Bits
[7:0]
Bit Name
Temperature
hysteresis
R/W
R/W
Description
These bits set the temperature (RTD) measurement hysteresis. The OT_FAULT flag is reset when
the RTD ADC value is higher than the temperature fault limit plus hysteresis. The OT_WARN flag
is reset when the RTD ADC value is higher than the temperature warning limit plus hysteresis.
Rev. 0 | Page 74 of 84
Data Sheet
ADP1047/ADP1048
VAC ADC GAIN TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 125. Register 0xFE40—VAC ADC Gain Trim
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
VAC ADC gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the VAC voltage sense gain.
VFB ADC GAIN TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 126. Register 0xFE41—VFB ADC Gain Trim
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
VFB ADC gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the output voltage sense gain.
CS ADC GAIN TRIM FOR 500 mV RANGE REGISTER
This register must be unlocked for write access; see Table 61.
Table 127. Register 0xFE42—CS ADC Gain Trim for 500 mV Range
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
CS ADC gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This value calibrates the CS current sense gain.
IBAL GAIN REGISTER (ADP1048 ONLY)
Table 128. Register 0xFE43—IBAL Gain (ADP1048 Only)
Bits
7
Bit Name
IBAL enable
R/W
R/W
[6:0]
IBAL gain
R/W
Description
1 = enable current balancing.
0 = disable current balancing and reset the IBAL integrator.
The gain can be set from 0 to 127.
SMART VOUT LOW POWER THRESHOLD (P1) REGISTER
Table 129. Register 0xFE44—Smart VOUT Low Power Threshold (P1)
Bits
[15:13]
[12:0]
Bit Name
RSVD
P1
R/W
R
R/W
Description
Reserved.
These bits set the threshold value for low power mode operation when the smart output
voltage function is enabled. When the input power is lower than this value, the output voltage
is VOL1 for low line input and VOH1 for high line input.
SMART VOUT HIGH POWER THRESHOLD (P2) REGISTER
Table 130. Register 0xFE45—Smart VOUT High Power Threshold (P2)
Bits
[15:13]
[12:0]
Bit Name
RSVD
P2
R/W
R
R/W
Description
Reserved.
These bits set the threshold value for high power mode operation when the smart output
voltage function is enabled. When the input power is higher than this value, the output
voltage is VOL2 for low line input and VOH2 for high line input.
Rev. 0 | Page 75 of 84
ADP1047/ADP1048
Data Sheet
SMART VOUT LOW LINE (VOL1) REGISTER
Table 131. Register 0xFE46—Smart VOUT Low Line (VOL1)
Bits
[15:11]
[10:0]
Bit Name
RSVD
VOL1
R/W
R
R/W
Description
Reserved.
These bits set the output voltage under low power mode operation with low line input.
SMART VOUT LOW LINE (VOL2) REGISTER
Table 132. Register 0xFE47—Smart VOUT Low Line (VOL2)
Bits
[15:11]
[10:0]
Bit Name
RSVD
VOL2
R/W
R
R/W
Description
Reserved.
These bits set the output voltage under high power mode operation with low line input.
SMART VOUT HIGH LINE (VOH1) REGISTER
Table 133. Register 0xFE48—Smart VOUT High Line (VOH1)
Bits
[15:11]
[10:0]
Bit Name
RSVD
VOH1
R/W
R
R/W
Description
Reserved.
These bits set the output voltage under low power mode operation with high line input.
SMART VOUT HIGH LINE (VOH2) REGISTER
Table 134. Register 0xFE49—Smart VOUT High Line (VOH2)
Bits
[15:11]
[10:0]
Bit Name
RSVD
VOH2
R/W
R
R/W
Description
Reserved.
These bits set the output voltage under high power mode operation with high line input.
SMART VOUT UPPER LIMIT (VOH) REGISTER
Table 135. Register 0xFE4A—Smart VOUT Upper Limit (VOH)
Bits
[15:11]
[10:0]
Bit Name
RSVD
VOH
R/W
R
R/W
Description
Reserved.
These bits set the output voltage when the VAC input voltage is higher than the value set in
Register 0xFE4B.
SMART VOUT SUPER HIGH LINE REGISTER
Table 136. Register 0xFE4B—Smart VOUT Super High Line
Bits
[15:11]
[10:0]
Bit Name
RSVD
Super high line
voltage
R/W
R
R/W
Description
Reserved.
These bits set the input voltage value as a super high line limit.
SYNC DELAY REGISTER
Table 137. Register 0xFE4C—SYNC Delay
Bits
[15:0]
Bit Name
tSYNC_DELAY
R/W
R/W
Description
These bits set the additional delay between the external synchronization reference clock signal
and the rising edge of PWM. Each LSB corresponds to 80 ns resolution.
Rev. 0 | Page 76 of 84
Data Sheet
ADP1047/ADP1048
SMART_VOUT_SUPER_HIGH_LINE_HYS REGISTER
Table 138. Register 0xFE4D—SMART_VOUT_SUPER_HIGH_LINE_HYS
Bits
[7:0]
Bit Name
Super high line
voltage hysteresis
R/W
R/W
Description
These bits set the voltage hysteresis of the super high line voltage for the smart output voltage
function. The output voltage is VOH2 if the input voltage is lower than the super high line
voltage minus the voltage hysteresis.
POWER_HYS REGISTER
Table 139. Register 0xFE4E—POWER_HYS
Bits
[7:0]
Bit Name
Power hysteresis
R/W
R/W
Description
These bits set the power hysteresis for low power mode operation. The PFC exits the low power
mode if the input power is higher than the low power threshold plus the power hysteresis.
ADVANCED FEATURE ENABLE REGISTER
Table 140. Register 0xFE4F—Advanced Feature Enable
Bits
7
6
Bit Name
RSVD
Enable current loop
feedforward
R/W
R
R/W
5
Enable light load
current loop filter
R/W
4
Enable phase
shedding
R/W
3
Enable smart
switching frequency
R/W
2
Enable smart output
voltage
R/W
1
Enable PWM
synchronization
R/W
0
Enable frequency
dithering
R/W
Description
Reserved.
1 = current loop feedforward is enabled.
0 = current loop feedforward is disabled.
1 = light load current loop filter is enabled.
0 = light load current loop filter is disabled.
1 = phase shedding is enabled.
0 = phase shedding is disabled.
This bit applies to the ADP1048 only.
1 = smart switching frequency is enabled.
0 = smart switching frequency is disabled.
1 = smart output voltage is enabled.
0 = smart output voltage is disabled.
1 = PWM frequency synchronization is enabled.
0 = PWM frequency synchronization is disabled.
1 = frequency dithering is enabled.
0 = frequency dithering is disabled.
VOUT_OV_FAULT_HYS REGISTER
Table 141. Register 0xFE50—VOUT_OV_FAULT_HYS
Bits
[7:0]
Bit Name
VOUT OV fault hysteresis
R/W
R/W
Description
This register determines the mantissa hysteresis for the VOUT_OV_FAULT_LIMIT condition. This
hysteresis applies only when the disable output option is selected as the VOUT_OV_FAULT_
RESPONSE (Register 0x41, Bits[7:6]). The PFC output is reenabled when the output voltage is
lower than VOUT_OV_FAULT_LIMIT minus this hysteresis.
VIN_UV_FAULT_HYS REGISTER
Table 142. Register 0xFE51—VIN_UV_FAULT_HYS
Bits
[7:0]
Bit Name
VIN UV fault hysteresis
R/W
R/W
Description
This register determines the mantissa hysteresis for the VIN_UV_FAULT_LIMIT condition. This
hysteresis applies only when the disable output option is selected as the VIN_UV_FAULT_
RESPONSE (Register 0x5A, Bits[7:6]). The PFC output is reenabled when the input voltage is
higher than VIN_UV_FAULT_LIMIT plus this hysteresis.
Rev. 0 | Page 77 of 84
ADP1047/ADP1048
Data Sheet
VAC ADC OFFSET TRIM REGISTER
This register must be unlocked for write access; see Table 61.
Table 143. Register 0xFE53—VAC ADC Offset Trim
Bits
[7:0]
Bit Name
VAC ADC offset trim
R/W
R/W
Description
This register calibrates the VAC ADC offset (the offset is always subtracted from the ADC output).
CS ADC OFFSET TRIM FOR 500 mV RANGE REGISTER
This register must be unlocked for write access; see Table 61.
Table 144. Register 0xFE54—CS ADC Offset Trim for 500 mV Range
Bits
[7:0]
Bit Name
CS ADC offset trim
R/W
R/W
Description
This register calibrates the CS current sense offset (the offset is always subtracted from the ADC
output).
CS ADC GAIN TRIM FOR HIGH (750 mV) RANGE REGISTER
This register must be unlocked for write access; see Table 61.
Table 145. Register 0xFE7E—CS ADC Gain Trim for High (750 mV) Range
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
CS ADC gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
This register calibrates the CS current sense gain.
CS ADC OFFSET TRIM FOR HIGH (750 mV) RANGE REGISTER
This register must be unlocked for write access; see Table 61.
Table 146. Register 0xFE7F—CS ADC Offset Trim for High (750 mV) Range
Bits
[7:0]
Bit Name
CS ADC offset trim
R/W
R/W
Description
This register calibrates the CS current sense offset (the offset is always subtracted from the ADC
output).
LATCHED FLAG REGISTERS
The bits in the latched flag registers remain set (latched) to allow users to detect an intermittent fault. Reading a latched flag register resets
the flags in that register.
Table 147. Register 0xFE80—Latched Flag 0
Bits
7
6
5
4
3
Bit Name
MAX_MODULATION
MIN_MODULATION
OLP
FAST_OVP
AC_PERIOD
R/W
R
R
R
R
R
2
1
0
BROWN_OUT
SOFT_START
INRUSH
R
R
R
Description
1 = maximum modulation limit is reached.
1 = minimum modulation limit is reached.
1 = one of the two voltage dividers is probably disconnected or malfunctioning.
1 = the threshold set for the comparator on the OVP pin has been crossed.
1 = controller is not able to detect the ac line period; the maximum value of the period is used
and this flag is set.
1 = VAC is lower than the value stored in VIN_ON (Register 0x35).
1 = system is in soft start sequence; fast loop filter is in use.
1 = INRUSH control relay is off.
Rev. 0 | Page 78 of 84
Data Sheet
ADP1047/ADP1048
Table 148. Register 0xFE81—Latched Flag 1
Bits
7
6
5
4
Bit Name
RSVD
EEPROM_UNLOCKED
EEPROM_CRC
I2C_ADDRESS
R/W
R
R
R
R
3
2
1
0
LOW_LINE
FAST_OCP
SYNC_LOCK
AC_OK
R
R
R
R
Description
Reserved.
1 = EEPROM is unlocked and its contents can be written.
1 = downloaded EEPROM contents are incorrect.
1 = the resistor on the ADD pin has a value that can cause an error in the address assignment
(the address falls too close to the threshold between two addresses).
1 = input voltage is higher than the high line threshold.
1 = the threshold set for the comparator on the ILIM pin has been crossed.
1 = external synchronization frequency is locked.
This flag is a programmable combination of other internal flags and refers to the condition of
the input voltage. A value of 1 means that the output of the AC_OK pin is low.
Table 149. Register 0xFE82—Latched Flag 2
Bits
[7:6]
5
4
3
2
1
0
Bit Name
RSVD
LOW_POWER
FAST_LOOP
VCORE_OV
VDD_3.3V_OV
VDD_3.3V_UV
RSVD
R/W
R
R
R
R
R
R
R
Description
Reserved.
1 = input power has dropped below the threshold for low power mode operation.
1 = fast loop compensation filter is in use.
1 = an overvoltage condition is present on the VCORE rail.
1 = an overvoltage condition is present on the VDD rail.
1 = an undervoltage condition is present on the VDD rail.
Reserved.
PWM VALUE REGISTER
Table 150. Register 0xFE84—PWM Value
Bits
[7:0]
Bit Name
PWM value
R/W
R
Description
Return the eight MSBs of the PWM value (10 bits).
VAC_LINE_PERIOD REGISTER
Table 151. Register 0xFE85—VAC_LINE_PERIOD
Bits
[7:0]
Bit Name
VAC line period
R/W
R
Description
Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs.
READ TEMPERATURE ADC REGISTER
Table 152. Register 0xFE86—Read Temperature ADC
Bits
[15:0]
Bit Name
RTD temperature
R/W
R
Description
Return the measured temperature in ADC 12-bit format.
POWER METERING OFFSET TRIM FOR HIGH LINE INPUT REGISTER
Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input
Bits
7
Bit Name
Offset trim polarity
R/W
R/W
[6:0]
Power meter offset
trim
R/W
Description
1 = negative offset trim is introduced.
0 = positive offset trim is introduced.
This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds
to 0.0625/128 of the full input power.
Rev. 0 | Page 79 of 84
ADP1047/ADP1048
Data Sheet
POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER
Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input
Bits
7
Bit Name
Gain trim polarity
R/W
R/W
[6:0]
Power meter gain
trim
R/W
Description
1 = negative gain trim is introduced.
0 = positive gain trim is introduced.
This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds
to 0.0625/128 of the input power.
CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
gain for low line and
light load
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
zero for low line and
light load
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
gain for high line and
light load
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
zero for high line and
light load
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
SMART VOUT POWER READING REGISTER
Table 159. Register 0xFE94—Smart VOUT Power Reading
Bits
[15:0]
Bit Name
Power reading
R/W
R
Description
Return the average power reading for smart output voltage (averaged over 16 full line cycles).
Rev. 0 | Page 80 of 84
Data Sheet
ADP1047/ADP1048
IBAL CONFIGURATION REGISTER (ADP1048 ONLY)
Table 160. Register 0xFE95—IBAL Configuration (ADP1048 Only)
Bits
7
Bit Name
IBAL disconnect
R/W
R/W
6
IBAL at load transient
R/W
[5:4]
3
RSVD
IBAL at low power
mode
R
R/W
[2:0]
RSVD
R
Description
1 = disconnect the output of the current balance block from the PWM outputs.
0 = connect the output of the current balance block to the PWM outputs.
0 = disable current balancing when the fast loop is triggered.
1 = enable current balancing when the fast loop is triggered.
It is recommended that this bit be set to 0.
Reserved.
1 = disable current balancing under low power mode if the output of the current balancing
block reaches the limit.
0 = enable current balancing under low power mode even if the output of the current
balancing block reaches the limit.
It is recommended that this bit be set to 1.
Reserved.
DEBUG FLAG REGISTERS
Table 161. Register 0xFE96—Debug Flag 0
Bits
7
6
5
4
3
2
1
Bit Name
OT_WARN
OT_FAULT
TEMPERATURE
UNKNOWN
MFR_FAULT
PSON
PGOOD
R/W
R
R
R
R
R
R
R
0
AC_OK
R
Description
1 = measured temperature is above the value of OT_WARN_LIMIT.
1 = measured temperature is above the value of OT_FAULT_LIMIT.
1 = temperature fault or warning.
1 = fault or warning not listed in Register 0x79, Bits[15:1].
1 = manufacturer-specific fault or warning (Register 0xFE80, Register 0xFE81, Register 0xFE82).
1 = PSON signal (hardware or software) is inactive.
Power good. This flag is a programmable combination of other internal flags and refers to the
condition of the output voltage. A value of 1 means that the output of the PGOOD pin is low.
This flag is a programmable combination of other internal flags and refers to the condition of
the input voltage. A value of 1 means that the output of the AC_OK pin is low.
Table 162. Register 0xFE97—Debug Flag 1
Bits
7
6
5
Bit Name
EEPROM_UNLOCKED
EEPROM_CRC
I2C_ADDRESS
R/W
R
R
R
4
3
2
1
0
FAST_LOOP
MAX_MODULATION
MIN_MODULATION
SOFT_START
SYNC_LOCK
R
R
R
R
R
Description
1 = EEPROM is unlocked and its contents can be written.
1 = downloaded EEPROM contents are incorrect.
1 = the resistor on the ADD pin has a value that can cause an error in the address assignment
(the address falls too close to the threshold between two addresses).
1 = fast loop compensation filter is in use.
1 = maximum modulation limit is reached.
1 = minimum modulation limit is reached.
1 = system is in soft start sequence; fast loop filter is in use.
1 = external synchronization frequency is locked.
Table 163. Register 0xFE98—Debug Flag 2
Bits
7
6
5
4
3
2
1
0
Bit Name
VIN_UV
VIN_LOW
VIN_UV_FAULT
VIN_UV_WARN
LOW_LINE
BROWN_OUT
CML
VDD_3.3V_OV
R/W
R
R
R
R
R
R
R
R
Description
1 = general input undervoltage fault (same as Register 0x7C, Bit 4).
1 = VAC is lower than VIN_OFF (Register 0x36). This signal shuts down the power supply.
1 = input voltage on VAC is smaller than the value in VIN_UV_FAULT_LIMIT (Register 0x59).
1 = input voltage on VAC is smaller than the value in VIN_UV_WARN_LIMIT (Register 0x58).
1 = input voltage is higher than the high line threshold.
1 = VAC is lower than the value stored in VIN_ON (Register 0x35).
1 = communications, memory, or logic fault.
1 = an overvoltage condition is present on the VDD rail.
Rev. 0 | Page 81 of 84
ADP1047/ADP1048
Data Sheet
Table 164. Register 0xFE99—Debug Flag 3
Bits
7
6
5
4
Bit Name
VIN_OV_FAULT
VCORE_OV
PIN_OP_WARN
AC_PERIOD
R/W
R
R
R
R
3
IIN_OC_WARN
R
2
IIN_OC_FAULT
R
1
0
FAST_OCP
INPUT
R
R
Description
1 = input voltage on VAC is larger than the value in VIN_OV_FAULT_LIMIT (Register 0x55).
1 = an overvoltage condition is present on the VCORE rail.
1 = input overpower warning.
1 = controller is not able to detect the ac line period; the maximum value of the period is used
and this flag is set.
1 = input current measured on the CS ADC is larger than the value in IIN_OC_WARN_LIMIT
(Register 0x5D).
1 = input current measured on the CS ADC is larger than the value in IIN_OC_FAULT_LIMIT
(Register 0x5B).
1 = the threshold set for the comparator on the ILIM pin has been crossed.
1 = input voltage, input current, or input power fault or warning.
Table 165. Register 0xFE9A—Debug Flag 4
Bits
7
6
5
4
3
2
1
Bit Name
OLP
FAST_OVP
VOUT_UV_FAULT
VOUT_UV_WARN
VOUT_OV_WARN
VOUT_OV_FAULT
VOUT_OV
R/W
R
R
R
R
R
R
R
0
VOUT
R
Description
1 = one of the two voltage dividers is probably disconnected or malfunctioning.
1 = the threshold set for the comparator on the OVP pin has been crossed.
1 = output voltage is below the VOUT_UV_FAULT_LIMIT (Register 0x44).
1 = output voltage is below the VOUT_UV_WARN_LIMIT (Register 0x43).
1 = output voltage is above the VOUT_OV_WARN_LIMIT (Register 0x42).
1 = output voltage is above the VOUT_OV_FAULT_LIMIT (Register 0x40).
General output overvoltage fault: this flag is a combination (OR) of any output overvoltage flag
(Register 0x7A, Bit 7 and Register 0xFE80, Bit 4 (FAST_OVP)).
1 = any fault on output voltage (overvoltage, undervoltage, fast OVP, or accurate OVP).
Table 166. Register 0xFE9B—Debug Flag 5
Bits
[7:3]
2
1
0
Bit Name
RSVD
LOW_POWER
VDD_3.3V_UV
INRUSH
R/W
R
R
R
R
Description
Reserved.
1 = input power has dropped below the threshold for low power mode operation.
1 = an undervoltage condition is present on the VDD rail.
1 = INRUSH control relay is off.
Rev. 0 | Page 82 of 84
Data Sheet
ADP1047/ADP1048
OUTLINE DIMENSIONS
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
13
1
12
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.025 (0.64)
BSC
SEATING
PLANE
0.012 (0.30)
0.008 (0.20)
8°
0°
0.050 (1.27)
0.016 (0.41)
COMPLIANT TO JEDEC STANDARDS MO-137-AE
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.51)
0.010 (0.25)
0.041 (1.04)
REF
01-03-2008-A
24
Figure 45. 24-Lead Shrink Small Outline Package [QSOP]
(RQ-24)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1
ADP1047ARQZ-R7
ADP1048ARQZ-R7
ADP1047-300-EVALZ
ADP1048-600-EVALZ
ADP1047DC1-EVALZ
ADP1048DC1-EVALZ
ADP-I2C-USB-Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Shrink Small Outline Package [QSOP]
24-Lead Shrink Small Outline Package [QSOP]
ADP1047 300 W Evaluation Board
ADP1048 600 W Evaluation Board
ADP1047 Daughter Card
ADP1048 Daughter Card
USB to I2C Adapter
Z = RoHS Compliant Part.
Rev. 0 | Page 83 of 84
Package Option
RQ-24
RQ-24
ADP1047/ADP1048
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09696-0-9/11(0)
Rev. 0 | Page 84 of 84