Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • • • • • • – 8051 Instruction Compatible – Six 8-bit I/O Ports (64 pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 bytes Scratch Pad RAM – 10 Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture – In Standard Mode: 40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) – In X2 Mode (6 Clocks/Machine Cycle) 20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only) 64K bytes On-chip Flash Program/Data Memory – Byte and Page (128 bytes) Erase and Write – 100k Write Cycles On-chip 1792 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024, 1792 bytes) – 768 bytes Selected at Reset for T89C51RD2 Compatibility On-chip 2048 bytes EEPROM block for Data Storage – 100k Write Cycles Dual Data Pointer 32 KHz Crystal Oscillator Variable Length MOVX for Slow RAM/Peripherals Improved X2 Mode with Independant Selection for CPU and Each Peripheral Keyboard Interrupt Interface on Port 1 SPI Interface (Master/Slave Mode) 8-bit Clock Prescaler Two Wire Interface 400K bit/s Programmable Counter Array with: – High Speed Output – Compare/Capture – Pulse Width Modulator – Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator Low EMI (inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag Power Control Modes: Idle Mode, Power-down Mode Power Supply: 2.7V to 5.5V Temperature Ranges: Industrial (-40 to +85°C) Packages: PLCC44, VQFP44 8-bit Flash Microcontroller AT89C51ID2 Description AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program and for data. The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. 4289B–8051–12/03 1 The AT89C51ID2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51ID2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI and Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The fully static design of the AT89C51ID2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The AT89C51ID2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the AT89C51ID2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. Table 1. Memory Size and I/O pins 2 AT89C51ID2 Flash (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O PLCC44/VQFP44 64K 1792 2048 34 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Block Diagram (2) (2) (1) (1) (1) Keyboard T2 T2EX PCA ECI Vss VCC TxD RxD Figure 1. Block Diagram (1) (1) XTALA1 EUART XTALA2 Flash 64Kx8 RAM 256x8 XRAM 1792 x 8 PCA Timer2 Keyboard XTALB1(1) C51 CORE XTALB2 Watch Dog E² DATA POR 2K x 8 PFD IB-bus CPU ALE/ PROG PSEN EA Timer 0 Timer 1 (2) INT Ctrl External Bus TWI SPI BOOT Regulator 2K x8 POR / PFD ROM SCL MISO MOSI SCK SS SDA P5 P4 P3 P2 P1 (3) (3) (1) (1)(1)(1) P0 INT1 (2) (2) T1 (2) (2) INT0 Port 0 Port 1Port 2 Port 3 Port4 Port 5 RESET WR Parallel I/O Ports & (2) T0 RD (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port I2 3 4289B–8051–12/03 SFR Mapping The Special Function Registers (SFRs) of the AT89C51ID2 fall into the following categories: • 4 C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) • Power and clock control registers: PCON • Hardware Watchdog Timer registers: WDTRST, WDTPRG • Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 • Keyboard Interface registers: KBE, KBF, KBLS • SPI registers: SPCON, SPSTR, SPDAT • 2-wire Interface registers: SSCON, SSCS, SSDAT, SSADR • BRG (Baud Rate Generator) registers: BRL, BDRCON • Flash register: FCON • Clock Prescaler register: CKRL • 32 kHz Sub Clock Oscillator registers: CKSEL, OSSCON • Others: AUXR, AUXR1, CKCON0, CKCON1 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low byte DPH 83h Data Pointer High byte 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL XRS1 XRS0 EXTRA M AO Table 3. System Management SFRs Mnemonic Add Name PCON 87h Power Control AUXR 8Eh Auxiliary Register 0 - - M0 AUXR1 A2h Auxiliary Register 1 - - ENBOO T - GF3 0 - DPS CKRL 97h Clock Reload Register - - - - - - - - CKSEL 85h Clock Selection Register - - - - - - - CKS OSCON 86h Oscillator Control Register - - - - - SCLKT0 OscBEn OscAEn CKCKON0 8Fh Clock Control Register 0 TWIX2 WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 CKCKON1 AFh Clock Control Register 1 - - - - - - - SPIX2 Table 4. Interrupt SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0 IEN1 B1h Interrupt Enable Control 1 - - - - - ESPI ETWI EKBD IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L IPH1 B3h Interrupt Priority Control High 1 - - - - - SPIH IE2CH KBDH IPL1 B2h Interrupt Priority Control Low 1 - - - - - SPIL IE2CL KBDL 5 4289B–8051–12/03 Table 5. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 8-bit Port 4 P5 E8h 8-bit Port 5 P5 C7h 8-bit Port 5 (byte addressable) 7 6 5 4 3 2 1 0 - - - - 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY 7 6 5 4 3 2 1 0 Table 6. Flash and EEPROM Data Memory SFR Mnemonic FCON Add Name D1h Flash Control EECON EEPROM data Control Table 7. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 TL0 8Ah Timer/Counter 0 Low Byte TH0 8Ch Timer/Counter 0 High Byte TL1 8Bh Timer/Counter 1 Low Byte TH1 8Dh Timer/Counter 1 High Byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program - - - - - WTO2 WTO1 WTO0 T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# T2MOD C9h Timer/Counter 2 Mode - - - - - - T2OE DCEN RCAP2H CBh Timer/Counter 2 Reload/Capture High byte RCAP2L CAh Timer/Counter 2 Reload/Capture Low byte TH2 CDh Timer/Counter 2 High Byte TL2 CCh Timer/Counter 2 Low Byte 6 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 8. PCA SFRs Mnemo -nic Add Name 7 6 5 4 3 2 1 0 CCON D8h PCA Timer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 ECF CL E9h PCA Timer/Counter Low byte CH F9h PCA Timer/Counter High byte CCAPM0 DAh PCA Timer/Counter Mode 0 ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 CCAPM1 DBh PCA Timer/Counter Mode 1 ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 CCAPM3 DDh PCA Timer/Counter Mode 3 ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 CCAPM4 DEh PCA Timer/Counter Mode 4 ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 CCAPM2 DCh PCA Timer/Counter Mode 2 - CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0 CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 CCAP4H FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0 CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0 CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0 CCAP2L ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0 CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0 Table 9. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI BRR TBCK RBCK SPD SRC Table 10. SPI Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPSTA C4h SPI Status SPIF WCOL SSERR MODF - - - - SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 7 4289B–8051–12/03 Table 11. Two-Wire Interface Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SSCON 93h Synchronous Serial control SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 SSCS 94h Synchronous Serial Status SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 SSDAT 95h Synchronous Serial Data SSD7 SSD6 SSD5 SSD4 SSD3 SSD2 SSD1 SSD0 SSADR 96h Synchronous Serial Address SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSGC 7 6 5 4 3 2 1 0 Table 12. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 7 6 5 4 3 2 1 0 EEE EEBUSY Table 13. EEPROM data Memory SFR Mnemonic Add Name EECON D2h EEPROM Data Control 8 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table below shows all SFRs with their address and their reset value. Table 14. SFR Mapping Bit Non Bit addressable addressable 0/8 F8h F0h E8h 2/A 3/B 4/C 5/D 6/E PI2 CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H XXXX XX11 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX P5 bit addressable CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX E7h CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 00XX X000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 D0h PSW 0000 0000 FCON (1) XXXX 0000 EECON xxxx xx00 C8h T2CON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 B8h B0h A8h A0h 98h 90h 88h 80h EFh ACC 0000 0000 CCON C0h FFh F7h 00X0 0000 D8h 7/F B 0000 0000 1111 1111 E0h 1/9 D7h RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 P4 SPCON SPSTA SPDAT 1111 1111 0001 0100 0000 0000 XXXX XXXX IPL0 SADEN X000 000 0000 0000 DFh CFh P5 byte Addressable C7h 1111 1111 BFh P3 IEN1 IPL1 IPH1 IPH0 1111 1111 XXXX X000 XXXX X000 XXXX X111 X000 0000 IEN0 SADDR CKCON1 0000 0000 0000 0000 XXXX XXX0 P2 AUXR1 WDTRST WDTPRG 1111 1111 XXXX X0X0 XXXX XXXX XXXX X000 SCON SBUF BRL BDRCON KBLS KBE KBF 0000 0000 XXXX XXXX 0000 0000 XXX0 0000 0000 0000 0000 0000 0000 0000 P1 SSCON SSCS SSDAT SSADR CKRL 0000 0000 1111 1000 1111 1111 1111 1110 1111 1111 AUXR XX00 1000 0000 0000 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B 4/C AFh A7h 9Fh 1111 1111 0000 0000 B7h CKCON0 CKSEL OSSCON PCON XXXX XXX0 XXXX X001 00X1 0000 5/D 6/E 7/F 97h 8Fh 87h Reserved 9 4289B–8051–12/03 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VCC XTALB2 P1.0/T2/XTALB1 P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 P1.4/CEX1 Pin Configurations 6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO 39 38 P0.4/AD4 P1.6/CEX3/SCK 7 8 P1.7/CEx4/MOSI 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 EA PI2.1/SDA 11 12 P3.1/TxD 13 33 ALE/PROG P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 AT89C51ID2 PLCC44 P0.5/AD5 PI2.0/SCL P2.7/A15 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC XTALB2 P1.0/T2/XTALB1 P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 P1.4/CEX1 P2.3/A11 P2.4/A12 P2.2/A10 P2.1/A9 NIC* P2.0/A8 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO 1 P1.6/CEX3/SCK P1.7/CEX4/MOSI 2 33 32 P0.4/AD4 31 P0.6/AD6 30 P0.7/AD7 29 28 EA 27 ALE/PROG PSEN P0.5/AD5 RST 3 4 P3.0/RxD 5 PI2.1/SDA 6 P3.1/TxD P3.2/INT0 7 8 P3.3/INT1 9 26 25 P3.4/T0 10 24 P2.6/A14 P3.5/T1 11 23 P2.5/A13 AT89C51ID2 VQFP44 1.4 PI2.0/SCL P2.7/A15 10 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 NIC* P2.0/A8 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 15. Pin Description Pin Number Type Mnemonic PLCC44 VQFP44 PLCC68 VQFP64 VSS 22 16 51 40 I Ground: 0V reference VCC 44 38 17 8 I Power Supply: This is the power supply voltage for normal, idle and power-down operation 43 - 36 37 - 30 P0.0 - P0.7 P1.0 - P1.7 2-9 40 - 44 1-3 15, 14, 12, 11, 9,6, 5, 3 6, 5, 3, 2, 64, 61,60,59 19, 21, 22, 23, 25, 27, 28, 29 10, 12, 13, 14, 16, 18, 19, 20 Name and Function I/O I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51ID2 Port 1 include: 2 40 19 10 I/O P1.0: Input/Output I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout I 3 4 41 42 21 22 12 13 I/O 6 7 43 44 1 23 25 27 14 16 18 P1.1: Input/Output I T2EX: Timer/Counter 2 Reload/Capture/Direction Control I SS: SPI Slave Select I/O I 5 XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier P1.2: Input/Output ECI: External Clock for the PCA I/O P1.3: Input/Output I/O CEX0: Capture/Compare External I/O for PCA module 0 I/O P1.4: Input/Output I/O CEX1: Capture/Compare External I/O for PCA module 1 I/O P1.5: Input/Output I/O CEX2: Capture/Compare External I/O for PCA module 2 I/O MISO: SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. 8 9 2 3 28 29 19 20 I/O P1.6: Input/Output I/O CEX3: Capture/Compare External I/O for PCA module 3 I/O SCK: SPI Serial Clock I/O P1.7: Input/Output: 11 4289B–8051–12/03 Table 15. Pin Description (Continued) Pin Number Type Mnemonic PLCC44 VQFP44 PLCC68 VQFP64 Name and Function I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. XTALA1 21 15 49 38 I Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTALA2 20 14 48 37 O Crystal A 2: Output from the inverting oscillator amplifier XTALB1 2 40 10 19 I XTALB2 1 39 9 18 O Crystal B 2: (Sub Clock) Output from the inverting oscillator amplifier 24 - 31 18 - 25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.7 P5.0 - P5.7 12 54, 55, 56, 58, 59, 61, 64, 65 43, 44, 45, 47, 48, 50, 53, 54 Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. 11, 13 - 19 5, 7 - 13 34, 39, 40, 41, 42, 43, 45, 47 25, 28, 29, 30, 31, 32, 34, 36 11 5 34 25 I RXD (P3.0): Serial input port 13 7 39 28 O TXD (P3.1): Serial output port 14 8 40 29 I INT0 (P3.2): External interrupt 0 15 9 41 30 I INT1 (P3.3): External interrupt 1 16 10 42 31 I T0 (P3.4): Timer 0 external input 17 11 43 32 I T1 (P3.5): Timer 1 external input 18 12 45 34 O WR (P3.6): External data memory write strobe 19 13 47 36 O RD (P3.7): External data memory read strobe - 20, 24, 26, 44, 46, 50, 53, 57 11, 15, 17,33, 35,39, 42, 46 I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 4 pins that are externally pulled low will source current because of the internal pull-ups. - 60, 62, 63, 7, 8, 10, 13, 16 49, 51, 52, 62, 63, 1, 4, 7 I/O Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 5 pins that are externally pulled low will source current because of the internal pull-ups. - - I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 15. Pin Description (Continued) Pin Number Type Mnemonic PI2.0 - PI2.1 PLCC44 VQFP44 PLCC68 VQFP64 34, 12 28, 6 1, 36 57, 26 34 28 1 57 Name and Function Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc with external resistor to prevent any parasitic current consumption). I/O SCL (PI2.0): 2-wire Serial Clock SCL output the serial clock to slave peripherals SCL input the serial clock from master SDA (PI2.1): 2-wire Serial Data 12 6 36 26 I/O SDA is the bidirectional 2-wire data line Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a poweron reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. RST 10 4 30 21 I ALE/PROG 33 27 68 56 O (I) PSEN 32 26 67 55 O Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 35 29 2 58 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If security level 1 is programmed, EA will be internally latched on Reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. 13 4289B–8051–12/03 Oscillators Overview Two oscillators are available (for AT8xC51IxD2 devices only, the others part number provide only the main high frequency oscillator): • OSCA used for high frequency: Up to 40 MHz • OSCB used for low frequency: 32.768 kHz Several operating modes are available and programmable by software: • to switch OSCA to OSCB and vice-versa • to stop OSCA or OSCB to reduce consumption In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature has been implemented between the selected oscillator and the CPU. Registers Table 16. CKSEL Register (for AT8xC51Ix2 only) CKSEL - Clock Selection Register (85h) 7 6 5 4 3 2 1 0 - - - - - - - CKS Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved CPU Oscillator Select Bit: (CKS) Cleared, CPU and peripherals connected to OSCB 0 CKS Set, CPU and peripherals connected to OSCA Programmed by hardware after a Power-up regarding Hardware Security Byte (HSB).HSB.OSC (Default setting, OSCA selected) Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable 14 AT89C51ID2 D–8051–12/03 AT89C51ID2 Table 17. OSCCON Register (for AT8xC51Ix2 only) OSCCON- Oscillator Control Register (86h) 7 6 5 4 3 2 1 0 - - - - - SCLKT0 OscBEn OscAEn Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved Sub Clock Timer0 2 SCLKT0 Cleared by software to select T0 pin Set by software to select T0 Sub Clock Cleared by hardware after a Power Up OscB enable bit Set by software to run OscB 1 OscBEn Cleared by software to stop OscB Programmed by hardware after a Power-up regarding HSB.OSC (Default cleared, OSCB stopped) OscA enable bit Set by software to run OscA 0 OscAEn Cleared by software to stop OscA Programmed by hardware after a Power-up regarding HSB.OSC(Default Set, OSCA runs) Reset Value = XXXX X0’HSB.OSC’’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable Table 18. CKRL Register CKRL - Clock Reload Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7:0 Mnemonic Description CKRL Clock Reload Register: Prescaler value Reset Value = 1111 1111b Not bit addressable 15 D–8051–12/03 Table 19. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by software for general purpose usage. Set by software for general purpose usage. 2 GF0 General purpose Flag Cleared by software for general purpose usage. Set by software for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable 16 AT89C51ID2 D–8051–12/03 AT89C51ID2 Functional Block Diagram Figure 2. Functional Oscillator Block Diagram Reload Reset PwdOscA CKRL FOSCA XtalA1 OscA XtalA2 1 :2 0 OscAEn OSCCON 8-bit Prescaler-Divider 0 1 X2 1 CKCON0 CLK Peripheral Clock PERIPH 0 CLK CPU CKRL=0xFF? FOSCB CKS CPU clock Idle CKSEL PwdOscB XtalB1 XtalB2 :128 OscB Sub Clock OscBEn OSCCON Operating Modes Reset A hardware RESET puts the Clock generator in the following state: The selected oscillator depends on OSC bit in Hardware Security Byte (HSB). HSB.OSC = 1 (Oscillator A selected) • OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped. • CKS = 1: OscA is selected for CPU. HSB.OSC = 0 (Oscillator B selected) • OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped. • CKS = 0: OscB is selected for CPU. • CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1 and CKRL registers • CKS bit in CKSEL register selects either OscA or OscB • CKRL register determines the frequency of the OscA clock. Functional Modes Normal Modes 17 D–8051–12/03 Idle Modes Power Down Modes • It is always possible to switch dynamically by software from OscA to OscB, and vice versa by changing CKS bit. • IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL) • IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 bit: • IDLE MODE A: OscA is running (OscAEn = 1) and selected (CKS = 1) • IDLE MODE B: OscB is running (OscBEn = 1) and selected (CKS = 0) • The unused oscillator OscA or OscB can be stopped by software by clearing OscAEn or OscBEn respectively. • IDLE mode can be canceled either by Reset, or by activation of any enabled interruption • In both cases, PCON.0 bit (IDL) is cleared by hardware • Exit from IDLE modes will leave Oscillators control bits (OscEnA, OscEnB, CKS) unchanged. • POWER DOWN modes are achieved by using any instruction that writes into PCON.1 bit (PD) • POWER DOWN modes A and B depend on previous software sequence, prior to writing into PCON.1 bit: • Both OscA and OscB will be stopped. • POWER DOWN mode can be cancelled either by a hardware Reset, an external interruption, or the keyboard interrupt. • By Reset signal: The CPU will restart according to OSC bit in Hardware Security Bit (HSB) register. • By INT0 or INT1 interruption, if enabled: (standard behavioral), request on Pads must be driven low enough to ensure correct restart of the oscillator which was selected when entering in Power down. • By keyboard Interrupt if enabled: a hardware clear of the PCON.1 flag ensure the restart of the oscillator which was selected when entering in Power down. Table 20. Overview 18 PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment 0 0 0 1 1 NORMAL MODE A, OscB stopped Default mode after power-up or Warm Reset 0 0 1 1 1 NORMAL MODE A, OscB running Default mode after power-up or Warm Reset + OscB running 0 0 1 0 0 NORMAL MODE B, OscA stopped OscB running and selected 0 0 1 1 0 NORMAL MODE B, OscA running OscB running and selected + OscA running X X 0 0 X INVALID OscA & OscB cannot be stopped at the same time X X X 0 1 INVALID OscA must not be stopped, as used for CPU and peripherals X X 0 X 0 INVALID OscB must not be stopped as used for CPU and peripherals AT89C51ID2 D–8051–12/03 AT89C51ID2 Table 20. Overview (Continued) PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment 0 1 X 1 1 IDLE MODE A The CPU is off, OscA supplies the peripherals, OscB can be disabled (OscBEn = 0) 0 1 1 X 0 IDLE MODE B The CPU is off, OscB supplies the peripherals, OscA can be disabled (OscAEn = 0) 1 X X 1 X POWER DOWN MODE The CPU and peripherals are off, OscA and OscB are stopped Design Considerations Oscillators Control Prescaler Divider • PwdOscA and PwdOscB signals are generated in the Clock generator and used to control the hard blocks of oscillators A and B. • PwdOscA =’1’ stops OscA • PwdOscB =’1’ stops OscB • The following tables summarize the Operating modes: • PCON.1 OscAEn PwdOscA Comments 0 1 0 OscA running 1 X 1 OscA stopped by Power-down mode 0 0 1 OscA stopped by clearing OscAEn PCON.1 OscBEn PwdOscB Comments 0 1 0 OscB running 1 X 1 OscB stopped by Power-down mode 0 0 1 OscB stopped by clearing OscBEn A hardware RESET puts the prescaler divider in the following state: – CKRL = FFh: F CLK CPU = FCLK PERIPH = FOSCA/2 (Standard C51 feature) • CKS signal selects OSCA or OSCB: FCLK OUT = FOSCA or FOSCB • Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: – CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSCA/1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSCA/510 (X2 Mode) – CKRL = FFh: maximum frequency FCLK CPU = FCLK PERIPH = FOSCA/2 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSCA (X2 Mode) 19 D–8051–12/03 – FCLK CPU and FCLK PERIPH, for CKRL≠0xFF In X2 Mode: F OSCA 2 × ( 255 CKRL ) F CPU = F CLK PERIPH = ---------------------------------------------– F CPU = F CLK PERIPH = ---------------------------------------------– In X1 Mode: Timer 0: Clock Inputs F OSCA 4 × ( 255 CKRL ) Figure 1. Timer 0: Clock Inputs FCLK PERIPH :6 T0 pin 0 Sub Clock (AT 8xC51Ix2 only) 1 0 Timer 0 1 Control C/T TMOD SCLKT0 OSCCON Gate INT0 TR0 Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock. 20 AT89C51ID2 D–8051–12/03 AT89C51ID2 Enhanced Features In comparison to the original 80C52, the AT89C51ID2 implements some new features, which are: • X2 Feature X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware Watchdog • SPI interface • 4-level interrupt priority system • power-off flag • ONCE mode • ALE disabling • Enhanced features on the UART and the timer 2 The AT89C51ID2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Save power consumption while keeping same CPU power (oscillator power saving). • Save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes. • Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripherals is first divided by two before being used by the CPU core and the peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3 shows the clock generation block diagram. X2 bit is validated on the rising edge of the XTAL1÷2 to avoid glitches when switching from X2 to STD mode. Figure 4 shows the switching mode waveforms. Figure 3. Clock Generation Diagram CKRL 2 XTAL1 FXTAL FOSC XTAL1:2 0 1 8 bit Prescaler FCLK CPU FCLK PERIPH X2 CKCON0 21 4289B–8051–12/03 Figure 4. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit FOSC CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON0 register (see Table 21) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode). The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See Table 21.) and SPIX2 bit in the CKCON1 register (see Table 22) allows a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. 22 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 21. CKCON0 Register CKCON0 - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 Bit Mnemonic Description TWIX2 2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Watchdog Clock 6 WDX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array Clock 5 PCAX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART Clock (Mode 0 and 2) 4 SIX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 Clock 3 T2X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer1 Clock 2 T1X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 Clock 1 T0X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU Clock 0 X2 Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is cleared. Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”) Not bit addressable 23 4289B–8051–12/03 Table 22. CKCON1 Register CKCON1 - Clock Control Register (AFh) 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved 0 SPIX2 SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Reset Value = XXXX XXX0b Not bit addressable 24 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Dual Data Pointer Register DPTR The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 23) that allows the program code to switch between them (Refer to Figure 5). Figure 5. Use of Dual Pointer External Data Memory 7 0 DPS AUXR1(A2H) DPTR1 DPTR0 DPH(83H) DPL(82H) 25 4289B–8051–12/03 Table 23. AUXR1 register AUXR1- Auxiliary Register 1(0A2h) 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Bit Number Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 ENBOOT Enable Boot Flash Cleared to disable boot ROM. Set to map the boot ROM between F800h - 0FFFFh. Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - 3 GF3 2 0 Always cleared. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 DPS This bit is a general purpose user flag. * Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. Reset Value: XXXX XX0X0b Not bit addressable Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS 26 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 27 4289B–8051–12/03 Expanded RAM (XRAM) The AT89C51ID2 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51ID2 devices have expanded RAM in external data space configurable up to 1792bytes (see Table 24.). The AT89C51ID2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only. 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 24). The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. Figure 6. Internal and External Data Memory Address 0FFh to 6FFh 0FFh 0FFh Upper 128 bytes Internal Ram indirect accesses XRAM 80h 0FFFFh Special Function Register direct accesses External Data Memory 80h 7Fh Lower 128 bytes Internal Ram direct or indirect accesses 00 00 00FFh up to 06FFh 0000 When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. 28 • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 24. This can be AT89C51ID2 4289B–8051–12/03 AT89C51ID2 useful if external peripherals are mapped at addresses already used by the internal XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR. • With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals. 29 4289B–8051–12/03 Registers Table 24. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - M0 XRS2 XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse length 5 M0 Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods. 4 XRS2 XRAM Size 3 XRS1 XRS2XRS1XRS0XRAM size 0 0 0256 bytes 2 XRS0 0 0 1512 bytes 0 1 0768 bytes(default) 0 1 11024 bytes 1 0 01792 bytes EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. 0 AO ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable 30 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Reset Introduction The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 7. Reset schematic Power Monitor Hardware Watchdog Internal Reset PCA Watchdog RST Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VCC as shown in Figure 8. Resistor value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51ID2 datasheet. Figure 8. Reset Circuitry and Power-On Reset VDD To internal reset RST R RST + RST VSS a. RST input circuitry b. Power-on Reset 31 4289B–8051–12/03 Reset Output As detailed in Section “Hardware Watchdog Timer”, page 107, the WDT generates a 96clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown Figure 9. Figure 9. Recommended Reset Output Schematic VDD + RST VDD 1K AT89C51ID2 RST VSS 32 To other on-board circuitry AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By gen erating the Re se t the Power Monito r insures a correct start up whe n AT89C51ID2 is powered up. Description In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH/VIL. These parameters are controlled during the three phases: power-up, normal operation and power going down. See Figure 10. Figure 10. Power Monitor Block Diagram VCC CPU core Power On Reset Power Fail Detect Voltage Regulator Regulated Supply Memories Peripherals XTAL1 (1) Internal Reset RST pin PCA Watchdog Note: Hardware Watchdog 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect threshold level, the Reset will be applied immediately. The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator. 33 4289B–8051–12/03 The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 11 below. Figure 11. Power Fail Detect Vcc t Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. 34 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Timer 2 The Timer 2 in the AT89C51ID2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 25) and T2MOD (Table 26) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F OSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON). Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. Timer 2 includes the following enhancements: Auto-Reload Mode • Auto-reload mode with up or down counter • Programmable clock-output The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 12. In this mode the T2EX pin controls the direction of count. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution. 35 4289B–8051–12/03 Figure 12. Auto-Reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6 0 1 T2 C/T2 TR2 T2CON T2CON T2EX: (DOWN COUNTING RELOAD VALUE) if DCEN=1, 1=UP FFh FFh if DCEN=1, 0=DOWN (8-bit) (8-bit) if DCEN = 0, up counting TOGGLE T2CON EXF2 TL2 TH2 (8-bit) (8-bit) TIMER 2 INTERRUPT TF2 T2CON RCAP2L (8-bit) RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Programmable ClockOutput In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 13). The input clock increments TL2 at frequency FCLK PERIPH/2.The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2.In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F CLKPERIPH Clock –O utFrequency = --------------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L ) For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz (FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: • Set T2OE bit in T2MOD register. • Clear C/T2 bit in T2CON register. • Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2.It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. 36 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 13. Clock-Out Mode C/T2 = 0 FCLK PERIPH :6 TR2 T2CON TL2 (8-bit) TH 2 (8-bit) OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q D T2OE T2MOD T2EX EXF2 EXEN2 T2CON T2CON TIMER 2 INTERRUPT 37 4289B–8051–12/03 Registers Table 25. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1). 5 RCLK Receive Clock bit Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 EXEN2 2 TR2 1 0 Timer 2 External Enable bit Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. Timer 2 Run control bit Cleared to turn off Timer 2. Set to turn on Timer 2. C/T2# Timer/Counter 2 select bit Cleared for timer operation (input from internal clock system: FCLK PERIPH). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. CP/RL2# Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable 38 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 26. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 T2OE Timer 2 Output Enable bit Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. 0 DCEN Down Counter Enable bit Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable 39 4289B–8051–12/03 Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: • ÷6 Peripheral clock frequency (FCLK PERIPH) ÷ 2 • Timer 0 overflow • External input on ECI (P1.2) • Peripheral clock frequency (FCLK PERIPH) Each compare/capture modules can be programmed in any one of the following modes: • Rising and/or falling edge capture • Software timer • High-speed output • Pulse width modulator Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 51). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 The PCA timer is a common time base for all five modules (See Figure 14). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 27) and can be programmed to run at: 40 • 1/6 the peripheral clock frequency (FCLK PERIPH) • 1/2 the peripheral clock frequency (FCLK PERIPH) • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 14. PCA Timer/Counter To PCA modules Fclk periph /6 overflow Fclk periph / 2 CH T0 OVF It CL 16 bit up counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 CCF0 CCON 0xD8 Idle CCF4 CCF3 CCF2 CCF1 41 4289B–8051–12/03 Table 27. CMOD Register CMOD - PCA Counter Mode Register (D9h) 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 CPS1 1 0 CPS0 ECF PCA Count Pulse Select CPS1 0 CPS0Selected PCA input 0 Internal clock fCLK PERIPH/6 0 1Internal clock fCLK PERIPH/2 1 0Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4) PCA Enable Counter Overflow Interrupt Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 14 and Table 27). • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4. • The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 28). 42 • Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 28. CCON Register CCON - PCA Counter Control Register (D8h) 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description PCA Counter Overflow flag 7 CF Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit 6 CR Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. 5 - 4 CCF4 Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 3 interrupt flag 3 CCF3 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 2 interrupt flag 2 CCF2 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 1 interrupt flag 1 CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 interrupt flag 0 CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. Reset Value = 00X0 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 17). The PCA interrupt system is shown in Figure 15. 43 4289B–8051–12/03 Figure 15. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt priority decoder Module 2 Module 3 Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IEN0.6 EC IEN0.7 EA PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer • 16-bit High Speed Output • 8-bit Pulse Width Modulator In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 29). The registers contain the bits that control the mode that each module will operate in. 44 • The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. • PWM (CCAPMn.1) enables the pulse width modulation mode. • The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. • The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. • The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 29 shows the CCAPMn settings for the various PCA functions. Table 29. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number Bit Mnemonic Description 7 - 6 ECOMn Reserved The value read from this bit is indeterminate. Do not set this bit. Enable Comparator Cleared to disable the comparator function. Set to enable the comparator function. Capture Positive 5 CAPPn 4 CAPNn Cleared to disable positive edge capture. Set to enable positive edge capture. Capture Negative Cleared to disable negative edge capture. Set to enable negative edge capture. Match 3 MATn When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle 2 TOGn When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode 1 PWMn Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt 0 CCF0 Cleared to disable compare/capture flag CCFn in the CCON register to generate an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. Reset Value = X000 0000b Not bit addressable 45 4289B–8051–12/03 Table 30. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer / Compare mode. 1 0 0 1 1 0 X 16-bit High Speed Output 1 0 0 0 0 1 0 8-bit PWM 1 0 0 1 X 0 X Watchdog Timer (module 4 only) There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 31 & Table 32). Table 31. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - PCA Module n Compare/Capture Control CCAPnH Value Reset Value = 0000 0000b Not bit addressable 46 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 32. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - PCA Module n Compare/Capture Control CCAPnL Value Reset Value = 0000 0000b Not bit addressable Table 33. CH Register CH - PCA Counter Register High (0F9h) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - PCA counter CH Value Reset Value = 0000 0000b Not bit addressable Table 34. CL Register CL - PCA Counter Register Low (0E9h) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - PCA Counter CL Value Reset Value = 0000 0000b Not bit addressable 47 4289B–8051–12/03 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 16). Figure 16. PCA Capture Mode CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCO N 0xD8 PCA IT PCA Counter/Timer Cex.n CH CL CCAPnH CCAPnL Capture ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE 16-bit Software Timer/ Compare Mode 48 The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 17). AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 17. PCA Compare Mode and PCA Watchdog Timer CCON CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA I T Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16 bit comparator CH RESET * CL PCA counter/ timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA t o 0xDE CMOD 0xD9 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 18). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. 49 4289B–8051–12/03 Figure 18. PCA High Speed Output Mode CCON CF Write to CCA PnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable 16 bit comparator CH Match CL CEXn PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. Pulse Width Modulator Mode 50 All of the PCA modules can be used as PWM outputs. Figure 19 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 19. PCA PWM Mode CCAPnH Overflow CCAPnL “0” CEXn Enable 8 bit comparator “1” CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 17 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then reenable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 51 4289B–8051–12/03 Serial I/O Port The serial I/O port in the AT89C51ID2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: Framing Error Detection • Framing error detection • Automatic address recognition Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 20). Figure 20. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1SMOD0 - POF GF1 GF0 PD IDL PCON (87h) To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 38.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 21. and Figure 22.). Figure 21. UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 Stop bit RI SMOD0=X FE SMOD0=1 52 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 22. UART Timings in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, the user may enable the automatic address recognition feature in mode 1.In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: Given Address The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect). Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b 53 4289B–8051–12/03 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e. g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e. g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e. g. : SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0011b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses 54 On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Registers Table 35. SADEN Register SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 36. SADDR Register SADDR - Slave Address Register (A9h) 7 6 5 4 Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 23. Baud Rate Selection TIMER1 TIMER2 0 TIMER_BRG_RX 0 1 / 16 Rx Clock 1 RCLK RBCK INT_BRG TIMER1 TIMER2 0 1 TIMER_BRG_TX 0 1 / 16 Tx Clock TCLK INT_BRG TBCK 55 4289B–8051–12/03 Table 37. Baud Rate Selection Table UART Internal Baud Rate Generator (BRG) TCLK RCLK TBCK RBCK Clock Source Clock Source (T2CON) (T2CON) (BDRCON) (BDRCON) UART Tx UART Rx 0 0 0 0 Timer 1 Timer 1 1 0 0 0 Timer 2 Timer 1 0 1 0 0 Timer 1 Timer 2 1 1 0 0 Timer 2 Timer 2 X 0 1 0 INT_BRG Timer 1 X 1 1 0 INT_BRG Timer 2 0 X 0 1 Timer 1 INT_BRG 1 X 0 1 Timer 2 INT_BRG X X 1 1 INT_BRG INT_BRG When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Figure 24. Internal Baud Rate FPER 0 /6 auto reload counter overflow BRG 1 SPD /2 0 INT_BRG 1 BRL SMOD1 BRR • The baud rate for UART is token by formula: Baud_Rate = BRL = 256 - 56 2SMOD1 ⋅ FPER 6(1-SPD) ⋅ 32 ⋅ (256 -BRL) 2SMOD1 ⋅ FPER ⋅ 32 ⋅ Baud_Rate (1-SPD) 6 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 38. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit. 6 SM1 Serial port Mode bit 1 SM0 SM1 Mode 0 0 Shift Register 0 1 8-bit UART 1 0 9-bit UART 1 1 9-bit UART Baud Rate FXTAL /12 (or FXTAL /6 in mode X2) Variable FXTAL /64 or FXTAL/32 Variable Serial port Mode 2 bit / Multiprocessor Communication Enable bit 5 SM2 4 REN 3 TB8 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1.This bit should be cleared in mode 0. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 2 RB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 0 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 21. and Figure 22. in the other modes. Reset Value = 0000 0000b Bit addressable 57 4289B–8051–12/03 Table 39. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Table 40. Example of Computed Value When X2=0, SMOD1=0, SPD=0 Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 The baud rate generator can be used for mode 1 or 3 (refer to Figure 23.), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 47.) UART Registers Table 41. SADEN Register SADEN - Slave Address Mask Register for UART (B9h) 7 6 5 4 3 2 1 0 2 1 0 Reset Value = 0000 0000b Table 42. SADDR Register SADDR - Slave Address Register for UART (A9h) 7 6 5 4 3 Reset Value = 0000 0000b 58 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 43. SBUF Register SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 3 2 1 0 Reset Value = XXXX XXXXb Table 44. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b 59 4289B–8051–12/03 Table 45. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) 5 RCLK Receive Clock bit for UART Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit for UART Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 EXEN2 2 TR2 1 0 Timer 2 External Enable bit Cleared to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Cleared to turn off timer 2. Set to turn on timer 2. C/T2# Timer/Counter 2 select bit Cleared for timer operation (input from internal clock system: FCLK PERIPH ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. CP/RL2# Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable 60 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 46. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Description Serial port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 61 4289B–8051–12/03 Table 47. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. 3 TBCK Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 2 RBCK Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 1 SPD Description Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART 0 SRC Cleared to select FOSC /12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. Reset Value = XXX0 0000b Not bit addressablef 62 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Interrupt System The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 25. Figure 25. Interrupt Control System High priority interrupt IPH, IPL 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 Interrupt polling sequence, decreasing from high to low priority TF1 0 3 PCA IT 0 RI TI 3 TF2 EXF2 3 0 0 3 KBD IT 0 3 TWI IT 0 3 SPI IT 0 Low priority interrupt Individual Enable Global Disable Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 52 and Table 50). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 53) and in the Interrupt Priority High register (Table 51 and Table 52) shows the bit values and priority levels associated with each combination. 63 4289B–8051–12/03 Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 0043H and Keyboard interrupt vector is located at address 004BH. All other vectors addresses are the same as standard C52 devices. Table 48. Priority Level Bit Values IPH. x IPL. x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. 64 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 49. IENO Register IEN0 - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA 6 EC Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit Cleared to disable. Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. 4 ES Serial port Enable bit Cleared to disable serial port interrupt. Set to enable serial port interrupt. 3 ET1 Timer 1 overflow interrupt Enable bit Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2 EX1 External interrupt 1 Enable bit Cleared to disable external interrupt 1. Set to enable external interrupt 1. 1 ET0 Timer 0 overflow interrupt Enable bit Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0 EX0 External interrupt 0 Enable bit Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable 65 4289B–8051–12/03 Table 50. IPL0 Register IPL0 - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPCL PCA interrupt Priority bit Refer to PPCH for priority level. 5 PT2L Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PSL Serial port Priority bit Refer to PSH for priority level. 3 PT1L Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1L External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0L Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0L External interrupt 0 Priority bit Refer to PX0H for priority level. Reset Value = X000 0000b Bit addressable 66 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 51. IPH0 Register IPH0 - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. PPCH PCA interrupt Priority high bit. PPCHPPCLPriority Level 0 0Lowest 0 1 1 0 1 1Highest PT2H Timer 2 overflow interrupt Priority High bit PT2HPT2LPriority Level 0 0Lowest 0 1 1 0 1 1Highest PSH Serial port Priority High bit PSH PSLPriority Level 0 0Lowest 0 1 1 0 1 1Highest PT1H Timer 1 overflow interrupt Priority High bit PT1HPT1L Priority Level 0 0 Lowest 0 1 1 0 1 1Highest PX1H External interrupt 1 Priority High bit PX1HPX1LPriority Level 0 0Lowest 0 1 1 0 1 1Highest PT0H Timer 0 overflow interrupt Priority High bit PT0HPT0LPriority Level 0 0Lowest 0 1 1 0 1 1Highest PX0H External interrupt 0 Priority High bit PX0H PX0LPriority Level 0 0Lowest 0 1 1 0 1 1Highest Reset Value = X000 0000b Not bit addressable 67 4289B–8051–12/03 Table 52. IEN1 Register IEN1 - Interrupt Enable Register (B1h) 7 6 5 4 3 2 1 0 - - - - - ESPI ETWI EKBD Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 ESPI SPI interrupt Enable bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt. Set to enable TWI interrupt. 0 EKBD Keyboard interrupt Enable bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt. Reset Value = XXXX X000b Bit addressable 68 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 53. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Table 54. 7 6 5 4 3 2 1 0 - - - - - SPIL TWIL KBDL Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 SPIL SPI interrupt Priority bit Refer to SPIH for priority level. 1 TWIL TWI interrupt Priority bit Refer to TWIH for priority level. 0 KBDL Keyboard interrupt Priority bit Refer to KBDH for priority level. Reset Value = XXXX X000b Bit addressable 69 4289B–8051–12/03 Table 55. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) 7 6 5 4 3 2 1 0 - - - - - SPIH TWIH KBDH Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 1 0 SPIH SPI interrupt Priority High bit SPIH SPILPriority Level 0 0Lowest 0 1 1 0 1 1Highest TWIH TWI interrupt Priority High bit TWIH TWILPriority Level 0 0Lowest 0 1 1 0 1 1Highest KBDH Keyboard interrupt Priority High bit KB DH KBDLPriority Level 0 0 Lowest 0 1 1 0 1 1Highest Reset Value = XXXX X000b Not bit addressable 70 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Interrupt Sources and Vector Addresses Table 56. Interrupt Sources and Vector Addresses Interrupt Request Vector Number Polling Priority Interrupt Source Address 0 0 Reset 1 1 INT0 IE0 0003h 2 2 Timer 0 TF0 000Bh 3 3 INT1 IE1 0013h 4 4 Timer 1 IF1 001Bh 5 6 UART RI+TI 0023h 6 7 Timer 2 TF2+EXF2 002Bh 7 5 PCA CF + CCFn (n = 0-4) 0033h 8 8 Keyboard KBDIT 003Bh 9 9 TWI TWIIT 0043h 9 9 SPI SPIIT 004Bh 0000h 71 4289B–8051–12/03 Power Management Introduction Two power reduction modes are implemented in the AT89C51ID2. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”, page 21. Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 57. Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 58). The AT89C51ID2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: Exiting Idle Mode If IDL bit and PD bit are set simultaneously, the AT89C51ID2 enters Power-Down mode. Then it does not go in Idle mode when exiting Power-Down mode. There are two ways to exit Idle mode: 1. Generate an enabled interrupt. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – Note: Power-Down Mode 72 A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51ID2 and vectors the CPU to address C:0000h. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. The Power-Down mode places the AT89C51ID2 in a very low power state. Power-Down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-Down mode. In addition, the SFR AT89C51ID2 4289B–8051–12/03 AT89C51ID2 and RAM contents are preserved. The status of the Port pins during Power-Down mode is detailed in Table 57. Note: Entering Power-Down Mode VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissipation. Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51ID2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level. There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt. – The AT89C51ID2 provides capability to exit from Power-Down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 26). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode. Note: The external interrupt used to exit Power-Down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. Note: Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content. Figure 26. Power-Down Exit Waveform Using INT1:0# INT1:0# OSC Active phase Power-down phase Oscillator restart phase Active phase 2. Generate a reset. – Note: A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-Down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C51ID2 and vectors the CPU to address 0000h. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port 73 4289B–8051–12/03 pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Note: Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content. Table 57. Pin Conditions in Special Operating Modes 74 Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN# Reset Floating High High High High High High Idle (internal code) Data Data Data Data Data High High Idle (external code) Floating Data Data Data Data High High PowerDown(inter nal code) Data Data Data Data Data Low Low PowerDown (external code) Floating Data Data Data Data Low Low AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Registers Table 58. PCON Register PCON (S87:h) Power configuration Register 7 6 5 4 3 2 1 0 - - - POF GF1 GF0 PD IDL Bit Number 7-5 Bit Mnemonic Description - Reserved The value read from these bits is indeterminate. Do not set these bits. 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2 GF0 General Purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. PD Power-Down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. IDL Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. 1 0 Reset Value= XXXX 0000b 75 4289B–8051–12/03 Keyboard Interface The AT89C51ID2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. The keyboard interface interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 61), KBE, The Keyboard interrupt Enable register (Table 60), and KBF, the Keyboard Flag register (Table 59). Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 27). As detailed in Figure 28 each keyboard input has the capability to detect a programmable level according to KBLS. x bit value. Level detection is then reported in interrupt flags KBF. x that can be masked by software using KBE. x bits. This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1 inputs for other purpose. Figure 27. Keyboard Interface Block Diagram Vcc 0 P1:x KBF. x 1 Internal Pullup KBE. x KBLS. x Figure 28. Keyboard Input Circuitry P1.0 Input Circuitry P1.1 Input Circuitry P1.2 Input Circuitry P1.3 Input Circuitry P1.4 Input Circuitry P1.5 Input Circuitry P1.6 Input Circuitry P1.7 Input Circuitry KBDIT Power Reduction Mode 76 KBD IE1 Keyboard Interface Interrupt Request P1 inputs allow exit from idle and power down modes as detailed in Section “Power Management”, page 72. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Registers Table 59. KBF Register KBF-Keyboard Flag Register (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description KBF7 Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. Must be cleared by software. KBF6 Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set. Must be cleared by software. KBF5 Keyboard line 5 flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set. Must be cleared by software. KBF4 Keyboard line 4 flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set. Must be cleared by software. KBF3 Keyboard line 3 flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set. Must be cleared by software. KBF2 Keyboard line 2 flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set. Must be cleared by software. KBF1 Keyboard line 1 flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set. Must be cleared by software. KBF0 Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software. Reset Value= 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. 77 4289B–8051–12/03 Table 60. KBE Register KBE-Keyboard Input Enable Register (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic Description 7 KBE7 Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 6 bit in KBF register to generate an interrupt request. 5 KBE5 Keyboard line 5 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 5 bit in KBF register to generate an interrupt request. 4 KBE4 Keyboard line 4 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 4 bit in KBF register to generate an interrupt request. 3 KBE3 Keyboard line 3 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 3 bit in KBF register to generate an interrupt request. 2 KBE2 Keyboard line 2 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 2 bit in KBF register to generate an interrupt request. 1 KBE1 Keyboard line 1 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. 0 KBE0 Keyboard line 0 Enable bit Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request. Reset Value= 0000 0000b 78 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 61. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. 5 KBLS5 Keyboard line 5 Level Selection bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. 4 KBLS4 Keyboard line 4 Level Selection bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. 3 KBLS3 Keyboard line 3 Level Selection bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. 2 KBLS2 Keyboard line 2 Level Selection bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. 1 KBLS1 Keyboard line 1 Level Selection bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. 0 KBLS0 Keyboard line 0 Level Selection bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value= 0000 0000b 79 4289B–8051–12/03 2-wire Interface (TWI) This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 400 Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure 29 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave. Figure 29. 2-wire Bus Configuration device1 device2 device3 ... deviceN SCL SDA 80 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 30. Block Diagram 8 Address Register SSADR Comparator Input Filter SDA PI2.1 Output Stage SSDAT ACK Shift Register Arbitration & Sink Logic Input Filter Timing & Control logic SCL PI2.0 FCLK PERIPH/4 Interrupt Serial clock generator Output Stage Internal Bus 8 Timer 1 overflow SSCON Control Register 7 Status Bits SSCS Status Decoder Status Register 8 81 4289B–8051–12/03 Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 71), the Synchronous Serial Data register (SSDAT; Table 72), the Synchronous Serial Control and Status register (SSCS; Table 73) and the Synchronous Serial Address register (SSADR Table 76). SSCON is used to enable the TWI interface, to program the bit rate (see Table 64), to enable slave modes, to acknowledge or not a received data, to send a START or a STOP condition on the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI module. SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus. The three least significant bits are always zero. The five most significant bits contains the status code. There are 26 possible status codes. When SSCS contains F8h, no relevant state information is available and no serial interrupt is requested. A valid status code is available in SSCS one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. to Table 70. give the status for the master modes and miscellaneous states. SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always contains the last byte present on the bus. SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI module will respond when programmed as a slave transmitter or receiver. The LSB is used to enable general call address (00h) recognition. Figure 31 shows how a data transfer is accomplished on the 2-wire bus. Figure 31. Complete Data Transfer on 2-wire Bus SDA MSB acknowledgement signal from receiver acknowledgement signal from receiver SCL 1 2 7 S start condition 8 9 ACK 1 2 3-8 9 ACK clock line held low while interrupts are serviced P stop condition The four operating modes are: • Master Transmitter • Master Receiver • Slave transmitter • Slave receiver Data transfer in each mode of operation is shown in Table to Table 70 and Figure 32. to Figure 35.. These figures contain the following abbreviations: S : START condition R : Read bit (high level at SDA) 82 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 32 to Figure 35, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When the serial interrupt routine is entered, the status code in SSCS is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table to Table 70. Master Transmitter Mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (Figure 32). Before the master transmitter mode can be entered, SSCON must be initialised as follows: Table 62. SSCON Initialization CR2 SSIE STA STO SI AA CR1 CR0 bit rate 1 0 0 0 X bit rate bit rate CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not used. SSIE must be set to enable TWI. STA, STO and SI must be cleared. The master transmitter mode may now be entered by setting the STA bit. The 2-wire logic will now test the 2-wire bus and generate a START condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON) is set, and the status code in SSCS will be 08h. This status must be used to vector to an interrupt routine that loads SSDAT with the slave address and the data direction bit (SLA+W). When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, SI is set again and a number of status code in SSCS are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted. SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master receiver mode by loading SSDAT with SLA+R. Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (Figure 33). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue. 83 4289B–8051–12/03 When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table . This scheme is repeated until a STOP condition is transmitted. SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may switch to the master transmitter mode by loading SSDAT with SLA+W. Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmitter (Figure 34). To initiate the slave receiver mode, SSADR and SSCON must be loaded as follows: Table 63. SSADR: Slave Receiver Mode Initialization A6 A5 A4 A3 A2 A1 A0 GC own slave address The upper 7 bits are the address to which the TWI module will respond when addressed by a master. If the LSB (GC) is set the TWI module will respond to the general call address (00h); otherwise it ignores the general call address. Table 64. SSCON: Slave Receiver Mode Initialization CR2 SSIE STA STO SI AA CR1 CR0 bit rate 1 0 0 0 1 bit rate bit rate CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The AA bit must be set to enable the own slave address or the general call address acknowledgement. STA, STO and SI must be cleared. When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine.The appropriate action to be taken for each of these status code is detailed in Table . The slave receiver mode may also be entered if arbitration is lost while TWI is in the master mode (states 68h and 78h). If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the module from the 2-wire bus. Slave Transmitter Mode 84 In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 35). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by AT89C51ID2 4289B–8051–12/03 AT89C51ID2 its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine. The appropriate action to be taken for each of these status code is detailed in Table . The slave transmitter mode may also be entered if arbitration is lost while the TWI module is in the master mode. If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the transfer and enter state C0h or C8h. the TWI module is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1’s as serial data. While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the TWI module from the 2-wire bus. Miscellaneous States There are two SSCS codes that do not correspond to a define TWI hardware state (Table 70 ). These codes are discuss hereafter. Status F8h indicates that no relevant information is available because the serial interrupt flag is not set yet. This occurs between other states and when the TWI module is not involved in a serial transfer. Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus error is caused when a START or a STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions happen during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes the TWI module to enter the not addressed slave mode and to clear the STO flag (no other bits in SSCON are affected). The SDA and SCL lines are released and no STOP condition is transmitted. Notes the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock line) and SDA (serial data line). To avoid low level asserting on these lines when the TWI module is enabled, the output latches of SDA and SLC must be set to logic 1. Table 65. Bit Frequency Configuration Bit Frequency ( kHz) CR2 CR1 CR0 FOSCA = 12 MHz FOSCA = 16 MHz FOSCA divided by 0 0 0 47 62.5 256 0 0 1 53.5 71.5 224 0 1 0 62.5 83 192 0 1 1 75 100 160 1 0 0 - - Unused 1 0 1 100 133.3 120 1 1 0 200 266.6 60 1 1 1 0.5 <. < 62.5 0.67 <. < 83 96 · (256 - reload valueTimer 1) (reload value range: 0-254 in mode 2) 85 4289B–8051–12/03 Figure 32. Format and State in the Master Transmitter Mode MT Successfull transmission to a slave receiver S SLA 08h W A Data A P 28h 18h Next transfer started with a repeated start condition S SLA W 10h Not acknowledge received after the slave address A R P 20h MR Not acknowledge received after a data byte A P 30h Arbitration lost in slave address or data byte A or A Other master continues 38h Arbitration lost and addressed as slave From slave to master 86 Other master continues 38h Other master continues A 68h From master to slave A or A Data n 78h A B0h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 66. Status in Master Transmitter Mode Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware 08h A START condition has Write SLA+W been transmitted X 0 0 X Write SLA+W X 0 0 X 10h A repeated START condition has been transmitted Write SLA+R X 0 0 X Write data byte 0 0 0 X No SSDAT action 1 0 0 X No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. No SSDAT action 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Write data byte 0 0 0 X No SSDAT action 1 0 0 X No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. No SSDAT action 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Write data byte 0 0 0 X No SSDAT action 1 0 0 X No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. No SSDAT action 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Write data byte 0 0 0 X No SSDAT action 1 0 0 X No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. No SSDAT action 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. No SSDAT action 0 0 0 X Two-wire bus will be released and not addressed slave mode will be entered. No SSDAT action 1 0 0 X A START condition will be transmitted when the bus becomes free. 18h 20h 28h 30h 38h SLA+W has been transmitted; ACK has been received SLA+W has been transmitted; NOT ACK has been received Data byte has been transmitted; ACK has been received Data byte has been transmitted; NOT ACK has been received Arbitration lost in SLA+W or data bytes SLA+W will be transmitted. SLA+W will be transmitted. SLA+R will be transmitted. Logic will switch to master receiver mode Data byte will be transmitted. Repeated START will be transmitted. Data byte will be transmitted. Repeated START will be transmitted. Data byte will be transmitted. Repeated START will be transmitted. Data byte will be transmitted. Repeated START will be transmitted. 87 4289B–8051–12/03 Figure 33. Format and State in the Master Receiver Mode MR Successfull transmission to a slave receiver S SLA 08h R Data A A 50h 40h Data A P 58h Next transfer started with a repeated start condition S SLA R 10h Not acknowledge received after the slave address A W P MT 48h Arbitration lost in slave address or acknowledge bit A or A Other master continues 38h Arbitration lost and addressed as slave From slave to master 88 Other master continues 38h Other master continues A 68h From master to slave A Data n 78h A B0h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 67. Status in Master Receiver Mode Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware 08h A START condition has Write SLA+R been transmitted X 0 0 X Write SLA+R X 0 0 X 10h A repeated START condition has been transmitted Write SLA+W X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode. Arbitration lost in SLA+R or NOT ACK bit No SSDAT action 0 0 0 X Two-wire bus will be released and not addressed slave mode will be entered. No SSDAT action 1 0 0 X A START condition will be transmitted when the bus becomes free. SLA+R has been transmitted; ACK has been received No SSDAT action 0 0 0 0 Data byte will be received and NOT ACK will be returned. No SSDAT action 0 0 0 1 Data byte will be received and ACK will be returned. No SSDAT action 1 0 0 X No SSDAT action 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. No SSDAT action 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. Read data byte 0 0 0 0 Data byte will be received and NOT ACK will be returned. Read data byte 0 0 0 1 Data byte will be received and ACK will be returned. Read data byte 1 0 0 X Read data byte 0 1 0 X STOP condition will be transmitted and SSSTO flag will be reset. Read data byte 1 1 0 X STOP condition followed by a START condition will be transmitted and SSSTO flag will be reset. 38h 40h 48h 50h 58h SLA+R has been transmitted; NOT ACK has been received Data byte has been received; ACK has been returned Data byte has been received; NOT ACK has been returned SLA+R will be transmitted. SLA+R will be transmitted. Repeated START will be transmitted. Repeated START will be transmitted. 89 4289B–8051–12/03 Figure 34. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. S SLA W Data A 60h A Data 80h Last data byte received is not acknowledged. A P or S 80h A0h A P or S 88h Arbitration lost as master and addressed as slave A 68h Reception of the general call address and one or more data bytes. General Call Data A 70h Last data byte received is not acknowledged. A 90h Data A P or S 90h A0h A P or S 98h A Arbitration lost as master and addressed as slave by general call 78h From master to slave From slave to master 90 Data n A Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 68. Status in Slave Receiver Mode Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware 70h 78h STO SI AA Next Action Taken By 2-wire Software No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No SSDAT action X 0 0 1 Data byte will be received and ACK will be returned Arbitration lost in SLA+R/W as master; own SLA+W has been received; ACK has been returned No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No SSDAT action X 0 0 1 Data byte will be received and ACK will be returned General call address has been received; ACK has been returned No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No SSDAT action X 0 0 1 Data byte will be received and ACK will be returned No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No SSDAT action X 0 0 1 Data byte will be received and ACK will be returned No SSDAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No SSDAT action X 0 0 1 Data byte will be received and ACK will be returned Arbitration lost in SLA+R/W as master; general call address has been received; ACK has been returned Previously addressed with own SLA+W; data has been received; ACK has been returned 80h 88h STA Own SLA+W has been received; ACK has been returned 60h 68h To SSCON Previously addressed with own SLA+W; data has been received; NOT ACK has been returned 90h Previously addressed with general call; data has been received; ACK has been returned Read data byte or 0 0 0 0 Read data byte or 0 0 0 1 Read data byte or 1 0 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Read data byte 1 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free Read data byte or X 0 0 0 Data byte will be received and NOT ACK will be returned Read data byte X 0 0 1 Data byte will be received and ACK will be returned 91 4289B–8051–12/03 Table 68. Status in Slave Receiver Mode (Continued) Application Software Response Status Code (SSCS) 98h A0h 92 To/from SSDAT Status of the 2-wire bus and 2-wire hardware Previously addressed with general call; data has been received; NOT ACK has been returned A STOP condition or repeated START condition has been received while still addressed as slave To SSCON STA STO SI AA Read data byte or 0 0 0 0 Read data byte or 0 0 0 1 Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Read data byte or 1 0 0 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free Read data byte 1 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free No SSDAT action or 0 0 0 0 No SSDAT action or 0 0 0 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 No SSDAT action or 1 0 0 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free No SSDAT action 1 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 35. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes SLA A R A Data A8h Arbitration lost as master and addressed as slave B8h Data A P or S C0h A B0h Last data byte transmitted. Switched to not addressed slave (AA=0) A All 1’s P or S C8h From master to slave Data From slave to master A Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus n Table 69. Status in Slave Transmitter Mode Application Software Response Status Code (SSCS) To/from SSDAT Status of the 2-wire bus and 2-wire hardware Own SLA+R has been received; ACK has been returned A8h B0h B8h Arbitration lost in SLA+R/W as master; own SLA+R has been received; ACK has been returned Data byte in SSDAT has been transmitted; NOT ACK has been received To SSCON STA STO SI AA Next Action Taken By 2-wire Software Load data byte or X 0 0 0 Last data byte will be transmitted and NOT ACK will be received Load data byte X 0 0 1 Data byte will be transmitted and ACK will be received Load data byte or X 0 0 0 Last data byte will be transmitted and NOT ACK will be received Load data byte X 0 0 1 Data byte will be transmitted and ACK will be received Load data byte or X 0 0 0 Last data byte will be transmitted and NOT ACK will be received Load data byte X 0 0 1 Data byte will be transmitted and ACK will be received 93 4289B–8051–12/03 Table 69. Status in Slave Transmitter Mode (Continued) Application Software Response Status Code (SSCS) C0h C8h To/from SSDAT Status of the 2-wire bus and 2-wire hardware Data byte in SSDAT has been transmitted; NOT ACK has been received Last data byte in SSDAT has been transmitted (AA=0); ACK has been received To SSCON STA STO SI AA No SSDAT action or 0 0 0 0 No SSDAT action or 0 0 0 1 Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 No SSDAT action or 1 0 0 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free No SSDAT action 1 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free No SSDAT action or 0 0 0 0 No SSDAT action or 0 0 0 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 No SSDAT action or 1 0 0 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA. A START condition will be transmitted when the bus becomes free No SSDAT action 1 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1. A START condition will be transmitted when the bus becomes free Table 70. Miscellaneous Status Application Software Response 94 Status Code (SSCS) Status of the 2-wire bus and 2-wire hardware F8h No relevant state information available; SI= 0 00h Bus error due to an illegal START or STOP condition To/from SSDAT To SSCON STA No SSDAT action No SSDAT action STO SI Next Action Taken By 2-wire AA Software No SSCON action Wait or proceed current transfer 0 Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and STO is reset. 1 0 X AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Registers Table 71. SSCON Register SSCON - Synchronous Serial Control register (93h) 7 6 5 4 3 2 1 0 CR2 SSIE STA STO SI AA CR1 CR0 Bit Number Bit Mnemonic Description 7 CR2 Control Rate bit 2 See Table 65. 6 SSIE Synchronous Serial Interface Enable bit Clear to disable the TWI module. Set to enable the TWI module. 5 STA Start flag Set to send a START condition on the bus. 4 ST0 Stop flag Set to send a STOP condition on the bus. 3 SI Synchronous Serial Interrupt flag Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt. 2 AA Assert Acknowledge flag Clear in master and slave receiver modes, to force a not acknowledge (high level on SDA). Clear to disable SLA or GCA recognition. Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter modes. Set in master and slave receiver modes, to force an acknowledge (low level on SDA). This bit has no effect when in master transmitter mode. 1 CR1 Control Rate bit 1 See Table 65. 0 CR0 Control Rate bit 0 See Table 65. Table 72. SSDAT (095h) - Syncrhonous Serial Data register (read/write) SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 7 6 5 4 3 2 1 0 Bit Number Bit Mnemonic Description 7 SD7 Address bit 7 or Data bit 7. 6 SD6 Address bit 6 or Data bit 6. 5 SD5 Address bit 5 or Data bit 5. 4 SD4 Address bit 4 or Data bit 4. 3 SD3 Address bit 3 or Data bit 3. 2 SD2 Address bit 2 or Data bit 2. 95 4289B–8051–12/03 Bit Number Bit Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 73. SSCS (094h) read - Synchronous Serial Control and Status Register 7 6 5 4 3 2 1 0 SC4 SC3 SC2 SC1 SC0 0 0 0 Table 74. SSCS Register: Read Mode - Reset Value = F8h Bit Number Bit Mnemonic Description 0 0 Always zero 1 0 Always zero 2 0 Always zero 3 SC0 4 SC1 5 SC2 Status Code bit 2 See to Table 70. 6 SC3 Status Code bit 3 See to Table 70. 7 SC4 Status Code bit 4 See to Table 70. Status Code bit 0 See to Table 70. Status Code bit 1 See to Table 70. Table 75. SSADR (096h) - Synchronus Serial Address Register (read/write) 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 Table 76. SSADR Register - Reset value = FEh Bit Number 96 Bit Mnemonic Description 7 A7 Slave Address bit 7 6 A6 Slave Address bit 6 5 A5 Slave Address bit 5 4 A4 Slave Address bit 4 3 A3 Slave Address bit 3 2 A2 Slave Address bit 2 1 A1 Slave Address bit 1 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Bit Number Bit Mnemonic Description General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition. 97 4289B–8051–12/03 Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features Features of the SPI Module include the following: Signal Description • Full-duplex, three-wire synchronous transfers • Master or Slave operation • Eight programmable Master clock rates • Serial clock with programmable polarity and phase • Master Mode fault error flag with MCU interrupt capability • Write collision flag protection Figure 36 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices. Figure 36. SPI Master/Slaves Interconnection Slave 1 MISO MOSI SCK SS MISO MOSI SCK SS VDD Slave 4 Slave 3 MISO MOSI SCK SS 0 1 2 3 MISO MOSI SCK SS MISO MOSI SCK SS PORT Master Slave 2 The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. Master Input Slave Output (MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can 98 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 drive the network. The Master may select each Slave device by software through port pins (Figure 37). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: • The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be set(1). • The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device. Note: 1. Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this mode, the SS is used to start the transmission. Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128. Table 77 gives the different clock rates selected by SPR2:SPR1:SPR0. Table 77. SPI Master Baud Rate Selection SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD) 0 0 0 FCLK PERIPH /2 2 0 0 1 FCLK PERIPH /4 4 0 1 0 FCLK PERIPH/8 8 0 1 1 FCLK PERIPH /16 16 1 0 0 FCLK PERIPH /32 32 1 0 1 FCLK PERIPH /64 64 1 1 0 FCLK PERIPH /128 128 1 1 1 Don’t Use No BRG 99 4289B–8051–12/03 Functional Description Figure 37 shows a detailed structure of the SPI Module. Figure 37. SPI Module Block Diagram Internal Bus SPDAT FCLK PERIPH Clock Divider /4 /8 /16 /32 /64 /128 Shift Register 7 6 5 4 3 2 1 0 Receive Data Register Pin Control Logic Clock Logic M S Clock Select SPR2 MOSI MISO SCK SS SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPCON SPI Interrupt Request SPI Control 8-bit bus 1-bit signal SPSTA SPIF WCOL Operating Modes - MODF - - - - The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module is made through one register: • The Serial Peripheral Control register (SPCON) Once the SPI is configured, the data exchange is made using: • SPCON • The Serial Peripheral STAtus register (SPSTA) • The Serial Peripheral DATa register (SPDAT) During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 38). 100 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Figure 38. Full-Duplex Master-Slave Interconnection 8-bit Shift register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU 8-bit Shift register SCK VDD SS VSS Slave MCU Master Mode The SPI operates in Master mode when the Master bit, MSTR (1) , in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to ’0’. SS must remain low until the transmission is complete. In a Slave SPI Module, data enters the shift register under the control of the SCK from the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another Byte enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission. The maximum SCK frequency allowed in slave mode is FCLK PERIPH /4. Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (4) ) and the Clock Phase (CPHA4). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 39 and Figure 40). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. 1. The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Master SPI should be configured before the Slave SPI. 2. 3. The SPI Module should be configured as a Slave before it is enabled (SPEN set). The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). 4. 101 4289B–8051–12/03 Figure 39. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 40. Data Transmission Format (CPHA = 1) 1 2 3 4 5 6 7 8 MOSI (from Master) MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) MSB bit6 bit5 bit4 bit3 bit2 bit1 SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) LSB SS (to Slave) Capture Point Figure 41. CPHA/SS Timing MISO/MOSI Byte 1 Byte 2 Byte 3 Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) As shown in Figure 39, the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each Byte transmitted (Figure 41). Figure 40 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 41). This format may be preffered in systems having only one Master and only one Slave driving the MISO data line. 102 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Error Conditions The following flags in the SPSTA signal SPI error conditions: Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated • The SPEN bit in SPCON is cleared. This disables the SPI • The MSTR bit in SPCON is cleared When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes ’0’. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master attempts to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data Bytes and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost. This condition is not detected by the SPI peripheral. SS Error Flag (SSERR) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit (reset of the SPI state machine). Interrupts Two SPI status flags can generate a CPU interrupt requests: Table 78. SPI Interrupts Flag Request SPIF (SP data transfer) SPI Transmitter Interrupt request MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 42 gives a logical view of the above statements. 103 4289B–8051–12/03 Figure 42. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS Registers There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs. Serial Peripheral Control Register (SPCON) • The Serial Peripheral Control Register does the following: • Selects one of the Master clock rates • Configure the SPI Module as Master or Slave • Selects serial clock polarity and phase • Enables the SPI Module • Frees the SS pin for a general-purpose Table 79 describes this register and explains the use of each bit Table 79. SPCON Register SPCON - Serial Peripheral Control Register (0C3H) Table 1. 7 6 5 4 3 2 1 0 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic 7 SPR2 6 SPEN Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate. Serial Peripheral Enable Cleared to disable the SPI interface. Set to enable the SPI interface. SS Disable Cleared to enable SS in both Master and Slave modes. 5 SSDIS 4 MSTR Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request is generated. Serial Peripheral Master Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle low. Clock Phase 2 CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). 104 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Bit Number Bit Mnemonic SPR1 1 0 SPR0 Description SPR2 SPR1 0 0 0 FCLK PERIPH /2 0 0 1 FCLK PERIPH /4 0 1 0 FCLK PERIPH /8 0 1 1 FCLK PERIPH /16 1 0 0 FCLK PERIPH /32 1 0 1 FCLK PERIPH /64 1 1 0 FCLK PERIPH /128 1 1 1 Invalid SPR0 Serial Peripheral Rate Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent logic level on SS pin (mode fault error) Table 80 describes the SPSTA register and explains the use of every bit in the register. Table 80. SPSTA Register SPSTA - Serial Peripheral Status and Control register (0C4H) Table 2. 7 6 5 4 3 2 1 0 SPIF WCOL SSERR MODF - - - - Bit Number Bit Mnemonic Description Serial Peripheral Data Transfer Flag 7 SPIF Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision Flag 6 WCOL Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. Synchronous Serial Slave Error Flag 5 SSERR Set by hardware when SS is deasserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). Mode Fault 4 MODF Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level. 3 - 2 - Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. 105 4289B–8051–12/03 Bit Number Bit Mnemonic Description 1 - 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 81) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 81. SPDAT Register SPDAT - Serial Peripheral Data Register (0C5H) Table 3. 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0 Reset Value = Indeterminate R7:R0: Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: 106 • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where T CLK PERIPH= 1/FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSCA = 12MHz. To manage this feature, refer to WDTPRG register description, Table 82. Table 82. WDTRST Register WDTRST - Watchdog Reset Register (0A6h) 7 6 5 4 3 2 1 0 - - - - - - - - Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. 107 4289B–8051–12/03 Table 83. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Reserved The value read from this bit is undetermined. Do not try to set this bit. S2S1 S0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Selected Time-out 0 (214 - 1) machine cycles, 16. 3 ms @ F OSCA =12 MHz 1 (215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz 0 (216 - 1) machine cycles, 65. 5 ms @ F OSCA=12 MHz 1 (217 - 1) machine cycles, 131 ms @ FOSCA=12 MHz 0 (218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz 1 (219 - 1) machine cycles, 542 ms @ FOSCA=12 MHz 0 (220 - 1) machine cycles, 1.05 s @ F OSCA=12 MHz 1 (221 - 1) machine cycles, 2.09 s @ F OSCA=12 MHz Reset value = XXXX X000 WDT During Power Down In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of and Idle exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the AT89C51ID2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is better to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51ID2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 108 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 ONCE(TM) Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using AT89C51ID2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51ID2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51ID2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 84 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 84. External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 Port I2 XTALA1/2 XTALB1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Float Active Active (a) "Once" is a registered trademark of Intel Corporation. 109 4289B–8051–12/03 Power-off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (Table 85). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. Table 85. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable 110 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 EEPROM Data Memory The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read or write access to the EEPROM memory is done with a MOVX instruction. Write Data Data is written by byte to the EEPROM memory block as for an external RAM memory. The following procedure is used to write to the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save and disable interrupts. • Load DPTR with the address to write • Store A register with the data to be written • Set bit EEE of EECON register • Execute a MOVX @DPTR, A • Clear bit EEE of EECON register • Restore interrupts. • EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading or writing. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Figure 43 represents the optimal write sequence to the on-chip EEPROM data memory. 111 4289B–8051–12/03 Figure 43. Recommended EEPROM Data Write Sequence EEPROM Data Write Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Write DPTR= Address ACC= Data Exec: MOVX @DPTR, A EEPROM Mapping EECON = 00h (EEE=0) Restore IT Last Byte to Load? 112 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Read Data The following procedure is used to read the data stored in the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save and disable interrupts. • Load DPTR with the address to read • Set bit EEE of EECON register • Execute a MOVX A, @DPTR • Clear bit EEE of EECON register • Restore interrupts. Figure 44. Recommended EEPROM Data Read Sequence EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Read DPTR= Address ACC= Data Exec: MOVX A, @DPTR Last Byte to Read? EEPROM Data Mapping EECON = 00h (EEE = 0 Restore IT 113 4289B–8051–12/03 Registers Table 86. EECON Register EECON (0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 - - - - - - EEE EEBUSY Bit Number Bit Mnemonic 7-2 - 1 EEE Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to the EEPROM . Clear to map the XRAM space during MOVX. 0 EEBUSY Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable 114 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 87. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - M0 XRS2 XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse length 5 M0 Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods. 4 XRS2 XRAM Size 3 XRS1 XRS2 XRS1XRS0XRAM size 0 0 0 256 bytes 0 0 1 512 bytes 2 XRS0 0 1 0 768 bytes(default) 0 1 1 1024 bytes 1 0 0 1792 bytes EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. 0 AO ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable 115 4289B–8051–12/03 Flash Memory The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized respectively in 512 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash. The programming does not require external dedicated programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of the microcontroller. Features Flash Programming and Erasure • Flash internal program memory. • Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. • Default loader in Boot ROM allows programming via the serial port without the need of a user provided loader. • Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). • Programming and erase voltage with standard power supply. • Read/Programming/Erase: • Byte-wise read without wait state • Byte or page erase and programming (10 ms) • Typical programming time (64K bytes) is 22s with on chip serial bootloader • Parallel programming with 87C51 compatible hardware interface to programmer • Programmable security for the code in the Flash • 100k write cycles • 10 years data retention The 64K bytes Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or a page before programming. The programming of a byte or a page includes a self erase before programming. There are three methods of programming the Flash memory: 116 • First, the on-chip ISP bootloader may be invoked which will use low level routines to program the pages. The interface used for serial downloading of Flash is the UART. • Second, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot ROM. • Third, the Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51ID2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Flash Registers and Memory Map Hardware Register The AT89C51ID2 Flash memory uses several registers for his management: • Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. • Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB). Table 88. Hardware Security Byte (HSB) 7 6 5 4 3 2 1 0 X2 BLJB OSC - XRAM LB2 LB1 LB0 Bit Number 7 Bit Mnemonic X2 Description X2 Mode Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset. Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset (Default). Boot Loader Jump Bit 6 BLJB Unprogrammed (‘1’ value) to start the user’s application on next reset at address 0000h. Programmed (‘0’ value) to start the boot loader at address F800h on next reset (Default). Oscillator Bit 5 OSC Programmed to allow oscillator B at startup Unprogrammed this bit to allow oscillator A at startup ( Default). 4 - 3 XRAM Reserved XRAM config bit (only programmable by programmer tools) Programmed to inhibit XRAM Unprogrammed, this bit to valid XRAM (Default) 2-0 LB2-0 User Memory Lock Bits (only programmable by programmer tools) See Table 89 Boot Loader Jump Bit (BLJB) One bit of the HSB, the BLJB bit, is used to force the boot address: Flash Memory Lock Bits • When this bit is programmed (‘1’ value) the boot address is 0000h. • When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default, this bit is unprogrammed and the ISP is enabled. The three lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 89. 117 4289B–8051–12/03 Table 89. Program Lock Bits Program Lock Bits Security level LB0 LB1 LB2 1 U U U No program lock features enabled. U MOVC instruction executed from external program memory is disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the on chip code memory is disabled. 2 P U Protection description ISP and software programming with API are still allowed. Writing EEprom Data from external parallel programmer is disabled but still allowed from internal code execution. 3 X P U 4 X X P Note: Same as 2, also verify code memory through parallel programming interface is disabled. Writing And Reading EEPROM Data from external parallel programmer is disabled but still allowed from internal code execution.. Same as 3, also external execution is disabled. (Default) U: unprogrammed or "one" level. P: programmed or "zero" level. X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. These security bits protect the code access through the parallel programming interface. They are set by default to level 4. The code access through the ISP is still possible and is controlled by the "software security bits" which are stored in the extra Flash memory accessed by the ISP firmware. To load a new application with the parallel programmer, a chip erase must first be done. This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes. Default Values Software Registers The default value of the HSB provides parts ready to be programmed with ISP: • BLJB: Programmed force ISP operation. • X2: Unprogrammed to force X1 mode (Standard Mode). • XRAM: Unprogrammed to valid XRAM • LB2-0: Security level four to protect the code from a parallel access with maximum security. Several registers are used, in factory and by parallel programmers. These values are used by Atmel ISP. These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers described in Table 90. 118 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 90. Default Values Mnemonic Definition Default value Description SBV Software Boot Vector FCh HSB Copy of the Hardware security byte BSB Boot Status Byte SSB Software Security Byte FFh Copy of the Manufacturer Code 58h ATMEL Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable Copy of the Device ID #2: memories size and type ECh AT89C51ID2 64KB Copy of the Device ID #3: name and revision EFh AT89C51ID2 64KB, Revision 0 101x 1011b 0FFh After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h. The content of the Software Security Byte (SSB) is described in Table 90 and Table 93. To assure code protection from a parallel access, the HSB must also be at the required level. Table 91. Software Security Byte Table 92. 7 6 5 4 3 2 1 0 - - - - - - LB1 LB0 Bit Number Bit Mnemonic Description 7 - Reserved Do not clear this bit. 6 - Reserved Do not clear this bit. 5 - Reserved Do not clear this bit. 4 - Reserved Do not clear this bit. 3 - Reserved Do not clear this bit. 2 - Reserved Do not clear this bit. 1-0 LB1-0 User Memory Lock Bits See Table 93 The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 93. 119 4289B–8051–12/03 Table 93. Program Lock bits of the SSB Program Lock Bits Security level LB0 LB1 1 U U No program lock features enabled. 2 P U ISP programming of the Flash is disabled. 3 X P Same as 2, also verify through ISP programming interface is disabled. Note: Flash Memory Status Protection description U: unprogrammed or "one" level. P: programmed or "zero" level. X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C51ID2 parts are delivered in standard with the ISP rom bootloader. After ISP or parallel programming, the possible contents of the Flash memory are summarized on the figure below: Figure 45. Flash memory possible contents FFFFh Virgin Application Virgin or application Application Dedicated ISP Virgin or application Virgin or application Dedicated ISP 0000h Default After ISP After ISP After parallel programming After parallel programming After parallel programming Memory Organization When the EA pin high, the processor fetches instructions from internal program Flash. . If the EA pin is tied low, all program memory fetches are from external memory. 120 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Bootloader Architecture Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 46. Diagram Context Description access via specific protocol Bootloader Flash memory access from user application Acronyms ISP : In-System Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte 121 4289B–8051–12/03 Functional Description Figure 47. Bootloader Functional Description Exernal host with Specific Protocol Communication User Application User Call Management (API ) ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication frame (UART) into flash memory acess (read, write, erase ...). • User Call Management Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontroller’s registers before making a call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory Management. • Flash Memory Management This process manages low level access to flash memory (performs read and write access). 122 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Bootloader Functionality Introduction The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’s code but can be manually forced into default ISP operation. As PSEN is a an output port in normal operating mode after reset, user application should take care to release PSEN after falling edge of reset signal. The hardware conditions are sampled at reset signal falling edge, thus they can be released at any time when reset input is low. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on (See Figure 48). Figure 48. Hardware conditions typical sequence during power-on. VCC PSEN RST The on-chip bootloader boot process is shown Figure 49 Purpose Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB, BSB and SBV values. The Boot Loader Jump Bit forces the application execution. BLJB = 0 => Boot loader execution. BLJB = 1 => Application execution BLJB The BLJB is a fuse bit in the Hardware Byte. That can be modified by hardware (programmer) or by software (API). Note: The BLJB test is perform by hardware to prevent any program execution.. 123 4289B–8051–12/03 Purpose The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value) if no custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction. 124 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Boot Process Figure 49. Bootloader Process RESET If BLJB=0 then ENBOOT bit (AUXR1) is set else ENBOOT bit (AUXR1) is cleared Yes (PSEN = 0, EA = 1, and ALE =1 or not connected) Hardware Hardware condition? FCON = 00h FCON = F0h BLJB=1 ENBOOT=0 BLJB!= 0 ? BLJB=0 ENBOOT=1 F800h Software FCON = 00h ? yes = hardware boot conditions BSB = 00h ? PC=0000h USER APPLICATION SBV = FCh ? USER BOOT LOADER Atmel BOOT LOADER PC= [SBV]00h 125 4289B–8051–12/03 ISP Protocol Description Physical Layer Frame Description The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader to compute the baudrate choosen by the host. The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below Figure 50. Intel Hex Type Frame • Record Mark ’:’ Reclen Load Offset Record Type 1-byte 1-byte 2-bytes 1-byte Data or Info n-bytes Checksum 1-byte Record Mark: Record Mark is the start of frame. This field must contain ’:’. • Reclen: Reclen specifies the number of bytes of information or data which follows the Record Type field of the record. • Load Offset: Load Offset specifies the 16-bit starting load offset of the data bytes, therefore this field is used only for Data Program Record (see Section “ISP Commands Summary”). • Record Type: Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types is described in Section “ISP Commands Summary”. • Data/Info: Data/Info is a variable length field. It consists of zero or more bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. • Checksum: The two’s complement of the 8-bit bytes that result from converting each pair of ASCII hexadecimal digits to one byte of binary, and including the Reclen field to and including the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. 126 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Functional Description Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. • level 1: WRITE_SECURITY (FEh ) For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns ’P’ on write access. From level 1, one can write only level 2. • level 2: RD_WR_SECURITY (FCh The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory. The Bootloader returns ’L’ on read or write access. Only a full chip erase in parallel mode (using a programmer) or ISP command can reset the software security bits. From level 2, one cannot read and write anything. Table 94. Software Security Byte Behavior Level 0 Level 1 Level 2 Flash/EEprom Any access allowed Read only access allowed Any access not allowed Fuse bit Any access allowed Read only access allowed Any access not allowed BSB & SBV Any access allowed Read only access allowed Any access not allowed SSB Any access allowed Write level 2 allowed Read only access allowed Manufacturer info Read only access allowed Read only access allowed Read only access allowed Bootloader info Read only access allowed Read only access allowed Read only access allowed Erase block Allowed Not allowed Not allowed Full chip erase Allowed Allowed Allowed Blank Check Allowed Allowed Allowed 127 4289B–8051–12/03 Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. Checksum Error 128 When a checksum error is detected send ‘X’ followed with CR&LF. AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Flow Description Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an autobaud sequence ( see section ‘autobaud performance’). When the communication is initialized the protocol depends on the record type requested by the host. FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel the web site. Communication Initialization The host initializes the communication by sending a ’U’ character to help the bootloader to compute the baudrate (autobaud). Figure 51. Initialization Bootloader Host Autobaud Performances Init communication "U" If (not received "U") Else Communication opened "U" Performs autobaud Sends back U character The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51ID2 to establish the baud rate. Table show the autobaud capability. Table 95. Autobaud Performances Frequency (MHz) Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728 2400 OK OK OK OK OK OK OK OK OK 4800 OK - OK OK OK OK OK OK OK 9600 OK - OK OK OK OK OK OK OK 19200 OK - OK OK OK - - OK OK 38400 - - OK OK - OK OK OK 57600 - - - - OK - - - OK 115200 - - - - - - - - OK Frequency (MHz) Baudrate (kHz) 2400 8 10 OK 11.0592 OK OK 12 14.746 OK OK 16 20 OK 24 OK 26.6 OK OK 129 4289B–8051–12/03 Table 95. Autobaud Performances (Continued) Frequency (MHz) Baudrate (kHz) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728 4800 OK OK OK OK OK OK OK OK OK 9600 OK OK OK OK OK OK OK OK OK 19200 OK OK OK OK OK OK OK OK OK 38400 - - OK OK OK OK OK OK OK 57600 - - OK - OK OK OK OK OK 115200 - - OK - OK - - - - Command Data Stream Protocol All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. Figure 52. Command Flow Host Sends first character of the Frame Sends frame (made of 2 ASCII characters per byte) Echo analysis 130 Bootloader ":" If (not received ":") ":" Else Sends echo and start reception Gets frame, and sends back ec for each received byte AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Write / Program Commands This flow is common to the following frames: • Flash / Eeprom Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • Config Byte Programming Data Frame • Baud Rate Frame Description Figure 53. Write/Program Flow Bootloader Host Send Write Command Write Command Wait Write Command OR Wait Checksum Error Checksum error ’X’ & CR & LF Send Checksum error COMMAND ABORTED NO_SECURITY OR Wait Security Error ’P’ & CR & LF Send Security error COMMAND ABORTED Wait Programming Wait COMMAND_OK ’.’ & CR & LF Send COMMAND_OK COMMAND FINISHED Example Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 00 55 9A BOOTLOADER : 01 0010 00 55 9A . CR LF Programming Atmel function (write SSB to level 2) HOST : 02 0000 03 05 01 F5 BOOTLOADER : 02 0000 03 05 01 F5. CR LF Writing Frame (write BSB to 55h) HOST : 03 0000 03 06 00 55 9F BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF 131 4289B–8051–12/03 Blank Check Command Description Figure 54. Blank Check Flow Bootloader Host Blank Check Command Send Blank Check Command Wait Blank Check Command OR Checksum error ’X’ & CR & LF Wait Checksum Error Send Checksum error COMMAND ABORTED Flash blank OR ’.’ & CR & LF Wait COMMAND_OK Send COMMAND_OK COMMAND FINISHED address & CR & LF Wait Address not erased Send first Address not erased COMMAND FINISHED Example Blank Check ok HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF Blank Check ko at address xxxx HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF Blank Check with checksum error 132 HOST : 05 0000 04 0000 7FFF 01 70 BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Display Data Description Figure 55. Display Flow Host Bootloader Send Display Command Display Command Wait Display Command OR Wait Checksum Error Checksum error ’X’ & CR & LF Send Checksum Error COMMAND ABORTED RD_WR_SECURITY OR Wait Security Error ’L’ & CR & LF Send Security Error COMMAND ABORTED Read Data All data read Complet Frame Wait Display Data All data read COMMAND FINISHED Note: "Address = " "Reading value" CR & LF Send Display Data All data read COMMAND FINISHED The maximum size of block is 400h. To read more than 400h bytes, the Host must send a new command. 133 4289B–8051–12/03 Example Display data from address 0000h to 0020h Read Function HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF (16 data) BOOTLOADER 0010=-----data------ CR LF (16 data) BOOTLOADER 0020=data CR LF ( 1 data) This flow is similar for the following frames: • Reading Frame • EOF Frame/ Atmel Frame (only reading Atmel Frame) Description Figure 56. Read Flow Bootloader Host Send Read Command Read Command Wait Read Command OR Wait Checksum Error Checksum error ’X’ & CR & LF Send Checksum error COMMAND ABORTED RD_WR_SECURITY OR Wait Security Error ’L’ & CR & LF Send Security error COMMAND ABORTED Read Value Wait Value of Data ’value’ & ’.’ & CR & LF Send Data Read COMMAND FINISHED 134 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Example Read function (read SBV) HOST : 02 0000 05 07 02 F0 BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF Atmel Read function (read Bootloader version) HOST : 02 0000 01 02 00 FB BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF 135 4289B–8051–12/03 ISP Commands Summary Table 96. ISP Commands Summary Command Command Name data[0] data[1] Command Effect Program Nb Data Byte. 00h Bootloader will accept up to 128 (80h) data bytes. The data bytes should be 128 byte page flash boundary. Program Data 00h Erase block0 (0000h-1FFFh) 20h Erase block1 (2000h-3FFFh) 40h Erase block2 (4000h-7FFFh) 80h Erase block3 (8000h- BFFFh) C0h Erase block4 (C000h- FFFFh) 03h 00h Hardware Reset 04h 00h Erase SBV & BSB 00h Program SSB level 1 01h Program SSB level 2 00h Program BSB (value to write in data[2]) 01h Program SBV (value to write in data[2]) - Full Chip Erase (This command needs about 6 sec to be executed) 02h Program Osc fuse (value to write in data[2]) 04h Program BLJB fuse (value to write in data[2]) 08h Program X2 fuse (value to write in data[2]) 01h 05h 03h Write Function 06h 07h 0Ah Data[0:1] = start address Data [2:3] = end address 04h Display Function Display Data Blank Check Data[4] = 00h -> Display data Data[4] = 01h -> Blank check Display EEPROM data Data[4] = 02h -> Display EEPROMk 136 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 96. ISP Commands Summary (Continued) Command Command Name data[0] data[1] Command Effect 00h Manufacturer Id 01h Device Id #1 02h Device Id #2 03h Device Id #3 00h Read SSB 01h Read BSB 02h Read SBV 06h Read Extra Byte 00h Read Hardware Byte 00h Read Device Boot ID1 01h Read Device Boot ID2 00h Read Bootloader Version 00h 05h Read Function 07h 0Bh 0Eh 0Fh Program Nb EEProm Data Byte. 07h Program EEPROM data Bootloader will accept up to 128 (80h) data bytes. 137 4289B–8051–12/03 API Call Description Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h. Results are returned in the registers. When several bytes have to be programmed, it is highly recommended to use the Atmel API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 bytes in a single command. All routines for software access are provided in the C Flash driver available on Atmel web site. The API calls description and arguments are shown in Table Table 97. API Call Summary Command R1 A DPTR0 DPTR1 Returned Value Command Effect READ MANUF ID 00h XXh 0000h XXh ACC = Manufacturer Id Read Manufacturer identifier READ DEVICE ID1 00h XXh 0001h XXh ACC = Device Id 1 Read Device identifier 1 READ DEVICE ID2 00h XXh 0002h XXh ACC = Device Id 2 Read Device identifier 2 READ DEVICE ID3 00h XXh 0003h XXh ACC = Device Id 3 Read Device identifier 3 ERASE BLOCK 01h XXh DPH = 00h Erase block 0 DPH = 20h Erase block 1 DPH = 40h Erase block 2 Address of byte to program 00h ACC = DPH Program one Data Byte in user Flash Erase Software boot vector and boot status byte. (SBV = FCh and BSB = FFh) XXh DPH = 00h Set SSB level 1 DPL = 00h DPH = 00h Set SSB level 2 DPL = 01h PROGRAM SSB 05h XXh 00h ACC = SSB value DPH = 00h Set SSB level 0 DPL = 10h DPH = 00h Set SSB level 1 DPL = 11h 138 PROGRAM BSB 06h New BSB value 0000h XXh none Program boot status byte PROGRAM SBV 06h New SBV value 0001h XXh none Program software boot vector READ SSB 07h XXh 0000h XXh ACC = SSB Read Software Security Byte READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Status Byte READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Table 97. API Call Summary (Continued) Command R1 A DPTR0 DPTR1 Returned Value Command Effect PROGRAM DATA PAGE 09h Number of byte to program Address of the first byte to program in the Flash memory Address in XRAM of the first data to program ACC = 0: DONE Remark: number of bytes to program is limited such as the Flash write remains in a single 128 bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or, 80h. PROGRAM X2 FUSE 0Ah 0008h XXh none Program X2 fuse bit with ACC PROGRAM BLJB FUSE 0Ah 0004h XXh none Program BLJB fuse bit with ACC READ HSB 0Bh XXh XXXXh XXh ACC = HSB Read Hardware Byte READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC = ID1 Read boot ID1 READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC = ID2 Read boot ID2 READ BOOT VERSION 0Fh XXh XXXXh XXh ACC = Boot_Version Read bootloader version Fuse value 00h or 01h Fuse value 00h or 01h Program up to 128 bytes in user Flash. 139 4289B–8051–12/03 Electrical Characteristics Absolute Maximum Ratings Note: I = industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS (standard voltage) .........-0.5V to + 6.5V Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation ........................................................... 1 W(2) Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package. DC Parameters TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) Symbol Parameter Min VIL Input Low Voltage V IH Input High Voltage except RST, XTAL1 VIH1 Input High Voltage RST, XTAL1 Typ Max Unit Test Conditions -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 V IOL = 100 µA(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) 0.45 V IOL = 0.8 mA(4) 0.3 V IOL = 200 µA(4) 0.45 V IOL = 3.2 mA(4) 1.0 V IOL = 7.0 mA(4) 0.45 V IOL = 1.6 mA(4) VCC = 4.5V to 5.5V VOL Output Low Voltage, ports 1, 2, 3, 4 (6) VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V VOL1 Output Low Voltage, port 0, ALE, PSEN (6) VCC = 2.7V to 5.5V VCC = 5V ± 10% VOH Output High Voltage, ports 1, 2, 3, 4 VCC - 0.3 V IOH = -10 µA VCC - 0.7 V IOH = -30 µA VCC - 1.5 V IOH = -60 µA 0.9 VCC V IOH = -10 µA VCC = 2.7V to 5.5V 140 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued) Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5V ± 10% VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3 V IOH = -200 µA VCC - 0.7 V IOH = -3.2 mA VCC - 1.5 V IOH = -7.0 mA 0.9 VCC V IOH = -10 µA VCC = 2.7V to 5.5V RRST RST Pull-down Resistor 50 200(5) 250 kΩ IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 µA VIN = 0.45V ILI Input Leakage Current ±10 µA 0.45V < VIN < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 -650 µA VIN = 2.0V CIO Capacitance of I/O Buffer 10 pF FC = 3 MHz TA = 25°C IPD Power-down Current 150 µA 2.7 < VCC < 5.5V(3) 75 ICCOP Power Supply Current on normal mode 0.4 x Frequency (MHz) + 5 mA VCC = 5.5V(1) ICCIDLE Power Supply Current on idle mode 0.3 x Frequency (MHz) + 5 mA VCC = 5.5V(2) Power Supply Current on flash or EEdata write 0.8 x Frequency (MHz) + 15 mA VCC = 5.5V 10 ms 2.7 < VCC < 5.5V ICCWRITE tWRITE Notes: Flash or EEdata programming time 7 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 60), VIL = VSS + 0.5V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V CC. ICC would be slightly higher if a crystal oscillator used (see Figure 57). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = V SS (see Figure 58). 3. Power-down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = V CC; XTAL2 NC.; RST = VSS (see Figure 59). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 141 4289B–8051–12/03 Figure 57. ICC Test Condition, Active Mode VCC ICC VCC VCC P0 VCC RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 58. ICC Test Condition, Idle Mode VCC ICC V CC VCC P0 RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 59. ICC Test Condition, Power-down Mode VCC ICC VCC VCC P0 RST (NC) EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 60. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 142 0.7VCC 0.2VCC-0.1 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. (Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.) Table 98 Table 101, and Table 104 give the description of each AC symbols. Table 99, Table 100, Table 102 and Table 105 gives the range for each AC parameter. Table 99, Table 100 and Table 106 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value in the correponding column (-M or -L) and use this value in the formula. Example: TLLIU for -M and 20 MHz, Standard clock. x = 35 ns T 50 ns TCCIV = 4T - x = 165 ns External Program Memory Characteristics Table 98. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float 143 4289B–8051–12/03 Table 99. AC Parameters for a Fix Clock Symbol -M -L Min Max Min Units Max T 25 25 ns TLHLL 35 35 ns TAVLL 5 5 ns TLLAX 5 5 ns TLLIV n 65 65 ns TLLPL 5 5 ns TPLPH 50 50 ns TPLIV 30 TPXIX 30 0 ns 0 ns TPXIZ 10 10 ns TAVIV 80 80 ns TPLAZ 10 10 ns Table 100. AC Parameters for a Variable Clock 144 Symbol Type Standard Clock X2 Clock X parameter for -M range X parameter for -L range Units TLHLL Min 2T-x T-x 15 15 ns TAVLL Min T-x 0.5 T - x 20 20 ns TLLAX Min T-x 0.5 T - x 20 20 ns TLLIV Max 4T-x 2T-x 35 35 ns TLLPL Min T-x 0.5 T - x 15 15 ns TPLPH Min 3T-x 1.5 T - x 25 25 ns TPLIV Max 3T-x 1.5 T - x 45 45 ns TPXIX Min x x 0 0 ns TPXIZ Max T-x 0.5 T - x 15 15 ns TAVIV Max 5T-x 2.5 T - x 45 45 ns TPLAZ Max x x 10 10 ns AT89C51ID2 4289B–8051–12/03 AT89C51ID2 External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN TPLIV TPLAZ A0-A7 TPXAV TPXIZ TPXIX INSTR IN A0-A7 INSTR IN TAVIV PORT 2 External Data Memory Characteristics ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 Table 101. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data Set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high 145 4289B–8051–12/03 Table 102. AC Parameters for a Fix Clock -M -L Symbol Min Max TRLRH 125 125 ns TWLWH 125 125 ns TRLDV Min Max 95 TRHDX Units 95 0 ns 0 ns TRHDZ 25 25 ns TLLDV 155 155 ns TAVDV 160 160 ns 105 ns TLLWL 45 TAVWL 70 70 ns TQVWX 5 5 ns TQVWH 155 155 ns TWHQX 10 10 ns TRLAZ 0 0 ns TWHLH 5 105 45 45 5 45 ns Table 103. AC Parameters for a Variable Clock 146 Symbol Type Standard Clock X2 Clock X parameter for -M range X parameter for -L range Units TRLRH Min 6T-x 3T-x 25 25 ns TWLWH Min 6T-x 3T-x 25 25 ns TRLDV Max 5T-x 2.5 T - x 30 30 ns TRHDX Min x x 0 0 ns TRHDZ Max 2T-x T-x 25 25 ns TLLDV Max 8T-x 4T -x 45 45 ns TAVDV Max 9T-x 4.5 T - x 65 65 ns TLLWL Min 3T-x 1.5 T - x 30 30 ns TLLWL Max 3T+x 1.5 T + x 30 30 ns TAVWL Min 4T-x 2T-x 30 30 ns TQVWX Min T-x 0.5 T - x 20 20 ns TQVWH Min 7T-x 3.5 T - x 20 20 ns TWHQX Min T-x 0.5 T - x 15 15 ns TRLAZ Max x x 0 0 ns TWHLH Min T-x 0.5 T - x 20 20 ns TWHLH Max T+x 0.5 T + x 20 20 ns AT89C51ID2 4289B–8051–12/03 AT89C51ID2 External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TQVWX TLLAX PORT 0 TWHQX TQVWH A0-A7 DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TRHDX A0-A7 DATA IN TRLAZ TAVWL PORT 2 ADDRESS OR SFR-P2 Serial Port Timing - Shift Register Mode ADDRESS A8-A15 OR SFR P2 Table 104. Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid 147 4289B–8051–12/03 Table 105. AC Parameters for a Fix Clock -M -L Symbol Min Max TXLXL 300 300 ns TQVHX 200 200 ns TXHQX 30 30 ns TXHDX 0 0 ns TXHDV Min Max 117 Units 117 ns Table 106. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X Parameter For -M Range X Parameter For -L Range TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 ns TXHQX Min 2T-x T-x 20 20 ns TXHDX Min x x 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 ns 2 3 Units ns Shift Register Timing Waveforms INSTRUCTION 0 1 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA 0 1 2 3 4 5 6 TXHDX TXHDV VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI External Clock Drive Waveforms 7 VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCHCX TCLCH TCLCX TCLCL 148 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 AC Testing Input/Output Waveforms VCC -0.5V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms FLOAT VOH - 0.1V VOL + 0.1V VLOAD VLOAD + 0.1V VLOAD - 0.1V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level occurs. IOL/IOH ≥ ± 20 mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. 149 4289B–8051–12/03 Figure 61. Internal Clock Signals INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT P2 DATA SAMPLED FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR P0 PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) DATA OUT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION PORT OPERATION OLD DATA NEW DATA MOV PORT SRC P0 PINS SAMPLED P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK P1, P2, P3 PINS SAMPLED RXD SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED TXD (MODE 0) This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 150 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Ordering Information Table 107. Possible Order Entries Part Number Supply Voltage Temperature Range Package AT89C51ID2-SLSIM 2.7V-5.5V AT89C51ID2-RLTIM Change Log for 4289A 09/03 to 4289B - 12/03 Packing Product Marking PLCC44 Stick AT89C51ID2-IM VQFP44 Tray AT89C51ID2-IM Industrial 1. Improvement of explanations throughout the document. 151 4289B–8051–12/03 Packaging Information PLCC44 152 AT89C51ID2 4289B–8051–12/03 AT89C51ID2 VQFP44 153 4289B–8051–12/03 Table of Contents Features................................................................................................. 1 Description ............................................................................................ 1 Block Diagram....................................................................................... 3 SFR Mapping......................................................................................... 4 Pin Configurations.............................................................................. 10 Oscillators ........................................................................................... 14 Overview............................................................................................................. Registers............................................................................................................. Functional Block Diagram................................................................................... ............................................................................................................................ Operating Modes ................................................................................................ Design Considerations........................................................................................ Timer 0: Clock Inputs.......................................................................................... 14 14 17 17 17 19 20 Enhanced Features............................................................................. 21 X2 Feature .......................................................................................................... 21 Dual Data Pointer Register DPTR...................................................... 25 Expanded RAM (XRAM) ..................................................................... 28 Registers............................................................................................................. 30 Reset .................................................................................................... 31 Introduction ......................................................................................................... 31 Reset Input ......................................................................................................... 31 Reset Output....................................................................................................... 32 Power Monitor..................................................................................... 33 Description.......................................................................................................... 33 Timer 2 ................................................................................................. 35 Auto-Reload Mode.............................................................................................. 35 Programmable Clock-Output .............................................................................. 36 Registers............................................................................................................. 38 Programmable Counter Array PCA................................................... 40 PCA Capture Mode............................................................................................. 48 16-bit Software Timer/ Compare Mode............................................................... 48 High Speed Output Mode ................................................................................... 49 i AT89C51ID2 4289B–8051–12/03 AT89C51ID2 Pulse Width Modulator Mode.............................................................................. 50 PCA Watchdog Timer ......................................................................................... 51 Serial I/O Port ...................................................................................... 52 Framing Error Detection ..................................................................................... Automatic Address Recognition.......................................................................... Registers............................................................................................................. Baud Rate Selection for UART for Mode 1 and 3............................................... UART Registers.................................................................................................. 52 53 55 55 58 Interrupt System ................................................................................. 63 Registers............................................................................................................. 64 Interrupt Sources and Vector Addresses............................................................ 71 Power Management ............................................................................ 72 Introduction ......................................................................................................... Idle Mode ............................................................................................................ Power-Down Mode ............................................................................................. Registers............................................................................................................. 72 72 72 75 Keyboard Interface ............................................................................. 76 Registers............................................................................................................. 77 2-wire Interface (TWI) ......................................................................... 80 Description.......................................................................................................... 82 Notes .................................................................................................................. 85 Registers............................................................................................................. 95 Serial Port Interface (SPI)................................................................... 98 Features.............................................................................................................. 98 Signal Description............................................................................................... 98 Functional Description ...................................................................................... 100 Hardware Watchdog Timer .............................................................. 107 Using the WDT ................................................................................................. 107 WDT During Power Down and Idle................................................................... 108 ONCE(TM) Mode (ON Chip Emulation) ........................................... 109 Power-off Flag................................................................................... 110 EEPROM Data Memory..................................................................... 111 Write Data......................................................................................................... 111 Read Data......................................................................................................... 113 Registers........................................................................................................... 114 ii 4289B–8051–12/03 Reduced EMI Mode........................................................................... 115 Flash Memory.................................................................................... 116 Features............................................................................................................ Flash Programming and Erasure ...................................................................... Flash Registers and Memory Map.................................................................... Flash Memory Status........................................................................................ Memory Organization ....................................................................................... Bootloader Architecture .................................................................................... ISP Protocol Description................................................................................... Functional Description ...................................................................................... Flow Description ............................................................................................... API Call Description.......................................................................................... 116 116 117 120 120 121 126 127 129 138 Electrical Characteristics ................................................................. 140 Absolute Maximum Ratings .............................................................................. 140 DC Parameters ................................................................................................. 140 AC Parameters ................................................................................................. 143 Ordering Information........................................................................ 151 Change Log for 4289A - 09/03 to 4289B - 12/03.............................................. 151 Packaging Information ..................................................................... 152 PLCC44 ............................................................................................................ 152 VQFP44 ............................................................................................................ 153 Table of Contents ............................................................................. 154 iii AT89C51ID2 4289B–8051–12/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4289B–8051–12/03