CY7C1069BV33 16-Mbit (2M x 8) Static RAM Features Functional Description • High speed The CY7C1069BV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE LOW) and Write Enable (WE) inputs LOW. — tAA = 10 ns • Low active power — 990 mW (max.) Reading from the device is accomplished by enabling the chip (CE LOW) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Available in Pb-free and non Pb-free 54-pin TSOP II package The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW and WE LOW). The CY7C1069BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. Pin Configurations[1, 2] Logic Block Diagram 54-pin TSOP II (Top View) 2M x 8 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0–I/O7 WE COLUMN DECODER OE CE NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE VCC WE DNU/VCC A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS DNU/VSS A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC VCC NC Notes: 1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application. 2. NC - No Connect Pins are not connected to the die. Cypress Semiconductor Corporation Document #: 38-05694 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 CY7C1069BV33 Selection Guide –10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current –12 Unit 10 12 ns Commercial 275 260 mA Industrial 275 260 Commercial/Industrial 50 50 mA Maximum Ratings DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Current into Outputs (LOW)......................................... 20 mA Storage Temperature ................................. –65°C to +150°C Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Commercial Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V Ambient Temperature VCC 0°C to +70°C 3.3V ± 0.3V Industrial –40°C to +85°C DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range –10 Parameter Description Test Conditions Min. 2.4 –12 Max. Min. Max. Unit 0.4 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 2.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input LOW Voltage[3] –0.3 0.8 –0.3 0.8 V 0.4 IIX Input Leakage Current IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 GND < VI < VCC –1 +1 –1 +1 µA –1 +1 –1 +1 µA Comm’l 275 260 mA Ind’l 275 260 mA 70 70 mA 50 50 mA Comm’l/ Ind’l Capacitance[4] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 6 pF 8 pF Thermal Resistance[4] Parameter ΘJA ΘJC Description Test Conditions Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring Thermal Resistance (Junction to Case) thermal impedance, per EIA/JESD51. TSOP-II Unit 49.95 °C/W 3.34 °C/W Notes: 3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05694 Rev. *B Page 2 of 7 CY7C1069BV33 AC Test Loads and Waveforms[5] R1 317 Ω 50Ω 3.3V VTH = 1.5V OUTPUT Z0 = 50Ω OUTPUT 30 pF* *Capacitive Load consists of all components of the test environment (a) *Including jig and scope All input pulses 3.3V GND Rise time > 1V/ns 90% 10% (b) 90% 10% Fall time: > 1V/ns (c) AC Switching Characteristics Over the Operating Range [6] –10 Parameter Description R2 351Ω 5 pF* Min. –12 Max. Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[7] 1 1 ms tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns Low-Z[8] tLZOE OE LOW to tHZOE OE HIGH to High-Z[8] tLZCE CE LOW to Low-Z[8] CE to tPU CE to Power-up[9] Write CE to 3 12 3 1 3 5 Power-down[9] ns 6 3 0 ns ns 6 0 10 ns ns 1 5 High-Z[8] tHZCE tPD 10 ns ns 12 ns Cycle[10, 11] tWC Write Cycle Time 10 12 ns tSCE CE to Write End 7 8 ns tAW Address Set-up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-up to Write End 5.5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low-Z[8] 3 3 ns tHZWE [8] WE LOW to High-Z 5 6 ns Notes: 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05694 Rev. *B Page 3 of 7 CY7C1069BV33 Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tASCE OE tHZOE tDOE tHZSCE tLZOE DATA OUT HIGH IMPEDANCE tLZSCE VCC SUPPLY CURRENT HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 12. Device is continuously selected. CE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05694 Rev. *B Page 4 of 7 CY7C1069BV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS tSA CE tSCE tAW tHA tPWE WE tBW tSD tHD DATAI/O Write Cycle No. 2 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE I/O0–I/O7 Mode Power H X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05694 Rev. *B Page 5 of 7 CY7C1069BV33 Ordering Information Speed (ns) 10 12 Ordering Code CY7C1069BV33-10ZC CY7C1069BV33-10ZXC CY7C1069BV33-10ZI CY7C1069BV33-10ZXI CY7C1069BV33-12ZC CY7C1069BV33-12ZXC CY7C1069BV33-12ZI CY7C1069BV33-12ZXI Package Diagram 51-85160 Package Type 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) Operating Range Commercial Industrial Commercial Industrial Package Diagram 54-pin TSOP II (51-85160) 51-85160-** All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05694 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1069BV33 Document History Page Document Title: CY7C1069BV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05694 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 283950 See ECN RKF New data sheet *A 314014 See ECN RKF Final data sheet *B 492137 See ECN NXR Removed 8 ns speed bin Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Document #: 38-05694 Rev. *B Page 7 of 7