AD ADA4891-2ARMZ-R7 Low cost cmos, high speed, rail-to-rail amplifier Datasheet

Low Cost CMOS, High Speed,
Rail-to-Rail Amplifiers
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
NC 1
8
NC
–IN 2
7
+VS
+IN 3
6
OUT
–VS 4
5
NC
NC = NO CONNECT
Figure 1. 8-Lead SOIC_N (R-8)
ADA4891-1
OUT 1
GENERAL DESCRIPTION
The ADA4891-1 (single), ADA4891-2 (dual), ADA4891-3 (triple),
and ADA4891-4 (quad) are CMOS, high speed amplifiers that
offer high performance at a low cost. The amplifiers feature true
single-supply capability, with an input voltage range that extends
300 mV below the negative rail.
In spite of their low cost, the ADA4891 family provides high
performance and versatility. The rail-to-rail output stage enables
the output to swing to within 50 mV of each rail, enabling maximum dynamic range.
The ADA4891 family of amplifiers is ideal for imaging applications, such as consumer video, CCD buffers, and contact image
sensor and buffers. Low distortion and fast settling time also
make them ideal for active filter applications.
The ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4 are available in a wide variety of packages. The ADA4891-1 is available
in 8-lead SOIC and 5-lead SOT-23 packages. The ADA4891-2
is available in 8-lead SOIC and 8-lead MSOP packages. The
ADA4891-3 and ADA4891-4 are available in 14-lead SOIC and
14-lead TSSOP packages. The amplifiers are specified to operate
over the extended temperature range of −40°C to +125°C.
5
+VS
4
–IN
+IN 3
08054-001
–VS 2
Figure 2. 5-Lead SOT-23 (RJ-5)
APPLICATIONS
ADA4891-2
1
OUT1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
NC = NO CONNECT
08054-027
Imaging
Consumer video
Active filters
Coaxial cable drivers
Clock buffers
Photodiode preamp
Contact image sensor and buffers
08054-026
ADA4891-1
Figure 3. 8-Lead SOIC_N (R-8) and 8-Lead MSOP (RM-8)
ADA4891-3
PD1 1
14
OUT2
PD2 2
13
–IN2
PD3 3
12
+IN2
+VS 4
11
–VS
+IN1 5
10
+IN3
–IN1 6
9
–IN3
OUT1 7
8
OUT3
08054-073
High speed and fast settling
−3 dB bandwidth: 220 MHz (G = +1)
Slew rate: 170 V/μs
Settling time to 0.1%: 28 ns
Video specifications (G = +2, RL = 150 Ω)
0.1 dB gain flatness: 25 MHz
Differential gain error: 0.05%
Differential phase error: 0.25°
Single-supply operation
Wide supply range: 2.7 V to 5.5 V
Output swings to within 50 mV of supply rails
Low distortion: 79 dBc SFDR at 1 MHz
Linear output current: 125 mA at −40 dBc
Low power: 4.4 mA per amplifier
CONNECTION DIAGRAMS
Figure 4. 14-Lead SOIC_N (R-14) and 14-Lead TSSOP (RU-14)
ADA4891-4
OUT4
OUT1 1
14
–IN1 2
13
–IN4
+IN1 3
12
+IN4
+VS 4
11
–VS
+IN2 5
10
+IN3
–IN2 6
9
–IN3
OUT2 7
8
OUT3
08054-074
FEATURES
Figure 5. 14-Lead SOIC_N (R-14) and 14-Lead TSSOP (RU-14)
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Values ............................................................... 15
Applications ....................................................................................... 1
Effect of RF on 0.1 dB Gain Flatness ........................................ 16
General Description ......................................................................... 1
Driving Capacitive Loads .......................................................... 17
Connection Diagrams ...................................................................... 1
Terminating Unused Amplifiers .............................................. 18
Revision History ............................................................................... 2
Disable Feature (ADA4891-3 Only) ........................................ 18
Specifications..................................................................................... 3
Single-Supply Operation ........................................................... 18
5 V Operation ............................................................................... 3
Video Reconstruction Filter ...................................................... 19
3 V Operation ............................................................................... 4
Multiplexer .................................................................................. 19
Absolute Maximum Ratings............................................................ 6
Layout, Grounding, and Bypassing .............................................. 20
Maximum Power Dissipation ..................................................... 6
Power Supply Bypassing ............................................................ 20
ESD Caution .................................................................................. 6
Grounding ................................................................................... 20
Typical Performance Characteristics ............................................. 7
Input and Output Capacitance ................................................. 20
Applications Information .............................................................. 15
Input-to-Output Coupling ........................................................ 20
Using the ADA4891 ................................................................... 15
Leakage Currents ........................................................................ 20
Wideband, Noninverting Gain Operation .............................. 15
Outline Dimensions ....................................................................... 21
Wideband, Inverting Gain Operation ..................................... 15
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/10—Rev. A to Rev. B
Added ADA4891-3 and ADA4891-4 ............................... Universal
Added 14-Lead SOIC and 14-Lead TSSOP Packages .... Universal
Deleted Figure 4; Renumbered Figures Sequentially ................... 1
Changes to Features Section and General Description Section . 1
Added Figure 4 and Figure 5 ........................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Maximum Power Dissipation Section
and Figure 6 ....................................................................................... 6
Added Table 4; Renumbered Tables Sequentially ........................ 6
Deleted Figure 11 .............................................................................. 6
Changes to Typical Performance Characteristics Section ........... 7
Deleted Figure 12 .............................................................................. 7
Changes to Wideband, Noninverting Gain Operation Section,
Wideband, Inverting Gain Operation Section, and Table 5 ..... 15
Added Table 6.................................................................................. 16
Changes to Figure 52...................................................................... 16
Added Figure 53 ............................................................................. 16
Changed Layout of Driving Capacitive Loads Section.............. 17
Added Disable Feature (ADA4891-3 Only) Section
and Single-Supply Operation Section .......................................... 18
Added Multiplexer Section ........................................................... 19
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
6/10—Rev. 0 to Rev. A
Changes to Figure 26.........................................................................9
Changes to Figure 33 and Figure 34............................................. 10
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
2/10—Revision 0: Initial Version
Rev. B | Page 2 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
SPECIFICATIONS
5 V OPERATION
TA = 25°C, VS = 5 V, RL = 1 kΩ to 2.5 V, unless otherwise noted. All specifications are for the ADA4891-1, ADA4891-2, ADA4891-3, and
ADA4891-4, unless otherwise noted. For the ADA4891-1 and ADA4891-2, RF = 604 Ω; for the ADA4891-3 and ADA4891-4, RF = 453 Ω,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth
Bandwidth for 0.1 dB Gain Flatness
Slew Rate, tR/tF
−3 dB Large-Signal Frequency Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
All-Hostile Crosstalk
DC PERFORMANCE
Input Offset Voltage
Test Conditions/Comments
ADA4891-1/ADA4891-2, G = +1, VO = 0.2 V p-p
ADA4891-3/ADA4891-4, G = +1, VO = 0.2 V p-p
ADA4891-1/ADA4891-2, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V
ADA4891-3/ADA4891-4, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V
ADA4891-1/ADA4891-2, G = +2, VO = 2 V p-p,
RL = 150 Ω to 2.5 V, RF = 604 Ω
ADA4891-3/ADA4891-4, G = +2, VO = 2 V p-p,
RL = 150 Ω to 2.5 V, RF = 374 Ω
G = +2, VO = 2 V step, 10% to 90%
G = +2, VO = 2 V p-p, RL = 150 Ω
G = +2, VO = 2 V step
fC = 1 MHz, VO = 2 V p-p, G = +1
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
f = 5 MHz, G = +2, VO = 2 V p-p
Min
TMIN to TMAX
Offset Drift
Input Bias Current
Open-Loop Gain
RL = 1 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short-Circuit Current
Sourcing
Sinking
POWER-DOWN PINS (PD1, PD2, PD3)
Threshold Voltage, VTH
Bias Current
−50
77
Typ
Max
Unit
240
220
90
MHz
MHz
MHz
96
MHz
25
MHz
25
MHz
170/210
40
28
V/μs
MHz
ns
−79/−93
−75/−91
9
0.05
0.25
−80
dBc
dBc
nV/√Hz
%
Degrees
dB
±2.5
±3.1
6
+2
83
71
±10
+50
mV
mV
μV/°C
pA
dB
dB
GΩ
pF
V
VCM = 0 V to 3.0 V
5
3.2
−VS − 0.3 to
+VS − 0.8
88
RL = 1 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
1% THD with 1 MHz, VO = 2 V p-p
0.01 to 4.98
0.08 to 4.90
125
V
V
mA
205
307
mA
mA
2.4
65
−22
V
nA
μA
dB
ADA4891-3 only
Part enabled
Part powered down
Rev. B | Page 3 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Parameter
Turn-On Time
Turn-Off Time
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Supply Current When Powered Down
Power Supply Rejection Ratio (PSRR)
Positive PSRR
Negative PSRR
OPERATING TEMPERATURE RANGE
Test Conditions/Comments
Part enabled, output rises to 90% of final value
Part powered down, output falls to 10% of final
value
Min
Typ
166
49
2.7
ADA4891-3 only
4.4
0.8
+VS = 5 V to 5.25 V, −VS = 0 V
+VS = 5 V, −VS = −0.25 V to 0 V
65
63
−40
Max
Unit
ns
ns
5.5
V
mA
mA
+125
dB
dB
°C
3 V OPERATION
TA = 25°C, VS = 3 V, RL = 1 kΩ to 1.5 V, unless otherwise noted. All specifications are for the ADA4891-1, ADA4891-2, ADA4891-3, and
ADA4891-4, unless otherwise noted. For the ADA4891-1 and ADA4891-2, RF = 604 Ω; for the ADA4891-3 and ADA4891-4, RF = 453 Ω,
unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth
Bandwidth for 0.1 dB Gain Flatness
Slew Rate, tR/tF
−3 dB Large-Signal Frequency Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
All-Hostile Crosstalk
DC PERFORMANCE
Input Offset Voltage
Test Conditions/Comments
ADA4891-1/ADA4891-2, G = +1, VO = 0.2 V p-p
ADA4891-3/ADA4891-4, G = +1, VO = 0.2 V p-p
ADA4891-1/ADA4891-2, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 1.5 V
ADA4891-3/ADA4891-4, G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 1.5 V
ADA4891-1/ADA4891-2, G = +2, VO = 2 V p-p,
RL = 150 Ω to 1.5 V, RF = 604 Ω
ADA4891-3/ADA4891-4, G = +2, VO = 2 V p-p,
RL = 150 Ω to 1.5 V, RF = 374 Ω
G = +2, VO = 2 V step, 10% to 90%
G = +2, VO = 2 V p-p, RL = 150 Ω
G = +2, VO = 2 V step
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V
G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V
f = 5 MHz, G = +2
Min
TMIN to TMAX
Offset Drift
Input Bias Current
Open-Loop Gain
RL = 1 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
−50
72
Typ
Rev. B | Page 4 of 24
Unit
190
175
75
MHz
MHz
MHz
80
MHz
18
MHz
18
MHz
140/230
40
30
V/μs
MHz
ns
−70/−89
9
0.23
0.77
−80
dBc
nV/√Hz
%
Degrees
dB
±2.5
±3.1
6
+2
76
65
5
3.2
−VS − 0.3 to
+VS − 0.8
87
VCM = 0 V to 1.5 V
Max
±10
+50
mV
mV
μV/°C
pA
dB
dB
GΩ
pF
V
dB
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short-Circuit Current
Sourcing
Sinking
POWER-DOWN PINS (PD1, PD2, PD3)
Threshold Voltage, VTH
Bias Current
Turn-On Time
Turn-Off Time
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Supply Current When Powered Down
Power Supply Rejection Ratio (PSRR)
Positive PSRR
Negative PSRR
OPERATING TEMPERATURE RANGE
Test Conditions/Comments
Min
RL = 1 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
1% THD with 1 MHz, VO = 2 V p-p
Typ
Max
Unit
0.01 to 2.98
0.07 to 2.87
37
V
V
mA
80
163
mA
mA
1.3
48
−13
185
58
V
nA
μA
ns
ns
ADA4891-3 only
Part enabled
Part powered down
Part enabled, output rises to 90% of final value
Part powered down, output falls to 10% of final
value
2.7
5.5
ADA4891-3 only
3.5
0.73
+VS = 3 V to 3.15 V, −VS = 0 V
+VS = 3 V, −VS = −0.15 V to 0 V
76
72
−40
Rev. B | Page 5 of 24
+125
V
mA
mA
dB
dB
°C
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
ABSOLUTE MAXIMUM RATINGS
To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 6. These curves
are derived by setting TJ = 150°C in Equation 1. Figure 6 shows
the maximum safe power dissipation in the package vs. the
ambient temperature on a JEDEC standard 4-layer board.
Table 3.
Rating
6V
−VS − 0.5 V to +VS
±VS
−65°C to +125°C
−40°C to +125°C
300°C
2.0
TJ = 150°C
14-LEAD TSSOP
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1.5
1.0
The still-air thermal properties of the package (θJA), the ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
8-LEAD MSOP
5-LEAD SOT-23
0.5
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4 is limited
by the associated rise in junction temperature. The maximum
safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately 150°C. Temporarily exceeding this limit can
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.
8-LEAD SOIC_N
14-LEAD SOIC_N
0
–55
–35
(1)
25
45
65
85
105
125
Figure 6. Maximum Power Dissipation vs. Ambient Temperature
Table 4 lists the thermal resistance (θJA) for each ADA4891-1/
ADA4891-2/ADA4891-3/ADA4891-4 package.
Table 4.
Package Type
5-Lead SOT-23
8-Lead SOIC_N
8-Lead MSOP
14-Lead SOIC_N
14-Lead TSSOP
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. It can be calculated by
PD = (VT × IS) + (VS − VOUT) × (VOUT/RL)
5
AMBIENT TEMPERATURE (°C)
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
–15
08054-002
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
(2)
where:
VT is the total supply rail.
IS is the quiescent current.
VS is the positive supply rail.
VOUT is the output of the amplifier.
RL is the output load of the amplifier.
Rev. B | Page 6 of 24
θJA
146
115
133
162
108
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TYPICAL PERFORMANCE CHARACTERISTICS
5
3
4
2
1
0
G = +1
–2
–3
–4
G = +10
G = +5
–5
–6
–7
VS = 5V
–8 VOUT = 200mV p-p
RF = 604Ω
–9
RL = 1kΩ
–10
0.1
1
10
6
100
1k
VS = 2.7V
–4
G = +5
–5
–6
VS = 5V
VOUT = 200mV p-p
RF = 453Ω
RL = 1kΩ
–7
–8
1
CLOSED-LOOP GAIN (dB)
0
VS = 5V
–3
–6
–9
100
1k
FREQUENCY (MHz)
–6
–9
4
4
+25°C
CLOSED-LOOP GAIN (dB)
+85°C
0°C
1
–40°C
0
–1
–2
–4
0.1
VS = 5V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
1
10
FREQUENCY (MHz)
100
1k
1
10
FREQUENCY (MHz)
100
1k
Figure 9. Small-Signal Frequency Response vs. Temperature, VS = 5 V,
ADA4891-1/ADA4891-2
+125°C
+85°C
+25°C
0°C
–40°C
3
2
1
0
–1
–2
–3
–4
08054-030
–3
G = +1
VOUT = 200mV p-p
RL = 1kΩ
Figure 11. Small-Signal Frequency Response vs. Supply Voltage,
ADA4891-3/ADA4891-4
5
+125°C
VS = 3V
–3
5
2
1k
VS = 5V
–15
0.1
Figure 8. Small-Signal Frequency Response vs. Supply Voltage,
ADA4891-1/ADA4891-2
3
100
0
–12
G = +1
VOUT = 200mV p-p
RL = 1kΩ
10
10
FREQUENCY (MHz)
VS = 2.7V
3
1
G = +10
6
VS = 3V
08054-029
CLOSED-LOOP GAIN (dB)
–3
Figure 10. Small-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-3/ADA4891-4
3
CLOSED-LOOP GAIN (dB)
–2
–10
0.1
Figure 7. Small-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-1/ADA4891-2
–15
0.1
0
–1
–9
FREQUENCY (MHz)
–12
G = +1
1
08054-077
G = –1
OR +2
G = –1 OR +2
2
VS = 5V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
0.1
1
10
FREQUENCY (MHz)
100
1k
08054-078
–1
3
08054-076
NORMALIZED CLOSED-LOOP GAIN (dB)
4
08054-028
NORMALIZED CLOSED-LOOP GAIN (dB)
Unless otherwise noted, all plots are characterized for the ADA4891-1, ADA4891-2, ADA4891-3, and ADA4891-4. For the ADA4891-1
and ADA4891-2, the typical RF value is 604 Ω. For the ADA4891-3 and ADA4891-4, the typical RF value is 453 Ω.
Figure 12. Small-Signal Frequency Response vs. Temperature, VS = 5 V,
ADA4891-3/ADA4891-4
Rev. B | Page 7 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
5
0°C
CLOSED-LOOP GAIN (dB)
+125°C
4
3
2
1
0
–40°C
–1
–2
–3
1
10
100
1k
0
–1
–2
–3
–6
0.1
VS = 3V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
1
100
1k
Figure 16. Small-Signal Frequency Response vs. Temperature, VS = 3 V,
ADA4891-3/ADA4891-4
0.1
VS = 3V
VOUT = 2V p-p
–0.1
VS = 5V
VOUT = 1.4V p-p
–0.2
VS = 5V
VOUT = 2V p-p
–0.3
G = +2
RF = 604Ω
RL = 150Ω
0.1
1
08054-019
VS = 3V
VOUT = 1.4V p-p
10
NORMALIZED CLOSED-LOOP GAIN (dB)
0
100
0
VS = 5V
VOUT = 1.4V p-p
–0.1
–0.2
VS = 3V
VOUT = 2V p-p
–0.3
VS = 5V
VOUT = 2V p-p
–0.4 G = +2
RF = 374Ω
RL = 150Ω
–0.5
0.1
VS = 3V
VOUT = 1.4V p-p
1
FREQUENCY (MHz)
10
FREQUENCY (MHz)
100
Figure 17. 0.1 dB Gain Flatness vs. Supply Voltage, G = +2,
ADA4891-3/ADA4891-4
1
1
0
0
–1
–2
G = +2
RF = 604Ω
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 14. 0.1 dB Gain Flatness vs. Supply Voltage, G = +2,
ADA4891-1/ADA4891-2
G = +1
RF = 0Ω
–3
–4
–5
G = +5
RF = 604Ω
G = –1
RF = 604Ω
–6
–7
–8
VS = 5V
–9 RL = 150Ω
VOUT = 2V p-p
–10
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 15. Large-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-1/ADA4891-2
G = –1
RF = 453Ω
–1
–2
G = +5
RF = 453Ω
–3
G = +1
RF = 0Ω
–4
–5
–6
–7
–8
–9
–10
0.1
08054-036
NORMALIZED CLOSED-LOOP GAIN (dB)
10
FREQUENCY (MHz)
0.1
NORMALIZED CLOSED-LOOP GAIN (dB)
1
–5
Figure 13. Small-Signal Frequency Response vs. Temperature, VS = 3 V,
ADA4891-1/ADA4891-2
–0.5
2
–4
FREQUENCY (MHz)
–0.4
3
VS = 5V
RL = 150Ω
VOUT = 2V p-p
1
G = +2
RF = 453Ω
10
FREQUENCY (MHz)
100
1k
Figure 18. Large-Signal Frequency Response vs. Gain, VS = 5 V,
ADA4891-3/ADA4891-4
Rev. B | Page 8 of 24
08054-080
–6
0.1
4
–40°C
08054-081
–5
VS = 3V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
08054-031
–4
+85°C
+125°C
+25°C
0°C
6
+85°C
5
CLOSED-LOOP GAIN (dB)
7
+25°C
6
08054-079
7
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
1
G = –1
VOUT = 2V p-p
–2
G = +1
VOUT = 1V p-p
–4
–5
G = +5
VOUT = 2V p-p
–6
–7
VS = 3V
RF = 604Ω
RL = 150Ω
–8
–9
–10
0.1
1
10
FREQUENCY (MHz)
100
1k
–2
G = +1
VOUT = 1V p-p
–3
–4
G = +5
VOUT = 2V p-p
–5
–6
–7
VS = 3V
RF = 453Ω
RL = 150Ω
–8
–9
–10
0.1
1
1k
Figure 22. Large-Signal Frequency Response vs. Gain, VS = 3 V,
ADA4891-3/ADA4891-4
–40
–30
VS = 5V
RL = 1kΩ
VOUT = 2V p-p
G = +2
SECOND HARMONIC
VS = 3V
RL = 1kΩ
VOUT = 2V p-p
–40
–70
DISTORTION (dBc)
–60
G = +1
SECOND HARMONIC
–80
–90
–100
–110
1
10
–70
–40
DISTORTION (dBc)
–80
–90
G = +1
THIRD HARMONIC
–110
G = +1 CONFIGURATION
OUT
G = –1
THIRD HARMONIC
IN
50Ω
–70
1kΩ
–VS = –1.1V
–80
G = –1
THIRD HARMONIC
G = +1
SECOND HARMONIC
–90
–100
G = +1
THIRD HARMONIC
–110
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V p-p)
4.0
4.5
5.0
–120
08054-040
0
10
G = –1
SECOND HARMONIC
G = +1
CONFIGURATION
+VS = +1.9V
–60
–100
–VS = –1.1V
1
–50
G = –1
SECOND HARMONIC
–70
1kΩ
Figure 23. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 3 V
G = +1
SECOND HARMONIC
VS = 5V
RF = 604Ω
RL = 1kΩ
fC = 1MHz
IN
50Ω
G = +2
THIRD HARMONIC
FREQUENCY (MHz)
–60
–120
+VS = +1.9V
–90
0.1
Figure 20. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 5 V
–50
G = +2
SECOND HARMONIC
–60
–80
FREQUENCY (MHz)
–40
G = +1
SECOND HARMONIC
–50
G = +1
THIRD HARMONIC
–120
0.1
G = +1
THIRD HARMONIC
OUT
G = +2
THIRD HARMONIC
08054-038
DISTORTION (dBc)
100
Figure 19. Large-Signal Frequency Response vs. Gain, VS = 3 V,
ADA4891-1/ADA4891-2
–50
DISTORTION (dBc)
10
FREQUENCY (MHz)
08054-039
–3
G = –1
VOUT = 2V p-p
G = +2
VOUT = 2V p-p
0
0.5
1.0
1.5
VS = 3V
fC = 1MHz
2.0
OUTPUT VOLTAGE (V p-p)
Figure 21. Harmonic Distortion (HD2, HD3) vs. Output Voltage, VS = 5 V
2.5
3.0
08054-041
G = +2
VOUT = 2V p-p
0
–1
08054-082
NORMALIZED CLOSED-LOOP GAIN (dB)
0
–1
08054-037
NORMALIZED CLOSED-LOOP GAIN (dB)
1
Figure 24. Harmonic Distortion (HD2, HD3) vs. Output Voltage, VS = 3 V
Rev. B | Page 9 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
G = +2
RF = 604Ω
RL = 150Ω
fC = 1MHz
–50
1k
VS = 3V
SECOND HARMONIC
VS = 3V
THIRD HARMONIC
VOLTAGE NOISE (nV/ Hz)
–40
DISTORTION (dBc)
–60
–70
VS = 5V
SECOND HARMONIC
–80
VS = 5V
THIRD HARMONIC
100
10
–90
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V p-p)
100
80
GAIN
–18
40
–90
30
–108
20
–126
10
–144
0
–162
–10
0.001
0.01
0.1
1
10
100
–180
1k
FREQUENCY (MHz)
0.02
0
–0.02
–0.04
–0.06
DIFFERENTIAL
PHASE ERROR (Degrees)
–72
PHASE (Degrees)
–54
PHASE
–0.2
–0.3
NORMALIZED CLOSED-LOOP GAIN (dB)
CL = 47pF
4
1
0
CL = 0pF
–1
–3
VS = 5V
G = +2
RL = 150Ω
VOUT = 200mV p-p
–4
0.1
1
10
FREQUENCY (MHz)
100
1k
9TH 10TH
5TH
3RD 4TH 5TH 6TH 7TH 8TH
MODULATING RAMP LEVEL (IRE)
9TH 10TH
6TH
7TH
VS = 5V, G = +2
RF = 604Ω, RL = 150Ω
1ST
2ND
5
CL = 47pF
4
CL = 22pF
3
CL = 10pF
2
1
0
CL = 0pF
–1
–2
–3
VS = 5V
G = +2
RL = 150Ω
VOUT = 200mV p-p
–4
0.1
08054-044
–2
4TH
Figure 29. Differential Gain and Phase Errors
6
CL = 10pF
8TH
3RD
0
–0.1
7
2
2ND
0.1
6
CL = 22pF
1ST
0.2
7
3
VS = 5V, G = +2
RF = 604Ω, RL = 150Ω
0.3
Figure 26. Open-Loop Gain and Phase vs. Frequency
5
10M
0.04
08054-043
50
1M
0.06
0
–36
60
NORMALIZED CLOSED-LOOP GAIN (dB)
OPEN-LOOP GAIN (dB)
70
100k
Figure 28. Input Voltage Noise vs. Frequency
DIFFERENTIAL
GAIN ERROR (%)
VS = 5V
RL = 1kΩ
10k
FREQUENCY (Hz)
Figure 25. Harmonic Distortion (HD2, HD3) vs. Output Voltage, G = +2
90
1k
08054-045
1.5
1.0
08054-060
0.5
VS = 5V
G = +1
Figure 27. Small-Signal Frequency Response vs. CL,
ADA4891-1/ADA4891-2
1
10
FREQUENCY (MHz)
100
Figure 30. Small-Signal Frequency Response vs. CL,
ADA4891-3/ADA4891-4
Rev. B | Page 10 of 24
1k
08054-083
0
1
10
08054-042
–100
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
100
100k
VS = 5V
G = +1
10k
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
10
1
0.1
1k
100
10
0.1
1
10
100
FREQUENCY (MHz)
1
0.01
08054-046
0.01
0.01
1
10
100
FREQUENCY (MHz)
Figure 31. Closed-Loop Output Impedance vs. Frequency, Part Enabled
VS = 3V
0.1
08054-089
VS = 5V
G = +1
Figure 34. Closed-Loop Output Impedance vs. Frequency, Part Disabled
(ADA4891-3 Only)
1.5
G = +1
VOUT = 200mV p-p
RL = 1kΩ
G = +2
VOUT = 2V p-p
VS = 5V
RL = 1kΩ
OUTPUT VOLTAGE (V)
0
–100
50mV/DIV
5ns/DIV
0.5
–0.5
–1.5
10
20
30
40
50
60
TIME (ns)
70
80
90
Figure 35. Large-Signal Step Response, G = +2
VS = 3V
G = +1
VOUT = 1V p-p
RL = 1kΩ
OUTPUT VOLTAGE (V)
0.5
RL = 150Ω
0
RL = 150Ω
0
0.5V/DIV
5ns/DIV
0.5V/DIV
5ns/DIV
Figure 36. Large-Signal Step Response, VS = 3 V, G = +1
Figure 33. Large-Signal Step Response, VS = 5 V, G = +1
Rev. B | Page 11 of 24
08054-050
–0.5
–1
08054-049
OUTPUT VOLTAGE (V)
VS = 3V
RL = 1kΩ
–1.0
VS = 5V
G = +1
VOUT = 2V p-p
1
VS = 3V
RL = 150Ω
0
Figure 32. Small-Signal Step Response, G = +1
RL = 1kΩ
VS = 5V
RL = 150Ω
08054-047
VS = 5V
08054-048
OUTPUT VOLTAGE (mV)
1.0
100
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
200
0.30
VS = 5V
G = +2
RL = 150Ω
VOUT = 2V p-p
0.20
190
FALLING EDGE
SLEW RATE (V/µs)
0
–0.10
–0.20
180
170
160
RISING EDGE
30
35
40
45
TIME (ns)
140
1.0
1.5
1
OUTPUT
1
5ns/DIV
08054-071
1V/DIV
OUTPUT
INPUT
2
AMPLITUDE (V)
1
INPUT
0
–1
–2
5ns/DIV
–3
5ns/DIV
VS = ±2.5V
G = –2
RL = 1kΩ
1
0
–1
–2
1V/DIV
1V/DIV
3
08054-070
AMPLITUDE (V)
2
5.0
Figure 41. Input Overdrive Recovery from Negative Rail
VS = ±2.5V
G = –2
RL = 1kΩ
OUTPUT
4.5
–1
–3
Figure 38. Input Overdrive Recovery from Positive Rail
3
4.0
INPUT
–2
0
–1
3.5
VS = ±2.5V
G = +1
RL = 1kΩ
0
AMPLITUDE (V)
AMPLITUDE (V)
2
3.0
Figure 40. Slew Rate vs. Output Step
VS = ±2.5V
G = +1
RL = 1kΩ
INPUT
2.5
OUTPUT STEP (V)
Figure 37. Short-Term Settling Time to 0.1%
3
2.0
08054-063
25
08054-061
0
08054-051
150
OUTPUT
1V/DIV
5ns/DIV
–3
Figure 39. Output Overdrive Recovery from Positive Rail
Figure 42. Output Overdrive Recovery from Negative Rail
Rev. B | Page 12 of 24
08054-052
SETTLING (%)
0.10
–0.30
VS = 5V
G = +2
RL = 150Ω
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
–10
0
VS = 5V
–10
–20
–20
VS = 5V
G = +2
RL = 150Ω
–30
ISOLATION (dB)
CMRR (dB)
–30
–40
–50
–60
TSSOP
–40
–50
–60
SOIC
–70
–70
–80
–80
10
100
FREQUENCY (MHz)
08054-090
1
0.1
–100
0.1
OUTPUT SATURATION VOLTAGE (V)
–40
+PSRR
–50
–60
–PSRR
–70
0.8
0.7
VOH, +125°C
VOH, +25°C
VOH, –40°C
VOL, +125°C
VOL, +25°C
VOL, –40°C
0.6
0.5
0.4
0.3
0.2
10
100
0
Figure 44. PSRR vs. Frequency
0
10
20
30
40
50
60
70
80
90
100
ILOAD (mA)
08054-056
1
08054-054
0.1
FREQUENCY (MHz)
Figure 47. Output Saturation Voltage vs. Load Current and Temperature
6.0
QUIESCENT SUPPLY CURRENT (mA)
Vs = 5V
G = +2
RL = 1 kΩ
VOUT = 2V p-p
–30
–40
–50
–60
–70
–80
VS = 5V
5.5
5.0
4.5
4.0
3.5
–90
–100
0.1
1
10
100
1k
FREQUENCY (MHz)
08054-072
CROSSTALK (dB)
VS = 5V
0.9 G = –2
RF = 604Ω
0.1
–80
0.01
–20
1k
Figure 45. All-Hostile Crosstalk (Output-to-Output) vs. Frequency
3.0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (ºC)
Figure 48. Supply Current per Amplifier vs. Temperature
Rev. B | Page 13 of 24
08054-057
PSRR (dB)
–30
–10
100
1.0
Vs = 5V
G = +1
–20
0
10
FREQUENCY (MHz)
Figure 46. Forward Isolation vs. Frequency (ADA4891-3 Only)
Figure 43. CMRR vs. Frequency
–10
1
08054-084
–90
–90
0.01
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
SUPPLY VOLTAGE (V)
08054-058
QUIESCENT SUPPLY CURRENT (mA)
4.4
Figure 49. Supply Current per Amplifier vs. Supply Voltage
Rev. B | Page 14 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
APPLICATIONS INFORMATION
WIDEBAND, INVERTING GAIN OPERATION
USING THE ADA4891
+VS
Understanding the subtleties of the ADA4891 family of amplifiers
provides insight into how to extract the peak performance from
the device. The following sections describe the effect of gain,
component values, and parasitics on the performance of the
ADA4891. The wideband, noninverting gain configuration of
the ADA4891 is shown in Figure 50; the wideband, inverting
gain configuration of the ADA4891 is shown in Figure 51.
0.1µF
VO
ADA4891
50Ω
SOURCE
VI
WIDEBAND, NONINVERTING GAIN OPERATION
10µF
RL
RG
RF
RT
0.1µF
0.1µF
10µF
08054-024
+VS
10µF
50Ω
SOURCE
–VS
VI
Figure 51. Inverting Gain Configuration
VO
ADA4891
RT
Figure 51 shows the inverting gain configuration. For the
inverting gain configuration, set the parallel combination of
RT and RG to match the input source impedance.
RL
RF
Note that a bias current cancellation resistor is not required in
the noninverting input of the amplifier because the input bias
current of the ADA4891 is very low (less than 2 pA). Therefore,
the dc errors caused by the bias current are negligible.
RG
10µF
08054-023
0.1µF
–VS
Figure 50. Noninverting Gain Configuration
In Figure 50, RF and RG denote the feedback and gain resistors,
respectively. Together, RF and RG determine the noise gain of the
amplifier. The value of RF defines the 0.1 dB bandwidth (for
more information, see the Effect of RF on 0.1 dB Gain Flatness
section). Typical RF values range from 549 Ω to 698 Ω for the
ADA4891-1/ADA4891-2. Typical RF values range from 301 Ω
to 453 Ω for the ADA4891-3/ADA4891-4.
In a controlled impedance signal path, RT is used as the input
termination resistor designed to match the input source impedance. Note that RT is not required for normal operation. RT is
generally set to match the input source impedance.
For both noninverting and inverting gain configurations, it is
often useful to increase the RF value to decrease the load on the
output. Increasing the RF value improves harmonic distortion at
the expense of reducing the 0.1 dB bandwidth of the amplifier.
This effect is discussed further in the Effect of RF on 0.1 dB Gain
Flatness section.
RECOMMENDED VALUES
Table 5 and Table 6 provide a quick reference for various configurations and show the effect of gain on the −3 dB small-signal
bandwidth, slew rate, and peaking of the ADA4891-1/ADA4891-2/
ADA4891-3/ADA4891-4. Note that as the gain increases, the
small-signal bandwidth decreases, as is expected from the gain
bandwidth product relationship. In addition, the phase margin
improves with higher gains, and the amplifier becomes more
stable. As a result, the peaking in the frequency response is
reduced (see Figure 7 and Figure 10).
Table 5. Recommended Component Values and Effect of Gain on ADA4891-1/ADA4891-2 Performance (RL = 1 kΩ)
Gain
−1
+1
+2
+5
+10
Feedback Network Values
RF (Ω)
RG (Ω)
604
604
0
Open
604
604
604
151
604
67.1
−3 dB Small-Signal Bandwidth (MHz)
VOUT = 200 mV p-p
118
240
120
32.5
12.7
Rev. B | Page 15 of 24
tR
188
154
170
149
71
Slew Rate (V/μs)
tF
192
263
210
154
72
Peaking (dB)
1.3
2.6
1.4
0
0
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
Table 6. Recommended Component Values and Effect of Gain on ADA4891-3/ADA4891-4 Performance (RL = 1 kΩ)
−3 dB Small-Signal Bandwidth (MHz)
VOUT = 200 mV p-p
97
220
97
31
13
0.3
Gain flatness is an important specification in video applications.
It represents the maximum allowable deviation in the signal
amplitude within the pass band. Tests have revealed that the
human eye is unable to distinguish brightness variations of
less than 1%, which translates into a 0.1 dB signal drop within
the pass band or, put simply, 0.1 dB gain flatness.
0.2
The PCB layout configuration and bond pads of the chip often
contribute to stray capacitance. The stray capacitance at the
inverting input forms a pole with the feedback and gain resistors.
This additional pole adds phase shift and reduces phase margin
in the closed-loop phase response, causing instability in the
amplifier and peaking in the frequency response.
Figure 52 and Figure 53 show the effect of using various values
for Feedback Resistor RF on the 0.1 dB gain flatness of the parts.
Figure 52 shows the effect for the ADA4891-1/ADA4891-2.
Figure 53 show the effect for the ADA4891-3/ADA4891-4.
Note that a larger RF value causes more peaking because the
additional pole formed by RF and the input stray capacitance
shifts down in frequency and interacts significantly with the
internal poles of the amplifier.
0.2
RG = RF = 649Ω
Slew Rate (V/μs)
tF
194
262
223
120
67
RG = RF = 402Ω
Peaking (dB)
0.9
4.1
0.9
0
0
RG = RF = 453Ω
RG = RF = 357Ω
0.1
0
RG = RF = 301Ω
–0.1
–0.2
–0.3
–0.4
VS = 5V
G = +2
VOUT = 2V p-p
RL = 150Ω
–0.5
0.1
1
10
100
FREQUENCY (MHz)
Figure 53. 0.1 dB Gain Flatness, Noninverting Gain Configuration,
ADA4891-3/ADA4891-4
To obtain the desired 0.1 dB bandwidth, adjust the feedback
resistor, RF, as shown in Figure 52 and Figure 53. If RF cannot
be adjusted, a small capacitor can be placed in parallel with RF
to reduce peaking.
The feedback capacitor, CF, forms a zero with the feedback
resistor, which cancels out the pole formed by the input stray
capacitance and the gain and feedback resistors. For a first pass
in determining the CF value, use the following equation:
RG × CS = RF × CF
where:
RG is the gain resistor.
CS is the input stray capacitance.
RF is the feedback resistor.
CF is the feedback capacitor.
0
RG = RF = 549Ω
–0.1
–0.2
–0.3
Using this equation, the original closed-loop frequency response of
the amplifier is restored, as if there is no stray input capacitance.
Most often, however, the value of CF is determined empirically.
VS = 5V
G = +2
VOUT = 2V p-p
RL = 150Ω
–0.4
0.1
1
10
100
FREQUENCY (MHz)
Figure 52. 0.1 dB Gain Flatness, Noninverting Gain Configuration,
ADA4891-1/ADA4891-2
08054-022
NORMALIZED CLOSED-LOOP GAIN (dB)
RG = RF = 698Ω
RG = RF = 604Ω
0.1
NORMALIZED CLOSED-LOOP GAIN (dB)
EFFECT OF RF ON 0.1 dB GAIN FLATNESS
tR
186
151
181
112
68
08054-085
Feedback Network Values
RG (Ω)
RF (Ω)
453
453
0
Open
453
453
453
90.6
453
45.3
Gain
−1
+1
+2
+5
+10
Figure 54 shows the effect of using various values for the feedback
capacitor to reduce peaking. In this case, the ADA4891-1/
ADA4891-2 are used for demonstration purposes and RF = RG =
604 Ω. The input stray capacitance, together with the board
parasitics, is approximately 2 pF.
Rev. B | Page 16 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
These four methods minimize the output capacitive loading effect.
•
Reducing the output resistive load. This pushes the pole
further away and, therefore, improves the phase margin.
Increasing the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitive loads with less peaking.
Adding a parallel capacitor (CF) with RF, from −IN to the
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by the
capacitive load and the output impedance of the amplifier.
See the Effect of RF on 0.1 dB Gain Flatness section for
more information.
Placing a small value resistor (RS) in series with the output
to isolate the load capacitor from the output stage of the
amplifier.
•
CF = 1pF
0
–0.2
•
CF = 3.3pF
–0.1
VS = 5V
G = +2
RF = 604Ω
RL = 150Ω
VOUT = 2V p-p
–0.3
0.1
1
10
100
FREQUENCY (MHz)
•
Figure 54. 0.1 dB Gain Flatness vs. CF, VS = 5 V,
ADA4891-1/ADA4891-2
DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation. The ADA4891-1/ADA4891-2 are
used to demonstrate this effect (see Figure 55 and Figure 56).
8
Figure 57 shows the effect of using a snub resistor (RS) on reducing
the peaking in the worst-case frequency response (gain of +1).
Using RS = 100 Ω reduces the peaking by 3 dB, with the trade-off
that the closed-loop gain is reduced by 0.9 dB due to attenuation
at the output. RS can be adjusted from 0 Ω to 100 Ω to maintain
an acceptable level of peaking and closed-loop gain, as shown in
Figure 57.
6
8
2
4
MAGNITUDE (dB)
0
–2
–4
–6
–8
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
6
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
–10
0.1
1
2
10
100
FREQUENCY (MHz)
RS = 0Ω
0
RS = 100Ω
–2
–4
–6
–8
08054-032
MAGNITUDE (dB)
4
VIN
200mV
STEP
RS
CL
50Ω
–10
0.1
Figure 55. Closed-Loop Frequency Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
OUT
RL
1
10
100
FREQUENCY (MHz)
08054-033
CF = 0pF
0.1
08054-025
NORMALIZED CLOSED-LOOP GAIN (dB)
0.2
Figure 57. Closed-Loop Frequency Response with Snub Resistor, CL = 6.8 pF
Figure 58 shows that the transient response is also much improved
by the snub resistor (RS = 100 Ω) compared to that of Figure 56.
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
RS = 100Ω
0
–100
50mV/DIV
50ns/DIV
Figure 56. 200 mV Step Response, CL = 6.8 pF,
ADA4891-1/ADA4891-2
100
0
–100
50mV/DIV
50ns/DIV
Figure 58. 200 mV Step Response, CL = 6.8 pF, RS = 100 Ω
Rev. B | Page 17 of 24
08054-035
OUTPUT VOLTAGE (mV)
100
08054-034
OUTPUT VOLTAGE (mV)
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
TERMINATING UNUSED AMPLIFIERS
SINGLE-SUPPLY OPERATION
Terminating unused amplifiers in a multiamplifier package is
an important step in ensuring proper operation of the functional
amplifier. Unterminated amplifiers can oscillate and draw
excessive power. The recommended procedure for terminating
unused amplifiers is to connect any unused amplifiers in a
unity-gain configuration and to connect the noninverting input
to midsupply voltage. With symmetrical bipolar power supplies,
this means connecting the noninverting input to ground, as
shown in Figure 59.
The ADA4891 can also be operated from a single power supply.
Figure 61 shows the ADA4891-3 configured as a single 5 V
supply video driver.
•
•
•
+VS
•
ADA4891
The large-signal frequency response obtained with singlesupply operation is identical to the bipolar supply operation
(Figure 18 shows the large-signal frequency response).
08054-064
–VS
The input signal is ac-coupled into the amplifier via
Capacitor C1.
Resistor R2 and Resistor R4 establish the input midsupply
reference for the amplifier.
Capacitor C5 prevents constant current from being drawn
through the gain set resistor (RG) and enables the ADA4891-3
at dc to provide unity gain to the input midsupply voltage,
thereby establishing the output voltage at midsupply.
Capacitor C6 is the output coupling capacitor.
Figure 59. Terminating Unused Amplifier with
Symmetrical Bipolar Power Supplies
In single power supply applications, a synthetic midsupply
source must be created. This can be accomplished with a simple
resistive voltage divider. Figure 60 shows the proper connection
for terminating an unused amplifier in a single-supply
configuration.
+VS
2.5kΩ
Four pairs of low frequency poles are formed by R2/2 and C2,
R3 and C1, RG and C5, and RL and C6. With this configuration,
the −3 dB cutoff frequency at low frequency is 12 Hz. The
values of C1, C2, C5, and C6 can be adjusted to change the low
frequency −3 dB cutoff point to suit individual design needs.
For more information about single-supply operation of op amps,
see the Analog Dialogue article “Avoiding Op Amp Instability
Problems in Single-Supply Applications” (Volume 35, Number 2)
at www.analog.com.
+5V
+5V
Figure 60. Terminating Unused Amplifier with Single Power Supply
The ADA4891-3 includes a power-down feature that can be
used to save power when an amplifier is not in use. When an
amplifier is powered down, its output goes to a high impedance
state. The output impedance decreases as frequency increases;
this effect can be observed in Figure 34. With the power-down
function, a forward isolation of −40 dB can be achieved at
50 MHz. Figure 46 shows the forward isolation vs. frequency
data. The power-down feature is asserted by pulling the PD1,
PD2, or PD3 pin low.
R4
50kΩ
C4
0.01µF
C6
22µF
VIN
Table 7 summarizes the operation of the power-down feature.
Table 7. Disable Function
>VTH or floating
<VTH
C3
10µF
R3
100kΩ
DISABLE FEATURE (ADA4891-3 ONLY)
Power-Down Pin Connection (PDx)
R2
50kΩ
C2
1µF
Amplifier Status
Enabled
Disabled
Rev. B | Page 18 of 24
R1
50Ω
C1
22µF
VOUT
RL
150Ω
RG
453Ω
C5
22µF
RF
453Ω
ADA4891-3
–VS
Figure 61. Single-Supply Video Driver Schematic
08054-086
ADA4891
08054-065
2.5kΩ
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
VIDEO RECONSTRUCTION FILTER
MULTIPLEXER
A common application for active filters is at the output of video
digital-to-analog converters (DACs)/encoders. The filter, or more
appropriately, the video reconstruction filter, is used at the output
of a video DAC/encoder to eliminate the multiple images that
are created during the sampling process within the DAC. For
portable video applications, the ADA4891 is an ideal choice due
to its lower power requirements and high performance.
The ADA4891-3 has a disable pin used to power down the
amplifier to save power or to create a mux circuit. If two or
more ADA4891-3 outputs are connected together and only one
output is enabled, then only the signal of the enabled amplifier
appears at the output. This configuration is used to select from
various input signal sources. Additionally, the same input signal
is applied to different gain stages, or differently tuned filters, to
make a gain-step amplifier or a selectable frequency amplifier.
For active filters, a good rule of thumb is that the −3 dB bandwidth of the amplifiers be at least 10 times higher than the corner
frequency of the filter. This ensures that no initial roll-off is
introduced by the amplifier and that the pass band is flat until
the cutoff frequency.
An example of a 15 MHz, 3-pole, Sallen-Key, low-pass video
reconstruction filter is shown in Figure 62. This circuit features
a gain of +2, a 0.1 dB bandwidth of 7.3 MHz, and over 17 dB
attenuation at 29.7 MHz (see Figure 63). The filter has three
poles: two poles are active, with a third passive pole (R6 and C4)
placed at the output. C3 improves the filter roll-off. R6, R7, and
R8 make up the video load of 150 Ω. Components R6, C4, R7,
R8, and the input termination of the network analyzer form a
6 dB attenuator; therefore, the reference level is roughly 0 dB,
as shown in Figure 63.
Figure 64 shows a schematic of two ADA4891-3 devices used
to create a mux that selects between two inputs. One input is a
1 V p-p, 3 MHz sine wave; the other input is a 2 V p-p, 1 MHz
sine wave.
+2.5V
49.9Ω
R6
6.8Ω
C1
51pF
R1
C4
1nF
R4
1kΩ
–2.5V
R8
75Ω
49.9Ω
453Ω
VOUT
+2.5V
49.9Ω
2V p-p
1MHz
VOUT
10µF
453Ω
49.9Ω
0.1µF
10µF
0.1µF
10µF
49.9Ω
ADA4891-3
–2.5V
453Ω
453Ω
C3
15pF
HCO4
08054-062
R5
1kΩ
R7
68.1Ω
0.1µF
08054-087
VIN
+5V
10µF
ADA4891-3
1V p-p
3MHz
C2
51pF
R2
R3
47Ω 125Ω
0.1µF
SELECT
Figure 64. Two-to-One Multiplexer Using Two ADA4861-3 Devices
Figure 62. 15 MHz Video Reconstruction Filter Schematic
The select signal and the output waveforms for this circuit are
shown in Figure 65.
0
–3
–6
1V/DIV
1µs/DIV
5V/DIV
1µs/DIV
–12
OUTPUT
–15
–18
–21
–24
–27
SELECT
–30
–33
–39
0.03
0.1
1
10
100
FREQUENCY (MHz)
Figure 63. Video Reconstruction Filter Frequency Performance
Rev. B | Page 19 of 24
Figure 65. ADA4861-3 Mux Output
08054-088
–36
08054-059
MAGNITUDE (dB)
–9
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
LAYOUT, GROUNDING, AND BYPASSING
POWER SUPPLY BYPASSING
INPUT-TO-OUTPUT COUPLING
Power supply pins are additional op amp inputs, and care must
be taken so that a noise-free, stable dc voltage is applied. The
purpose of bypass capacitors is to create a low impedance path
from the supply to ground over a range of frequencies, thereby
shunting or filtering the majority of the noise to ground. Bypassing
is also critical for stability, frequency response, distortion, and
PSRR performance.
To minimize capacitive coupling between the inputs and outputs
and to avoid any positive feedback, the input and output signal
traces should not be parallel. In addition, the input traces should
not be close to each other. A minimum of 7 mils between the
two inputs is recommended.
GROUNDING
When possible, ground and power planes should be used. Ground
and power planes reduce the resistance and inductance of the
power supply feeds and ground returns. If multiple planes are
used, they should be stitched together with multiple vias. The
returns for the input, output terminations, bypass capacitors,
and RG should all be kept as close to the ADA4891 as possible.
Ground vias should be placed at the side or at the very end of
the component mounting pads to provide a solid ground return.
The output load ground and the bypass capacitor grounds should
be returned to a common point on the ground plane to minimize
parasitic inductance and to help improve distortion performance.
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 5× the typical input
bias current of the amplifier. Poor PCB layout, contamination,
and the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and that the board surface be free of
contaminants to take full advantage of the low input bias
currents of the ADA4891.
To significantly reduce leakage paths, a guard ring/shield should
be used around the inputs. The guard ring circles the input pins
and is driven to the same potential as the input signal, thereby
reducing the potential difference between pins. For the guard ring
to be completely effective, it must be driven by a relatively low
impedance source and should completely surround the input
leads on all sides, above and below, using a multilayer board
(see Figure 66).
GUARD RING
INPUT AND OUTPUT CAPACITANCE
GUARD RING
Parasitic capacitance can cause peaking and instability and,
therefore, should be minimized to ensure stable operation.
NONINVERTING
INVERTING
08054-067
If traces are used between components and the package, chip
capacitors of 0.1 μF (X7R or NPO) are critical and should be
placed as close as possible to the amplifier package. The 0508
case size for such a capacitor is recommended because it offers
low series inductance and excellent high frequency performance.
Larger chip capacitors, such as 0.1 μF capacitors, can be shared
among a few closely spaced active components in the same
signal path. A 10 μF tantalum capacitor is less critical for high
frequency bypassing, but it provides additional bypassing for
lower frequencies.
LEAKAGE CURRENTS
Figure 66. Guard Ring Configurations
The 5-lead SOT-23 package for the ADA4891-1 presents a
challenge in keeping the leakage paths to a minimum. The
pin spacing is very tight, so extra care must be used when
constructing the guard ring (see Figure 67 for the recommended guard ring construction).
In addition, the ground and power planes under the pins of
the ADA4891 should be cleared of copper to prevent parasitic
capacitance between the input and output pins to ground. This
is because a single mounting pad on a SOIC footprint can add
as much as 0.2 pF of capacitance to ground if the ground or
power plane is not cleared under the ADA4891 pins. In fact, the
ground and power planes should be kept at a distance of at least
0.05 mm from the input pins on all layers of the board.
Rev. B | Page 20 of 24
OUT
ADA4891-1
+VS
OUT
ADA4891-1
+VS
–VS
–VS
+IN
–IN
INVERTING
+IN
–IN
NONINVERTING
Figure 67. Guard Ring Layout, 5-Lead SOT-23
08054-068
High speed amplifiers are sensitive to parasitic capacitance between
the inputs and ground. A few picofarads of capacitance reduce
the input impedance at high frequencies, in turn increasing the
gain of the amplifier and causing peaking of the frequency
response or even oscillations, if severe enough. It is recommended
that the external passive components that are connected to the
input pins be placed as close as possible to the inputs to avoid
parasitic capacitance.
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
5°
0°
0.20
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 69. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. B | Page 21 of 24
0.55
0.45
0.35
121608-A
1.30
1.15
0.90
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
100709-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 70. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
8
14
1
7
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 71. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
ORDERING GUIDE
Model 1
ADA4891-1ARZ
ADA4891-1ARZ-RL
ADA4891-1ARZ-R7
ADA4891-1ARJZ-R7
ADA4891-1ARJZ-RL
ADA4891-2ARZ
ADA4891-2ARZ-RL
ADA4891-2ARZ-R7
ADA4891-2ARMZ
ADA4891-2ARMZ-RL
ADA4891-2ARMZ-R7
ADA4891-3ARUZ
ADA4891-3ARUZ-R7
ADA4891-3ARUZ-RL
ADA4891-3ARZ
ADA4891-3ARZ-R7
ADA4891-3ARZ-RL
ADA4891-4ARUZ
ADA4891-4ARUZ-R7
ADA4891-4ARUZ-RL
ADA4891-4ARZ
ADA4891-4ARZ-R7
ADA4891-4ARZ-RL
ADA4891-1AR-EBZ
ADA4891-1ARJ-EBZ
ADA4891-2AR-EBZ
ADA4891-2ARM-EBZ
ADA4891-3AR-EBZ
ADA4891-3ARU-EBZ
ADA4891-4AR-EBZ
ADA4891-4ARU-EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13” Tape and Reel
8-Lead SOIC_N, 7” Tape and Reel
5-Lead SOT-23, 7” Tape and Reel
5-Lead SOT-23, 13” Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13” Tape and Reel
8-Lead SOIC_N, 7” Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 7” Tape and Reel
14-Lead TSSOP, 13” Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 7” Tape and Reel
14-Lead SOIC_N, 13” Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 7” Tape and Reel
14-Lead TSSOP, 13” Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 7” Tape and Reel
14-Lead SOIC_N, 13” Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 5-Lead SOT-23
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 8-Lead MSOP
Evaluation Board for 14-Lead SOIC_N
Evaluation Board for 14-Lead TSSOP
Evaluation Board for 14-Lead SOIC_N
Evaluation Board for 14-Lead TSSOP
Z = RoHS Compliant Part.
Rev. B | Page 23 of 24
Package Option
R-8
R-8
R-8
RJ-5
RJ-5
R-8
R-8
R-8
RM-8
RM-8
RM-8
RU-14
RU-14
RU-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
R-14
R-14
R-14
Branding
H1W
H1W
H1U
H1U
H1U
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08054-0-7/10(B)
Rev. B | Page 24 of 24