16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC AD9261 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD OR VIN+ VIN– Σ-Δ MODULATOR LOW-PASS DECIMATION FILTER SAMPLE RATE CONVERTER CMOS BUFFER D15 D0 PLL_ LOCKED VREF PHASE LOCKED LOOP AD9261 CLK+ CLK– SERIAL INTERFACE CFILT AGND SDIO SCLK CSB DCO DGND 07803-001 SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: 87 dBc to 10 MHz input Noise figure: 15 dB Input impedance: 1 kΩ Power: 340 mW 1.8 V analog supply operation 1.8 V to 3.3 V output supply Selectable bandwidth 2.5 MHz/5 MHz/10 MHz Output data rate: 30 MSPS to 160 MSPS Integrated decimation filters Integrated sample rate converter On-chip PLL clock multiplier On-chip voltage reference Offset binary, Gray code, or twos complement data format Serial control interface (SPI) Figure 1. APPLICATIONS Data acquisition Automated test equipment Instrumentation Medical imaging GENERAL DESCRIPTION The AD9261 is a single 16-bit analog-to-digital converter (ADC) based on a continuous time (CT) sigma-delta (Σ-Δ) architecture that achieves 87 dBc of dynamic range over a 10 MHz input bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components. The AD9261 has a resistive input impedance that relaxes the requirements of the driver amplifier. In addition, a 32× oversampled fifth-order continuous time loop filter significantly attenuates out-of-band signals and aliases, reducing the need for external filters at the input. An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate from 30 MSPS to 160 MSPS, enabling a more efficient and direct interface. The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic. The AD9261 operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 340 mW. The AD9261 is available in a 48-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth. Passive input structure reduces or eliminates the requirements for a driver amplifier. An oversampling ratio of 32× and high order loop filter provide excellent alias rejection reducing or eliminating the need for antialiasing filters. An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference provide ease of use. This part operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD9261* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Technical Articles • MS-2210: Designing Power Supplies for High Speed ADC EVALUATION KITS • AD9261 Evaluation Board • Understanding Continuous-Time, Discrete-Time SigmaDelta ADCs And Nyquist ADCs DOCUMENTATION DESIGN RESOURCES Application Notes • AD9261 Material Declaration • AN-1142: Techniques for High Speed ADC PCB Layout • PCN-PDN Information • AN-282: Fundamentals of Sampled Data Systems • Quality And Reliability • AN-283: Sigma-Delta ADCs and DACs • Symbols and Footprints • AN-807: Multicarrier WCDMA Feasibility • AN-808: Multicarrier CDMA2000 Feasibility DISCUSSIONS • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit View all AD9261 EngineerZone Discussions. • AN-835: Understanding High Speed ADC Testing and Evaluation SAMPLE AND BUY Visit the product page to see pricing options. • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual Data Sheet • AD9261: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC Preliminary Data Sheet TECHNICAL SUPPORT Submit a technical question or find your regional support number. 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AD9261 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Equivalent Circuits ......................................................................... 13 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 14 General Description ......................................................................... 1 Analog Input Considerations ................................................... 14 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 16 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 18 Specifications..................................................................................... 3 Digital Engine ............................................................................. 19 DC Specifications ......................................................................... 3 Digital Outputs ........................................................................... 21 AC Specifications.......................................................................... 4 Timing ......................................................................................... 21 Digital Decimation Filtering Characteristics ............................ 4 Serial Port Interface (SPI) .............................................................. 23 Digital Specifications ................................................................... 5 Configuration Using the SPI ..................................................... 23 Switching Specifications .............................................................. 6 Hardware Interface..................................................................... 24 Absolute Maximum Ratings............................................................ 7 Memory Map .................................................................................. 25 Thermal Resistance ...................................................................... 7 Memory Map Definitions ......................................................... 25 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 27 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 27 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9261 SPECIFICATIONS DC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT BANDWIDTH ACCURACY No Missing Codes Offset Error Gain Error Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE ANALOG INPUT Input Span, VREF = 0.5 V Common-Mode Voltage Input Resistance POWER SUPPLIES Supply Voltage AVDD CVDD DVDD DRVDD Supply Current IAVDD2 ICVDD2 PLL Enabled ICVDD2 PLL Disabled IDVDD2 IDRVDD2 (1.8 V) IDRVDD2 (3.3 V) POWER CONSUMPTION Sine Wave Input2 PLL Disabled Sine Wave Input2 PLL Enabled Power-Down Power Standby Power2 Sleep Power 1 2 Temp Full Min Typ 16 Max 10 Unit Bits MHz Full Full Full Full Guaranteed ±0.02 ±0.15 ±0.7 ±3.0 ±1.5 % FSR % FSR LSB Full Full ±1.5 ±50 500 ppm/°C ppm/°C mV 490 510 Full Full Full 1.7 2 1.8 1 1.9 V p-p diff V kΩ Full Full Full Full 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.9 1.9 1.9 3.6 V V V V Full Full Full Full Full Full 74 57 8.0 100 5.5 10 83 654 8.8 108 5.8 mA mA mA mA mA mA Full Full Full Full Full 340 425 20 7 3 370 465 mW mW mW mW mW 4 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. Measured with a low input frequency, full-scale sine wave. Rev. 0 | Page 3 of 28 AD9261 AC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 4.2 MHz fIN = 8.4 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 4.2 MHz fIN = 8.4 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 4.2 MHz fIN = 8.4 MHz NOISE SPECTRAL DENSITY (NSD) AIN= −2 dBFS AIN = −40 dBFS NOISE FIGURE2 TWO-TONE SFDR fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS fIN1 = 7.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS ANALOG INPUT BANDWIDTH APERTURE JITTER 1 2 Temp Min Typ Max Full 25°C 25°C 81 83 83 83 dB dB dB 25°C 25°C 25°C 13.5 13.5 13.5 Bits Bits Bits Full 25°C 25°C 87 87 <120 80 dBc dBc dBc Full Full 25°C −155 −156 15 −153 −154.5 dB/Hz dB/Hz dB 25°C 25°C 25°C 25°C 25°C 93 92.5 92.5 10 1 Unit dBc dBc dBc MHz ps rms See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition. DIGITAL DECIMATION FILTERING CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 3. Parameter1 Pass-Band Transition Pass-Band Ripple Stop Band Stop Band Attenuation 1 Min 2.5 2.5 MHz BW Typ <0.1 3.75 MHz − fS/2 >85 Max 3.75 Min 5 5 MHZ BW Typ Max 6.5 Min 10 <0.1 6.5 MHz − fS/2 >85 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 4 of 28 10 MHz BW Typ <0.1 13 MHz − fS/2 >85 Max 13 Unit MHz dB MHz dB AD9261 DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 4. Parameter1 DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Range High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO, CSB, RESET) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH, IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) DRVDD = 1.8 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH, IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) 1 Temp Min Full Full Full Full Full Full 0.4 0.3 −60 −60 Full Full Full Full Full Full 1.2 0 −50 −10 Full Full Full Full Full Full 1.2 0 −10 +40 Full Full Full Full 3.29 3.25 Full Full Full Full 1.79 1.75 Typ CMOS/LVPECL 0.8 2 0.450 0.5 +60 +60 20 1 Unit V p-p V μA μA kΩ pF DRVDD + 0.3 0.8 −75 +10 V V μA μA kΩ pF DRVDD + 0.3 0.8 +10 +135 V V μA μA kΩ pF 30 2 26 5 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 28 Max 0.2 0.05 V V V V 0.2 0.05 V V V V AD9261 SWITCHING SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS, unless otherwise noted. Table 5. Parameter1 CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate CLK± Period CLK± Duty Cycle CLOCK INPUT (DIRECT CLOCKING) Conversion Rate CLK± Period CLK± Duty Cycle DATA OUTPUT PARAMETERS Output Data Rate DCO to Data Skew (tSKEW)2 Sample Latency WAKE-UP TIME3 Power Down Power Standby Power Sleep Power OUT-OF-RANGE RECOVERY TIME SERIAL PORT INTERFACE4 SCLK Period SCLK Pulse Width High Time (tSHIGH) SCLK Pulse Width Low Time (tSLOW) SDIO to SCLK Setup Time (tSDS) SDIO to SCLK Hold Time (tSDH) CSB to SCLK Setup Time (tSS) CSB to SCLK Hold Time (tSH) Temp Min Typ Max Unit Full Full Full 30 6.25 40 50 160 33 60 MSPS ns % Full Full Full 608 1.49 40 640 1.5625 50 672 1.64 60 MSPS ns % Full Full Full Full Full Full Full Full 20 3 168 960 MSPS ns Cycles 3 9 15 960 μs μs μs Cycles Full Full Full Full Full Full Full 40 16 16 5 2 5 2 ns ns ns ns ns ns ns 1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT. 4 See Figure 50 and the Serial Port Interface (SPI) section. 2 Timing Diagram DCO 07803-002 tSKEW D0 TO D15 Figure 2. Timing Diagram Rev. 0 | Page 6 of 28 AD9261 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Electrical AVDD to AGND DVDD to DGND DRVDD to DGND AGND to DGND AVDD to DRVDD CVDD to CGND CGND to DGND D0 to D15 to DGND DCO to DGND OR to DGND PDWN to GND PLLMULTx to DGND SDIO to DGND CSB to AGND SCLK to AGND VIN+, VIN− to AGND CLK+, CLK− to CGND Environmental Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 Sec) Junction Temperature The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package. Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −3.9 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +2.5 V −0.3 V to +2.0 V Table 7. Thermal Resistance Package Type 48-Lead LFCSP (CP-48-1) θJA 27.7 θJB 11.8 θJC 1.1 Unit °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. ESD CAUTION −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 28 AD9261 48 47 46 45 44 43 42 41 40 39 38 37 CLK+ CGND AGND AVDD VIN– VIN+ AVDD CFILT VREF AVDD AGND CSB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK– CVDD 1 2 AD9261 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 PLLMULT0/SCLK PLLMULT1/SDIO PLLMULT2 PLLMULT3 PLLMULT4 DVDD DGND DRVDD OR D15 D14 D13 NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. 07803-003 D4 D5 D6 D7 DRVDD DGND DVDD D8 D9 D10 D11 D12 13 14 15 16 17 18 19 20 21 22 23 24 PDWN 3 DVDD 4 DGND 5 DRVDD 6 PLL_LOCKED 7 DCO 8 D0 9 D1 10 D2 11 D3 12 PIN 1 INDICATOR Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4, 19, 31 5, 18, 30 6, 17, 29 7 8 9 to 16, 20 to 27 28 32, 33, 34 35 36 37 38, 46 39, 42, 45 40 41 43 44 47 48 49 Mnemonic CLK− CVDD PDWN DVDD DGND DRVDD PLL_LOCKED DCO D0 to D15 OR PLLMULT4, PLLMULT3, PLLMULT2 PLLMULT1/SDIO PLLMULT0/SCLK CSB AGND AVDD VREF CFILT VIN+ VIN– CGND CLK+ EPAD Description Clock Input (−). Clock Supply (1.8 V). External Power-Down Pin. Digital Supply (1.8 V). Digital Ground. Digital Output Driver Supply (1.8 V to 3.3 V). PLL Lock Indicator. Data Clock Output. Data Output Bits. D0 is the LSB and D15 is the MSB. Overrange Indicator. PLL Mode Selection Pins. PLL Mode Selection Pin/Serial Port Interface Data Input/Output. PLL Mode Selection Pin/Serial Port Interface Clock. Serial Port Interface Chip Select. Active low. Analog Ground. Analog Supply (1.8 V). Voltage Reference Input/Output. Noise Limiting Filter Capacitor. Analog Input (+). Analog Input (−). Clock Ground. Clock Input (+). Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package. Rev. 0 | Page 8 of 28 AD9261 TYPICAL PERFORMANCE CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, TA = 25°C, unless otherwise noted. 0 BANDWIDTH: 2.5MHz DATA RATE: 40MSPS fIN: 600kHz AT –2dBFS SNR: 88.8dB SFDR: 90dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –80 –100 –120 –140 –140 –160 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 –160 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 Figure 6. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.5 MHz, and BW = 2.5 MHz Figure 4. Single-Tone FFT with fIN = 600 kHz and BW = 2.5 MHz 0 BANDWIDTH: 5MHz DATA RATE: 40MSPS fIN: 1.2MHz AT –2dBFS SNR: 86dB SFDR: 90.3dBc –20 –40 AMPLITUDE (dBFS) –40 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 Figure 5. Single-Tone FFT with fIN = 1.2 MHz and BW = 5 MHz –160 07803-015 –160 0 BANDWIDTH: 5MHz DATA RATE: 40MSPS fIN1: 2.1MHz AT –8dBFS fIN2: 2.4MHz AT –8dBFS SFDR: 91.9dBc –20 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 07803-053 0 AMPLITUDE (dBFS) –60 –120 07803-011 AMPLITUDE (dBFS) –40 BANDWIDTH: 2.5MHz DATA RATE: 40MSPS fIN1: 2.1MHz AT –8dBFS fIN2: 2.5MHz AT –8dBFS SFDR: 90.6dBc –20 07803-052 0 Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz and BW = 5 MHz Rev. 0 | Page 9 of 28 AD9261 All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, 10 MHz bandwidth, output data rate 40 MSPS, TA = 25°C, unless otherwise noted. 0 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN: 2.4MHz AT –2dBFS SNR: 83.2dB SFDR: 92.6dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –100 –140 –140 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 –160 0 Figure 8. Single-Tone FFT with fIN = 2.4 MHz 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 Figure 11. Two-Tone FFT with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz 0 0 –40 AMPLITUDE (dBFS) –40 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 –160 07803-019 –160 0 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN1: 3.6MHz AT –8dBFS fIN2: 4.2MHz AT –8dBFS SFDR: 92.2dBc –20 0 Figure 9. Single-Tone FFT with fIN = 4.2 MHz 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 07803-055 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN: 4.2MHz AT –2dBFS SNR: 83.1dB SFDR: 91.5dBc –20 Figure 12. Two-Tone FFT with fIN1 = 3.6 MHz and fIN2 = 4.2 MHz 0 0 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN: 8.4MHz AT –2dBFS SNR: 83dB SFDR: 105.7dBc –20 –40 AMPLITUDE (dBFS) –40 –60 –80 –100 –60 –80 –100 –120 –140 –140 –160 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 07803-020 –120 0 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN1: 7.2MHz AT –8dBFS fIN2: 8.4MHz AT –8dBFS SFDR: 93dBc –20 Figure 10. Single-Tone FFT with fIN = 8.4 MHz –160 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 Figure 13. Two-Tone FFT with fIN1 = 7.2 MHz and fIN2 = 8.4 MHz Rev. 0 | Page 10 of 28 20 07803-056 AMPLITUDE (dBFS) –80 –120 –160 AMPLITUDE (dBFS) –60 –120 07803-018 AMPLITUDE (dBFS) –40 BANDWIDTH: 10MHz DATA RATE: 40MSPS fIN1: 2.1MHz AT –8dBFS fIN2: 2.4MHz AT –8dBFS SFDR: 91.2dBc –20 07803-054 0 AD9261 110 120 SFDR (dBFS) 105 SNR (dBFS) AMPLITUDE (dBFS) 80 60 SFDR (dB) 40 100 95 SFDR (dBc) 90 SNR (dB) 85 20 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 80 07803-024 0 –100 SNR (dB) 0 1 Figure 14. Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 2.4 MHz 2 3 4 5 6 FREQUENCY (MHz) 7 8 9 10 07803-023 SNR/SFDR (dBFS AND dB) 100 Figure 17. SNR/SFDR vs. Input Frequency –40 92 91 –50 1.9V SFDR 90 SFDR (dBc) –70 –80 –90 –100 SFDR (dB) 1.8V 89 88 1.7V 87 86 85 SNR 84 1.9V 1.8V 83 –110 1.7V 82 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 81 –60 07803-057 –120 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 07803-059 SNR (dB)/SFDR (dBc) SFDR (dBc AND dB) –60 Figure 18. SFDR/SNR vs. Temperature with fIN = 2.4 MHz Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz 94 84.0 SFDR (dBc) 83.8 92 83.6 83.4 SNR (dB) 88 86 84 83.2 83.0 82.8 82.6 SNR (dBc) 82.4 82 40 60 80 100 120 OUTPUT DATA RATE (MSPS) 140 160 82.0 1.700 Figure 16: SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz 1.725 1.750 1.775 1.800 1.825 1.850 COMMON-MODE VOLTAGE (V) 1.875 1.900 Figure 19. SNR vs. Input Common Mode Voltage with fIN = 2.4 MHz Rev. 0 | Page 11 of 28 07803-058 82.2 80 20 07803-025 SNR/SFDR (dBc) 90 AD9261 1.0 84 83 0.5 2.4MHz INL ERROR (LSB) 82 81 80 0 –0.5 –1.0 79 77 1 8 9 10 12 14 15 16 17 18 20 21 24 25 28 30 32 34 42 PLL DIVIDE RATIO –2.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 OUTPUT CODE Figure 21. INL with fIN = 2.4 MHz Figure 20. Single-Tone SNR vs. PLL Divide Ratio Rev. 0 | Page 12 of 28 07803-021 –1.5 78 07803-026 SNR (dB) 8.4MHz AD9261 EQUIVALENT CIRCUITS AVDD 26kΩ 1kΩ CSB 500Ω 07803-004 07803-008 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 22. Equivalent Analog Input Circuit Figure 26. Equivalent CSB Input Circuit CVDD DRVDD 10kΩ 10kΩ 90kΩ 30kΩ 07803-009 CVDD CLK– 07803-005 CLK+ DRGND Figure 27. Equivalent Digital Output Circuit Figure 23. Equivalent Clock Input Circuit DRVDD 2.85kΩ 10kΩ 8.5kΩ 0.5V 1kΩ 3.5kΩ 07803-006 10µF TO CURRENT GENERATOR Figure 28. Equivalent VREF Circuit Figure 24. Equivalent SDIO Input Circuit 1kΩ SCLK 07803-007 30kΩ Figure 25. Equivalent SCLK Input Circuit Rev. 0 | Page 13 of 28 07803-010 SDIO AD9261 THEORY OF OPERATION BAND OF INTEREST ADC H(f) fOUT fMOD/16 BAND OF INTEREST 07803-033 fOUT/2 DECIMATION SAMPLE RATE FILTER CONVERTER QUANTIZER Figure 33. Sample Rate Converter SRC ANALOG INPUT CONSIDERATIONS 07803-029 DAC – Figure 29. Σ-Δ Modulator Overview The quantizer produces a nine-level digital word. The quantization noise is spread uniformly over the Nyquist band (see Figure 30), but the feedback loop causes the quantization noise present in the nine-level output to have a nonuniform spectral shape. This noise-shaping technique (see Figure 31) pushes the in-band noise out of band; therefore, the amount of quantization noise in the frequency band of interest is minimal. The digital decimation filter that follows the modulator removes the large out-of-band quantization noise (see Figure 32), while also reducing the data rate from fMOD to fMOD/16. If the internal PLL is enabled, the sample rate converter generates samples at the same frequency as the input clock frequency. If the internal PLL is disabled, the sample rate converter can be programmed to give an output frequency that is a divide ratio of the modulator clock. The sample rate converter is designed to attenuate images outside the band of interest (see Figure 33). fMOD/2 BAND OF INTEREST 07803-030 QUANTIZATION NOISE The continuous time modulator removes the need for an antialias filter at the input to the AD9261. A discrete time converter aliases signals around the sample clock frequency and its multiples to the band of interest (see Figure 34). Therefore, an external antialias filter is needed to reject these signals. DESIRED INPUT UNDESIRED SIGNAL fS fS/2 ADC 07803-034 + fMOD/16 Figure 32. Digital Filter Cutoff Frequency MODULATOR LOOP FILTER fMOD/32 07803-032 DIGITAL FILTER CUTOFF FREQUENCY The AD9261 uses a continuous time Σ-Δ modulator to convert the analog input to a digital word. The digital word is processed by the decimation filter and rate-adjusted by the sample rate converter (see Figure 29). The modulator consists of a continuous time loop filter preceding a quantizer that samples at fMOD = 640 MSPS. This produces an oversampling ratio (OSR) of 32 for a 10 MHz input bandwidth. The output of the quantizer is fed back to a DAC that ideally cancels the input signal. The incomplete input cancellation residue is filtered by the loop filter and is used to form the next quantizer sample. Figure 34. Discrete Time Converter In contrast, the continuous time Σ-Δ modulator used within the AD9261 has inherent antialiasing. The antialiasing property results from sampling occurring at the output of the loop filter (see Figure 35), and thus aliasing occurs at the same point in the loop as quantization noise is injected; aliases are shaped by the same mechanism as quantization noise. The quantization noise transfer function, NTF(f), has zeros in the band of interest and in all alias bands because NTF(f) is a discrete time transfer function, whereas the loop filter transfer function, LF(f), is a continuous time transfer function, which introduces poles only in the band of interest. The signal transfer function, being the product of NTF(f) and LF(f), only has zeros in alias bands and therefore suppresses all aliases. Figure 30. Quantization Noise L F (f) LOOP FILTER INP UT LF(f) fMOD QUANTIZATION NOISE BAND OF INTEREST fMOD/2 07803-031 NOISE SHAPING H(z) fMOD OUTPUT NTF(f) f fMOD Figure 35. Continuous Time Converter Rev. 0 | Page 14 of 28 07803-035 Figure 31. Noise Shaping AD9261 VIN+ 1:1 RT 50Ω VS AD9261 SIGNAL SOURCE VIN– AVDD 0.1µF Figure 38. Differential Transformer Configuration Voltage Reference AVDD – 0.5V 500Ω VCM = AVDD VIN p-p = 2V TO LOOP FILTER STAGE 2 VIN– 500Ω FROM QUANTIZER 07803-036 DAC Figure 36. Input Common Mode Differential Input Configurations A stable and accurate 0.5 V voltage reference is built into the AD9261. The reference voltage should be decoupled to minimize the noise bandwidth using a 10 μF capacitor. The reference is used to generate a bias current into a matched resistor such that, when used to bias the current in the feedback DAC, a voltage of AVDD − 0.5 V is developed at the internal side of the input resistors (see Figure 39). The current bias circuit should also be decoupled on the CFILT pin with a 10 μF capacitor. For this reason, the VREF voltage should always be 0.5 V. AVDD – 0.5V The AD9261 can also be configured for differential inputs. The ADA4937-1 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4937-1 is easily set by connecting AVDD to the VOCM pin of the ADA4937-1 (see Figure 37). The noise and linearity of the ADA4937-1 needs important consideration because the system performance may be limited by the ADA4937-1. +5V VCM = AVDD VIN p-p = 2V 500Ω VIN+ 500Ω VIN– 0.5V VREF 10kΩ REF TO LOOP FILTER STAGE 2 AVDD 10µF AVDD – 0.5V 500Ω +1.8V 0.1µF CFILT 0.1µF 07803-039 VIN+ 2V p-p 50Ω The analog inputs of the AD9261 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that VCM = AVDD is recommended for optimum performance. The analog inputs are 500 Ω resistors, and the internal reference loop aims to develop 0.5 V across each input resistor (see Figure 36). With 0 V differential input, the driver sources 1 mA into each analog input. 07803-038 Input Common Mode 10µF 200Ω RT 60.4Ω VS AVDD 8 200Ω 2 VOCM 9 SIGNAL SOURCE ADA4937-1 0.1µF Internal Reference Connection AD9261 3 10 15 200Ω 49.9Ω Figure 39. Voltage Reference Loop 11 60.4Ω VIN+ 0.1µF –5V 07803-037 2V p-p 50Ω VIN– To minimize thermal noise, the internal reference on the AD9261 is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor, which, when externally decoupled with a 10 μF capacitor, limits the noise (see Figure 40). The unbuffered reference should not be used to drive any external circuitry. The internal reference is used by default. Figure 37. Differential Input Configuration Using the ADA4937-1 The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a couple of megahertz (MHz), and excessive signal power can cause core saturation, which leads to distortion. Rev. 0 | Page 15 of 28 2.85kΩ 10kΩ 8.5kΩ 0.5V 3.5kΩ 10µF TO CURRENT GENERATOR Figure 40. Internal Reference Configuration 07803-040 For frequencies offset from dc, where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 38. The center tap of the secondary winding of the transformer is connected to AVDD to bias the analog input. AD9261 External Reference Operation If an external reference is desired, the internal reference can be disabled by setting Register 0x18[6] high. Figure 41 shows an application using the ADR130B as a stable external reference. Direct Clocking TO CURRENT GENERATOR Figure 41. External Reference Configuration CLOCK INPUT CONSIDERATIONS The AD9261 offers two modes of sourcing the ADC sample clock (CLK+ and CLK−). The first mode uses an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency. The on-chip phase-locked loop (PLL) then multiplies the reference clock up to a higher frequency, which is then used to generate all the internal clocks required by the ADC The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed clock. The second mode bypasses the clock multiplier circuitry and allows the clock to be directly sourced. This mode enables the user to source a very high quality clock directly to the Σ-Δ modulator. Sourcing the ADC clock directly may be necessary in demanding applications that require the lowest possible ADC output noise. Refer to Figure 20, which shows the degradation in SNR performance for the various PLL settings. In either case, when using the on-chip clock multiplier or sourcing the high speed clock directly, it is necessary that the clock source have low jitter to maximize the ADC noise performance. High speed, high resolution ADCs are sensitive to the quality of the clock input. As jitter increases, the SNR performance of the AD9261 degrades from that specified in Table 2. The jitter inherent to the part due to the PLL root sum squares with any external clock jitter, thereby degrading performance. To prevent jitter from dominating the performance of the AD9261, the input clock source should be no greater than 1 ps rms of jitter. The CLK± inputs are self-biased to 450 mV (see Figure 23); if dc-coupled, it is important to maintain the specified 450 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p single-ended about the 450 mV common-mode voltage. The recommended clock inputs are CMOS or LVPECL. The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz. The clock rate possesses a direct relationship with the available input bandwidth of the ADC. Bandwidth = fMOD ÷ 64 The default configuration of the AD9261 is for direct clocking where the PLL is bypassed. Figure 42 shows one preferred method for clocking the AD9261. A low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes across the secondary side of the transformer limits clock excursions into the AD9261 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9261 while preserving the fast rise and fall times of the signal, which are critical to achieving low jitter. 0.1µF CLOCK INPUT MINI-CIRCUITS® TC1-1-13M+, 1:1 0.1µF XFMR CLK+ 0.1µF CLK– 50Ω ADC AD9261 SCHOTTKY DIODES: 0.1µF HSM2812 07803-042 10kΩ Figure 42. Transformer-Coupled Differential Clock If a differential clock is not available, the AD9261 can be driven by a single-ended signal into the CLK+ terminal with the CLK− terminal ac-coupled to ground. Figure 43 shows the circuit configuration. 0.1µF CLOCK INPUT CLK+ ADC AD9261 50Ω CLK– SCHOTTKY DIODES: 0.1µF HSM2812 Figure 43. Single-Ended Clock Another option is to ac couple a differential LVPECL signal to the sample clock input pins, as shown in Figure 44. The AD951x family of clock drivers is recommended because it offers excellent jitter performance. 0.1µF CLOCK INPUT AD951x LVPECL DRIVER CLOCK INPUT 0.1µF 50Ω 1 150Ω 0.1µF CLK ADC AD9261 100Ω CLK– CLK 240Ω CLK+ 240Ω 0.1µF 50Ω 1 RESISTORS ARE OPTIONAL. Figure 44. Differential LVPECL Sample Clock Rev. 0 | Page 16 of 28 07803-044 10µF 07803-043 0.1µF 0.5V 07803-041 ADR130B AVDD In either case, using the on-chip clock multiplier to generate the Σ-Δ modulator clock rate or directly sourcing the clock, any deviation from 640 MHz results in a change in input bandwidth. The input range of the clock is limited to 640 MHz ± 5%. AD9261 Internal PLL Clock Distribution Table 10. Internal PLL Multiplication Factors The alternative clocking option available on the AD9261 is to apply a low frequency reference clock and use the on-chip clock multiplier to generate the high frequency fMOD rate. The internal clock architecture is shown in Figure 45. 0x0A[5:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+/CLK– PHASE DETECTOR LOOP FILTER 1.28GHz VCO PLL DIVIDER ÷N ÷2 MODULATOR CLOCK 640MSPS 07803-045 PLL MULT 0x0A[5:0] PLLENABLE 0x09[2] Figure 45. Internal Clock Architecture The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the reference clock input multiplied by N fVCO = (CLK±) × (N) where N is the PLL multiplication (PLLMULT) factor. The Σ-Δ modulator clock frequency, fMOD, is equal to fMOD = fVCO ÷ 2 The reference clock, CLK±, is limited to 30 MHz to 160 MHz when configured to use the on-chip clock multiplier. Given the input range of the reference clock and the available multiplication factors, the fVCO is approximately 1280 MHz. This results in the desired fMOD rate of 640 MHz with a 50% duty cycle. Before the PLL enable (PLLENABLE) register bit is set, the PLL multiplication factor should be programmed into Register 0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and reports a locked state in Register 0x0A[7]. If the PLL multiplication factor is changed, the PLL enable bit should be reset and set again. Some common clock multiplication factors are shown in Table 11. The recommended sequence for enabling and programming the on-chip clock multiplier is summarized in Table 9. Table 9. Sequence for Enabling and Programming the PLL Step 1 2 3 4 5 6 Procedure Apply a reference clock to the CLK± pins. Program the PLL multiplication factor in Register 0x0A[5:0]. See Table 10. Enable the PLL; Register 0x09 = 04 (decimal). Enable the PLL autoband select. Initiate an SRC reset; Register 0x101[5:0] = 0. Set SRC to the desired value via Register 0x101[5:0]. PLLMULT (N) 8 8 8 8 8 8 8 8 9 10 10 12 12 14 15 16 17 18 18 20 21 21 21 24 25 25 25 28 28 30 30 32 0x0A[5:0] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLLMULT (N) 32 34 34 34 34 34 34 34 34 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 42 External PLL Control At power-up, the serial interface is disabled until the first serial port access. If the serial interface is disabled, the PLLMULTx pins control the PLL multiplication factor. The five PLLMULTx pins (Pin 32 to Pin 36) offer all the available multiplication factors. If all PLLMULTx pins are tied high, the PLL is disabled and the AD9261 assumes the high frequency modulator clock rate that is applied to the CLK± pins. Table 12 shows the relationship between PLLMULTx pins and the PLL multiplication factor. Rev. 0 | Page 17 of 28 AD9261 PLL Autoband Select Jitter Considerations The PLL VCO has a wide operating range that is covered by overlapping frequency bands. For any desired VCO output frequency, there are multiple valid PLL band select values. The AD9261 possesses an automatic PLL band select feature on chip that determines the optimal PLL band setting. This feature can be enabled by writing to Register 0x0A[6] and is the recommended configuration with the PLL clocking option. Follow the sequence shown in Table 9 for enabling the autoband select and configuring the PLL. The aperture jitter requirements for continuous time Σ-Δ converters may be more forgiving than Nyquist rate converters. The continuous time Σ-Δ architecture is an oversampled system, and to accurately represent the analog input signal to the ADC, a large number of output samples must be averaged together. As a result, the jitter contribution from each sample is root sum squared, resulting in a more subtle impact on noise performance as compared to Nyquist converters where aperture jitter has a direct impact on each sampled output. When the device is taken out of sleep or standby mode, Register 0x0A[6] must be toggled to reinitiate the autoband detect. In the block diagram of the continuous time Σ-Δ modulator (see Figure 29), the two building blocks most susceptible to jitter are the quantizer and the DAC. The error introduced through the sampling process or quantizer is reduced by the loop gain and shaped in the same way as the quantization noise and, therefore, its effect can be neglected. On the contrary, the jitter error associated to the DAC directly adds to the input signal, thus increasing the in-band noise power and degrading the modulator performance. The SNR degradation due to jitter can be represented by the following equation: Table 11. Common Modulator Clock Multiplication Factors CLK± (MHz) 30.72 39.3216 52.00 61.44 76.80 78.00 78.6432 89.60 92.16 122.88 134.40 153.60 157.2864 0x0A[5:0] (PLLMULT) 42 32 25 21 17 17 16 15 14 10 10 8 8 fVCO (MHz) 1290.24 1258.29 1300.00 1290.24 1305.60 1326.00 1258.29 1344.00 1290.24 1228.80 1344.00 1228.80 1258.29 fMOD (MHz) 645.12 629.15 650.00 645.12 652.80 663.00 629.15 672.00 645.12 614.40 672.00 614.40 629.15 BW (MHz) 10.08 9.83 10.16 10.08 10.20 10.36 9.83 10.50 10.08 9.60 10.50 9.60 9.83 Table 12. External PLLMULTx Pins and PLL Multiplication Factor PLLMULTx[4:0] Pins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 to 30 31 PLL Multiplication Factors (N) 8 9 10 12 14 15 16 17 18 20 21 24 25 28 30 32 34 42 Direct clocking SNR = −20 log (2πfanalogtjitter_rms) dB where fanalog is the analog input frequency and tjitter_rms is the jitter. The SNR performance of the AD9261 remains constant within the input bandwidth of the converter, from dc to 10 MHz. Therefore, the minimal jitter specification is determined at the highest input frequency. From the calculation, the aperture jitter of the input clock must be no greater than 1 ps to achieve optimal SNR performance. POWER DISSIPATION AND STANDBY MODE The AD9261 power consumption can be further reduced by configuring the chip in channel power-down, standby, or sleep mode. The low power modes turn off internal blocks of the chip including the reference. As a result, the wake-up time is dependent on the amount of circuitry that is turned off. Fewer internal circuits that are powered down result in proportionally shorter wake-up time. The different low power modes are shown in Table 13. In the standby mode, all clock related activity and the output channels are disabled. Only the references and CMOS outputs remain powered up to ensure a short recovery and link integrity. During sleep mode, all internal circuits are powered down, putting the device into its lowest power mode, and the CMOS outputs are disabled. If the serial port interface is not available, the AD9261 can be configured in power-down mode by connecting Pin 3 (PDWN) to AVDD. Rev. 0 | Page 18 of 28 AD9261 Table 13. Low Power Modes 0x08[1:0] 0x0 0x1 0x2 0x3 Table 14. DEC4 Filter Coefficients Analog Circuitry On Off Off Off Clock On On Off Off Ref On On On Off Coefficient Number C0, C22 C1, C21 C2, C20 C3, C19 C4, C18 C5, C17 DIGITAL ENGINE Bandwidth Selection The digital engine (see Figure 46) selects the decimation signal bandwidth by cascading third-order sinc (sinc3) decimate-by-2 filters. For a 10 MHz signal band, no filters are cascaded; for a 5 MHz signal band, a single filter is used; and for a 2.5 MHz signal band, the 5 MHz filter is cascaded with a second filter. Depending on the signal bandwidth, this drops the data rate into the fixed decimation filter. As a result, lower signal bandwidth options result in lower power. Bandwidth selection is determined by setting Register 0x0F[6:5]. Coefficient Number C0, C62 C1, C61 C2, C60 C3, C59 C4, C58 C5, C57 C6, C56 C7, C55 C8, C54 C9, C53 C10, C52 C11, C51 C12, C50 C13, C49 C14, C48 C15, C47 A fixed frequency low-pass filter is used to define the signal band. This filter incorporates magnitude equalization for the droop of the preceding sinc decimation filters and the sinc filters of the sample rate converter. Table 14 and Table 15 detail the coefficients for the DEC4 and LPF/EQZ filters. The preceding sinc decimation filters are a standard sinc filter implementation. BANDWIDTH SELECTION 10MHz Σ-Δ OUTPUT 5MHz DEC01 SINC3 2 10MHz 5MHz Coefficient Number C6, C16 C7, C15 C8, C14 C9, C13 C10, C12 C11 Coefficient 1121 0 −2796 0 10,184 16,384 Table 15. LPF/EQZ Filter Coefficients Decimation Filters 4 Coefficient −21 0 122 0 −418 0 Coefficient 17 31 −15 −52 36 78 −84 −98 170 97 −291 −42 441 −98 −592 353 Coefficient Number C16, C46 C17, C45 C18, C44 C19, C43 C20, C42 C21, C41 C22, C40 C23, C39 C24, C38 C25, C37 C26, C36 C27, C35 C28, C34 C29, C33 C30, C32 C31 Coefficient 694 −744 −677 1271 450 −1909 103 2612 −1147 −3326 3022 4051 −6870 −5305 21,141 38,956 DECIMATION FILTERS DEC1 DEC2 DEC3 DEC4 LPF/EQZ SINC4 2 SINC4 2 SINC6 2 HB 2 FIR INT1 INT2 INT3 2.5MHz 2.5MHz DEC02 SINC3 2 HB 2 HB 2 SINC5 4 2 10MHz INT4 5MHz SINC5 8 DATA OUTPUT 2.5MHz SAMPLE RATE CONVERTER Figure 46. Digital Engine Rev. 0 | Page 19 of 28 16 NCO 07803-046 Mode Normal Power-Down Standby Sleep AD9261 Sample Rate Converter Table 18. SRC Conversion Factors The sample rate converter (SRC) allows the flexibility of a userdefined output sample rate, enabling a more efficient and direct interface to the digital receiver blocks. The sample rate converter performs an interpolation and resampling procedure to provide an output data rate of 20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coefficients for the INT1 and INT2 filters. The sinc filters are a standard implementation. Table 16. INT1 Filter Coefficients Coefficient Number C7, C19 C8, C18 C9, C17 C10, C16 C11, C15 C12, C14 C13 Coefficient 0 2450 0 −5761 0 20433 32768 Table 17. INT2 Filter Coefficients Coefficient Number C0, C14 C1, C13 C2, C12 C3, C11 Coefficient −27 0 227 0 Coefficient Number C4, C10 C5, C9 C6, C8 C7 KOUT SRC reset 4 4 4 4 4 4 4 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 0x101[5:0] 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 KOUT 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 16.5 17 17.5 18 18.5 19 19.5 20 20.5 21 21.5 0x101[5:0] 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 KOUT 22 22.5 23 23.5 24 24.5 25 25.5 26 26.5 27 27.5 28 28.5 29 29.5 30 30.5 31 31.5 Cascaded Filter Responses Coefficient −1032 0 4928 8192 The relationship between the output sample rate and the Σ-Δ modulator clock rate is expressed as follows: fOUT = fMOD ÷ KOUT Table 18 shows the available KOUT conversion factors. If the main clocking source of the AD9261 is provided by the PLL, it is important that once the PLL has been programmed and locked, to initiate an SRC reset before programming the desired KOUT factor. This is done by first writing 0x101[5:0] = 0 and then rewriting to the same register with the appropriate KOUT value. In addition, if the AD9261 loses its clock source and then later regains it, an SRC reset should be initiated. The cascaded filter responses for the three signal bandwidth settings are for a 160 MSPS output data rate, as shown in Figure 47, Figure 48, and Figure 49. 0 0.08 –20 0.04 Rev. 0 | Page 20 of 28 –40 0 –60 –0.04 –80 –0.08 0 –100 2 4 6 FREQUENCY (MHz) 8 10 –120 –140 –160 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 Figure 47. 10 MHz Signal Bandwidth, 160 MSPS 80 07803-047 Coefficient 15 0 −97 0 361 0 −1017 AMPLITUDE (dBFS) Coefficient Number C0, C26 C1, C25 C2, C24 C3, C23 C4, C22 C5, C21 C6, C20 0x101[5:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 AD9261 an overrange condition typically extends well beyond one clock cycle—that is, it does not toggle at the DCO rate—data can usually be successfully detected on the rising edge of DCO or monitored asynchronously. 0 0.08 –20 AMPLITUDE (dBFS) 0.04 –40 0 –60 –0.04 –80 –0.08 0 1 –100 2 3 FREQUENCY (MHz) 4 5 –120 –140 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 07803-048 –160 Figure 48. 5 MHz Signal Bandwidth, 160 MSPS 0 0.08 The second trip point is in the digital block. If the input signal is large enough to cause the data bits to clip to the maximum full-scale level, an overrange condition occurs. The overrange trip point can be adjusted by specifying a threshold level. –20 AMPLITUDE (dBFS) 0.04 –40 0 –60 –0.04 –80 –0.08 0.5 –100 1.5 FREQUENCY (MHz) 2.5 –120 –140 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 07803-049 –160 0 The AD9261 has two trip points that can trigger an overrange condition: analog and digital. The analog trip point is located in the modulator, and the second trip point is in the digital engine. In normal operation, it is possible for the analog trip point to toggle the OR pin for a number of clock cycles as the analog input approaches full scale. Because the OR pin is a pulsewidth modulated (PWM) signal, as the analog input increases in amplitude, the duration of overrange pin toggling increases. Eventually, when the OR pin is high for an extended period of time, the ADC is overloaded, and there is little correspondence between analog input and digital output. Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS DIGITAL OUTPUTS Digital Output Format The AD9261 offers a variety of digital output formats for ease of system integration. The digital output consists of 16 data bits and an output clock signal (DCO) for data latching. The data bits can be configured for offset binary, twos complement, or Gray code by writing to Register 0x14[1:0]. In addition, the voltage swing of the digital outputs can be configured to 3.3 V TTL levels or a reduced voltage swing of 1.8 V by accessing Register 0x14[7]. When 3.3 V voltage levels are desirable, the DRVDD power supply must be set to 3.3 V. Overrange (OR) Condition The OR pin serves as an indicator for an overrange condition. The OR pin is triggered by in-band signals that exceed the full-scale range of the ADC. In addition, the AD9261 possesses out-ofband gain above 10 MHz; therefore, a large out-of-band signal may trip an overrange condition. The OR pin is a synchronous output that is updated at the output data rate. Ideally, OR should be latched on the falling edge of DCO to ensure proper setup-and-hold time. However, because Table 19 shows the corresponding threshold level in dBFS vs. register setting. If the input signal crosses this level, the OR pin is set. In the case where 0x111[5:0] is set to all 0s, the threshold level is set to the maximum code of 32,76710. This feature provides a means of reporting the instantaneous amplitude as it crosses a user-provided threshold. This gives the user a sense for the signal level without needing to perform a full power measurement. The user has the ability to select how the overrange conditions are reported, and this is controlled through Register 0x111 via AUTORST, OR_IND, and ORTHRESH (see Table 20). By enabling the AUTORST bit, Register 0x111[7], if an overrange occurs, the ADC automatically resets itself. The OR pin remains high until the automatic reset has completed. If an analog trip occurs, the modulator resets itself after 16 consecutive clock cycles of overrange. If the AD9261 is used in a system that incorporates automatic gain control (AGC), the OR signal can be used to indicate that the signal amplitude should be reduced. This may be particularly effective for use in maximizing the signal dynamic range if the signal includes high occurrence components that occasionally exceed full scale by a small amount. TIMING The AD9261 provides a data clock out (DCO) pin to assist in capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless changed by setting Register 0x16[7]. See Figure 2 for a graphical timing description. Rev. 0 | Page 21 of 28 AD9261 Table 19. OR Threshold Levels 0x111[5:0] 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 Threshold (dBFS) −36.12 −30.10 −26.58 −24.08 −22.14 −20.56 −19.22 −18.06 −17.04 −16.12 −15.29 −14.54 −13.84 −13.20 −12.60 −12.04 −11.51 −11.02 −10.56 −10.10 −9.68 0x111[5:0] 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A Threshold (dBFS) −9.28 −8.89 −8.52 −8.16 −7.82 −7.50 −7.18 −6.88 −6.58 −6.30 −6.02 −5.75 −5.49 −5.24 −5.00 −4.76 −4.53 −4.30 −4.08 −3.87 −3.66 0x111[5:0] 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Threshold (dBFS) −3.45 −3.25 −3.06 −2.87 −2.68 −2.50 −2.32 −2.14 −1.97 −1.80 −1.64 −1.48 −1.32 −1.16 −1.00 −0.86 −0.71 −0.56 −0.42 −0.28 −0.14 Table 20. OR Conditions OR Conditions Normal, Reset Off Digital Threshold, Reset Off Full Overrange, Reset Off Data Valid, No Reset Normal, Reset On Digital Threshold, Reset On Full Overrange, Reset On Data Valid, Reset On 1 AUTORST 0 0 OR_IND 0 0 ORTHRESH[5:0] 0 ORTHRESH[4:0] 00000 0 1 0 X1 0 1 1 1 0 0 1 0 X1 00000 1 1 0 X1 If analog trip or digital trip or calibration, OR = 0, else OR = 1 Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0 Digital threshold: if 16-bit output > ORTHRESH, OR = 1, else OR = 0 If analog trip or digital trip, OR = 1, else OR = 0 1 1 1 X1 If analog trip or digital trip or calibration, OR = 0 else OR = 1 >0 >0 X = don’t care. Rev. 0 | Page 22 of 28 Description Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0 Digital threshold: If 16-bit output > ORTHRESH, OR = 1, else OR = 0 If analog trip or digital trip, OR = 1, else OR = 0 AD9261 SERIAL PORT INTERFACE (SPI) During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase and the length is determined by the W0 bit and the W1 bit. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. The AD9261 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that are further divided into fields, as documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip as well as to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI As summarized in Table 21, three pins define the SPI of this ADC. The SCLK pin synchronizes the read and write data presented to the ADC. The SDIO pin allows data to be sent and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 21. Serial Port Interface Pins Data can be sent in MSB-first or in LSB-first mode. MSB first is the default setting on power-up and can be changed via the configuration register. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Pin Name SCLK Table 22. SPI Timing Diagram Specifications SDIO CSB Description SCLK (serial clock) is the serial shift clock. SCLK synchronizes serial interface reads and writes. SDIO (serial data input/output) is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB (chip select bar) is an active low control that gates the read and write cycles. Parameter tSDS tSDH tSCLK tSS tSH tSHIGH The falling edge of CSB in conjunction with the rising edge of SCLK determines the start of the framing. Figure 50 and Table 22 provide an example of the serial timing and its definitions. Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state tSLOW Other modes involving CSB are available. CSB can be held low indefinitely to permanently enable the device (this is called streaming). CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. tSDS tSS tSHIGH tSDH tSCLK tSH tSLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 50. Serial Port Interface Timing Diagram Rev. 0 | Page 23 of 28 D4 D3 D2 D1 D0 DON’T CARE 07803-050 SCLK DON’T CARE AD9261 HARDWARE INTERFACE The pins described in Table 21 comprise the physical interface between the programming device of the user and the serial port of the AD9261. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. such method is described in detail in the AN-812 Application Note, MicroController-Based Serial Port Interface (SPI) Boot Circuit. When the SPI interface is not used, some pins serve a dual function. When strapped to AVDD or ground during device power-on, the pins are associated with a specific function. The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user with the ability to use an alternate method to program the ADC. One Rev. 0 | Page 24 of 28 AD9261 MEMORY MAP Table 23. Memory Map Register Name SPI Port Config Chip ID Chip Grade Power Modes PLLENABLE PLL Analog Input Output Modes Output Adjust Output Clock Reference Output Data Overrange Address 0x00 0x01 0x02 0x08 0x09 0x0A 0x0F 0x14 0x15 0x16 0x18 0x101 0x111 Bit 7 0 Bit 6 LSBFIRST Bit 5 SOFTRESET Bit 4 Bit 3 1 1 CHIPID[7:0] CHILDID[2:0] Bit 2 SOFTRESET Bit 1 LSBFIRST Bit 0 0 PWRDWN[1:0] PLLLOCKED DRVSTD PLLAUTO BW[1:0] Interleave PLLENABLE PLLMULT[5:0] OUTENB OUTINV DRVSTR33[1:0] Format[1:0] DRVSTR18[1:0] DCOINV EXTREF AUTORST KOUT[5:0] ORTHRESH[5:0] OR_IND MEMORY MAP DEFINITIONS Table 24. Memory Map Definitions Register SPI Port Config Address 0x00 Bit(s) 6, 1 Mnemonic LSBFIRST Default 0 Chip ID Chip Grade Power Modes 0x01 0x02 0x08 5, 2 [7:0] [5:4] [1:0] SOFTRESET CHIPID CHILDID PWRDWN 0 0x26 0 0 PLLENABLE PLL 0x09 0x0A 2 7 PLLENABLE PLLLOCKED 0 0 Analog Input 0x0F 6 [5:0] [6:5] PLLAUTO PLLMULT BW 0 0 0 Output Modes 0x14 7 DRVSTD 0 5 4 2 [1:0] Interleave OUTENB OUTINV Format 0 0 0 0 Description 0: serial interface uses MSB first format 1: serial interface uses LSB first format 1: default all serial registers except 0x00, 0x09, and 0x0A 0x26: AD9261 0x00: 10 MHz bandwidth 0x0: normal operation 0x1: power-down (local) 0x2: standby (everything except reference circuits) 0x3: sleep 1: enable PLL 0: PLL is not locked 1: PLL is locked 1: PLL autoband enabled See Table 10 0x0: 10 MHz 0x1: 5 MHz 0x2: 2.5 MHz 0x3: 10 MHz 0: 3.3 V 1: 1.8 V 1: interleave both channels onto D[15:0] 1: data outputs tristated 1: data outputs bitwise inverted 0: offset binary 1: twos complement 2: Gray code 3: offset binary Rev. 0 | Page 25 of 28 AD9261 Register Output Adjust Output Clock Reference Output Data Overrange Address 0x15 0x16 0x18 0x101 0x111 Bit(s) [3:2] Mnemonic DRVSTR33 Default 0 [1:0] DRVSTR18 2 7 6 [5:0] 7 6 [5:0] DCOINV EXTREF KOUT AUTORST OR_IND ORTHRESH 0 0 0 0 0 0 Description Typical output sink current to DGND 0: 33 mA 1: 63 mA 2: 93 mA 3: 120 mA Typical output sink current to DGND 0: 10 mA 1: 20 mA 2: 30 mA 3: 39 mA 1: invert DCO 1: use external reference Output data rate, see Table 18 1: enable loop filter reset indicator on OR pin See Table 20 See Table 19 Rev. 0 | Page 26 of 28 AD9261 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 0.50 BSC 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP SEATING PLANE 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX PIN 1 INDICATOR 48 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 080108-A TOP VIEW 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 51. 48-Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9261BCPZ-10 AD9261BCPZRL7-10 AD9261-10EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option CP-48-1 CP-48-1 AD9261 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07803-0-4/10(0) Rev. 0 | Page 28 of 28