ATMEL AT27C040 4-megabit Datasheet

Features
• Fast Read Access Time – 70 ns
• Low Power CMOS Operation
•
•
•
•
•
•
•
– 100 µA Max Standby
– 30 mA Max Active at 5 MHz
JEDEC Standard Packages
– 32-lead PDIP
– 32-lead PLCC
– 32-lead TSOP
5V ± 10% Supply
High Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
CMOS and TTL Compatible Inputs and Outputs
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
4-Megabit
(512K x 8)
OTP EPROM
AT27C040
1. Description
The AT27C040 chip is a low-power, high-performance, 4,194,304-bit one-time programmable read-only memory (OTP EPROM) organized as 512K by 8 bits. The
AT27C040 requires only one 5V power supply in normal read mode operation. Any
byte can be accessed in less than 70 ns, eliminating the need for speed reducing
WAIT states on high-performance microprocessor systems.
Atmel’s scaled CMOS technology provides low active power consumption, and fast
programming. Power consumption is typically 8 mA in active mode and less than
10 µA in standby mode.
The AT27C040 is available in a choice of industry-standard JEDEC-approved onetime programmable (OTP) plastic PDIP, PLCC and TSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems.
Atmel’s AT27C040 has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
0189H–EPROM–12/07
2. Pin Configurations
Pin Name
Function
A0 - A18
Addresses
O0 - O7
Outputs
CE
Chip Enable
OE
Output Enable
32-lead PDIP Top View
2.2
A12
A15
A16
VPP
VCC
A18
A17
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
07
06
05
04
03
A7
A6
A5
A4
A3
A2
A1
A0
O0
4
3
2
1
32
31
30
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
07
32-lead TSOP Top View
A11
A9
A8
A13
A14
A17
A18
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-lead PLCC Top View
14
15
16
17
18
19
20
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
2.3
01
02
GND
03
04
05
06
2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
07
06
05
04
03
GND
02
01
O0
A0
A1
A2
A3
AT27C040
0189H–EPROM–12/07
AT27C040
3. Switching Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground ............................................-2.0V to +7.0V
Voltage on A9 with
Respect to Ground .........................................-2.0V to +14.0V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
VPP Supply Voltage with
Respect to Ground ..........................................-2.0V to +14.0V
3
0189H–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
OE
Ai
VPP
Outputs
(1)
Read
VIL
VIL
Ai
X
DOUT
Output Disable
X
VIH
X
X
High Z
VIH
X
X
X
High Z
VIL
VIH
Ai
VPP
DIN
PGM Verify
X
VIL
Ai
VPP
DOUT
PGM Inhibit
VIH
VIH
X
VPP
High Z
X
Identification Code
Standby
Rapid Program
(2)
(3)
Product Identification(4)
Notes:
VIL
VIL
A9 = VH
A0 = VIH or VIL
A1 - A18 = VIL
1. X can be VIL or VIH.
2. Refer to Programming Characteristics
3. VH = 12.0 ± 0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
Industrial Operating Temperature (Case)
VCC Power Supply
AT27C040-70
AT27C040-90
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
IPP1
(2)
Max
Units
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP(1)
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
100
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
1
mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
30
mA
Read/Standby Current
Min
ISB
VCC1(1) Standby Current
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
Output High Voltage
IOH = -400 µA
VOH
Notes:
2.4
V
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
4
AT27C040
0189H–EPROM–12/07
AT27C040
9. AC Characteristics for Read Operation
AT27C040
-70
Symbol
Parameter
Condition
tACC(1)
Address to Output Delay
CE = OE
= VIL
tCE(1)
CE to Output Delay
tOE(1)
OE to Output Delay
tDF(1)
OE or CE High to Output Float, Whichever Occurred First
tOH
Output Hold from Address, CE or OE, Whichever Occurred
First
Note:
Min
-90
Max
Max
Units
70
90
ns
OE = VIL
70
90
ns
CE = VIL
30
35
ns
20
20
ns
0
Min
0
ns
1. See AC Waveforms for Read Operation
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0189H–EPROM–12/07
11. Input Test Waveforms and Measurement Levels
12. Output Test Load
1.3V
(1N914)
OUTPUT
PIN
3.3K
CL
13. Pin Capacitance
f = 1 MHz, T = 25° C (1)
Symbol
Typ
Max
Units
Conditions
CIN
4
8
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
6
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
AT27C040
0189H–EPROM–12/07
AT27C040
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C040 a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
7
0189H–EPROM–12/07
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.7
V
0.4
V
2.4
V
CE = VIL
11.5
40
mA
20
mA
12.5
V
Max
Units
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Test Conditions(1)
Symbol
Parameter
tAS
Address Setup Time
tOES
OE Setup Time
Input Rise and Fall Times:
(10% to 90%) 20 ns
tDS
Data Setup Time
tAH
Address Hold Time
tDH
Data Hold Time
Input Pulse Levels:
tDFP
OE High to Output Float Delay
tVPS
VPP Setup Time
tVCS
VCC Setup Time
tPW
CE Program Pulse Width(3)
tOE
Data Valid from OE(2)
tPRT
VPP Pulse Rise Time During
Programming
Notes:
Min
2
µs
2
µs
2
µs
0
µs
2
µs
0.45V to 2.4V
(2)
0
Input Timing Reference Level:
0.8V to 2.0V
130
2
µs
2
µs
95
Output Timing Reference Level:
0.8V to 2.0V
ns
105
µs
150
ns
50
ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µsec ± 5%.
17. Atmel’s AT27C040 Integrated Product Identification Code
Pins
Codes
8
A0
O7
O6
O5
O4
O3
O2
O1
O0
Hex Data
Manufacturer
0
0
0
0
1
1
1
1
0
1E
Device Type
1
0
0
0
0
1
0
1
1
0B
AT27C040
0189H–EPROM–12/07
AT27C040
18. Rapid Programming Algorithm
A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs
CE pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are
applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been
applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All bytes
are read again and compared with the original data to determine if the device passes or fails.
9
0189H–EPROM–12/07
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC (ns)
Standby
Ordering Code
Package
32J
32P6
32T
Industrial
(-40° C to 85° C)
32J
32P6
32T
Industrial
(-40° C to 85° C)
70
30
0.1
AT27C040-70JI
AT27C040-70PI
AT27C040-70TI
90
30
0.1
AT27C040-90JI
AT27C040-90PI
AT27C040-90TI
Note:
19.2
Active
Operation Range
Not recommended for new designs. Use Green package option.
Green Package Option (Pb/Halide-free)
ICC (mA)
tACC (ns)
Active
Standby
Ordering Code
Package
32J
32P6
32T
Industrial
(-40° C to 85° C)
32J
32P6
32T
Industrial
(-40° C to 85° C)
70
30
0.1
AT27C040-70JU
AT27C040-70PU
AT27C040-70TU
90
30
0.1
AT27C040-90JU
AT27C040-90PU
AT27C040-90TU
Operation Range
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP)
10
AT27C040
0189H–EPROM–12/07
AT27C040
20. Package Information
20.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
11
0189H–EPROM–12/07
20.2
32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
41.783
–
42.291
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
32P6
REV.
B
AT27C040
0189H–EPROM–12/07
AT27C040
20.3
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
13
0189H–EPROM–12/07
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0189H–EPROM–12/07