BOARDCOM AC101L-DS05-R Ultra low-power 10/100 ethernet transceiver with auto-mdix Datasheet

Preliminary Data Sheet
AC101L
Ultra Low-Power 10/100 Ethernet Transceiver with Auto-MDIX
G EN ER AL DE SC RI PTI O N
FEA TU RE S
The AC101L is a single-channel, low-power,
1 0 / 1 0 0 B A S E -T X / F X t r a n s c e i v e r . T h e A C 1 0 1 L
transceiver has an integrated voltage regulator to allow
operation from a single 3.3V or 2.5V supply source. The
device contains a full-duplex 10BASE-T/100BASE-TX/
100BASE-FX Fast Ethernet transceiver, which performs
all of the physical layer interface functions.
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The AC101L is a highly integrated solution combining an
encoder/decoder, link monitor, auto-negotiation
selection, parallel detection, adaptive equalization, clock/
data recovery, baseline wander correction, multimode
transmitter, scrambler/descrambler, far-end fault (FEF),
and auto-MDI/MDIX circuitry.
3.3V tolerant and 2.5V capable
Integrated voltage regulator to allow operation from a
single 3.3V or 2.5V supply source
10/100 TX/FX
Full-duplex or half-duplex
FEFI on 100FX
48-pin TQFP
Industrial temperature (–40°C to +85°C)
0.25 µm CMOS
Fully compliant with IEEE 802.3/802.3u
MII interface
Baseline wander correction
Multifunction LED outputs
Cable length indicator
HP auto-MDI/MDIX
Eight programmable interrupts
Diagnostic registers
RXN/RXP
100RX
PCS
Framer
Carrier
4B/5B
PMA
Clock Recov.
Link Monitor
Signal Detect
MAC
MII Serial
Interface
25 MHz
Interface
MII Data
Interface
TP_PMD
MLT3
BLW
Stream
Cipher
PHYAD[4:0]
TXN/TXP
MUX
10RX
10BASE-T
Control Status
MII Serial Management
Interface and Register
100TX
PLL CLK Gen.
Test/LED Control
10TX
RX
25 MHz
FLP
Auto-Negotiation
XTLI/CLKIN LED Drivers
Figure 1: Functional Block Diagram
AC101L-DS06-405-R
16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710
8/9/04
AC101L
Preliminary Data Sheet
8/9/04
REVISION HISTORY
Revision
Date
Change Description
AC101L-DS06-R
8/9/04
• Edits for consistency, minor error corrections
AC101L-DS05-R
3/10/03
• Replaced the # sign with an overline to indicate active low pins.
• In Table 1, changed description of pin 24 (PDOWN) from being pulled low
externally to being pulled high externally for normal operation.
AC101L-DS04-R
1/29/03
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AC101L-DS03-R
9/18/02
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Updated Table 1, ”Pinout and Signal Definitions,” on page 7.
Updated Figure 2, ”AC101L Pinout Diagram,” on page 11.
Updated Table 19, ”Register 23: Operation Mode Register,” on page 25.
Updated Table 22, ”Common Register 1: (Map to Reg. 29, Page 0
A28.[15:12]=0000) Test Mode Register,” on page 26.
• Updated Table 23, ”Common Register 4: (Map to Reg. 29, Page 1
A28.[15:12]=0001) LED Blink Rate,” on page 27.
• Updated Table 44, ”Recommended Operating Conditions,” on page 46.
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Updated Signal Types designations in Section 2 ”Pin Descriptions” on page 7.
Updated Table 35, ”Reset Timing,” on page 35.
Updated Table 37, ”100BASE-X MII Transmit System Timing,” on page 37.
Updated Table 38, ”100BASE-TX/FX MII Receive System Timing,” on page 38
and Figure 6, ”100BASE-T MII Receive Timing,” on page 39.
Updated Table 39, ”10BASE-T MII Transmit System Timing,” on page 40 and
Figure 7, ”10BASE-T Transmit Timing,” on page 40.
Updated Table 40, ”10BASE-T MII Receive System Timing,” on page 41 and
Figure 8, ”10BASE-T Receive Timing,” on page 42.
Removed Table 42,”RMII Receive Timing,” on page 39 and Figure 9,”RMII
Receive Timing,” on page 39 as well as all references to RMII in the document.
Updated Table 44, ”Recommended Operating Conditions,” on page 46.
Added table showing current requirements at 2.5 V operation with LED disabled.
Added table showing current requirements at 3.3 V operation with LED disabled.
Added output voltage high values and output voltage low values (all digital pins).
Added input voltage high and low values (all digital input pins).
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AC101L-DS02-R
6/6/02
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AC101L-DS01-R
02/20/02
Updated FX application figure and Power and ground filtering figure.
AC101L-DS00-R
01/02/02
Initial release.
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Document AC101L-DS06-405-R
Preliminary Data Sheet
AC101L
8/9/04
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AC101L-DS06-405-R
Page iii
Altima Communications, Inc.
A Wholly-Owned Subsidiary of Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, California 92619-7013
© 2004 by Altima Communications, Inc.
All Rights Reserved
Altima Communications, Broadcom, and the pulse logo are registered trademarks of Broadcom Corporation and/or its
subsidiaries in the United States and certain other countries. Any other trademarks are the property of their respective
owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended,
or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control,
hazardous substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "ASIS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND
IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
Preliminary Data Sheet
AC101L
8/9/04
Table of Contents
Section 1: Functional Description...................................................................................... 1
Encoder/Decoder ......................................................................................................................................... 1
Link Monitor.................................................................................................................................................. 1
Carrier Sense (CRS)/RXDV .......................................................................................................................... 2
Collision Detection....................................................................................................................................... 2
Auto-Negotiation .......................................................................................................................................... 2
Parallel Detection ......................................................................................................................................... 3
Analog Adaptive Equalizer .......................................................................................................................... 3
Clock Recovery ............................................................................................................................................ 3
Baseline Wander Correction ....................................................................................................................... 4
Multimode Transmitter ................................................................................................................................ 4
Stream Cipher Scrambler/Descrambler ..................................................................................................... 4
FEF (Far-End Fault) ...................................................................................................................................... 5
Transmit Driver............................................................................................................................................. 5
HP Auto-MDI/MDIX ....................................................................................................................................... 5
MAC Interface ............................................................................................................................................... 6
MII ........................................................................................................................................................... 6
SMI.......................................................................................................................................................... 6
Physical Layer Interfaces ............................................................................................................................ 6
Section 2: Pin Descriptions ................................................................................................ 7
Section 3: Pinout Diagram ..................................................................................................9
Section 4: Operational Description ..................................................................................10
Reset ........................................................................................................................................................... 10
Power Source ............................................................................................................................................. 10
Power Saving Mode ................................................................................................................................... 10
Clock Source .............................................................................................................................................. 11
Isolate Mode ............................................................................................................................................... 11
Loopback Mode .......................................................................................................................................... 11
Interrupt Mode ............................................................................................................................................ 11
LED Operation ............................................................................................................................................ 11
LED Interface ........................................................................................................................................ 11
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LED Configuration .................................................................................................................................12
LED [3:0] Event Table ...........................................................................................................................12
Section 5: Register Description ....................................................................................... 13
TP PHY Register Summary ........................................................................................................................13
Register 0: Control Register .................................................................................................................14
Register 1: Status Register ...................................................................................................................14
Register 2: PHY Identifier 1 Register ....................................................................................................16
Register 3: PHY Identifier 2 Register ....................................................................................................16
Register 4: Auto-Negotiation Advertisement Register ..........................................................................16
Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message ..............17
Register 6: Auto-Negotiation Expansion Register .................................................................................17
Register 7: Auto-Negotiation Next Page Transmit Register ..................................................................18
Register 16: BT and Interrupt Level Control Register............................................................................18
Register 17: Interrupt Control/Status Register.......................................................................................19
Register 18: Diagnostic Register ...........................................................................................................19
Register 19: Power/Loopback Register .................................................................................................20
Register 20: Cable Measurement Capability Register...........................................................................20
Register 21: Receive Error Counter ......................................................................................................21
Register 22: Power Management Register............................................................................................21
Register 23: Operation Mode Register ..................................................................................................21
Register 24: CRC for Recent Received Packet.....................................................................................22
Common Registers.....................................................................................................................................22
Common Register 0 (Map to Reg28) Mode Control Register................................................................22
Common Register 1: (Map to Reg. 29, Page 0 A28.[15:12]=0000) Test Mode Register ......................23
Common Register 4: (Map to Reg. 29, Page 1 A28.[15:12]=0001) LED Blink Rate .............................23
Common Register 5: (Map to Reg. 30, Page 1 A.28.[15:12]=0001) LED0 Setting1 Register ...............23
Common Register 6: (Map to Reg. 31, Page 1 A.28.[15:12]=0001) LED0 Setting2 Register ...............24
Common Register 7: (Map to Reg. 29, Page 2 A.28.[15:12]=0010) LED1 Setting1 Register ...............24
Common Register 8: (Map to Reg. 30, Page 2 A.28.[15:12]=0010) LED1 Setting2 Register ...............24
Common Register 9: (Map to Reg. 31, Page 2 A.28.[15:12]=0010) LED2 Setting1 Register ...............24
Common Register 10: (Map to Reg. 29, Page 3 A.28.[15:12]=0011) LED2 Setting2 Register .............25
Common Register 11: (Map to Reg. 30, Page 3 A.28[.15:12]=0011) LED3 Setting1 Register .............25
Common Register 12: (Map to Reg. 31, Page 3 A.28.[15:12]=0011) LED3 Setting2 Register .............25
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Preliminary Data Sheet
AC101L
8/9/04
Section 6: 4B/5B Code Group........................................................................................... 26
Section 7: SMI Read/Write Sequence............................................................................... 27
Section 8: Timing and AC Characteristics ...................................................................... 28
Clock Timing............................................................................................................................................... 28
Reset Timing............................................................................................................................................... 28
Management Data Interface timing........................................................................................................... 29
100BASE-TX/FX MII Transmit System Timing ......................................................................................... 29
100BASE-TX/FX MII Receive System Timing........................................................................................... 31
10BASE-T MII Transmit System Timing ................................................................................................... 33
10BASE-T MII Receive System Timing..................................................................................................... 34
Copper Application Termination............................................................................................................... 36
Section 9: Electrical Characteristics................................................................................ 37
Absolute Maximum Ratings ...................................................................................................................... 37
Recommended Operating Conditions...................................................................................................... 38
Section 10: Fiber Application Termination...................................................................... 39
Section 11: Power and Ground Filtering .........................................................................40
Section 12: Mechanical Information................................................................................. 41
Section 13: Thermal Parameters ...................................................................................... 42
Section 14: Ordering Information..................................................................................... 43
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AC101L
Preliminary Data Sheet
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LIST OF FIGURES
Figure 1: Functional Block Diagram ..................................................................................................................... i
Figure 2: AC101L Pinout Diagram ...................................................................................................................... 9
Figure 3: Reset Timing......................................................................................................................................28
Figure 4: Management Interface Timing ...........................................................................................................29
Figure 5: 100BASE-TX/FX MII Transmit Timing ...............................................................................................30
Figure 6: 100BASE-T MII Receive Timing ........................................................................................................32
Figure 7: 10BASE-T Transmit Timing ...............................................................................................................33
Figure 8: 10BASE-T Receive Timing ................................................................................................................35
Figure 9: TX Application....................................................................................................................................36
Figure 10: FX Application..................................................................................................................................39
Figure 11: Power and Ground Filtering .............................................................................................................40
Figure 12: Quad Flat Pack outline (7×7 mm) ....................................................................................................41
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AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
LIST OF TABLES
Table 1: Auto-Negotiation Mode......................................................................................................................... 2
Table 2: Pinout and Signal Definitions................................................................................................................ 7
Table 3: LED [3:0] Event Table ........................................................................................................................ 12
Table 4: TP PHY Register Summary................................................................................................................ 13
Table 5: Register 0: Control Register ............................................................................................................... 14
Table 6: Register 1: Status Register................................................................................................................. 14
Table 7: Register 2: PHY Identifier 1 Register.................................................................................................. 16
Table 8: Register 3: PHY Identifier 2 Register.................................................................................................. 16
Table 9: Register 4: Auto-Negotiation Advertisement Register ........................................................................ 16
Table 10: Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message ......... 17
Table 11: Register 6: Auto-Negotiation Expansion Register ............................................................................ 17
Table 12: Register 7: Auto-Negotiation Next Page Transmit Register ............................................................. 18
Table 13: Register 16: BT and Interrupt Level Control Register....................................................................... 18
Table 14: Register 17: Interrupt Control/Status Register.................................................................................. 19
Table 15: Register 18: Diagnostic Register ...................................................................................................... 19
Table 16: Register 19: Power/Loopback Register ............................................................................................ 20
Table 17: Register 20: Cable Measurement Capability Register...................................................................... 20
Table 18: Register 21: Receive Error Counter ................................................................................................. 21
Table 19: Register 22: Power Management Register....................................................................................... 21
Table 20: Register 23: Operation Mode Register ............................................................................................. 21
Table 21: Register 24: CRC for Recent Received Packet................................................................................ 22
Table 22: Common Register 0 (Map to Reg. 28) Mode Control Register......................................................... 22
Table 23: Common Register 1: (Map to Reg. 29, Page 0 A28.[15:12]=0000) Test Mode Register ................. 23
Table 24: Common Register 4: (Map to Reg. 29, Page 1 A28.[15:12]=0001) LED Blink Rate ........................ 23
Table 25: Common Register 5: (Map to Reg. 30, Page 1 A.28.[15:12]=0001) LED0 Setting1 Register .......... 23
Table 26: Common Register 6: (Map to Reg. 31, Page 1 A.28.[15:12]=0001) LED0 Setting2 Register .......... 24
Table 27: Common Register 7: (Map to Reg. 29, Page 2 A.28.[15:12]=0010) LED1 Setting1 Register .......... 24
Table 28: Common Register 8: (Map to Reg. 30, Page 2 A.28.[15:12]=0010) LED1 Setting2 Register .......... 24
Table 29: Common Register 9: (Map to Reg. 31, Page 2 A.28.[15:12]=0010) LED2 Setting1 Register .......... 24
Table 30: Common Register 10: (Map to Reg. 29, Page 3 A.28.[15:12]=0011) LED2 Setting2 Register ........ 25
Table 31: Common Register 11: (Map to Reg. 30, Page 3 A.28[.15:12]=0011) LED3 Setting1 Register ........ 25
Table 32: Common Register 12: (Map to Reg. 31, Page 3 A.28.[15:12]=0011) LED3 Setting2 Register ........ 25
Table 33: 4B/5B Code Group ........................................................................................................................... 26
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Table 34: SMI Read/Write Sequence ...............................................................................................................27
Table 35: Clock Timing .....................................................................................................................................28
Table 36: Reset Timing .....................................................................................................................................28
Table 37: Management Interface Timing ..........................................................................................................29
Table 38: 100BASE-X MII Transmit System Timing .........................................................................................29
Table 39: 100BASE-TX/FX MII Receive System Timing ..................................................................................31
Table 40: 10BASE-T MII Transmit System Timing ...........................................................................................33
Table 41: 10BASE-T MII Receive System Timing ............................................................................................34
Table 42: Absolute Maximum Ratings ..............................................................................................................37
Table 43: Current Requirement at 2.5V Operation with LED Disabled .............................................................37
Table 44: Current Requirement at 3.3V Operation with LED Disabled .............................................................37
Table 45: Recommended Operating Conditions ...............................................................................................38
Table 46: Thermal Parameters .........................................................................................................................42
Table 47: Ordering Information .........................................................................................................................43
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AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
S e c t io n 1 : F un c t i o na l D e s c r ip t io n
The AC101L is a single-chip, Fast Ethernet transceiver. It performs all of the physical layer interface functions for
100BASE-TX full-duplex or half-duplex on Category 5 twisted-pair cable, and 10BASE-T full-duplex or half-duplex on
Category 3 cable. It can be configured for 100BASE-FX full- or half-duplex transmission over fiber-optic cable when paired
with an external fiber-optic line driver and receiver.
The chip performs 4B5B, MLT3, NRZI, encoder/decoder, link monitor, auto-negotiation selection, adaptive equalization,
clock/data recovery, baseline wander correction, multimode transmitter, scrambler/descrambler, far-end fault (FEF), and
auto-MDI/MDIX. It can be connected to a MAC switch controller through the MII on one side and directly to the media on the
other side through a transformer for twisted-pair (TP) mode, or fiber-optic module for FX mode. It is fully compliant with the
IEEE 802.3 and 803.3u standards.
ENCODER/DECODER
In 100BASE-TX and 100BASE-FX modes, the AC101L transmits and receives data stream on twisted-pair or fiber-optic
cable. When the MII transmit enable is asserted, nibble wide (4-bit) data from transmit data pins is encoded into 5-bit code
groups and inserted into transmit data stream. The 4B/5B encoding is shown in Section 6: “4B/5B Code Group” on page 26.
The transmit packet is encapsulated by replacing the first 2 nibbles of preamble with a start of stream delimiter (J/K codes)
and appending an end of stream delimiter (T/R codes) to the end of packet. When the MII transmit error input is asserted
during a packet, the error code group (H) is sent in place of the corresponding data code group. The transmitter sends
repeatedly the idle code group between packets.
In 100BASE-TX mode, the encode data stream is first scrambled by a stream cipher block and then serialized and encoded
into an MLT3 signal level. Second, a multimode transmit DAC (digital to analog converter) is used to drive the MLT3 data
onto twisted-pair cable. Following baseline wander correction, adaptive equalization and clock/data recovery in 100BASETX mode, the receive data stream is converted from MLT3 to serial NRZ data. The NRZ data are descrambled by the stream
cipher block and then deserialized and aligned into 5-bit code groups.
In 100BASE-FX mode, the scrambling function is bypassed and the data are NRZII-encoded. The multi mode transmit DAC
drives differential Positive ECL (PECL) levels to an external fiber-optic transmitter. Baseline wander correction, adaptive
equalization, stream cipher descrambling functions are bypassed and NRZI decoding is used instead of MLT3.
The 5-bit code groups are decoded into 4-bit data nibbles. The start of stream delimiter is replaced with preamble nibbles
and the end of stream delimiter and idle codes are replaced with all zeros. The decoded data are driven onto the MII receive
data pins. When an invalid code group or bad SSD is detected in the data stream, the AC101L asserts the MII RXER signal.
In 10BASE-T mode, Manchester encoding and decoding is performed on the data stream. The multi mode transmit DAC
performs pre-equalization for 100 meters of Category 3 cable.
LINK MONITOR
In 100BASE-TX mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. The
signal levels are qualified using squelch detect circuits. When no signal or certain valid signal is detected on the receive pair
for a minimum period of time, the link monitor enters the link pass state, and the transmit and receive functions are enabled.
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Functional Description
Page 1
AC101L
Preliminary Data Sheet
8/9/04
In 100BASE-FX mode, the external fiber-optic receiver performs the signal energy detection function and communicates this
information directly to the SD signal (PIN 28).
In 10BASE-T mode, a link pulse detection circuit constantly monitors the RXP/RXN pins for the presence of valid link pulses.
CARRIER SENSE (CRS)/RXDV
Carrier sense is asserted asynchronously on the CRS pins as soon as activity is detected on the receive data stream. RXDV
is asserted as soon as a valid SSD (Start-of-Stream Delimiter) is detected. Carrier sense and RXDV are de-asserted
synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data
stream. However, if the carrier sense is asserted and a valid SSD is not detected immediately, RXER is asserted instead of
RXDV.
In 10BASE-T mode, CRS is asserted asynchronously when the valid preamble and data activity is detected on the RXIP and
RXIN pins.
In the half-duplex mode, the CRS is activated during data transmit. In the full-duplex mode, the CRS is activated during data
receiving only.
COLLISION DETECTION
In half-duplex mode, collision detect is asserted on the COL pin whenever carrier sense is asserted and transmission is in
progress.
AUTO-NEGOTIATION
Auto-negotiation selection is on 100BASE twisted-pair PHY only; it is not operating in 100BASE fiber PHY.
In 100BASE-TX mode, auto-negotiation can be enabled or disabled by hardware or software control. When the autonegotiation function is enabled, the 100BASE-TX PHY automatically chooses its mode of operation by advertising its abilities
and comparing them with those received from its link partner. 100BASE-TX PHY can be configured to advertise 100BASETX full-duplex or 100BASE-TX half-duplex.
The default auto-negotiation mode is configured via reset read value of ANEN/LED3 signal (pin 23) and SPD100/LED1.
Table 1: Auto-Negotiation Mode
Mode
Mode Name
Link Settings
0.13
Speed Select
The default value is SPD100.
0.12
ANEN Enable
1 = Enable Auto-negotiation.
0 = Disable Auto-negotiation.
0.8
Duplex
The default value is !ANEN && DUPLEX.
4.8/1.14
100BASE-TX Full-Duplex
The default value of this bit is SPD100 && DUPLEX.
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Carrier Sense (CRS)/RXDV
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AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Table 1: Auto-Negotiation Mode (Cont.)
Mode
Mode Name
Link Settings
4.7/1.13
100BASE-TX
The default value is SPD100 && (ANEN || !DUPLEX).
4.6/1.12
10BASE-T Full-Duplex
The default value of this bit is DUPLEX && (ANEN || !SPD100).
4.5/1.11
10BASE-T
The default value is ANEN || (!SPD100 && !DUPLEX).
PARALLEL DETECTION
Because there are many devices in the field that do not support the ANEN process, but must still be communicated with, it
is necessary to detect and link through the parallel detection process. The parallel detection circuit is enabled in the absence
of FLPs. The circuit is able to detect the following:
•
Normal link pulse (NLP)
•
10BASE-T receive data
•
100BASE-TX idle
The mode of operation gets configured based on the technology of the incoming signal. If any of the above is detected, the
device automatically configures to match the detected operating speed in the half-duplex mode. This ability allows the device
to communicate with the legacy 10BASE-T and 100BASE-TX systems, while maintaining the flexibility of auto-negotiation.
ANALOG ADAPTIVE EQUALIZER
The analog adaptive equalizer removes InterSymbol Interference (ISI) created by the transmission channel media.
The PHY is designed to accommodate a maximum of 140 meters of UTP Category 5 cable. An AT&T 1061 Category 5 cable
of this length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst
case cable attenuation is around 24–26 dB as defined by TP-PMD specification. The amplitude and phase distortion from
the cable causes ISI which makes clock and data recovery difficult. The adaptive equalizer is designed to closely match the
inverse transfer function of the twisted-pair cable. The equalizer has the ability to changes its equalizer frequency response
according to the cable length. The equalizer will tune itself automatically for any cable, compensating for the amplitude and
phase distortion introduced by the cable.
CLOCK RECOVERY
The equalized MLT3 signal passes through the slicer circuit and is converted to NRZI format. The PHY uses a proprietary
mixed-signal Phase Locked Loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock is
used to retime the data stream and set the data boundaries. The transmit clock is locked to the 25-MHz clock input while the
receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream,
extracts the 125-MHz clock, and uses it for the bit framing for the recovered data. The recovered 125-MHz clock is also used
to generate the 25-MHz RX_CLK signal. The PLL requires no external components for its operation and has high noise
immunity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time,
after power-on, is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of
signal transitions. When no valid data are present (that is, when the SD is deasserted), the PLL switches and locks on to
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Parallel Detection
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AC101L
Preliminary Data Sheet
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TX_CLK. This provides a continuously running RX_CLK. At the PCS interface, the 5-bit data RXD[4:0] is synchronized to
the 25-MHz RX_CLK.
BASELINE WANDER CORRECTION
A 100BASE-TX data stream is not always DC-balanced. Because the receive signal must pass through a transformer, the
DC offset of the differential receive input can wander. This effect, known as baseline wander, can greatly reduce the noise
immunity of the receiver. The 100BASE-TX PHY automatically compensates for baseline wander by removing the DC offset
from the input signal, thereby significantly reducing the chance of a receive symbol error.
The baseline wander circuit is not required in 100BASE-FX PHY operation.
MULTIMODE TRANSMITTER
The multimode transmitter transmits MLT3 coded symbols in 100BASE-TX mode, and NRZI coded symbols in 100BASE-FX
mode. It utilizes a current drive output, which is well balanced and produces very low noise transmit signals. PECL voltage
levels are produced with resistive terminations in 100BASE-FX mode.
The serialized data bypasses the scrambler and 4B/5B encoder in FX mode. The output data are NRZI PECL signals. The
PECL level signals are used to drive the fiber-optic transmitter.
STREAM CIPHER SCRAMBLER/DESCRAMBLER
In 100BASE-TX mode, the transmit data stream is scrambled to reduce radiated emissions on the twisted-pair cable. The
data are scrambled by exclusive ORing the NRZ signal with the output of an 11-bit wide Linear Feedback Shift register
(LFSR), which produces a 2047-bit nonrepeating sequence. The scrambler reduces peak emission by randomly spreading
the signal energy over the transmit frequency range and eliminating peaks at certain frequencies.
The receiver descrambles the incoming data stream by exclusive ORing it with the same sequence generated at the
transmitter. The descrambler detects the state of the transmit LFSR by looking for a sequence representing consecutive idle
codes. The descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code group.
The receiver does not attempt to decode the data stream unless the descrambler is locked. When locked, the descrambler
continuously monitors the data stream to make sure that it has not lost synchronization.
The receive data stream is expected to contain inter-packet idle periods. If the descrambler does not detect enough idle code
within 724 µs, it becomes unlocked and the receive decoder is disabled. The descrambler is always forced into the unlock
state when a link failure condition is detected.
Stream cipher descrambler is not used in the 100BASE-FX mode.
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Baseline Wander Correction
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AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
FEF (FAR-END FAULT)
Auto-negotiation provides the mechanism to inform the link partner that a remote fault has occurred. Auto-negotiation is
disabled, however, in the 100BASE-FX applications. An alternative in-band signaling function (FEFI) is used to signal a
remote fault condition.
FEFI is a stream of 84 consecutive ones followed by one logic zero. This pattern is repeated three times.
An FEFI signal is given under three conditions:
•
When no activity is received from the link partner.
•
When the clock recovery circuit detects a signal error or PLL lock error.
•
When a management entity sets the Transmit Far-End Fault bit.
The FEFI mechanism is enabled by default in the 100BASE-FX mode and disabled in 100BASE-TX or 10BASE-T modes.
The register setting can be changed by software after reset.
TRANSMIT DRIVER
In 100BASE-TX mode, the PHY transmit function converts synchronous 4-bit data nibbles from the MII to a pair of 125-Mbps
differential serial data streams. The serial data are transmitted over network twisted-pair cables via an isolation transformer.
Data conversion includes 4B/5B encoding, scrambling, parallel-to-serial, NRZ to NRZI, and MLT3 encoding. The entire
operation is synchronous to the 25-MHz and 125-MHz clocks. Both clocks are generated by an on-chip PLL clock
synthesizer that is locked on to an external 25-MHz clock source.
In 100BASE-FX, the transmit driver does not perform filtering; it utilizes a current drive output that is well balanced and
produces a low noise PECL signal. PECL voltage levels are produced with resistive terminations.
In 10BASE-T mode, if the MII interface is used, parallel-to-serial logic is used to convert the 4-bit data into the serial stream
through the output wave shaping driver. The wave shaper reduces any EMI emission by filtering out the harmonics, therefore
eliminating the need for an external filter.
HP AUTO-MDI/MDIX
This feature is able to detect the required cable connection type (straight-through or crossed-over) and make correction
automatically.
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AC101L-DS06-R
FEF (Far-End Fault)
Page 5
AC101L
Preliminary Data Sheet
8/9/04
MAC INTERFACE
MII
The Media Independent Interface (MII) is an 18-wire MAC/PHY interface described in IEEE 802.3u. The purpose of the
interface is to allow MAC layer devices to attach to a variety of physical layer devices through a common interface. MII
operates at either 100 Mbps or 10 Mbps, depending on the speed of the physical layer. With clocks running at either 25 MHz
or 2.5 MHz, 4-bit data are clocked between the MAC and PHY, synchronously with Enable and Error signals.
At the time of PLL lock on an incoming signal from the wire interface, the PHY generates RX_CLK at either 2.5 MHz for
10 Mbps or 25 MHz for 100 Mbps.
On receipt of valid data from the wire interface, RXDV goes active signaling the MAC that valid data will be presented on the
RXD[3:0] pins at the speed of the RX_CLK.
On transmission of data from the MAC, TXEN is presented to the PHY, indicating the presence of valid data on TXD[3:0].
TXD[3:0] are sampled by the PHY( synchronous to TX_CLK) during the time that TXEN is valid.
SMI
The PHYs internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI). MDC is a clock
input to the PHY, which is used to latch in or out data and instructions for the PHY. The clock can run at any speed from DC
to 25 MHz. MDIO is a bidirectional connection used to write instructions to, write data to, or read data from the PHY. Each
data bit is latched either in or out on the rising edge of the MDC. The MDC is not required to maintain any speed or duty
cycle, provided no half cycle is less than 20 ns, and that data are presented synchronous to the MDC.
MDC/MDIO are a common signal pair to all PHYs on a design. Therefore, each PHY needs to have its own unique physical
address. The physical address of the PHY is set using the pins defined as PHYAD[4:0]. These input signals are strapped
externally, and are sampled as reset is negated. At idle, the PHY is responsible to pull the MDIO line to a high state.
Therefore, a 1 kΩ resistor is required to connect the MDIO line to VCC.
PHYSICAL LAYER INTERFACES
The two supported interfaces are the twisted-pair (TP) interface with auto-MDI/MDIX selection, and the fiber-optic Interface
with PECL signaling.
The selection of these two interfaces is performed at reset time by the SD/FXEN signal (pin 28). Pull pin 28 LOW to enable
the TP interface, or connect pin 28 to the fiber module to enable FX interface.
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MAC Interface
Document
AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Section 2: Pin Des cr iptions
Many pins perform multiple functions. These pins are designated by a bold pin number, and their descriptions are listed in
the proper sections. Designers must verify that they have taken into account all modes of operation prior to final design.
Signal types:
•
B = Bidirection pin
•
P = Power pin
•
G = Ground pin
•
AI = Analog Input pin
•
AO = Analog output pin
•
D = Internal pull-down pin
•
U = Internal pull-up pin
•
Overline = Active low
All digital pins are bidirectional pins.
Table 2: Pinout and Signal Definitions
Pin
Pin Name Type Description
Number
1
VCC
P
+2.5V power supply.
2
GND
G
Ground.
2
GND
G
Ground.
3
RXDV
BD
RXDV (active HIGH output): Receive Data Valid is the output signal in the MII mode. RXDV is active HIGH to indicate that
the receive frame is in progress, and that the data stream present on the RXD output pins is valid.
4
RX_CLK
BD
Input function is reserved. This pin must be pulled low externally.
RX_CLK (Output): Receive clock in MII mode. RX_CLK is 25-MHz output in 100BASE and 2.5 MHz output in 10BASE. This
clock is recovered from the incoming data on the cable inputs.
5
RXER
BD
Input function is reserved. This pin must be pulled low externally.
RXER (active HIGH output): asserted to indicate that an invalid symbol or bad SSD is detected in MII modes.
6
GND
G
Ground.
7
VCC
P
+2.5V power supply.
8
TXER
BD
TXER (active HIGH input): Transmits an error in the MII interface. When TXER is asserted for one or more TX_CLK periods
while TXEN is also asserted, the PHY emits one or more symbols that are not part of the valid data or delimiter set
somewhere in the frame being transmitted. The relative position of the error within the frame need not be preserved.
9
TX_CLK
BD
TX_CLK (output): Transmits the clock signal of the MII mode. TX_CLK is
25-MHz output in 100BASE operation and 2.5-MHz in 10BASE operation. This clock is a continuously-driven output,
generated from the XI (crystal input) pin.
10
TXEN
BD
TXEN (active HIGH input): Transmits the Enable signal in the MII interfaces. TXEN is asserted by the MAC to indicate that
valid data are present on TXD[3:0].
11
TXD0
BD
TXD0: Transmits data input for the MII interface.
12
TXD1
BD
TXD1: Transmits data input for the MII interface.
13
TXD2
BD
TXD2: Transmits data input for the MII interface.
14
TXD3
BD
TXD3: Transmits data input for MII interface.
15
COL
BD
COL (active HIGH output): This pin must be pulled low externally. It is the collision detect signal in the MII interface. In halfduplex mode, COL active HIGH output indicates that a collision has occurred. In full-duplex mode, COL remains low.
16
REPEATER/
CRS
BD
REPEATER: Resets read input. Active HIGH puts the chip in repeater mode.
CRS (active HIGH output): Carrier sense signal in the MII interface. CRS is asserted when the twisted-pair media is nonidle and is deasserted when idle, or when a valid end-of-stream delimiter is detected.
17
GND
G
Ground.
18
VCC
P
+2.5V power supply.
19
PHYAD0/
INTR
BU
PHYAD0: Resets read input. Pull high or low to set the PHY Address bit 0 for the MII management function.
INTR (output): Active low Interrupt output. Cleared by reading register 17.
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Pin Descriptions
Page 7
AC101L
Preliminary Data Sheet
8/9/04
Table 2: Pinout and Signal Definitions (Cont.)
Pin
Pin Name Type Description
Number
20
BURNIN/
LED0
BU
BURNIN: Resets read input. Set Active LOW to put the chip in burn-in test mode.
LED0 (output): active LOW, the default behavior is ON when the chip is in link-up condition, and is BLINK when the chip
detects transmit or receive activity.
21
SPD100/
LED1
BU
SPD100: Resets read input.
If ANEN is Low, SPD100 sets the TP port speed in register 0.
If ANEN is High, SPD100 is used to set 100 Mbps half-duplex and 100 Mbps full-duplex bits in register 4.
LED1 (output): active LOW. The default behavior is ON when the chip is operating at 100 Mbps and is OFF when the chip
is operating at 10 Mbps.
22
DUPLEX/
LED2
BU
DUPLEX: Resets read input.
If ANEN is Low, DUPLEX sets the TP port in full-duplex mode in register 0.
If ANEN is High, DUPLEX is used to set 10 Mbps FDX and 100 Mbps FDX bits in register 4.
LED2 (output): active LOW. The default behavior is ON when the chip is operating in full-duplex mode and is OFF when
the chip is operating in half-duplex mode.
23
ANEN/LED3
BU
ANEN (resets read input): Auto-negotiation enable for the twisted-pair port. Pull high to enable auto-negotiation. Pull low to
disable auto-negotiation.
LED3 (output): active LOW. The default behavior is BLINK when the chip detect collision is in half-duplex mode.
24
PDOWN
BU
PDOWN (input): Power-down input. This pin must be pulled high externally for normal operation. Pulling this pin low puts
both the TP and fiber port into power-down mode. This is a regular input, not a reset read signal.
25
VCC
P
+2.5V power supply.
26
RXN
A
Receive. For TP port in MDI mode.
Transmit. For TP port in MDIX mode.
27
RXP
A
Receive +. For TP port in MDI mode.
Transmit +. For TP port in MDIX mode.
28
SD/FXEN
AI
SD/FXEN (analog input): This pin must be pulled low externally for normal TP mode.
Connect to fiber module to enable FX mode; also serves as signal detect input.
29
GND
G
Ground.
30
GND
G
Ground.
31
RBIAD
A
Bias resistor connection. Connect to a 10K 1% resistor to GND.
32
VCCPLL
P
+2.5V supply for analog bias, PLL modules.
33
GND
G
Ground.
34
TXN
A
Transmit. In MDI mode.
Receive. In MDIX mode.
35
TXP
A
Transmit +. In MDI mode.
Receive +. In MDIX mode.
36
VCC25OUT
P
+2.5VCC out from the on-chip regulator.
37
GND
G
Ground.
38
GND
G
Ground.
39
XO
A
XTAL output.
40
XI
A
XTAL input.
In MII Mode: XI and XO is designed to connect to a 25 MHz., 50 PPM XTAL or 25 MHz OSC.
41
VCC33IN
P
3.3V Power supply input.
42
RST
IU
Reset input. active LOW.
43
MDIO
BU
MDIO (input/ output): Management data I/O. This serial input/output pin is used to read from and write to the MII register.
The data value on the MDIO pin is valid and latched on the rising edge of the MDC. This pin requires a 1 kΩ resistor pull-up.
44
MDC
ID
MDC (input): Management data clock. This pin must be pulled low externally for normal operation. The MDC clock input
must be provided to allow MII management function. This pin has a Schmitt trigger input.
45
PHYAD1/
RXD3
BD
PHYAD1: Resets read input. Pull high or low to set the PHY Address bit 1 for MII management function.
RXD3: Receives the data output signal in the MII interface.
46
PHYAD2/
RXD2
BD
PHYAD2: Resets read input. Pull high or low to set the PHY Address bit 2 for MII management function.
RXD2: Receives the data output signal in the MII interface.
47
PHYAD3/
RXD1
BD
PHYAD3 (Reset Read Input): Pull High or Low to set the PHY Address bit 3 for MII management function.
RXD1: Receive data output signal in MII interface.
48
PHYAD4/
RXD0
BD
PHYAD4: Resets read input. Pull high or low to set the PHY Address bit 4 for MII management function.
RXD0: Receives the data output signal in the MII interface.
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Pin Descriptions
Document
AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
GND
VCC33IN
41
GND
RST#
42
37
MDIO
43
38
MDC
44
XI
PHYAD1/RXD3
45
XO
PHYAD2/RXD2
46
39
PHYAD3/RXD1
47
40
PHYAD4/RXD0
48
S e c t i on 3 : P i n ou t D ia gr a m
VCC
1
36
VCC25OUT
10
27
RXP
TXD0
11
26
RXN
TXD1
12
25
VCC
TXD2
24
TXEN
23
SD/FXEN
PDOWN#
TXC
ANEN/LED3
GND
28
22
29
9
21
8
SPD100/LED1
TXER
DUPLEX/LED2
GND
20
RBIAD
30
19
31
48TQFP_7x7mm
PHYAD0/INTR
AC101L
7
BURNIN#_L/LED0
6
VCC
18
GND
VCC
VCCPLL
17
GND
32
16
33
5
GND
4
RXER
REPEATER/CRS
RX_CLK
15
TXN
14
TXP
34
COL
35
3
TXD3
2
13
GND
RXDV
Figure 2: AC101L Pinout Diagram
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Pinout Diagram
Page 9
AC101L
Preliminary Data Sheet
8/9/04
S ec t io n 4 : O pe rat i o na l De scr ip t io n
RESET
The PHY can be reset in two ways:
•
Hardware reset: (See “Pin Descriptions” on page 7).
•
Software reset: (See “Register Description” on page 13).
POWER SOURCE
The AC101L chip provides an onboard 3.3V ±5% input to 2.5V ±5% output regulator with the capability to drive 150 mA of
current. The 2.5V output supplies the PHY operation, including the LEDs. It is recommended to limit the LED current below
10 mA per LED.
The 2.5V power should be decoupled to provide the digital and analog pins on the chip.
POWER SAVING MODE
The power consumption of the AC101L device is significantly reduced due to its built-in power management features.
Separate power supply lines are used to power the 10BASE-T circuitry and the 100BASE-TX circuitry. Therefore, the two
circuits can be turned on and turned off independently. When the PHY is set to operate in 100BASE-TX mode, 10BASE-T
circuitry is powered down.
The following power management features are supported:
•
Power-down mode: (see pin and register descriptions). During power down mode, the device is still able to interface
through the management interface.
•
Energy detect/power saving mode: Energy detect mode turns off the power to select internal circuitry when there is
no live network connected. The energy detect (ED) circuit is always turned on to monitor if there is signal energy
present on the media. The management circuitry is also powered on and ready to respond to any management
transaction. The transmit circuit still sends out link pulses with minimum power consumption. If a valid signal is received
from the media, the device powers up and resumes normal transmit/receive operations.
•
Valid data detection mode: This can be achieved by writing to the Receive Clock Register control bit. During this
mode, if there is no data other than incoming idles, the receive clock (RX_CLK) turns itself off. This could save the
power of the attached media access controller. RX_CLK resumes operation one clock period prior to the assertion of
RXDV. The receive clock again shuts off 64 clock cycles after RXDV is deasserted.
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Operational Description
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
CLOCK SOURCE
The clock source for this chip is from the XI pin. In MII mode, it can connect to a 25 MHz 50 ppm (parts per million) OSC or
a 25 MHz 50 ppm XTAL (crystal).
ISOLATE MODE
When the AC101L device is put into isolate mode, all MII inputs (TXD[3:0}, TXEN, TXER) are ignored, and all MII outputs
(TX_CLK, COL, CRS, RX_CLK, RXDV, RXER, RXD[3:0] are set to high impedance. Only the MII management pins (MDC,
MDIO) operate normally. Pull HIGH pin 4 at reset or write 1 to bit 10 register 0 to put the chip into isolate mode.
LOOPBACK MODE
Local loopback is provided for testing purpose. It can be enabled by writing a one to register 0 bit 14.
The local loopback routes transmitted data through the transmit path back to the clock and data recovery module of the
receiving path. The loopback data are presented to the PCS in 5-bit symbol format. This loopback is used to check the
operation of the 5-bit symbol decoder and the phase lock loop circuitry. In local loopback, the SD output is forced to a logical
1 and TXOP/N outputs are tristated.
INTERRUPT MODE
The INTR pin on the PHY is asserted whenever 1 of 8 selectable interrupt events occurs. The assertion state is high or low
and is programmable through the INTR_LEVL register bit. The selection is made by setting the appropriate bit in the upper
half of the Interrupt Control/Status register. When the INTR bit goes active, the MAC interface is required to read the Interrupt
Control/Status register to determine which event caused the interrupt. The Status bits are read-only and clear-on-read.
When INTR is not asserted, the pin is held in a high impedance state.
LED OPERATION
LED INTERFACE
The LED interface is fully configurable through register setting. The connection of LED (source/sink current) depends on the
default setting.
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Clock Source
Page 11
AC101L
Preliminary Data Sheet
8/9/04
The default LED modes are as shown below:
LED0
LED1
LED2
LED3
Link/Activity
Speed
Duplex
Collision
LED CONFIGURATION
The LEDs are fully configurable to other operational modes. Each LED has two 16-bit registers to define its operation. See
“Common Registers” on page 22 and Table 3 below to configure the LEDs to work with operational modes other than default
mode.
LED [3:0] EVENT TABLE
LED [3:0] are configurable. The following events are defined for AC101L operation:
Table 3: LED [3:0] Event Table
Bit#
Description
7
6
5
4
3
2
1
0
Duplex
Collision
Speed 100
Speed 10
Transmit activity
Transmit/Receive activity
Receive activity
Link
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LED Operation
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
S e ct io n 5 : R eg is te r Des cri p t io n
The first 7 registers of the MII register set are defined by the MII specification. In addition to these required registers there
are several registers specific to Altima Communications Inc. There are reserved registers and/or bits that are for Altima
internal use only. The following standard registers are supported (register numbers are in decimal notation; the values are
in hexadecimal notation):
When writing to registers, it is recommended that a read/modify/write operation be performed, as
unintended bits may get set to unwanted states. This applies to all registers, including those with reserved
bits.
Legend:
•
RW = Read and write access
•
SC = Self-clearing
•
LL = Latch low until cleared by reading
•
RO = Read-only
•
RC = Cleared on read
•
LH = Latch high until cleared by reading
TP PHY REGISTER SUMMARY
Table 4: TP PHY Register Summary
Register
Description
Default Value
Control register
Status register
PHY Identifier 1 register
PHY Identifier 2 register
Auto-Negotiation Advertisement register
Auto-Negotiation Link Partner Ability register
Auto-Negotiation Expansion register
Next Page Advertisement register
3000
7849
0022
5521
01E1
0001
0004
2001
Reserved
BT and Interrupt Level Control register
Interrupt Control/Status register
Reserved
Cable Measurement Capability register
Receive Error Counter register
Reserved
XXXX
1800
0000
XXXX
XXXX
0304
XXXX
Registers 0–7
0
1
2
3
4
5
6
7
Registers 8–31
8–15
16
17
18,19
20
21
22–31
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Register Description
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AC101L
Preliminary Data Sheet
8/9/04
REGISTER 0: CONTROL REGISTER
Table 5: Register 0: Control Register
Bit
Name
Description
Mode
Default
0.15
Reset
RW/
SC
0
0.14
Loopback
RW
0
0.13
Speed
Select
RW
Set by
SPD100
0.12
ANEN
Enable
RW
Set by
ANEN
0.11
Power
Down
RW
0
0.10
Isolate
RW
0
0.9
Restart
ANEN
RW/
SC
0
0.8
Duplex
Mode
RW
See
descriptio
n
0.7
Collision
Test
RW
0
0.[6:0
]
Reserved
1 = PHY reset.
This bit is self-clearing.
1 = Enable loopback mode. This loops back TXD to RXD and ignores all of the
activity on the cable media.
0 = Normal operation.
1 = 100 Mbps.
0 = 10 Mbps.
Default value:
SPD100
1 = Enable the auto-negotiate process (overrides 0.13 and 0.8).
0 = Disable the auto-negotiate process.
Mode selection is controlled via bit 0.8, 0.13.
Default value:
ANEN
1 = Power down. All blocks except for SMI will be turned off.
Setting PDOWN pin (24) to LOW will achieve the same result.
0 = Normal operation.
1 = N/A.
0 = Normal operation.
1 = Restart auto-negotiation process.
0 = Normal operation.
1 = Full-duplex operation.
0 = Half-duplex operation.
Default value:
!ANEN && DUPLEX
1 = Enable collision test that issues the COL signal in response to the assertion
of the TXEN signal. Collision test is disabled if the PCSBP pin is high. Collision
test is enabled regardless of the duplex mode.
0 = Disable COL test.
–
RW
0000000
REGISTER 1: STATUS REGISTER
Table 6: Register 1: Status Register
Bit
Name
Description
Mode
Default
1.15
1.14
100BASE-T4
100BASE-TX
Full-Duplex
Permanently tied to zero; indicates no 100BASE-T4 capability.
1 = 100BASE-TX full-duplex capable.
0 = Not 100BASE-TX full-duplex capable.
Default value:
SPD100 && DUPLEX
RO
RO
0
See
description
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TP PHY Register Summary
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Table 6: Register 1: Status Register (Cont.)
Bit
Name
Description
Mode
Default
1.13
100BASE-TX
Half-Duplex
RO
See
description
1.12
10BASE-T
Full-Duplex
RO
See
description
1.11
10BASE-T
Half-Duplex
RO
See
description
1.[10:7]
1.6
Reserved
MF Preamble
Suppression
RO
RO
0000
1
1.5
ANEN
Complete
RO
0
1.4
Remote Fault
RO/LH
0
1.3
ANEN Ability
RO
Set by
ANEN
1.2
Link Status
RO/LL
0
1.1
Jabber Detect
RO/LH
0
1.0
Extended
Capability
1 = 100BASE-TX half-duplex capable.
0 = Not TX half-duplex capable.
Default value:
SPD100 && (ANEN || !DUPLEX).
1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.
Default value:
DUPLEX && (ANEN || !SPD100).
1 = 10BASE-T half-duplex capable.
0 = Not 10BASE-T half-duplex capable.
Default value:
ANEN || (!SPD100 && !DUPLEX).
–
The PHY is able to perform management transaction without MDIO
preamble. The management interface needs a minimum of 32 bits
of preamble after reset.
1 = Auto-negotiation process completed. Registers 4, 5, and 6 are
valid after this bit is set.
0 = Auto-negotiation process is not completed.
1 = Remote fault condition detected.
0 = No remote fault.
This bit remains set until it is cleared by reading register 1.
1 = Able to perform the auto-negotiation function; default value is
determined by the ANEN pin.
0 = Unable to perform the auto-negotiation function.
1 = Link is established. If the link fails, this bit clears and remains
at 0 until the register is read again.
0 = Link is down.
1 = Jabber condition detected.
0 = No Jabber condition detected.
1 = Extended register capable. This bit is tied permanently to a
value of 1.
RO
1
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TP PHY Register Summary
Page 15
AC101L
Preliminary Data Sheet
8/9/04
REGISTER 2: PHY IDENTIFIER 1 REGISTER
Table 7: Register 2: PHY Identifier 1 Register
Bit
Name
2.[15:0]
a
OUI
Description
Mode
Default
Composed of bits 3 —18 of the Organizationally Unique
Identifier (OUI), respectively.
RO
0022(H)
a. Based on an OUI of 0010A9 (hexadecimal)
REGISTER 3: PHY IDENTIFIER 2 REGISTER
Table 8: Register 3: PHY Identifier 2 Register
Bit
Name
Description
Mode
Default
3.[15:10]
OUIa
Model Number
Revision
Number
Assigned to bits 19 — 24 of the OUI.
RO
010101
6-bit manufacturer’s model number.
4-bit manufacturer’s revision number.
RO
RO
010010
0001
3.[9:4]
3.[3:0]
a. Based on an OUI of 0010A9 (hexadecimal)
REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table 9: Register 4: Auto-Negotiation Advertisement Register
Bit
Name
Description
Mode
Default
4.15
Next Page
RW
0
4.14
Acknowledge
RO
0
4.[13:11]
4.10
Reserved
FDFC
4.9
4.8
100BASE-T4
100BASE-TX
Full-Duplex
RO
RW
0
See
description
4.7
100BASE-TX
RW
See
description
4.6
10BASE-T Full
Duplex
1 = Next Page enabled.
0 = Next Page disabled.
This bit is set internally after receiving 3 consecutive and
consistent FLP bursts.
–
Full-duplex flow control.
1 = Advertise that the DTE (MAC) has implemented both the
optional MAC control sublayer and the pause function as
specified in Clause 31 and Annex 31B of IEEE 802.3u.
0 = MAC does not support flow control.
Technology not supported. This bit is always 0.
1 = 100BASE-TX full-duplex capable.
0 = Not 100BASE-TX full-duplex capable.
Default value:
SPD100 && DUPLEX.
1 = 100BASE-TX half-duplex capable.
0 = Not TX half-duplex capable.
Default value:
SPD100 && (ANEN || !DUPLEX).
1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.
Default value:
DUPLEX && (ANEN || !SPD100).
RW
See
description
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TP PHY Register Summary
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Table 9: Register 4: Auto-Negotiation Advertisement Register (Cont.)
Bit
Name
Description
Mode
Default
4.5
10BASE-T
RW
See
Descriptio
n
4.[4:0]
Selector Field
1 = 10BASE-T half-duplex capable.
0 = Not 10BASE-T half-duplex capable.
Default value:
ANEN || (!SPD100 && !DUPLEX).
Protocol selection [00001] = IEEE 802.3.
RO
00001
REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER/LINK PARTNER NEXT
PAGE MESSAGE
Table 10: Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message
Bit
Name
Description
Mode
Default
5.15
Next Page
RO
0
5.14
Acknowledge
RO
0
5.[13:10]
5.9
Reserved
100BASE-T4
RO
0
5.8
100BASE-TX
Full Duplex
RO
0
5.7
100BASE-TX
RO
0
5.6
10BASE-T Full
Duplex
RO
0
5.5
10BASE-T
RO
0
5.[4:0]
Selector Field
1 = Link partner desires a Next Page transfer.
0 = Link partner does not desire Next Page transfer.
1 = Link Partner acknowledges reception of FLP words.
0 = Not acknowledged by the link partner.
–
1 = 100BASE-T4 operation supported by the link partner.
0 = 100BASE-T4 operation not supported by the link partner.
1 = 100BASE-TX full-duplex operation supported by the link partner.
0 = 100BASE-TX full-duplex operation not supported by the link
partner.
1 = 100BASE-TX half-duplex operation supported by the link
partner.
0 = 100BASE-TX half-duplex operation not supported by the link
partner.
1 = 10 Mbps full-duplex operation supported by the link partner.
0 = 10 Mbps full-duplex operation not supported by the link partner.
1 = 10 Mbps half-duplex operation supported by the link partner.
0 = 10 Mbps half-duplex operation not supported by the link partner.
Protocol Selection [00001] = IEEE 802.3.
RO
00001
Note: When this register is used as the Next Page message, the bit definition is the same as that of register 7.
REGISTER 6: AUTO-NEGOTIATION EXPANSION REGISTER
Table 11: Register 6: Auto-Negotiation Expansion Register
Bit
Name
Description
Mode
Default
6.[15:5]
Reserved
–
RO
0
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TP PHY Register Summary
Page 17
AC101L
Preliminary Data Sheet
8/9/04
Table 11: Register 6: Auto-Negotiation Expansion Register (Cont.)
Bit
Name
Description
Mode
Default
6.4
Parallel
Detection Fault
RO/LH
0
6.3
Link Partner
Next Page Able
RO
0
6.2
6.1
Next Page Able
Page Received
RO
RC
1
0
6.0
Link Partner
ANEN-Able
1 = Fault detected by parallel detection logic; this fault is due to
more than one technology detecting a concurrent link-up
condition. This bit can only be cleared by reading register 6,
using the management interface.
0 = No fault detected by parallel detection logic.
1 = Link partner supports Next Page function.
0 = Link partner does not support Next Page function.
Next page is supported.
This bit is set when a new link code word has been received into
the Auto-Negotiation Link Partner Ability register. This bit is
cleared upon a read of this register.
1 = Link partner is auto-negotiation capable.
0 = Link partner is not auto-negotiation capable.
RO
0
REGISTER 7: AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table 12: Register 7: Auto-Negotiation Next Page Transmit Register
Bit
Name
Description
Mode
Default
7.15
NP
RW
0
7.14
7.13
Reserved
MP
RO
RW
0
1
7.12
ACK2
RW
0
7.11
TOG_TX
RW
0
17.[10:0]
CODE
1 = Another Next Page desired.
0 = No other Next Page transmit desired.
–
1 = Message page.
0 = Unformatted page.
1 = Will comply with message.
0 = Cannot comply with message.
1 = Previous value of transmitted link code word equals to 0.
0 = Previous value of transmitted link code word equals to 1.
Message/Unformatted Code field.
RW
001
REGISTER 16: BT AND INTERRUPT LEVEL CONTROL REGISTER
Table 13: Register 16: BT and Interrupt Level Control Register
Bit
Name
Description
Mode
Default
16.15
Repeater
RW
16.14
16.13
Reserved
TXJAM
RW
RW
Set by
Repeater
0
0
16.12
16.11
Reserved
SQE Test
Inhibit
RO
RW
1
0
16.[10:6]
Reserved
1 = Repeater mode. Full-duplex is inactive, and CRS only
responds to receive activity. SQE test function is disabled.
1 = Forces CIM to send JAM pattern.
0 = Normal operation.
1 = Disable 10BASE-T SQE testing.
0 = Enable 10BASE-T SQE testing, which generates a COL
pulse following the completion of a packet transmission.
–
RO
0
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TP PHY Register Summary
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Table 13: Register 16: BT and Interrupt Level Control Register (Cont.)
Bit
Name
Description
Mode
Default
16.5
Autopolarity
Disable
RW
0
16.4
Reverse
Polarity
RW
0
16.[3:0]
Reserved
1 = Disables autopolarity detection/correction.
0 = Enables autopolarity detection/correction.
1 = Reverses polarity when register 16.5 = 0.
0 = Normal polarity when register 16.5 = 0.
If register 16.5 is set to 1, writing a 1 to this bit reverses the
polarity of the transmitter.
–
RO
0
REGISTER 17: INTERRUPT CONTROL/STATUS REGISTER
Table 14: Register 17: Interrupt Control/Status Register
Bit
Name
Description
Mode
Default
17.15
17.14
17.13
17.12
17.11
17.10
Jabber interrupt enable.
Receive error interrupt enable.
Page received interrupt enable.
Parallel detection fault interrupt enable.
Link partner acknowledge interrupt enable.
Link status change interrupt enable.
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
17.9
17.8
17.7
17.6
17.5
17.4
17.3
Jabber_IE
RXER_IE
Page_Rx_IE
PD_Fault_IE
LP_Ack_IE
Link_Status_Change_I
E
R_Fault_IE
ANEN_Comp_IE
Jabber_Int
RXER_Int
Page_Rx_Int
PD_Fault_Int
LP_Ack_Int
RW
RW
RC
RC
RC
RC
RC
0
0
0
0
0
0
0
17.2
Link_Not_OK Int
RC
0
17.1
17.0
R_Fault_Int
ANEN _Comp Int
Remote fault interrupt enable.
Auto-negotiation complete interrupt enable.
This bit is set when a jabber event is detected.
This bit is set when RXER transitions HIGH.
This bit is set when a new page is received during ANEN.
This bit is set when parallel detect fault is detected.
This bit is set when the FLP with acknowledge bit set is
received.
This bit is set when link status switches from OK status to
Non-OK status (fail or ready).
This bit is set when remote fault is detected.
This bit is set when ANEN is complete.
RC
RC
0
0
REGISTER 18: DIAGNOSTIC REGISTER
Table 15: Register 18: Diagnostic Register
Bit
Name
Description
Mode
Default
18.[15]
18.[14]
18.[13]
Reserved
Reserved
Force Link Pass 10BT
RW
RW
RW
0
0
0
18.[12]
Force Link Pass
100TX
RW
0
18.11
Reserved
Reserved.
Reserved.
1 = Enables force link pass 10BASE-T.
0 = Disables force link pass 10BASE-T.
1 = Force link pass 100BASE-TX.
0 = Disable Force link pass 100BASE-TX.
Reserved.
RO
0
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TP PHY Register Summary
Page 19
AC101L
Preliminary Data Sheet
8/9/04
Table 15: Register 18: Diagnostic Register (Cont.)
Bit
Name
Description
Mode
Default
18.10
18.9
18.8
18.[7:0]
Reserved
Reserved
Reserved
Reserved
Reserved.
Reserved.
Reserved.
Reserved.
RO
RO
RO/RC
RO
0
0
0
0
REGISTER 19: POWER/LOOPBACK REGISTER
Table 16: Register 19: Power/Loopback Register
Bit
Name
Description
Mode
Default
19.[14:7]
19.6
19.5
Reserved
Reserved
Disable
Watchdog
Timer for
Decipher
Low Power
Mode Disable
Reserved.
Reserved.
1 = Disables watchdog timer.
0 = Enables advanced power saving mode.
RW
RW
RW
00
0
0
0 = Enables advanced power saving mode.
1 = Disables advanced power saving mode. (Do not enable this
bit during normal operation).
Reserved.
Reserved.
1 = In auto-negotiation test mode, sends NLP instead of FLP to
test NLP receive integrity.
0 = Sends FLP in auto-negotiation test mode.
1 = Disables jabber.
RW
0
RW
RW
RW
0
0
0
RW
0
19.4
19.3
19. 2
19.1
Reserved
Reserved
NLP Link
Integrity Test
19.0
Jabber Disable
REGISTER 20: CABLE MEASUREMENT CAPABILITY REGISTER
Table 17: Register 20: Cable Measurement Capability Register
Bit
Name
Description
Mode
Default
20.15
20.14
Reserved
Reserved
RW
RW
1
1
20.[13:9]
Reserved
Adaptation
Disable
Reserved.
1 = On.
0 = Off.
Reserved.
1 = Disables adaptation.
0 = Enables adaptation.
These bits can be used as a cable length indicator. The bits are
incremented from 0000 to 1111, with an increment of
approximately 10 meters. The equivalent is 0 to 32 dB with an
increment of 2 dB @ 100 MHz. The value is a read back from
the equalizer, and the measured value is not absolute.
Reserved.
RO
RW
0
0
RW
X
RO
X
a20.8
20.[7:4]
Cable
Measurement
Capability
20.[3:0]
Reserved
a. To set the value of 20.[7:4], you must turn on bit 20.8 and turn off bit 20.14. Otherwise, this PHY rejects receive packets.
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TP PHY Register Summary
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
REGISTER 21: RECEIVE ERROR COUNTER
Table 18: Register 21: Receive Error Counter
Bit
Name
Description
Mode
Default
21.[15:0]
RXER Counter
Counts Receive Error events.
RO
0
REGISTER 22: POWER MANAGEMENT REGISTER
Table 19: Register 22: Power Management Register
Bit
Name
Description
Mode
Default
22.[15:14]
22.13
22.12
22.11
22.10
22.9
22.8
22.[7:6]
22.5
Reserved
PD_PLL
PD_EQUAL
PD_BT_RCVR
PD_LP
PD_EN_DET
PD_FX
Reserved
MSK_PLL
RO
RO
RO
RO
RO
RO
RO
RW
RW
00
X
X
X
X
X
X
00
1
22.4
22.3
22.2
22.1
22.0
MSK_EQUAL
MSK_BT_RCVR
MSK_LP
MSK_EN_DET
MSK_FX
–
1 = PLL circuit powers down.
1 = Equalizer circuit powers down.
1 = 10BASE-T receiver powers down.
1 = Link pulse receiver powers down.
1 = Energy-detect circuit powers down.
1 = FX circuit powers down.
–
0 = Forces PLL circuit to power up.
1 = PLL circuit auto power-down.
0 = Forces equalizer circuit to power up.
0 = Forces 10BASE-T receiver to power up.
0 = Forces link pulse receiver to power up.
0 = Forces energy-detect circuit to power up.
0 = Forces FX circuit to power up.
RW
RW
RW
RW
RW
X
X
X
X
X
REGISTER 23: OPERATION MODE REGISTER
Table 20: Register 23: Operation Mode Register
Bit
Name
Description
Mode
23.[15:14]
23.13
Reserved
Clk_rclk_save
23.12
23.11
Reserved
Scramble
Disable
23.10
23.9
Reserved
Pcsbp
23:8
23.7
Reserved
Auto-MDIX
disable
–
1 = Sets rclk save mode. Rclk shuts off after 64 cycles of each
packet.
–
1 = Disables scrambler.
0 = Enables scrambler.
–
1 = Enables PCS bypass mode.
0 = Disables PCS bypass mode.
–
0 = Auto-MDIX mode.
1 = Disable Auto-MDIX mode.
Default
0
RW
0
RW
RW
0
0
RW
RW
0
0
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TP PHY Register Summary
Page 21
AC101L
Preliminary Data Sheet
8/9/04
Table 20: Register 23: Operation Mode Register (Cont.)
Bit
Name
Description
Mode
Default
23.6
MDIX state
RW
0
23.5
23.[4:0]
Reserved
Reserved
Only valid when register 23.7 is set to 1.
0 = MDI
1= MDIX
–
–
RO
RO
0
XXXXX
REGISTER 24: CRC FOR RECENT RECEIVED PACKET
Table 21: Register 24: CRC for Recent Received Packet
Bit
Name
Description
Mode
Default
24.[15:0]
CRC16
Displays CRC16 value. For system-level test purposes.
RC
0000H
COMMON REGISTERS
The following registers are mapped to Reg28-31 on the TP PHY. Reg28.[15:12] is used as page selection. There are multiple
pages of Reg29-31, depends on the value of Reg28[15:12].
COMMON REGISTER 0 (MAP TO REG28) MODE CONTROL REGISTER
Table 22: Common Register 0 (Map to Reg. 28) Mode Control Register
Bit
Name
Description
Mode
Default
A.28.[15:12
]
A.28.[11:7]
A.28.6
A.28.5
A.28.4
A.28.3
A.28.2
Page Selection
Selects multiple common register pages.
RW
0000
Reserved
MII_enable
Reserved
Reserved
Reserved
Act select
RO
RW
RO
RW
RO
RW
0000
1
0
0
0
1
A.28.1
A.28.0
Reserved
Reserved
Reserved.
1 = Enables MII interface.
Reserved.
Reserved.
Reserved.
Selects activity event.
0 = Receive activity.
1 = TX or RX activity.
–
–
RO
RO
0
0
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Page 22
Common Registers
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
COMMON REGISTER 1: (MAP TO REG. 29, PAGE 0 A28.[15:12]=0000) TEST MODE REGISTER
Table 23: Common Register 1: (Map to Reg. 29, Page 0 A28.[15:12]=0000) Test Mode Register
Bit
Name
Description
Mode
Default
A0.29.15
Reduces millisecond counter to 256 microseconds.
RO
0
A0.29.[14:10
]
A0.29.[9:8]
A0.29.[7:4]
A0.29.3
Reduce_mcou
nt
Reserved
–
RO
00100
Reserved
Test Mode
Burn In
RW
RW
RW
00
0000
0
A0.29.2
Output Disable
RW
0
A0.29.1
A0.29.0
Reserved
Reduce Timer
–
0000 = Normal operation.
1 = Enables burn-in test mode.
0 = Normal operation.
1 = Disables all digital output.
0 = Normal operation.
0 = Normal operation.
1 = Reduces timer for auto-negotiation testing.
0 = Normal operation.
RW
RW
0
0
COMMON REGISTER 4: (MAP TO REG. 29, PAGE 1 A28.[15:12]=0001) LED BLINK RATE
Table 24: Common Register 4: (Map to Reg. 29, Page 1 A28.[15:12]=0001) LED Blink Rate
Bit
Name
Description
Mode
Default
A1.29.[15:8]
A1.29.[7:0]
Reserved
Blink Rate
–
Set LED blink rate. The blink rate is this number × 16 ms.
Default value is 256 ms.
RO
RW
00000000
00010000
COMMON REGISTER 5: (MAP TO REG. 30, PAGE 1 A.28.[15:12]=0001) LED0 SETTING1
REGISTER
Default operation for LED0 is ON when Link; BLINK when Activity.
Table 25: Common Register 5: (Map to Reg. 30, Page 1 A.28.[15:12]=0001) LED0 Setting1 Register
Bit
Name
Description
Mode
Default
A1.30.[15:13]
A1.30.12
A1.30.[11:9]
A1.30.8
A1.30.[7:0]
Reserved
Force LED On
Reserved
Force LED Off
Msk Blink
–
Forces LED0 on.
–
Forces LED0 off.
Blink mask. When the bits are set to 1, a corresponding event
causes the LED to blink.
RW
RW
RW
RW
RW
0000
0
000
0
00000100
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AC101L-DS06-R
Common Registers
Page 23
AC101L
Preliminary Data Sheet
8/9/04
COMMON REGISTER 6: (MAP TO REG. 31, PAGE 1 A.28.[15:12]=0001) LED0 SETTING2
REGISTER
Table 26: Common Register 6: (Map to Reg. 31, Page 1 A.28.[15:12]=0001) LED0 Setting2 Register
Bit
Name
Description
Mode
Default
A1.31. [15:8]
Msk On
RW
00000001
A1.31. [7:0]
Msk Off
On mask. When the bits are set to 1, a corresponding event
causes the LED to turn on.
Off mask. When the bits are set to 1, a corresponding event
causes the LED to turn off.
RW
00000000
COMMON REGISTER 7: (MAP TO REG. 29, PAGE 2 A.28.[15:12]=0010) LED1 SETTING1
REGISTER
Table 27: Common Register 7: (Map to Reg. 29, Page 2 A.28.[15:12]=0010) LED1 Setting1 Register
Bit
Name
Description
Mode
Default
A2.29.[15:13]
A2.29.12
A2.29.[11:9]
A2.29.8
A2.29.[7:0]
Reserved
Force LED On
Reserved
Force LED Off
Msk Blink
–
Forces LED1 on.
–
Forces LED1 off.
Blink mask. When the bits are set to 1, a corresponding event
causes the LED to blink.
RO
RW
RO
RW
RW
000
0
000
0
00000000
COMMON REGISTER 8: (MAP TO REG. 30, PAGE 2 A.28.[15:12]=0010) LED1 SETTING2
REGISTER
Default Operation for LED1 is ON during 100 Mbps operation.
Table 28: Common Register 8: (Map to Reg. 30, Page 2 A.28.[15:12]=0010) LED1 Setting2 Register
Bit
Name
Description
Mode
Default
A2.30.[15:8]
Msk On
RW
00100000
A2.30.[7:0]
Msk Off
On mask. When the bits are set to 1, a corresponding event
causes the led to turn on.
Off mask. When the bits are set to one, a corresponding event
causes the led to turn off.
RW
00000000
COMMON REGISTER 9: (MAP TO REG. 31, PAGE 2 A.28.[15:12]=0010) LED2 SETTING1
REGISTER
Table 29: Common Register 9: (Map to Reg. 31, Page 2 A.28.[15:12]=0010) LED2 Setting1 Register
Bit
Name
Description
Mode
Default
A2.31.[15:13]
A2.31.12
A2.31.[11:9]
A2.31.8
Reserved
Force LED On
Reserved
Force LED Off
–
Forces LED2 on.
–
Forces LED2 off.
RO
RW
RO
RW
000
0
000
0
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Common Registers
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Table 29: Common Register 9: (Map to Reg. 31, Page 2 A.28.[15:12]=0010) LED2 Setting1 Register (Cont.)
Bit
Name
Description
Mode
Default
A2.31.[7:0]
Msk Blink
Blink mask. When the bits are set to 1, a corresponding event
causes the led to blink.
RW
00000000
COMMON REGISTER 10: (MAP TO REG. 29, PAGE 3 A.28.[15:12]=0011) LED2 SETTING2
REGISTER
Default operation for LED2 is ON during duplex mode operation.
.
Table 30: Common Register 10: (Map to Reg. 29, Page 3 A.28.[15:12]=0011) LED2 Setting2 Register
Bit
Name
Description
Mode
Default
A3.29.[15:8]
Msk On
RW
10000000
A3.29.[7:0]
Msk Off
On mask. When the bits are set to 1, a corresponding event
causes the led to turn on.
Off mask. When the bits are set to 1, a corresponding event
causes the led to turn off.
RW
00000000
COMMON REGISTER 11: (MAP TO REG. 30, PAGE 3 A.28[.15:12]=0011) LED3 SETTING1
REGISTER
Default operation for LED3 is BLINK when COL.
Table 31: Common Register 11: (Map to Reg. 30, Page 3 A.28[.15:12]=0011) LED3 Setting1 Register
Reg.bit
Name
Description
Mode
Default
A3.30.[15:13]
A3.30.12
A3.30.[11:9]
A3.30.8
A3.30.[7:0]
Reserved
Force LED On
Reserved
Force LED Off
Msk Blink
–
Forces LED3 on.
–
Forces LED3 off.
Blink mask. When the bits are set to 1, a corresponding event
causes the led to blink.
RO
RW
RO
RW
RW
000
0
000
0
0100000
COMMON REGISTER 12: (MAP TO REG. 31, PAGE 3 A.28.[15:12]=0011) LED3 SETTING2
REGISTER
Table 32: Common Register 12: (Map to Reg. 31, Page 3 A.28.[15:12]=0011) LED3 Setting2 Register
Bit
Name
Description
Mode
Default
A3.31.[15:8]
Msk On
RW
00000000
A3.31.[7:0]
Msk Off
On mask. When the bits are set to 1, a corresponding event
causes the led to turn on.
Off mask. When the bits are set to 1, a corresponding event
causes the led to turn off.
RW
00000000
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AC101L-DS06-R
Common Registers
Page 25
AC101L
Preliminary Data Sheet
8/9/04
S ec t io n 6: 4 B /5 B Cod e G ro up
Table 33: 4B/5B Code Group
Symbol name
4B code
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Idle and control codes
I
0000
J
0101
K
0101
T
Undefined
R
Undefined
Invalid code
H
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
V
Undefined
5B code
Description
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
11111
11000
10001
01101
00111
Idle
Start-of-stream delimiter, part 1 of 2; always use in pair with K symbol
Start-of-stream delimiter, part 2 of 2; always use in pair with J symbol
End-of-stream delimiter, part 1 of 2; always use in pair with R symbol
End-of-stream delimiter, part 2 of 2; always use in pair with T symbol
00100
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Transmit error; used to send HALT code group
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
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Page 26
4B/5B Code Group
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Section 7: SMI Re ad/Write Sequenc e
Table 34: SMI Read/Write Sequence
SMI read/write sequence
–
Read
Write
Pream
(32 bits)
1…1
1…1
Start
(2 bits)
01
01
Opcode
(2 bits)
10
01
PHYAD
(5 bits)
AAAAA
AAAAA
REGAD
(5 bits)
RRRRR
RRRRR
TurnAround
(2 bits)
Z0
10
Data
(16 bits)
D…D
D…D
Idle
Z
Z
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
SMI Read/Write Sequence
Page 27
AC101L
Preliminary Data Sheet
8/9/04
Section 8: Ti ming a nd AC Chara cter is t ic s
CLOCK TIMING
Table 35: Clock Timing
Parameter
Symbol
Min
Typ
Max
Units
XTAL input cycle time
XTAL input high/low time
XTAL input rise/fall time
CK_CYCLE
CK_HI CK_LO
CK_EDGE
–
–
–
40
20
–
–
–
4
ns
ns
ns
RESET TIMING
Table 36: Reset Timing
Parameter
Symbol
Min
Typ
Max
Units
Reset pulse length low period with stable XTAL
input
Activity after end of hardware reset
Reset rise/fall time
RESET_LEN
1
–
–
µs
RESET_WAIT
RESET_EDGE
1
–
–
5
–
10
seconds
ns
CK_EDGE
CK_EDGE
XTAL Input
CK_HI
CK_LO
CK_CYCLE
Normal PHY
activity begins here
RESET_EDGE
RESET#
RESET_LEN
RESET_WAIT
RESET_EDGE
Figure 3: Reset Timing
B roa dcom Co rpo rat ion
Page 28
Timing and AC Characteristics
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
MANAGEMENT DATA INTERFACE TIMING
Table 37: Management Interface Timing
Parameter
Symbol
Min
Typ
Max
Units
MDC cycle time
MDC high/low
MDC rise/fall time
MDC_CYCLE
–
MDC_RISE
MDC_FALL
MDIO_SETUP
MDIO_HOLD
MDIO_DELAY
40
20
–
–
–
–
–
–
10
ns
ns
ns
10
10
0
–
–
–
–
–
30
ns
ns
ns
MDIO input setup time to MDC rising
MDIO input hold time from MDC rising
MDIO output delay from MDC rising
MDC_CYCLE
MDC_RISE
MDC
MDC_FALL
MDIO_SETUP
MDIO_HOLD
MDIO_HOLD
MDIO_SETUP
MDIO (Into AC101L)
MDIO (From AC101L)
MDIO_DELAY
Figure 4: Management Interface Timing
100BASE-TX/FX MII TRANSMIT SYSTEM TIMING
Table 38: 100BASE-X MII Transmit System Timing
Parameter
Symbol
Conditions
Min
Typ
Max
Units
TX_CLK period
TX_CLK high period
TX_CLK low period
TXEN to /J/
TXEN sampled to CRS
TXEN sampled to COL
!TXEN to /T/
!TXEN sampled to !CRS
!TXEN sampled to !COL
TX propagation delay
tCK
tCKH
tCKL
tTJ
tCSA
tCLA
tTT
tCSD
tCLD
tTJ
–
–
–
–
RPTR is logic low
RPTR is logic low
–
RPTR is logic low
RPTR is logic low
From TXD[3:0] to TXOP/N(FXTP/N)
39.998
18.000
18.000
–
–
–
–
–
–
–
40.000
20.000
20.000
60
60
60
60
60
60
60
40.002
22.000
22.000
140
140
140
140
140
140
140
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
Management Data Interface timing
Page 29
AC101L
Preliminary Data Sheet
8/9/04
Table 38: 100BASE-X MII Transmit System Timing (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
TXD[3:0], TXEN, TXER setup
TXD[3:0], TXEN, TXER hold
tTXS
tTXH
From rising edge of TX_CLK
From rising edge of TX_CLK
10
0
–
–
–
25
ns
ns
tCK
tCKH
Start of
Packet
tCKL
End of
Packet
TX_CLK
tTXS
TXEN
tTXH
TXD[3:0]
TX_ER
tTJ
/J/
/T/
tTT
TXOP/N
FXTP/N
CRS
tTCSD
tTCSA
tTCLA
tTCLD
COL
Figure 5: 100BASE-TX/FX MII Transmit Timing
B roa dcom Co rpo rat ion
Page 30
100BASE-TX/FX MII Transmit System Timing
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
100BASE-TX/FX MII RECEIVE SYSTEM TIMING
Table 39: 100BASE-TX/FX MII Receive System Timing
Parameter
Symbol
Conditions
Min
Typ
Max
Units
RX_CLK period
RX_CLK high period
RX_CLK low period
/J/K to RXDV assert
/J/K to CRS assert
/J/K to COL assert
/T/R to !RXDV
/T/R to !CRS
/T/R to !COL
RX propagation delay
tCK
tCKH
tCKL
tRDVA
tRCSA
tRCLA
tRDVD
tRCSD
tRCLD
tRDVA
39.998
18.000
18.000
–
–
–
–
–
–
–
40.000
20.000
20.000
40
40
40
40
40
40
40
40.002
22.000
22.000
180
180
180
180
180
180
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RXD[3:0], RXDV assert: Output
delay
RXD[3:0], RXDV de-assert: invalid
tpLH100
–
–
–
–
–
RPTR is logic low.
RPTR is logic low.
RPTR is logic low.
RPTR is logic low.
From RXIP/N(FXRP/N) to
RXD[3:0].
From rising edge RX_CLK.
10
–
30
ns
tpHL100
From rising edge RX_CLK.
10
–
30
ns
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Document
AC101L-DS06-R
100BASE-TX/FX MII Transmit System Timing
Page 31
AC101L
Preliminary Data Sheet
8/9/04
Start of
tCK
Packet
tCKL
tCKH
End of
Packet
RX_CLK
tRDVA
tRDVD
RXDV
RXD[3:0]
RXER
RXDV
/T/R
/J/K
RXIP/N
FXRP/N
tRCSA
tRCSD
CRS
tRCLA
tRCLD
COL
-
tCK
tCKH
25Mhz
RX_CLK
tCKL
tpLH100
tpHL100
RXD[3:0]; RXDV
Valid Data
tpHL = invalid
tpLH = Output delay
Figure 6: 100BASE-T MII Receive Timing
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Page 32
100BASE-TX/FX MII Transmit System Timing
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
10BASE-T MII TRANSMIT SYSTEM TIMING
Table 40: 10BASE-T MII Transmit System Timing
Parameter
SYM
Conditions
Min
Typ
Max
Units
TX_CLK period
TX_CLK high period
TX_CLK low period
TXEN to SOP
TXEN sampled to CRS
TXEN sampled to COL
!TXEN to EOP
!TXEN sampled to !CRS
!TXEN sampled to !COL
TX propagation delay
TXD[3:0], TXEN, TXER setup
TXD[3:0], TXEN, TXER hold
tCK
tCKH
tCKL
tTJ
tTCSA
tTCLA
tTJ
tTCSD
tTCLD
tTJ
tTXS
tTXH
–
–
–
–
RPTR is logic low
RPTR is logic low
–
RPTR is logic low
RPTR is logic low
From TXD[3:0] to TXOP/N
From rising edge of TX_CLK
From rising edge of TX_CLK
399.98
180.00
180.00
240
–
–
240
–
–
240
10
0
400.00
200.00
200.00
–
–
–
–
–
–
–
–
–
400.02
220.00
220.00
360
130
300
360
130
300
360
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCKH
Start of
Packet
tCKL
End of
Packet
TX_CLK
tTX_T
tTX_TX
X
tTXS
TXEN
tTXH
TXD[3:0]
TX_ER
tT
tTJ
J
tT
tTJ
J
TXOP/N
CRS
tTCSD
tTCS
D
tTCS
tTCSA
A
tTCLA
tTCLD
COL
Figure 7: 10BASE-T Transmit Timing
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Document
AC101L-DS06-R
10BASE-T MII Transmit System Timing
Page 33
AC101L
Preliminary Data Sheet
8/9/04
10BASE-T MII RECEIVE SYSTEM TIMING
Table 41: 10BASE-T MII Receive System Timing
Parameter
Symbol
Conditions
Min
Typ
Max
Units
RX_CLK period
RX_CLK high period
RX_CLK low period
SOP to CRS
SOP to COL
EOP to !RXDV
EOP to !CRS
EOP to !COL
RX propagation delay
RXD[3:0], RXDV assert: Output
delay
RXD[3:0], RXDV de-assert:
invalid
tCK
tCKH
tCKL
tRCSA
tRCLA
tRDVD
tRCSD
tRCLD
tRDVA
tpLH10
–
–
–
–
RPTR is logic low.
RPTR is logic low.
RPTR is logic low.
RPTR is logic low.
From RXIP/N to RXD[3:0].
From rising edge RX_CLK.
399.98
180.00
180.00
80
80
120
130
125
180
50
400.00
200.00
200.00
–
–
–
–
–
–
–
400.02
220.00
220.00
150
150
140
190
185
250
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpHL10
From rising edge RX_CLK.
50
–
350
ns
B roa dcom Co rpo rat ion
Page 34
10BASE-T MII Receive System Timing
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
tCK
tCKH
Start of
End of
Packet
tCKL
Packet
RX_CLK
tRDVA
tRDVD
RXDV
RXD[3:0]
RXER
RXDV
SOP
EOP
RXIP/N
tRCSA
tRCSD
CRS
tRCLA
tRCLD
COL
tCK
tCKH
25Mhz
RX_CLK
tCKL
tpLH10
tpHL10
RXD[3:0]; RXDV
Valid Data
tpHL=invalid
tpLH=Output delay
Figure 8: 10BASE-T Receive Timing
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Document
AC101L-DS06-R
10BASE-T MII Receive System Timing
Page 35
Preliminary Data Sheet
AC101L
8/9/04
COPPER APPLICATION TERMINATION
C1
C2
0.1 µF
0.1 µF
49.9Ω_1/16W_1%
R4
49.9Ω_1/16W_1%
R3
49.9Ω_1/16W_1%
R2
TXP
49.9Ω_1/16W_1%
R1
2.5 V
Auto MDI/MDIX
RJ45
1
AC101L
TXN
2
1:1
RXP
3
RXN
6 4578
2.5 V
C4
0.1 µF
Auto MDI/MDIX Magnetics:
BEL: S558-5999-W2;
PULSE: H1102;
HALO: TG110-S050N2
0.1 µF
C3
1:1
75Ω_1/16W_5%
R5
75Ω_1/16W_5%
R6
75Ω_1/16W_5%
R7
75Ω_1/16W_5%
R8
C5
1000PF_2KV
Figure 9: TX Application
B roa dcom Co rpo rat ion
Page 36
Copper Application Termination
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Se ction 9: Ele ctrica l Char acte ristics
Note: The following electrical characteristics are design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Table 42: Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Supply voltage
Storage temperature
Electrostatic discharge
3V3
Ts
VESD
GND-0.3
–40
–
3.465
+125
1000
V
°C
V
Table 43: Current Requirement at 2.5V Operation with LED Disabled
Current (mA)
Operational Mode
Traffic at 100 Mbps
Power-down
Standby
@VCC = 2.5V
@VCC = 2.625V
90
–
30
100
16
32
Table 44: Current Requirement at 3.3V Operation with LED Disabled
Current (mA)
Operational Mode
Traffic at 100 Mbps
Power-down
Standby
@VCC = 3.3V
@VCC = 3.465V
92
–
32
102
18
34
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Document
AC101L-DS06-R
Electrical Characteristics
Page 37
Preliminary Data Sheet
AC101L
8/9/04
RECOMMENDED OPERATING CONDITIONS
Table 45: Recommended Operating Conditions
Parameter
Symbol Pins
Operating mode
Min
Typ
Max
Units
Ambient operating
temperature AC101L
Bias voltage
TA
–
–
–40
–
+85
°C
VBIAS
RBIAD
–
1.18
–
1.30
V
Common mode input
voltage
Common mode input
voltage
Differential input
voltage
Differential output
voltage
Input current
VICM
RD±
100BASE-TX
1.8
–
VCC
V
VICM
RD±
100BASE-FX
1.8
–
2.2
V
VIDIFF
RD±
0.37
–
2.00
V
VODIFF
TD ±
100BASE-FX (with 100
ohm load)
100BASE-FX mode
1.5
–
1.7
V
II
VI = VCC
–
–
200
µA
Input voltage high
VIH
Digital inputs with
pull-up resistor
SD
100BASE-FX
2.2
–
Input voltage high
VIH
All digital input
VCC = 2.5V ±5%
1.4
–
–
V
Input voltage low
VIL
SD
100BASE-FX
–
–
1.7
V
Input voltage low
VIL
All digital input
VCC = 2.5V ±5%
–
–
1.1
V
Output voltage high
VOH
All digital output
VCC = 2.5V ±5%
2.3
–
–
V
2.0
–
–
–
–
–
VCC+1.5
V
–
–
0.4
–
–
–
0.4
–
Driving load magnetic
module
–
VCC–1.5
–
–
–
3.135
3.3
3.465
V
–
2.375
2.5
2.625
V
–
V
IOH = –10 µA
Output voltage high
VOH
All digital output
VCC = 2.5V ±5%
IOH = –4 mA
Output voltage high
VOH
TD±
Output voltage low
VOL
All digital output
Driving load magnetic
module
VCC = 2.5 V ±5%
IOL = 10 µA
Output voltage low
VOL
All digital output
Output voltage low
VOL
TD±
Supply voltage
AC101L
Supply voltage
AC101L
3V3
VCC33IN
VCC
VCC, VCCPLL,
VCC25OUT
VCC = 2.5V ±5%
IOL = 4 mA
B roa dcom Co rpo rat ion
Page 38
Recommended Operating Conditions
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
S e c t io n 1 0 : Fi be r A p pl i c a t i on Te r m i n a t io n
C8
0.1 µF
Z=50 Ω
Z=50 Ω
C9
0.1 µF
Z=50 Ω
5
4
3
9
10
SD/FXEN
Z=50 Ω
TXP
Z=50 Ohm C10
0.1 µF
Z=50 Ω
TXN
Z=50 Ohm C11
0.1 µF
Z=50 Ω
RD+
RDSD
TD+
TD-
R13
R14
R15
R16
82
82
R11
R12
20 kΩ
20 kΩ
20 kΩ
20 kΩ
R10
1 µF
82 Ω
C12
0.1 µF
BLM11A601S
8
Z=50 Ω
RXN
6
RXP
2
0.1 µF
C2
L2
7
C6
L1
BLM11A601S
0.1 µF
C3
10 µF
C7
0.1 µF
U1
RxVcc
RxVee
TxVcc
TxVee
NC
R9
R8
C1
130 Ω
C5
3_3 V
130 Ω
13 kΩ
13 kΩ
0.01 µF
R6
R7
C4
0.01 µF
R4
R5
50 Ω
50 Ω
R2
R3
3_3 V
1
AC101L
2_5 V
5 kΩ
5 kΩ
130 Ω
R1
3_3 V
HFBR-5903
Figure 10: FX Application
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
Fiber Application Termination
Page 39
Preliminary Data Sheet
AC101L
8/9/04
S e c t io n 11 : P o w e r a n d G r o un d F il t e r in g
Place all CAPs
as close as
possible to each
power pin of
AC101L
VCC
GND1
RXDV/CRSDV
RXC
RXER
GND2
VCC
TXER
TXC
TXEN
TXD0
TXD1
AC101L
4 8 TQFP_7x7mm
C5
0.1µ F
VCC25OUT
TXP
TXN
GND6
VCCPLL
RBIAD
GND5
GND4
SD/FXEN
RXP
RXN
VCC
36
35
34
33
32
31
30
29
28
27
26
25
C6
22 µ F
1µ F
2_5 V
VCCPLL
C10
C11
+
1 nF
2.2 µ F
2_5 V
C14
1
2
3
4
5
6
7
8
9
10
11
12
C4
0.01 µ F
RXD0/PHYAD4
RXD1/PHYAD3
RXD2/PHYAD2
RXD3/PHYAD1
MDC
MDIO
RST_L
VCC33IN
XI
XO
GND8
GND7
48
47
46
45
44
43
42
41
40
39
38
37
2_5 V
C1 3
0.01 µ F
0.01 µ F
13
14
15
16
17
18
19
20
21
22
23
24
C12
0.1µ F
0.1µ F
0.1 µ F
C9
0.01 µ F
C2
3_3 V
TXD2
TXD3
COL
CRS/REPEATER
GND3
VCC
INTR/PHYAD0
LED0/BURNIN_L
LED1/SPD100
LED2/DUPLEX
LED3/ANEN
PDOWN
C8
0.1µ F
10 µ F
C3
2_5 V
C7
C1
2_5 V
C15
0.1µ F
C16
0.01 µ F
Figure 11: Power and Ground Filtering
B roa dcom Co rpo rat ion
Page 40
Power and Ground Filtering
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Sec tion 12 : Me chan ic al Inform ation
Figure 12: Quad Flat Pack outline (7×7 mm)
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Document
AC101L-DS06-R
Mechanical Information
Page 41
Preliminary Data Sheet
AC101L
8/9/04
Se ction 13: Ther mal Para mete rs
Table 46: Thermal Parameters
Airflow (feet per minute)
0
100
200
400
600
ThetaJA (°C/W)
53.9
51.2
50
48.6
47.5
24.7
–
–
ThetaJC (°C/W) at maximum junction temperature of 125°C
B roa dcom Co rpo rat ion
Page 42
Thermal Parameters
Document AC101L-DS06-R
Preliminary Data Sheet
AC101L
8/9/04
Se ction 14: Orde ring Information
Table 47: Ordering Information
Part number
Package
Ambient temperature
AC101LKQT
48TQFP
0°C to +70°C
AC101LIQT
48TQFP
–40°C to +85°C
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
Ordering Information
Page 43
Preliminary Data Sheet
AC101L
8/9/04
Altima Communications, Inc.
A Wholly-Owned Subsidiary of Broadcom Corporation
16215 Alton Parkway
P.O. Box 57013
Irvine, California 92619-7013
Phone: 949-450-8700
Fax: 949-450-8710
Altima Communications reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.
Information furnished by Altima Communications is believed to be accurate and reliable. However, Altima Communications
does not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
D ocu ment
AC 101L- DS 06- R