A8698 Wide Input Voltage 3.0 A Step Down Regulator Features and Benefits Description ▪ ▪ ▪ ▪ ▪ The A8698 is a constant off-time current mode step-down regulator with a wide input voltage range. Regulation voltage is set by external resistors, to output voltages as low as 0.8 V. 8 to 25 V input range Integrated DMOS switch Adjustable fixed off-time Highly efficient Adjustable 0.8 to 20 V output The A8698 includes an integrated power DMOS switch to reduce the total solution footprint. It also features internal compensation, allowing users to design stable regulators with minimal design efforts. The off-time can be set with an external resistor, allowing flexibility in inductor selection. Additionally, the A8698 has a logic level enable pin which can shut the device down and put it into a low quiescent current mode for power sensitive applications. The A8698 is supplied in a low-profile 8-lead SOIC with exposed pad (package LJ). Applications include: Package: 8-Lead SOIC with exposed thermal pad (suffix LJ) ▪ ▪ ▪ ▪ Applications with 8 to 25 V input Consumer electronics, networking equipment 12 V lighter-powered applications (portable DVD, etc.) Point of Sale (POS) applications Approximate Scale 1:1 Typical Application +8 to 24 V Efficiency VIN = 12.0 V CBOOT 0.01 μF CIN3 82 μF 35 V BOOT CIN2 82 μF 35 V 92 CIN1 0.22 μF VOUT = 5.0 V 90 88 VIN VOUT = 3.3 V ENB LX L1 33 μH A8698 TSET VBIAS RTSET 30.1 k7 R1 6.34 k7 GND VOUT 3.3 V / 3 A FB D1 R2 2 k7 Efficiency (%) 86 84 82 VOUT = 2.5 V 80 78 76 COUT 330 μF 6.3 V ESR 74 72 70 0 0.5 1.0 1.5 2.0 Load Current (A) Circuit for 12 V step down to 3.3 V at 3 A. A8698-DS, Rev. 3 Efficiency curves for circuit at left. 2.5 3.0 A8698 Wide Input Voltage 3.0 A Step Down Regulator Absolute Maximum Ratings Min. Typ. Max. Units VIN Supply Voltage Characteristic Symbol VIN Conditions – – 25 V VBIAS Input Voltage VBIAS –0.3 – 7 V Switching Voltage VS –1 – – V ENB Input Voltage VENB Operating Ambient Temperature Range TA Range E –0.3 – 7 V –40 – 85 °C Junction Temperature TJ(max) – – 150 °C Storage Temperature TS –55 – 150 °C *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. Package Thermal Characteristics* Package RθJA (°C/W) PCB LJ 35 4-layer * Additional information is available on the Allegro website. Ordering Information Use the following complete part numbers when ordering: Part Numbera Packingb Description A8698ELJTR-T 13 in. reel, 3000 pieces/reel LJ package, SOIC surface mount with exposed thermal pad A8698ELJ-T aLeadframe 98 pieces/tube plating 100% matte tin. for additional packing options. bContact Allegro Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A8698 Wide Input Voltage 3.0 A Step Down Regulator Functional Block Diagram BOOT + VIN VIN VIN Boot Charge – VOUT LX L1 D1 ESR COUT ENB Switch PWM Control Switch Disable μC Clamp + TSET – I_Demand FB – Error + I_Peak COMP GND VBB UVLO TSD Soft Start Ramp Generation Bias Supply VBIAS VBIAS is connected to VOUT when VOUT target is between 3.3 and 5 V 0.8 V Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A8698 Wide Input Voltage 3.0 A Step Down Regulator ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 25 V (unless noted otherwise) Characteristics VIN Quiescent Current VBIAS Input Current Buck Switch On Resistance Symbol IVIN(Q) IBIAS RDS(on) Fixed Off-Time Proportion Feedback Voltage Output Voltage Regulation Test Conditions Min. Typ. Max. Units VENB = LOW, VIN = 12 V, VBIAS = 3.2 V, VFB = 1.5 V (not switching) – 1.0 – mA VENB = LOW, VIN = 12 V, VBIAS < 3 V, VFB = 1.5 V – 4.1 – mA VENB = HIGH – – 100 μA VBIAS = VOUT – 3.8 5 mA TA = 25°C, IOUT = 3 A – 180 – mΩ –15 – 15 % 0.784 0.8 0.816 V –3 – 3 % Based on calculated value VFB VOUT IOUT = 0 mA to 3 A Feedback Input Bias Current IFB –400 –100 100 nA Soft Start Time tss 5 10 15 ms Buck Switch Current Limit ICL VFB > 0.4 V 3.5 – 5 A VFB < 0.4 V – 1.15 – A ENB Open Circuit Voltage VOC 2.0 – 7 V – – 1.0 V Output disabled ENB Input Voltage Threshold VENB(0) LOW level input (Logic 0), output enabled ENB Input Current IENB(0) VENB = 0 V –10 – –1 μA VIN Undervoltage Threshold VUVLO VIN rising 6.6 6.9 7.2 V VIN Undervoltage Hysteresis VUVLO(hys) VIN falling 0.7 – 1.1 V Temperature increasing – 165 – °C Recovery = TJTSD – TJTSD(hys) – 15 – °C Thermal Shutdown Temperature Thermal Shutdown Hysteresis 1Negative TJTSD TJTSD(hys) current is defined as coming out of (sourcing) the specified device pin. over the junction temperature range of 0ºC to 125ºC are assured by design and characterization. 2Specifications Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A8698 Wide Input Voltage 3.0 A Step Down Regulator Performance Characteristics Start-up Operation VOUT; 2.00 V/div. VSW; 10.0 V/div. IOUT; 1.00 A/div. VOUTAC; 500 mV/div. VINAC; 1.00 V/div. IOUT; 2.00 A/div. t t t = 10.0 ms/div. t = 5.00 μs/div. Transient Response Power Off VIN = 12 V, VOUT = 3.3 V VOUTAC; 200 mV/div. VOUT; 2.00 V/div. IOUT; 500 mA/div. 1.45 A 1.0 A IOUT; 1.00 A/div. t 1.0 A t t = 1.00 ms/div. Detail: Step Up Transient Response VIN = 12 V, VOUT = 3.3 V t = 1.00 ms/div. Detail: Step Down Transient Response VIN = 12 V, VOUT = 3.3 V VOUTAC; 500 mV/div. 1.45 A IOUT; 500 mA/div. VOUTAC; 500 mV/div. IOUT; 500 mA/div. 1.45 A 1.0 A 1.0 A t t = 100 μs/div. t t = 100 μs/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A8698 Wide Input Voltage 3.0 A Step Down Regulator Load Regulation Line Regulation IOUT = 3.0 A 0.2 0.2 0.1 0.1 VOUT Error (%) VOUT Error (%) 0 0 –0.1 –0.2 –0.1 –0.2 –0.3 –0.4 –0.3 –0.5 –0.4 –0.6 0 0.5 1.0 1.5 Load Current (A) 2.0 2.5 3.0 9 11 13 15 17 19 21 23 25 VIN (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A8698 Wide Input Voltage 3.0 A Step Down Regulator Functional Description The A8698 is a fixed off-time, current-mode–controlled buck switching regulator. The regulator requires an external clamping diode, inductor, and filter capacitor, and operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. ON/OFF Control. The ENB pin is externally pulled to ground to enable the device and begin the soft start sequence. When the ENB is open circuited, the switcher is disabled and the output decays to 0 V. The value of a resistor between the TSET pin and ground determines the fixed off-time (see graph in the tOFF section). • VIN < 6 V • ENB pin = open circuit • TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. VOUT = VFB × (1 + R1/R2) (1) Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. Internally, the ramp is set to 10 ms nominal rise time. During soft start, current limit is 3.5 A minimum. The following conditions are required to trigger a soft start: • VIN > 6 V • ENB pin input falling edge • Reset of a TSD (thermal shut down) event VBIAS. To improve overall system efficiency, the regulator output, VOUT, is connected to the VBIAS input to supply the operating bias current during normal operating conditions. During startup the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and 5 V. If the output voltage is less than 3.3 V, then the A8698 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, VIN. VBIAS can also be supplied with an external voltage source. No power-up sequencing is required for normal opperation. tOFF. The value of a resistor between the TSET pin and ground determines the fixed off-time. The formula to calculate tOFF (μs) is: ⎛ 1–0.03 VBIAS ⎞ (2) ⎟ tOFF = RSET ⎜ 10.2 × 109 ⎝ ⎠ where RTSET (kΩ) is the value of the resistor. Results with the VBIAS pin connected are shown in the following graph (when VBIAS is not connected, use VBIAS = 0 in equation 2): Off-Time Setting versus Resistor Value 200 180 160 140 RTSET (kΩ) VOUT. The output voltage is adjustable from 0.8 to 20 V, based on the combination of the value of the external resistor divider and the internal 0.8 V ±2% reference. The voltage can be calculated with the following formula: Protection. The buck switch will be disabled under one or more of the following fault conditions: VBIAS = 5 V 120 100 VBIAS = 3.3 V 80 60 40 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tOFF (µs) tON. From the volt-second balance of the inductor, the turn-on time, ton , can be calculated approximately by the equation: tON = (VOUT + Vf + IOUT RL) tOFF VIN – IOUT RDS(on) – IOUT RL – VOUT (3) where Vf is the voltage drop across the external Schottky diode, RL is the winding resistance of the inductor, and Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A8698 Wide Input Voltage 3.0 A Step Down Regulator time is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. RDS(on) is the on-resistance of the switching MOSFET. The switching frequency is calculated as follows: 1 fSW = tON + tOFF (4) The extension of the off-time is based on the value of the TSET multiplier and the FB voltage, as shown in the following table: Shorted Load. If the voltage on the FB pin falls below 0.4 V, the regulator will invoke a 1.5 A typical overcurrent limit to handle the shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the off- VFB (V) TSET Multiplier < 0.16 8 × tOFF < 0.32 4 × tOFF < 0.5 2 × tOFF Component Selection L1. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by: IRIPPLE = VL(OFF) × tOFF / L (5) VL(OFF) = VOUT + Vf + IL(AV) × RL (6) Example: Given VOUT = 3.3 V, Vf = 0.55 V, VIN = 12 V, ILOAD = 3.0 A, power inductor with L = 33 μH and RL = 0.05 Ω Rdc at 55°C, tOFF = 2.67 μs, and RDS(on) = 0.2 Ω. Substituting into equation 6: Substituting into equation 8: tON = 323 mA × 33 μH / 7.95 V = 1.34 μs Substituting into equation 7: fSW = 1 / (2.67 μs + 1.34 μs) = 250 kHz Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. The maximum total current available, ILOAD(MAX) , is: ILOAD(MAX) = ICL(min) – IRIPPLE / 2 (10) where ICL(min) is 3.5 A, from the Electrical Chracteristics table. D1. The Schottky catch diode should be rated to handle 1.2 times the maximum load current. The voltage rating should be higher than the maximum input voltage expected during all operating conditions. The duty cycle for high input voltages can be very close to 100%. VL(OFF) = 3.3 V + 0.55 V+ 3.0 A × 0.05 Ω = 4.0 V Substituting into equation 5: IRIPPLE = 4.0 V × 2.67 μs / 33 μH = 323 mA The switching frequency, fSW, can then be estimated by: fSW = 1 / ( tON + tOFF ) (7) tON = IRIPPLE × L / VL(ON) (8) VL(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT (9) Substituting into equation 9: VL(ON) = 12 V – 3 A × 0.2 Ω – 3 A × 0.05 Ω – 3.3 V = 7.95 V COUT. The main consideration in selecting an output capacitor is voltage ripple on the output. For electrolytic output capacitors, a low-ESR type is recommended. The peak-to-peak output voltage ripple is simply IRIPPLE × ESR. Note that increasing the inductor value can decrease the ripple current. The ESR should be in the range from 50 to 500 mΩ. If a low ESR capacitor is used, such as a POSCAP or SP, an extra Rr , Cr circuit is needed to inject ripple into the feedback pin and ensure stability. Please refer to the Application Circuit section for Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A8698 Wide Input Voltage 3.0 A Step Down Regulator the connection. The Rr should be much larger than the feedback resistor to prevent any potential offset in output voltage. For example, if Rf < 10 kΩ, Rr should be 1 MΩ. Cr should be selected based on the following equation: Cr(max) = (VIN(min) – VFB ) × tON(min) Note. The curve represents the minimum RTSET value. When calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor tolerance should also be considered, so that under no operating conditions the resistance on the TSET pin is allowed to go below (5) 0.05 × Rr the minimum value. where Cr is in pF, tON(min) is in μs, and Rr is in MΩ. FB Resistor Selection. The impedance of the FB network RTSET Selection. Correct selection of RTSET values will ensure that minimum on-time of the switcher is not violated and prevent the switcher from cycle skipping. For a given VIN to VOUT ratio, the RTSET value must be greater than or equal to the value defined by the curve in the plot below. should be kept low to improve noise immunity. Large value resistors can pick up noise generated by the inductor, which can affect voltage regulation of the switcher. 13.0 12.5 12.0 Violation of Minimum On-Time 11.5 11.0 10.5 10.0 9.5 9.0 VIN / VOUT 8.5 8.0 7.5 um im n i M 7.0 6.5 6.0 e lu Va R of TS ET Safe Operating Area 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 70.0 67.5 65.0 62.5 57.5 60.0 52.5 55.0 47.5 50.0 42.5 45.0 37.5 40.0 32.5 35.0 27.5 30.0 22.5 25.0 20.0 15.0 17.5 10.0 12.5 RTSET (k7) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A8698 Wide Input Voltage 3.0 A Step Down Regulator Application Circuit Circuit with Low ESR Capacitor Efficiency versus Load Current fSW = 500 kHz nominal at 12 V Stabilized with low ESR capacitor 100 80 Efficiency (%) VIN 12 to 16.4 V CBOOT 0 .01 μF 90 BOOT VIN ENB LX CIN 22 μF 70 60 A8698 50 RTSET 16.4 kΩ 40 TSET VBIAS GND FB VOUT 5 V /2 . 5 A L 10 μH COUT 120 μF 18 mΩ D1 R3 1 MΩ 30 R1 6 .34 kΩ 20 10 Ratings: L: CDRH104R-100NC COUT: EEFUD0J121R CIN: ECJ-4YB1E226M 0 0 0.5 1.0 1.5 2.0 2.5 3.0 R2 1.2 kΩ 100 pF Load Current (A) Evaluation Board Silkscreen Layer Bottom Layer J1 8 to 24 Vdc C1.2 C1.3 C1.1 J2 GND C3 C2 ENB A8698 TSET R3 EN C4.1 VIN BOOT R4 J4 GND L1 LX D1 VBIAS C4.2 J3 3.3 V / 3.0 A C4.3 VOUT FB GND PAD R2 R1 Top and Silkscreen Layers R5 P1 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8698 Wide Input Voltage 3.0 A Step Down Regulator Evaluation Board Bill of Materials Description Manufacturer Footprint Part Number C1.1 1 Ceramic chip, 22 μF, 25 V, ±20%, X5R. Panasonic 1210 ECJ4YB1E226M C1.2, C1.3 2 Aluminum electrolytic capacitor, 35 V / 82 μF, 930 mA ripple current Rubycon Designator Quantity 8 mm × 12 mm 35V-ZAV-820-8 X 12 C2 1 Ceramic capacitor, X7R, ±10%, 0.1 μF / 50 V Murata 0603 GRM188R71H104KA93D C3 1 Ceramic capacitor, X7R, ±10%, 0.01 μF / 50 V Kemet 0603 C0603C103K5RACTU C4.2 0 Special polymer cap, 120 μF / 6.3 V, 15 mΩ Panasonic 7.3 mm × 4.3 mm × 3.1 mm EEFUD0J121R C4.1 0 Ceramic capacitor, X5R, ±20%, 47 μF / 6.3 V Panasonic 1210 ECJ4YB0J476M C4.3 1 Aluminum electrolytic capacitor, 6.3 V / 330 μF, 450 mA ripple current, 300 mΩ Panasonic L1 1 Inductor, 33 μH, 53 mΩ, 3.9 A, ±20% Sumida 10.3 mm × 10.5 mm × 4 mm CDRH127/LDNP-330MC D1 1 Schottky diode, 40 V / 3.0 A Diodes, Inc. SMA B340 R1 1 Chip resistor, 6.34 kΩ, 1/16 W, 1% Std 0603 Std. R2 3 Chip resistor, 2.0 kΩ,1/16 W, 1% Std 0603 Std. R3 1 Chip resistor, 30.1 kΩ, 1/16 W, 1% Std 0603 Std. R4 1 Chip resistor, 10 kΩ, 1/16 W, 1% Std 0603 Std. 8 mm × 10.2 mm EEVFC0J331P R5 1 Chip resistor, 0 Ω, 1/16 W, 1% Std 0603 Std. J1, J2, J3, J4 4 Header, 2-pin, 100 mil spacing Sullins 0.100 in. × 2 PTC36SAAN P1 1 Test point, Red, 1mm Farnell 0.038 in. 240-345 EN 1 Test point, Black, 1mm Farnell 0.038 in. 240-333 U1 1 Wide Input Voltage Step Down Regulator Allegro ESOIC8 A8698 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8698 Wide Input Voltage 3.0 A Step Down Regulator 6.20 .244 5.80 .228 Package LJ 8-Pin SOIC 0.25 [.010] M B M 8 5.00 .197 4.80 .189 8º 0º A B B 0.25 .010 0.17 .007 4.00 .157 3.80 .150 2.41 .095 NOM 1.27 .050 0.40 .016 A 1 3.30 .130 NOM 2 0.25 .010 8X SEATING PLANE 0.10 [.004] C 8X 0.51 .020 0.31 .012 0.25 .010 0.10 .004 1.27 .050 0.65 .026 MAX 1.27 .050 NOM 1.75 .069 NOM 2.41 .095 NOM 1 8 VIN ENB 2 7 LX TSET 3 6 VBIAS GND 4 5 FB Pad (Top View) All dimensions reference, not for tooling use (reference JEDEC MS-012 AA) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 2 6X 0.20 .008 MIN 3.30 .130 NOM BOOT 5.60 .220 NOM C 1 Pin-out Diagram SEATING PLANE GAUGE PLANE 1.75 .069 1.35 .053 0.25 [.010] M C A B 2X 0.20 .008 MIN C Terminal List Table Number 1 2 3 4 5 6 7 8 – Name BOOT ENB TSET GND FB VBIAS LX VIN Pad Description Gate drive boost node On/off control; logic input Off-time setting Ground Feedback for adjustable regulator Bias supply input Buck switching node Supply input Exposed pad for enhanced thermal dissipation The products described herein are manufactured under one or more patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties that may result from its use. Copyright © 2006 Allegro MicroSystems, Inc. 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com